diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..7a60b85 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +__pycache__/ +*.pyc diff --git a/benchmark_results/fpga_benchmark.csv b/benchmark_results/fpga_benchmark.csv new file mode 100644 index 0000000..930e736 --- /dev/null +++ b/benchmark_results/fpga_benchmark.csv @@ -0,0 +1,4 @@ +target_id,fpga,family,parallel,n_inputs,n_neurons,status,fmax_mhz,period_ns,slack_ns,lut,ff,dsp,lut_pct,ff_pct,dsp_pct,mac_per_cycle,groups_per_neuron,total_mac,cycles_per_layer,cost_eur,mac_per_second,mac_per_euro,build_time_s,error +ecp5_45f,LFE5U-45F-8BG381,ECP5,8,256,4,FAIL,,,,,,,,,,32,32,32,32,35.0,,,,nextpnr placement/routing failed +ecp5_45f,LFE5U-45F-8BG381,ECP5,4,256,4,FAIL,,,,,,,,,,16,64,16,64,35.0,,,,nextpnr placement/routing failed +ecp5_45f,LFE5U-45F-8BG381,ECP5,2,256,4,PASS,,,,,,,,,,8,128,8,128,35.0,,,1.504363291998743, diff --git a/benchmark_results/fpga_benchmark.json b/benchmark_results/fpga_benchmark.json new file mode 100644 index 0000000..3a9b5db --- /dev/null +++ b/benchmark_results/fpga_benchmark.json @@ -0,0 +1,83 @@ +[ + { + "target_id": "ecp5_45f", + "fpga": "LFE5U-45F-8BG381", + "family": "ECP5", + "parallel": 8, + "n_inputs": 256, + "n_neurons": 4, + "status": "FAIL", + "fmax_mhz": null, + "period_ns": null, + "slack_ns": null, + "lut": null, + "ff": null, + "dsp": null, + "lut_pct": null, + "ff_pct": null, + "dsp_pct": null, + "mac_per_cycle": 32, + "groups_per_neuron": 32, + "total_mac": 32, + "cycles_per_layer": 32, + "cost_eur": 35.0, + "mac_per_second": null, + "mac_per_euro": null, + "build_time_s": null, + "error": "nextpnr placement/routing failed" + }, + { + "target_id": "ecp5_45f", + "fpga": "LFE5U-45F-8BG381", + "family": "ECP5", + "parallel": 4, + "n_inputs": 256, + "n_neurons": 4, + "status": "FAIL", + "fmax_mhz": null, + "period_ns": null, + "slack_ns": null, + "lut": null, + "ff": null, + "dsp": null, + "lut_pct": null, + "ff_pct": null, + "dsp_pct": null, + "mac_per_cycle": 16, + "groups_per_neuron": 64, + "total_mac": 16, + "cycles_per_layer": 64, + "cost_eur": 35.0, + "mac_per_second": null, + "mac_per_euro": null, + "build_time_s": null, + "error": "nextpnr placement/routing failed" + }, + { + "target_id": "ecp5_45f", + "fpga": "LFE5U-45F-8BG381", + "family": "ECP5", + "parallel": 2, + "n_inputs": 256, + "n_neurons": 4, + "status": "PASS", + "fmax_mhz": null, + "period_ns": null, + "slack_ns": null, + "lut": null, + "ff": null, + "dsp": null, + "lut_pct": null, + "ff_pct": null, + "dsp_pct": null, + "mac_per_cycle": 8, + "groups_per_neuron": 128, + "total_mac": 8, + "cycles_per_layer": 128, + "cost_eur": 35.0, + "mac_per_second": null, + "mac_per_euro": null, + "build_time_s": 1.504363291998743, + "error": null + } +] \ No newline at end of file diff --git a/synth/ecp5/p2/report.txt b/synth/ecp5/p2/report.txt new file mode 100644 index 0000000..509233a --- /dev/null +++ b/synth/ecp5/p2/report.txt @@ -0,0 +1,388 @@ +Warning: IO 'y_bus[31]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[30]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[29]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[28]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[27]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[26]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[25]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[24]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[23]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[22]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[21]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[20]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[19]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[18]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[17]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[16]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[15]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[14]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[13]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[12]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[11]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[10]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[9]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[8]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[7]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[6]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[5]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[4]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[3]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[2]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[1]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[0]' is unconstrained in LPF and will be automatically placed +Warning: IO 'start' is unconstrained in LPF and will be automatically placed +Warning: IO 'rst' is unconstrained in LPF and will be automatically placed +Warning: IO 'done' is unconstrained in LPF and will be automatically placed +Warning: IO 'clk' is unconstrained in LPF and will be automatically placed +Warning: IO 'busy' is unconstrained in LPF and will be automatically placed + +Info: Logic utilisation before packing: +Info: Total LUT4s: 481/43848 1% +Info: logic LUTs: 95/43848 0% +Info: carry LUTs: 386/43848 0% +Info: RAM LUTs: 0/ 5481 0% +Info: RAMW LUTs: 0/10962 0% + +Info: Total DFFs: 198/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 191 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0x83be9e7c + +Info: Device utilisation: +Info: TRELLIS_IO: 37/ 245 15% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 108 0% +Info: MULT18X18D: 8/ 72 11% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 198/ 43848 0% +Info: TRELLIS_COMB: 551/ 43848 1% +Info: TRELLIS_RAMW: 0/ 5481 0% + +Info: Placed 0 cells based on constraints. +Info: Creating initial analytic placement for 129 cells, random placement wirelen = 25757. +Info: at initial placer iter 0, wirelen = 3145 +Info: at initial placer iter 1, wirelen = 2698 +Info: at initial placer iter 2, wirelen = 2587 +Info: at initial placer iter 3, wirelen = 2563 +Info: Running main analytical placer, max placement attempts per cell = 79003. +Info: at iteration #1, type ALL: wirelen solved = 2537, spread = 4133, legal = 5191; time = 0.01s +Info: at iteration #2, type ALL: wirelen solved = 2554, spread = 3904, legal = 4675; time = 0.00s +Info: at iteration #3, type ALL: wirelen solved = 2545, spread = 3704, legal = 4373; time = 0.00s +Info: at iteration #4, type ALL: wirelen solved = 2549, spread = 3862, legal = 4324; time = 0.00s +Info: at iteration #5, type ALL: wirelen solved = 2590, spread = 3707, legal = 4361; time = 0.00s +Info: at iteration #6, type ALL: wirelen solved = 2544, spread = 3885, legal = 4543; time = 0.00s +Info: at iteration #7, type ALL: wirelen solved = 2578, spread = 3986, legal = 4545; time = 0.00s +Info: at iteration #8, type ALL: wirelen solved = 2595, spread = 3719, legal = 4059; time = 0.00s +Info: at iteration #9, type ALL: wirelen solved = 2683, spread = 4065, legal = 4376; time = 0.00s +Info: at iteration #10, type ALL: wirelen solved = 2650, spread = 3696, legal = 3917; time = 0.00s +Info: at iteration #11, type ALL: wirelen solved = 2605, spread = 3682, legal = 4248; time = 0.00s +Info: at iteration #12, type ALL: wirelen solved = 2652, spread = 3920, legal = 4328; time = 0.00s +Info: at iteration #13, type ALL: wirelen solved = 2686, spread = 3988, legal = 4511; time = 0.00s +Info: at iteration #14, type ALL: wirelen solved = 2675, spread = 3787, legal = 4235; time = 0.00s +Info: at iteration #15, type ALL: wirelen solved = 2706, spread = 3567, legal = 4256; time = 0.00s +Info: HeAP Placer Time: 0.09s +Info: of which solving equations: 0.05s +Info: of which spreading cells: 0.01s +Info: of which strict legalisation: 0.01s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 124, wirelen = 3917 +Info: at iteration #5: temp = 0.000000, timing cost = 93, wirelen = 2856 +Info: at iteration #10: temp = 0.000000, timing cost = 103, wirelen = 2805 +Info: at iteration #13: temp = 0.000000, timing cost = 103, wirelen = 2799 +Info: SA placement time 0.16s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 98.23 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.59 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 7.53 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 2320, 2801) |****+ +Info: [ 2801, 3282) |****+ +Info: [ 3282, 3763) | +Info: [ 3763, 4244) | +Info: [ 4244, 4725) | +Info: [ 4725, 5206) |*******+ +Info: [ 5206, 5687) |*********************+ +Info: [ 5687, 6168) |*********+ +Info: [ 6168, 6649) |*** +Info: [ 6649, 7130) |*+ +Info: [ 7130, 7611) | +Info: [ 7611, 8092) |****+ +Info: [ 8092, 8573) |*****************+ +Info: [ 8573, 9054) |********************+ +Info: [ 9054, 9535) |****************************************+ +Info: [ 9535, 10016) |************************************+ +Info: [ 10016, 10497) |************************************************************ +Info: [ 10497, 10978) |*********************************************************+ +Info: [ 10978, 11459) |**********************************+ +Info: [ 11459, 11940) |***+ +Info: Checksum: 0x9ce6835b +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 1805 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 401 520 | 401 520 | 1232| 0.13 0.13| +Info: 2000 | 429 1378 | 28 858 | 263| 0.05 0.18| +Info: 2263 | 430 1606 | 1 228 | 0| 0.05 0.23| +Info: Routing complete. +Info: Router1 time 0.23s +Info: Checksum: 0xb5a832a6 + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.Q +Info: routing 0.87 1.27 Net u_layer.GEN_NEURON[3].u_neuron.w_group[10] (64,23) -> (65,22) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.B2 +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50 +Info: logic 3.07 4.33 Source u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.P5 +Info: routing 1.12 5.45 Net u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[1][5] (65,22) -> (64,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB1.A +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13 +Info: logic 0.35 5.81 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 5.81 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1_COUT (64,21) -> (65,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 5.86 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 5.86 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.00 5.86 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 5.86 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1_COUT (65,21) -> (65,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 5.92 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 5.92 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.00 5.92 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 5.92 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1_COUT (65,21) -> (65,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 5.98 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 5.98 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.00 5.98 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 5.98 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1_COUT (65,21) -> (65,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 6.03 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 6.03 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.00 6.03 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 6.03 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1_COUT (65,21) -> (66,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 6.09 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 6.09 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_FCI_INT (66,21) -> (66,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.00 6.09 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 6.09 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT (66,21) -> (66,21) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.33 6.42 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.F +Info: routing 0.89 7.31 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN_S0 (66,21) -> (66,19) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.B +Info: logic 0.35 7.66 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.FCO +Info: routing 0.00 7.66 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_COUT (66,19) -> (66,19) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 7.72 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCO +Info: routing 0.00 7.72 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_FCI_INT (66,19) -> (66,19) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCI +Info: logic 0.00 7.72 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCO +Info: routing 0.00 7.72 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_COUT (66,19) -> (66,19) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.33 8.05 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.F +Info: routing 0.87 8.92 Net u_layer.GEN_NEURON[3].u_neuron.acc_next[20] (66,19) -> (66,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42 +Info: logic 0.35 9.27 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (66,18) -> (66,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 9.27 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (66,18) -> (67,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.33 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 9.33 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (67,18) -> (67,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.39 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 9.39 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 9.39 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 9.39 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (67,18) -> (67,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.44 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 9.44 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN (67,18) -> (67,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.50 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 9.50 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 9.50 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 9.50 Net $nextpnr_CCU2C_13$CIN (67,18) -> (68,18) +Info: Sink $nextpnr_CCU2C_13$CCU2_COMB0.FCI +Info: logic 0.33 9.82 Source $nextpnr_CCU2C_13$CCU2_COMB0.F +Info: routing 0.52 10.35 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D (68,18) -> (68,20) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.D +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.18 10.53 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F +Info: routing 0.55 11.08 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D[2] (68,20) -> (67,20) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 11.26 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z.F +Info: routing 0.12 11.38 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI[5] (67,20) -> (67,20) +Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_5.DI +Info: setup 0.00 11.38 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_5.DI +Info: 6.43 ns logic, 4.95 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': +Info: type curr total name +Info: source 0.00 0.00 Source start$tr_io.O +Info: routing 3.44 3.44 Net start$TRELLIS_IO_IN (0,23) -> (70,21) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z_LUT4_Z.B +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:10.11-10.16 +Info: logic 0.18 3.62 Source u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z_LUT4_Z.F +Info: routing 0.66 4.28 Net u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z[1] (70,21) -> (72,24) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 4.46 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.F +Info: routing 0.60 5.07 Net u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D[3] (72,24) -> (72,24) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 5.25 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z.F +Info: routing 0.47 5.71 Net u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR (72,24) -> (72,23) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.LSR +Info: setup 0.29 6.00 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.LSR +Info: 0.83 ns logic, 5.17 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_4.Q +Info: routing 4.37 4.76 Net y_bus[28]$TRELLIS_IO_OUT (66,20) -> (18,71) +Info: Sink y_bus[28]$tr_io.I +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:6.26-6.31 +Info: 0.40 ns logic, 4.37 ns routing + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 87.88 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.00 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.76 ns + +Info: Slack histogram: +Info: legend: * represents 2 endpoint(s) +Info: + represents [1,2) endpoint(s) +Info: [ 1121, 1647) |***+ +Info: [ 1647, 2173) |*+ +Info: [ 2173, 2699) | +Info: [ 2699, 3225) | +Info: [ 3225, 3751) | +Info: [ 3751, 4277) |*****+ +Info: [ 4277, 4803) |**************+ +Info: [ 4803, 5329) |***+ +Info: [ 5329, 5855) |***+ +Info: [ 5855, 6381) |+ +Info: [ 6381, 6907) | +Info: [ 6907, 7433) |***+ +Info: [ 7433, 7959) |*******+ +Info: [ 7959, 8485) |****+ +Info: [ 8485, 9011) |********+ +Info: [ 9011, 9537) |****************+ +Info: [ 9537, 10063) |******************+ +Info: [ 10063, 10589) |************************************************************ +Info: [ 10589, 11115) |*************************************+ +Info: [ 11115, 11641) |*************************+ +37 warnings, 0 errors + +Info: Program finished normally. diff --git a/synth/ecp5/p2/synth.ys b/synth/ecp5/p2/synth.ys new file mode 100644 index 0000000..e0cbe3f --- /dev/null +++ b/synth/ecp5/p2/synth.ys @@ -0,0 +1,8 @@ + +read_verilog -sv /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v + +hierarchy -top top + +synth_ecp5 -top top + +write_json /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.json diff --git a/synth/ecp5/p2/top.config b/synth/ecp5/p2/top.config new file mode 100644 index 0000000..3f56c0b --- /dev/null +++ b/synth/ecp5/p2/top.config @@ -0,0 +1,10863 @@ +.device LFE5U-45F + +.comment Part: LFE5U-45F-8CABGA381 + +.tile CIB_R10C18:CIB_EBR +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R10C49:CIB_EBR +arc: N3_V06N0303 S3_V06N0203 + +.tile CIB_R10C51:CIB_EBR +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R13C1:CIB_LR +arc: E3_H06E0303 JQ5 + +.tile CIB_R19C1:CIB_LR +arc: S1_V02S0701 H06W0203 + +.tile CIB_R19C89:CIB_LR +arc: W3_H06W0303 JF5 + +.tile CIB_R1C18:CIB +arc: E1_H02E0701 V06N0203 +arc: JA0 S1_V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C19:CIB +arc: JA0 H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C37:CIB +arc: E3_H06E0303 S3_V06N0303 + +.tile CIB_R1C38:CIB +arc: E1_H02E0501 V02N0501 +arc: JA0 H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C39:CIB +arc: JA0 H02E0501 +arc: W1_H02W0701 S3_V06N0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C41:CIB +arc: E1_H02E0701 S1_V02N0701 + +.tile CIB_R1C43:CIB +arc: E3_H06E0303 W3_H06E0303 +arc: JA0 W1_H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C48:CIB +arc: JD7 E1_H01W0100 + +.tile CIB_R1C49:CIB +arc: H01W0100 W3_H06E0303 +arc: JA0 V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C51:CIB +arc: JA0 V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C60:CIB +arc: JA0 S1_V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C62:CIB +arc: JA0 H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C63:CIB +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R1C67:CIB +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02N0001 +arc: JA0 H00L0000 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C68:CIB +arc: JA0 H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C74:CIB +arc: JA0 H02W0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C75:CIB +arc: H00L0100 S1_V02N0301 +arc: JA0 H00L0100 +arc: W1_H02W0501 S1_V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C76:CIB +arc: JA0 S1_V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R20C1:CIB_LR +arc: JA0 E1_H02W0701 +arc: JA3 V02S0701 +arc: S1_V02S0701 H06W0203 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R20C89:CIB_LR +arc: JA0 W1_H02E0501 +arc: JA3 H02E0701 +arc: S1_V02S0701 W1_H02E0701 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R21C1:CIB_LR +arc: S1_V02S0701 E3_H06W0203 + +.tile CIB_R21C89:CIB_LR +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0701 H06E0203 + +.tile CIB_R22C17:CIB_DSP +arc: E1_H01E0101 JQ7 +arc: E3_H06E0303 JQ6 +arc: N1_V02N0401 JQ4 +arc: N1_V02N0701 JQ5 + +.tile CIB_R22C18:CIB_DSP +arc: E1_H01E0001 JQ7 +arc: E3_H06E0203 JQ4 +arc: E3_H06E0303 JQ5 +arc: N1_V01N0001 JQ3 +arc: N1_V01N0101 JQ6 +arc: N1_V02N0001 JQ0 +arc: N1_V02N0201 JQ2 +arc: N1_V02N0301 JQ1 +arc: N1_V02N0501 H01E0101 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R22C19:CIB_DSP +arc: E3_H06E0003 JQ3 +arc: N1_V01N0001 JQ0 +arc: N1_V01N0101 JQ2 +arc: N1_V02N0301 JQ1 +arc: N1_V02N0601 H01E0001 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 1 + +.tile CIB_R22C1:CIB_LR_S +arc: JA0 E1_H02W0501 +arc: JA3 N1_V02S0701 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R22C20:CIB_DSP +arc: JLSR1 H02W0301 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H02W0701 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C21:CIB_DSP +arc: H00L0100 E1_H02W0301 +arc: JCE3 H00L0100 +arc: JLSR0 V00B0000 +arc: JLSR1 V00B0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0701 N1_V01S0100 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C22:CIB_DSP +arc: E1_H01E0101 JF6 +arc: H00L0100 H02W0301 +arc: H01W0100 JF7 +arc: JCE0 H00L0100 +arc: JLSR0 V00B0000 +arc: JLSR1 V00B0000 +arc: N1_V01N0001 JF5 +arc: N1_V01N0101 JF0 +arc: N1_V02N0001 JF2 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0601 JF4 +arc: S1_V02S0101 JF1 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 JF3 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 1 + +.tile CIB_R22C23:CIB_DSP +arc: E1_H01E0001 JF4 +arc: E1_H01E0101 JF7 +arc: H01W0100 JF6 +arc: JLSR1 V00B0100 +arc: N1_V01N0101 JF2 +arc: N1_V02N0201 JF0 +arc: N1_V02N0301 JF3 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 JF5 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0101 JF1 +arc: W1_H02W0301 N1_V02S0301 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R22C24:CIB_DSP +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0701 H01E0101 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C3:CIB_DSP +arc: W1_H02W0501 V06S0303 + +.tile CIB_R22C49:CIB_DSP +arc: N3_V06N0103 S3_V06N0003 + +.tile CIB_R22C51:CIB_DSP +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R22C62:CIB_DSP +arc: N1_V02N0101 H06W0103 + +.tile CIB_R22C63:CIB_DSP +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H06W0003 + +.tile CIB_R22C64:CIB_DSP +arc: E1_H01E0101 JF7 +arc: H00R0100 N1_V02S0701 +arc: H01W0100 JF6 +arc: JCE2 H00R0100 +arc: JCE3 H00R0100 +arc: JD7 V01N0001 +arc: N1_V01N0001 JF5 +arc: N1_V01N0101 JQ4 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 JQ6 +arc: N1_V02N0501 JQ7 +arc: N1_V02N0601 JF4 +arc: N1_V02N0701 JQ5 +enum: CIB.JB6MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 1 + +.tile CIB_R22C65:CIB_DSP +arc: E1_H01E0001 JF0 +arc: E1_H01E0101 JF1 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 JQ7 +arc: H01W0100 JQ0 +arc: N1_V01N0001 JF5 +arc: N1_V01N0101 JQ4 +arc: N1_V02N0001 JQ2 +arc: N1_V02N0101 JQ3 +arc: N1_V02N0201 JF2 +arc: N1_V02N0301 JF3 +arc: N1_V02N0401 JF4 +arc: N1_V02N0501 JQ5 +arc: N1_V02N0601 JF6 +arc: N1_V02N0701 JF7 +arc: V01S0100 JQ6 +arc: W1_H02W0301 H01E0101 +arc: W3_H06W0103 JQ1 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R22C66:CIB_DSP +arc: E1_H01E0101 JF0 +arc: JLSR0 H02E0301 +arc: JLSR1 H02E0301 +arc: N1_V01N0001 JQ3 +arc: N1_V01N0101 JQ1 +arc: N1_V02N0001 JF2 +arc: N1_V02N0101 JF3 +arc: N1_V02N0201 JQ2 +arc: N1_V02N0301 JF1 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: W3_H06W0003 JQ0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 1 + +.tile CIB_R22C67:CIB_DSP +arc: E1_H02E0101 N1_V02S0101 +arc: JD1 V02N0001 +arc: JLSR1 V00B0100 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0100 N1_V02S0101 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C68:CIB_DSP +arc: JCE3 H02E0101 +arc: JLSR0 V00B0100 +arc: JLSR1 V00B0100 +arc: V00B0100 V02S0101 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C69:CIB_DSP +arc: E1_H02E0501 JQ5 +arc: E3_H06E0203 JQ7 +arc: E3_H06E0303 JQ6 +arc: N1_V01N0101 JQ0 +arc: N1_V02N0101 JQ1 +arc: N1_V02N0201 JQ2 +arc: N1_V02N0301 JQ3 +arc: N1_V02N0401 JQ4 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R22C70:CIB_DSP +arc: E1_H02E0101 JQ1 +arc: E3_H06E0203 JQ7 +arc: E3_H06E0303 JQ6 +arc: N1_V01N0001 JQ2 +arc: N1_V01N0101 JQ4 +arc: N1_V02N0001 JQ0 +arc: N1_V02N0101 JQ3 +arc: N1_V02N0501 JQ7 +arc: N1_V02N0701 JQ5 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 + +.tile CIB_R22C71:CIB_DSP +arc: JD3 V02N0001 +arc: JLSR0 V00B0100 +arc: JLSR1 V00B0100 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0100 V02S0101 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 1 + +.tile CIB_R22C72:CIB_DSP +arc: E1_H02E0001 V01N0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 + +.tile CIB_R22C73:CIB_DSP +arc: H00R0000 N1_V02S0601 +arc: H00R0100 N1_V02S0701 +arc: JCE0 H00R0000 +arc: JCE1 H00R0100 +arc: JCE2 H00R0100 +arc: JCE3 N1_V02S0601 +arc: JD5 H02E0001 +arc: N1_V01N0101 JF4 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 JF6 +arc: N1_V02N0701 JF7 +arc: W1_H02W0701 JF5 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 1 + +.tile CIB_R22C74:CIB_DSP +arc: E1_H01E0001 JF4 +arc: N1_V01N0101 JF5 +arc: N1_V02N0001 JF2 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 JF3 +arc: N1_V02N0401 JF6 +arc: N1_V02N0501 JF7 +arc: W3_H06W0003 JF0 +arc: W3_H06W0103 JF1 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R22C75:CIB_DSP +arc: H01W0100 JF1 +arc: JLSR0 V00B0000 +arc: JLSR1 V00B0100 +arc: N1_V01N0101 JF2 +arc: N1_V02N0301 JF3 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W3_H06W0003 JF0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C76:CIB_DSP +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R22C87:CIB_DSP +arc: E1_H02E0701 V06S0203 + +.tile CIB_R22C89:CIB_LR_S +arc: JA0 N1_V02S0701 +arc: JA3 W1_H02E0701 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R23C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 N1_V02S0701 + +.tile CIB_R23C89:CIB_LR +arc: JA0 N1_V02S0701 +arc: S1_V02S0501 N1_V02S0401 +enum: CIB.JB0MUX 0 + +.tile CIB_R25C1:CIB_LR +arc: JA0 N1_V02S0701 +arc: JA3 N1_V02S0501 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R25C89:CIB_LR +arc: JA3 N1_V02S0501 +enum: CIB.JB3MUX 0 + +.tile CIB_R34C49:CIB_EBR +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R34C51:CIB_EBR +arc: N3_V06N0003 S3_V06N0003 + +.tile CIB_R41C1:CIB_LR +arc: JA0 E1_H02W0701 +arc: S1_V02S0701 H06W0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R41C89:CIB_LR +arc: JA0 V02N0701 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R42C1:CIB_LR +arc: S1_V02S0701 H06W0203 + +.tile CIB_R42C89:CIB_LR +arc: N1_V02N0701 W3_H06E0203 + +.tile CIB_R43C1:CIB_LR +arc: JA0 N1_V02S0701 +arc: JA3 V02S0701 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R43C89:CIB_LR +arc: JA0 N1_V02S0701 +arc: JA3 N1_V02S0501 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R46C46:CIB_DSP +arc: N1_V01N0001 JQ7 +arc: N1_V01N0101 JQ6 +arc: N1_V02N0501 JQ5 +arc: N1_V02N0601 JQ4 + +.tile CIB_R46C47:CIB_DSP +arc: E1_H01E0001 JQ1 +arc: E1_H01E0101 JQ0 +arc: N1_V01N0001 JQ4 +arc: N1_V01N0101 JQ7 +arc: N1_V02N0201 JQ2 +arc: N1_V02N0301 JQ3 +arc: N1_V02N0601 JQ6 +arc: N1_V02N0701 JQ5 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R46C48:CIB_DSP +arc: N1_V01N0001 JQ2 +arc: N1_V01N0101 JQ0 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 JQ1 +arc: N1_V02N0301 JQ3 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 H01E0101 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 1 + +.tile CIB_R46C49:CIB_DSP +arc: E1_H02E0501 N1_V02S0501 +arc: JLSR1 V00T0100 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: V00T0100 N1_V02S0501 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R46C50:CIB_DSP +arc: E1_H02E0301 V02S0301 +arc: H00R0100 H02E0501 +arc: JCE3 H00R0100 +arc: JLSR0 V00B0100 +arc: JLSR1 V00B0100 +arc: V00B0100 V02S0301 +arc: W1_H02W0501 E1_H01W0100 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R46C51:CIB_DSP +arc: E1_H01E0001 JF2 +arc: E1_H01E0101 JF0 +arc: H00R0000 H02W0401 +arc: H01W0100 JF3 +arc: JCE0 H00R0000 +arc: JLSR0 H02E0301 +arc: JLSR1 H02E0301 +arc: N1_V01N0001 JF7 +arc: N1_V01N0101 JF6 +arc: N1_V02N0301 JF1 +arc: N1_V02N0601 JF4 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0501 JF5 +arc: W1_H02W0501 E1_H01W0100 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 1 + +.tile CIB_R46C52:CIB_DSP +arc: E1_H01E0001 JF3 +arc: H01W0100 JF2 +arc: JLSR1 V00T0000 +arc: N1_V01N0101 JF6 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0501 JF7 +arc: N1_V02N0701 H01E0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0701 JF5 +arc: W3_H06W0003 JF0 +arc: W3_H06W0103 JF1 +arc: W3_H06W0203 JF4 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R46C53:CIB_DSP +arc: N1_V02N0401 H01E0001 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R5C1:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C89:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C15:CIB +arc: JA0 E1_H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C17:CIB +arc: W1_H02W0701 N1_V01S0100 + +.tile CIB_R70C18:CIB +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C69:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C70:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C71:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C72:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C73:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C74:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C75:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C76:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C77:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C78:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C79:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R70C80:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C87:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile MIB_R0C18:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C19:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C38:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C39:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C3:BANKREF0 +enum: BANK.VCCIO 3V3 + +.tile MIB_R0C40:TMID_0 +arc: G_TDCC0CLKI G_JTRQPCLKCIB1 + +.tile MIB_R0C43:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C49:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C51:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C60:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C62:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C67:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C68:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C74:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C75:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C76:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C87:BANKREF1 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C12:EBR_SPINE_UL1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C30:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C40:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R10C41:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R10C50:EBR_SPINE_UR0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C77:EBR_SPINE_UR1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C90:BANKREF2 +enum: BANK.VCCIO 3V3 + +.tile MIB_R12C0:PICL1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON + +.tile MIB_R13C0:PICL2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R18C90:PICR1_DQS3 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R19C90:PICR2 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C18:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C19:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C38:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C39:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C43:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C49:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C51:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C60:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C62:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C67:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C68:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C74:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C75:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C76:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R20C0:PICL0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R20C90:PICR0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R21C0:PICL1 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R21C90:PICR1 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R22C0:MIB_CIB_LR +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R22C90:MIB_CIB_LR_A +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R23C0:PICL0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R23C90:PICR0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R24C0:PICL1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R24C90:PICR1 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R25C0:PICL2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R25C90:PICR2 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R41C0:PICL0_DQS2 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R41C90:PICR0_DQS2 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R42C0:PICL1_DQS3 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R42C90:PICR1_DQS3 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R43C0:PICL2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R43C90:PICR2 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R58C40:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R58C41:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R58C50:EBR_SPINE_LR0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R71C15:PICB0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C18:SPICB0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C1:BANKREF6 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C3:BANKREF8 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile MIB_R71C89:BANKREF3 +enum: BANK.VCCIO 3V3 + +.tile R11C41:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R11C60:PLC2 +arc: N1_V02N0601 S3_V06N0303 + +.tile R13C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R13C19:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R13C25:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R13C31:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R13C37:PLC2 +arc: N3_V06N0203 W3_H06E0203 + +.tile R13C39:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R13C63:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R13C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R14C38:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R14C67:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R15C18:PLC2 +arc: N3_V06N0103 S1_V02N0201 + +.tile R15C75:PLC2 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 + +.tile R15C76:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R16C18:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R16C49:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R16C51:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R17C16:PLC2 +arc: E1_H02E0401 E1_H01W0000 + +.tile R17C17:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 S1_V02N0501 +arc: H01W0000 E3_H06W0103 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 E3_H06W0103 +arc: V00T0000 S1_V02N0601 +arc: A0 E1_H02W0701 +arc: C0 H02E0401 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0000000010101111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R17C18:PLC2 +arc: H00R0000 S1_V02N0601 +arc: B0 V02N0101 +arc: C0 V02N0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D5 V02N0401 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEA.K0.INIT 0000001100001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R17C19:PLC2 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 V00T0000 +arc: B0 V00B0000 +arc: B2 V02N0101 +arc: B6 V02N0701 +arc: B7 S1_V02N0701 +word: SLICED.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R17C20:PLC2 +arc: V00T0000 V02N0601 +arc: A0 V02N0501 +arc: A1 V01N0101 +arc: A4 V02N0301 +arc: A5 V00T0000 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B6 V02N0701 +arc: B7 S1_V02N0501 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEA.K0.INIT 1001100110011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R17C21:PLC2 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: A1 V01N0101 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: B0 V02N0101 +arc: B2 V01N0001 +arc: B5 S1_V02N0701 +arc: B6 V02N0701 +arc: B7 V00T0000 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEA.K0.INIT 0011001100111100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R17C22:PLC2 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0401 +arc: A1 V01N0101 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: B0 V02N0101 +arc: B2 V01N0001 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 V00T0000 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEA.K0.INIT 0011001100111100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R17C23:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: B0 V02N0301 +arc: B1 V01N0001 +arc: F1 F1_SLICE +arc: W3_H06W0103 F1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0011001100111100 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R17C29:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R17C35:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R17C41:PLC2 +arc: N3_V06N0103 W3_H06E0103 + +.tile R17C60:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R18C17:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 V02N0501 +arc: N1_V02N0001 E3_H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0701 E1_H02W0701 + +.tile R18C18:PLC2 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0601 H01E0001 +arc: B0 H02E0101 +arc: C0 E1_H01W0000 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0000000011110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R18C19:PLC2 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: V00T0000 S1_V02N0601 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: B0 V02N0301 +arc: B2 S1_V02N0301 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: E1_H01E0101 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F5 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0303 F6 +arc: V01S0000 F3 +arc: V01S0100 F6 +arc: W1_H02W0701 F7 +word: SLICED.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C20:PLC2 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0501 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: A5 V00T0000 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F5 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F7 +arc: V01S0000 F6 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C21:PLC2 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 H01E0101 +arc: S1_V02S0001 H01E0001 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: A5 V00T0000 +arc: B0 S1_V02N0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F0 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F5 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V01S0000 F3 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C22:PLC2 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0101 H01E0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: A5 V00T0000 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F0 +arc: N1_V02N0001 F2 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F5 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C23:PLC2 +arc: N1_V02N0301 H01E0101 +arc: S1_V02S0201 H01E0001 +arc: B0 S1_V02N0101 +arc: F0 F0_SLICE +arc: N1_V01N0001 F0 +arc: S1_V02S0001 F0 +arc: W3_H06W0003 F0 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C24:PLC2 +arc: S1_V02S0001 W1_H02E0001 + +.tile R18C64:PLC2 +arc: H00R0000 V02N0601 +arc: V00T0000 V02N0401 +arc: A0 S1_V02N0701 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICED.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C65:PLC2 +arc: V00T0000 V02N0401 +arc: A2 V01N0101 +arc: B0 V01N0001 +arc: B1 V02N0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 V00T0000 +arc: B7 V02N0701 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 1001100110011100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C66:PLC2 +arc: V00T0000 V02N0401 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: B0 V01N0001 +arc: B1 V02N0101 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0011001100111100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C67:PLC2 +arc: V00T0000 V02N0401 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: B0 V01N0001 +arc: B1 V02N0301 +arc: B3 V02N0101 +arc: B5 V02N0701 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0011001100111100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C68:PLC2 +arc: F0 F0_SLICE +arc: S1_V02S0201 F0 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R19C11:PLC2 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R19C16:PLC2 +arc: E1_H02E0501 E1_H01W0100 + +.tile R19C17:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 E3_H06W0303 +arc: H00R0000 H02W0401 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 +arc: B0 V02S0301 +arc: C0 E1_H02W0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0201 +arc: F0 F0_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0011000000110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R19C18:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: A0 H02W0701 +arc: C0 V02S0601 +arc: C4 S1_V02N0201 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D4 S1_V02N0601 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H00R0000 F4 +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0601 F4 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEA.K0.INIT 0000101000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R19C19:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: A0 V02S0701 +arc: B1 S1_V02N0101 +arc: B2 V02N0101 +arc: B4 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0201 +arc: D4 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0011001111001100 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C20:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0501 E1_H01W0100 +arc: V00T0000 S1_V02N0401 +arc: A0 H02W0501 +arc: A2 V02S0501 +arc: A4 V02N0301 +arc: A7 V02S0301 +arc: B1 V02S0101 +arc: B5 V02S0701 +arc: B6 H02E0101 +arc: B7 H02E0101 +arc: C0 H02W0401 +arc: C1 H00L0100 +arc: C2 V02N0601 +arc: C4 V02S0201 +arc: C5 V02N0201 +arc: C6 V01N0101 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 Q4 +arc: S1_V02S0601 Q6 +arc: V01S0000 Q7 +arc: V01S0100 Q5 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1011101110001000 +word: SLICEC.K0.INIT 1111000010101010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R19C21:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 H02E0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: A6 N1_V01S0100 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 V02N0301 +arc: B4 H02E0101 +arc: B5 V02S0501 +arc: C0 H00L0100 +arc: C1 S1_V02N0401 +arc: C4 V02S0001 +arc: C5 V00T0100 +arc: C6 V01N0101 +arc: C7 H02E0601 +arc: CE0 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02S0201 +arc: D4 W1_H02E0201 +arc: D5 V02N0401 +arc: D6 W1_H02E0201 +arc: D7 W1_H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q6 +arc: V01S0100 Q7 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R19C22:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: A0 V01N0101 +arc: A1 V02S0701 +arc: A4 V02N0301 +arc: A5 V02S0301 +arc: B2 V01N0001 +arc: B6 H02E0101 +arc: C0 N1_V01S0100 +arc: C1 E1_H02W0401 +arc: C2 V02S0601 +arc: C4 V02S0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 V02N0201 +arc: D2 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 S1_V02N0401 +arc: D6 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 Q6 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1010111110100000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1111110000001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R19C23:PLC2 +arc: H00R0000 H02E0601 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 H02E0501 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 V02N0701 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0101 +arc: C1 V02N0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V00B0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q1 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1110111000100010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R19C24:PLC2 +arc: H00L0100 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: B1 S1_V02N0101 +arc: C1 V02N0401 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D1 W1_H02E0001 +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C26:PLC2 +arc: S1_V02S0401 H06W0203 + +.tile R19C29:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R19C35:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R19C39:PLC2 +arc: N3_V06N0203 H06W0203 + +.tile R19C3:PLC2 +arc: S3_V06S0303 E3_H06W0303 + +.tile R19C41:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R19C42:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R19C47:PLC2 +arc: S3_V06S0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R19C48:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C4:PLC2 +arc: W3_H06W0203 E1_H01W0000 + +.tile R19C50:PLC2 +arc: S3_V06S0103 H06W0103 + +.tile R19C53:PLC2 +arc: S3_V06S0103 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C54:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C59:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C5:PLC2 +arc: H01W0000 E3_H06W0103 + +.tile R19C60:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R19C62:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0103 H06W0103 + +.tile R19C63:PLC2 +arc: E1_H02E0701 E1_H01W0100 +arc: S1_V02S0301 E1_H02W0301 +arc: V00T0100 H02E0301 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: LSR1 E1_H02W0301 +arc: M0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C64:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0000 S1_V02N0401 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 S1_V02N0701 +arc: A2 V00B0000 +arc: A3 H00L0100 +arc: A4 H02E0701 +arc: A5 V02N0101 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B0 W1_H02E0301 +arc: B2 H00L0000 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 V00T0000 +arc: B7 S1_V02N0501 +arc: CE1 E1_H02W0101 +arc: CE2 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E3_H06E0203 F7 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 Q6 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F5 +arc: S1_V02S0701 F5 +arc: V00B0100 Q5 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C65:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 S1_V02N0601 +arc: S1_V02S0301 E3_H06W0003 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V02N0501 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 H01W0100 +arc: B1 S1_V02N0101 +arc: B2 H00L0000 +arc: B3 S1_V02N0301 +arc: B4 V01S0000 +arc: B5 S1_V02N0701 +arc: B6 H02W0301 +arc: B7 S1_V02N0501 +arc: CE0 H02E0101 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F5 +arc: N1_V02N0701 F7 +arc: V01S0000 Q4 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C66:PLC2 +arc: H00L0000 S1_V02N0001 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 H01E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 H02E0501 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V02N0101 +arc: B1 S1_V02N0301 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: CE0 W1_H02E0101 +arc: CE1 W1_H02E0101 +arc: CE2 W1_H02E0101 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q6 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F5 +arc: N1_V02N0701 F7 +arc: V00B0100 Q5 +arc: V01S0100 F6 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C67:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0000 H02W0001 +arc: S1_V02S0401 H06E0203 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 H01E0101 +arc: A0 E1_H01E0001 +arc: A1 H00L0100 +arc: A2 S1_V02N0501 +arc: A3 S1_V02N0701 +arc: A4 S1_V02N0301 +arc: A5 Q5 +arc: A6 S1_V02N0301 +arc: A7 S1_V02N0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 S1_V02N0501 +arc: B6 V01S0000 +arc: B7 V00B0100 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0000 Q4 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F5 +arc: V00B0100 Q7 +arc: V01S0000 Q6 +arc: V01S0100 F6 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C68:PLC2 +arc: H00L0000 S1_V02N0001 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 H06E0303 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 H02E0501 +arc: A1 H00L0100 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: V01S0000 F1 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C69:PLC2 +arc: H00R0000 V02N0601 +arc: A0 H01E0001 +arc: B0 W1_H02E0301 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0100010001010101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C70:PLC2 +arc: W1_H02W0301 S1_V02N0301 + +.tile R19C71:PLC2 +arc: E1_H02E0301 E3_H06W0003 +arc: S1_V02S0301 E3_H06W0003 +arc: S3_V06S0003 E3_H06W0003 +arc: V00T0000 V02N0601 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: A6 S1_V02N0101 +arc: B0 V02N0301 +arc: B3 V01N0001 +arc: B5 V02N0701 +arc: B7 V02N0501 +word: SLICED.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R19C72:PLC2 +arc: H00R0000 V02N0401 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02N0601 +arc: A0 V01N0101 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +arc: CE0 H02W0101 +arc: CLK0 G_HPBX0000 +arc: LSR1 H02E0301 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 1001100110011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C73:PLC2 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: A0 V01N0101 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 S1_V02N0701 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0101010101011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R19C74:PLC2 +arc: H00R0000 V02N0601 +arc: S1_V02S0001 H06W0003 +arc: V00T0000 V02N0401 +arc: A0 V01N0101 +arc: A4 V00T0000 +arc: A6 H00R0000 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B5 V02N0701 +arc: B7 V02N0501 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0101010101011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R19C75:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: F0 F0_SLICE +arc: S1_V02S0201 F0 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R19C77:PLC2 +arc: S1_V02S0301 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 + +.tile R19C81:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R19C83:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R19C87:PLC2 +arc: S3_V06S0203 W3_H06E0203 + +.tile R19C9:PLC2 +arc: W3_H06W0303 E1_H02W0501 + +.tile R20C10:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R20C11:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R20C16:PLC2 +arc: W3_H06W0103 E1_H01W0100 + +.tile R20C17:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0401 +arc: V00T0000 V02S0601 +arc: A1 N1_V02S0701 +arc: B0 N1_V02S0301 +arc: B1 N1_V02S0301 +arc: C0 H00L0000 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0103 Q1 +word: SLICEA.K1.INIT 0010001000110011 +word: SLICEA.K0.INIT 0011000000110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R20C18:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0101 E1_H01W0100 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 E1_H02W0401 +arc: A0 H02W0701 +arc: C0 H02W0401 +arc: CE0 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R20C19:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 W1_H02E0401 +arc: H00L0000 V02N0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 E1_H02W0501 +arc: A5 H02E0501 +arc: A6 N1_V01S0100 +arc: A7 H02W0701 +arc: B0 H02E0301 +arc: B2 H02W0301 +arc: B3 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 H01E0101 +arc: B6 V02N0501 +arc: B7 V02N0701 +arc: CE1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: LSR0 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: V00T0000 Q2 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C20:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: H00L0000 V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0701 V01N0101 +arc: A0 V02N0501 +arc: A1 V02S0501 +arc: A2 S1_V02N0701 +arc: A3 V00T0000 +arc: A4 W1_H02E0701 +arc: A5 H02W0701 +arc: A6 E1_H02W0701 +arc: A7 V00T0100 +arc: B0 V02N0301 +arc: B1 E1_H02W0101 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B4 N1_V01S0000 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 H02W0301 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R20C21:PLC2 +arc: H00R0000 V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V01N0101 +arc: A0 H00R0000 +arc: A1 V02N0701 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: A4 E1_H02W0501 +arc: A5 V00T0100 +arc: A6 V00T0100 +arc: A7 V02S0301 +arc: B0 H02E0101 +arc: B1 V02S0101 +arc: B2 H02W0301 +arc: B3 E1_H02W0301 +arc: B4 W1_H02E0101 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 E1_H02W0301 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R20C22:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0501 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 V02N0701 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V02S0701 +arc: A3 V01N0101 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 H02W0501 +arc: A7 N1_V01S0100 +arc: B0 V02S0101 +arc: B1 V00T0000 +arc: B2 V01N0001 +arc: B3 H00R0000 +arc: B4 V02S0501 +arc: B5 N1_V01S0000 +arc: B6 H02W0101 +arc: B7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0201 F0 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F7 +arc: V01S0000 F2 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R20C23:PLC2 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 E1_H02W0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: A0 V02S0501 +arc: A1 V02N0501 +arc: B0 V02N0301 +arc: B1 V01N0001 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 F0 +arc: N1_V02N0101 F1 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R20C24:PLC2 +arc: H00L0100 V02N0301 +arc: N1_V02N0401 H01E0001 +arc: W3_H06W0003 E3_H06W0303 +arc: B0 W1_H02E0101 +arc: C0 V02N0401 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V02S0001 +arc: F0 F0_SLICE +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111110000001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R20C25:PLC2 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile R20C30:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R20C31:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R20C36:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R20C37:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R20C38:PLC2 +arc: N3_V06N0303 E3_H06W0303 + +.tile R20C3:PLC2 +arc: W1_H02W0701 E1_H02W0701 + +.tile R20C42:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R20C43:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R20C44:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R20C48:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R20C49:PLC2 +arc: S3_V06S0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile R20C4:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R20C50:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R20C52:PLC2 +arc: S3_V06S0103 H06W0103 + +.tile R20C54:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R20C55:PLC2 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 1111111111111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R20C56:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R20C5:PLC2 +arc: W1_H02W0701 E3_H06W0203 + +.tile R20C60:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R20C61:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 + +.tile R20C62:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R20C63:PLC2 +arc: C6 V02N0001 +arc: D6 V02N0401 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: V01S0000 F6 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R20C64:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0701 H06E0203 + +.tile R20C65:PLC2 +arc: E1_H02E0301 V02S0301 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 N1_V01S0100 + +.tile R20C66:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0501 N1_V01S0100 +arc: V00B0100 E1_H02W0701 +arc: B0 E1_H02W0301 +arc: C0 W1_H02E0601 +arc: CE0 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0011000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C67:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 W3_H06E0103 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +word: SLICEA.K0.INIT 0011001100000011 +word: SLICEA.K1.INIT 0011001100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C68:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0100 H02W0501 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N1_V01S0100 +arc: B0 V02S0301 +arc: B1 V02S0101 +arc: C0 N1_V01S0100 +arc: C1 V02S0601 +arc: C7 N1_V02S0201 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0100 F7 +arc: V01S0100 F7 +arc: W1_H02W0701 F7 +arc: W3_H06W0003 Q0 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEA.K1.INIT 0011000000110011 +word: SLICEA.K0.INIT 0000110000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C69:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0601 W3_H06E0303 +arc: W1_H02W0501 W3_H06E0303 +arc: B0 H02W0101 +arc: C0 H02E0401 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0000110000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C70:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V01N0101 +arc: W1_H02W0101 W3_H06E0103 + +.tile R20C71:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0000 V02N0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0301 W1_H02E0301 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 V02S0301 +arc: A2 V01N0101 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B2 H00L0000 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 V02N0701 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: E3_H06E0203 F7 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H01W0100 Q4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F5 +arc: S1_V02S0501 F5 +arc: V00B0000 Q6 +arc: V01S0000 F2 +arc: V01S0100 F6 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C72:PLC2 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0701 +arc: V00T0000 V02N0601 +arc: A0 V01N0101 +arc: A1 H02W0501 +arc: A2 E1_H01E0001 +arc: A3 H00L0100 +arc: A4 V00T0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 H01W0100 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 V01S0000 +arc: B5 V02N0701 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q1 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F5 +arc: V00B0000 Q6 +arc: V01S0000 Q4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C73:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: H00R0000 E1_H02W0601 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B1 V02N0301 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 V01S0000 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F5 +arc: V00B0100 Q5 +arc: V01S0000 Q4 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C74:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02W0601 +arc: S1_V02S0701 H06E0203 +arc: W1_H02W0501 H01E0101 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 V02N0101 +arc: A7 V02N0301 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B6 V01S0000 +arc: B7 V00B0100 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F5 +arc: V00B0000 Q4 +arc: V00B0100 Q7 +arc: V01S0000 Q6 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C75:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 V01N0001 +arc: H00R0000 V02N0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: W1_H02W0601 V02N0601 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: V01S0000 F1 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C77:PLC2 +arc: W1_H02W0301 V02N0301 + +.tile R20C80:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R20C81:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 + +.tile R20C86:PLC2 +arc: E1_H02E0701 W3_H06E0203 + +.tile R20C87:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 + +.tile R20C88:PLC2 +arc: E1_H02E0701 W1_H02E0701 + +.tile R21C14:PLC2 +arc: W3_H06W0103 E1_H01W0100 + +.tile R21C15:PLC2 +arc: H01W0100 E3_H06W0303 + +.tile R21C17:PLC2 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 N1_V02S0401 +arc: V00T0000 N1_V02S0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F0 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C18:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06W0203 +arc: A0 V02S0501 +arc: C0 H02W0601 +arc: CE0 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R21C19:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 E1_H02W0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H01E0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0601 V06S0303 +arc: A0 V02S0501 +arc: A3 N1_V02S0501 +arc: B3 S1_V02N0301 +arc: C0 H02E0601 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D3 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0301 F3 +arc: V00T0100 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1010101011101110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R21C20:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 E1_H02W0001 +arc: A2 V02S0501 +arc: A3 H02E0701 +arc: A4 V00T0000 +arc: A5 V02N0101 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B0 W1_H02E0101 +arc: B2 E1_H02W0101 +arc: B3 S1_V02N0101 +arc: B4 V02N0501 +arc: B5 V00B0100 +arc: B6 V00B0000 +arc: B7 W1_H02E0301 +arc: E1_H01E0101 F4 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: N1_V01N0101 F7 +arc: V01S0100 F2 +arc: W1_H02W0501 F5 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C21:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0501 W1_H02E0501 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 E1_H02W0001 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 E1_H02W0501 +arc: A1 H02E0501 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 E1_H02W0701 +arc: B0 H02E0301 +arc: B1 V02N0301 +arc: B2 H00L0000 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B6 H02W0301 +arc: B7 W1_H02E0301 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F0 +arc: N1_V01N0101 F5 +arc: V01S0100 F2 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F4 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C22:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 H02W0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: A0 H02E0501 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 F0 +arc: H01W0100 F1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F2 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C23:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H01E0101 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 +arc: B0 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: CE0 H00L0000 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D2 Q2 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R21C24:PLC2 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A2 H01E0001 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 H02E0301 +arc: B3 Q3 +arc: CE1 E1_H02W0101 +arc: CE2 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: V00B0000 Q4 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C25:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: V00B0000 H02W0401 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 W3_H06E0003 +arc: B0 V00T0000 +arc: B4 F1 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D4 E1_H02W0001 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F1 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H00R0000 F4 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F4 +arc: W3_H06W0103 F1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEC.K0.INIT 0011001100000000 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C26:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 H01E0001 + +.tile R21C27:PLC2 +arc: V00B0000 H02E0401 +arc: W3_H06W0203 E3_H06W0103 +arc: B0 W1_H02E0101 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0011001111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C29:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R21C31:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R21C33:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile R21C35:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R21C37:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R21C39:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: W3_H06W0003 E3_H06W0003 + +.tile R21C41:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R21C43:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R21C45:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: W3_H06W0003 E3_H06W0303 + +.tile R21C47:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R21C49:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R21C50:PLC2 +arc: S3_V06S0303 H06E0303 + +.tile R21C51:PLC2 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: W3_H06W0303 E3_H06W0303 + +.tile R21C52:PLC2 +arc: S1_V02S0001 H06E0003 + +.tile R21C53:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 W3_H06E0303 + +.tile R21C57:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R21C59:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R21C60:PLC2 +arc: S1_V02S0301 H06E0003 + +.tile R21C61:PLC2 +arc: E1_H02E0601 S1_V02N0601 + +.tile R21C62:PLC2 +arc: E1_H02E0101 V02N0101 +arc: N1_V02N0301 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 N1_V02S0201 +arc: B0 V00T0000 +arc: C0 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C63:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: W3_H06W0303 E3_H06W0203 +arc: B2 N1_V02S0301 +arc: C2 W1_H02E0601 +arc: D2 H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: S1_V02S0201 F2 +word: SLICEB.K0.INIT 1100110011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R21C64:PLC2 +arc: E3_H06E0003 H01E0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0301 H01E0101 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 V02N0401 +arc: A2 V01N0101 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 E1_H02W0701 +arc: B0 H02W0301 +arc: B2 H00R0000 +arc: B3 V01N0001 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 W1_H02E0101 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C65:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 V01N0101 +arc: A3 V02N0501 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 E1_H02W0501 +arc: A7 H02W0501 +arc: B0 V00B0000 +arc: B1 V02N0301 +arc: B2 H00R0000 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B5 V02N0701 +arc: B6 W1_H02E0301 +arc: B7 H02W0301 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F5 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C66:PLC2 +arc: H00L0000 V02N0201 +arc: H00L0100 V02N0101 +arc: V00B0000 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 H00L0000 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: B0 V00B0000 +arc: B1 V01N0001 +arc: B2 V01N0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: N1_V01N0101 F0 +arc: N1_V02N0001 F2 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 F1 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C67:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 + +.tile R21C68:PLC2 +arc: N1_V02N0001 W3_H06E0003 +arc: S1_V02S0101 H06E0103 + +.tile R21C69:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V01N0101 +arc: W3_H06W0203 E3_H06W0203 + +.tile R21C70:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: H00L0100 H02W0301 +arc: N1_V02N0301 W3_H06E0003 +arc: B3 S1_V02N0301 +arc: C3 H00L0100 +arc: D3 H02E0001 +arc: E1_H01E0001 F3 +arc: F3 F3_SLICE +arc: N1_V01N0101 F3 +arc: S3_V06S0003 F3 +word: SLICEB.K1.INIT 1111000011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R21C71:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0003 H01E0001 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 H01E0001 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 E1_H01E0001 +arc: A2 W1_H02E0701 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 E1_H02W0701 +arc: A6 V02N0301 +arc: A7 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 W1_H02E0301 +arc: B6 V00B0000 +arc: B7 V02N0501 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F2 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C72:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0201 H01E0001 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 E1_H02W0001 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: A2 H02W0501 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 V02N0301 +arc: A7 W1_H02E0701 +arc: B0 V00T0000 +arc: B1 E1_H02W0301 +arc: B2 H00L0000 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0301 +arc: B7 E1_H02W0101 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F5 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C73:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0501 +arc: A1 H02E0501 +arc: A2 V00T0000 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0301 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 F1 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C74:PLC2 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V01N0101 +arc: A0 V02S0701 +arc: C0 H02W0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0000101000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C75:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 F5 +arc: A1 F5 +arc: A2 F5 +arc: A6 F5 +arc: A7 F5 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0601 +arc: C2 N1_V01S0100 +arc: C5 N1_V02S0201 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 V02S0001 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F5 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q6 +arc: W1_H02W0501 F5 +arc: W3_H06W0203 Q7 +word: SLICEA.K1.INIT 0000000011110101 +word: SLICED.K1.INIT 0000111100000101 +word: SLICEA.K0.INIT 0000000011110101 +word: SLICEB.K0.INIT 0000111100000101 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0000111100000101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C76:PLC2 +arc: H00R0000 S1_V02N0401 +arc: B0 H02E0101 +arc: C0 H02E0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: F0 F0_SLICE +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 0000110000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C77:PLC2 +arc: N1_V02N0301 W3_H06E0003 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 W3_H06E0303 + +.tile R21C7:PLC2 +arc: W3_H06W0203 E1_H01W0000 + +.tile R21C80:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R21C81:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R21C86:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R21C87:PLC2 +arc: E1_H02E0401 W3_H06E0203 + +.tile R21C8:PLC2 +arc: H01W0000 E3_H06W0103 + +.tile R23C11:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R23C13:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R23C17:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R23C19:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0301 W3_H06E0003 + +.tile R23C20:PLC2 +arc: N1_V02N0101 E1_H02W0101 + +.tile R23C22:PLC2 +arc: W1_H02W0101 V02S0101 + +.tile R23C23:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R23C25:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 + +.tile R23C26:PLC2 +arc: N1_V02N0601 H01E0001 + +.tile R23C29:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R23C31:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R23C35:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R23C37:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R23C41:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R23C43:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R23C47:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R23C49:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R23C4:PLC2 +arc: W3_H06W0303 E1_H01W0100 + +.tile R23C52:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: S1_V02S0501 H06E0303 + +.tile R23C53:PLC2 +arc: V00T0100 N1_V02S0701 +arc: A0 H00L0100 +arc: B0 H02W0101 +arc: B2 S1_V02N0101 +arc: C0 H02W0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V00T0100 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: LSR0 V00T0000 +arc: M1 H02E0001 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 F2 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 1100110011111111 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R23C54:PLC2 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0601 E3_H06W0303 + +.tile R23C55:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R23C58:PLC2 +arc: E1_H02E0601 V02N0601 + +.tile R23C5:PLC2 +arc: H01W0100 E3_H06W0303 + +.tile R23C60:PLC2 +arc: H00L0000 V02N0001 +arc: W3_H06W0303 E3_H06W0203 +arc: A4 N1_V02S0301 +arc: B4 H00L0000 +arc: C4 W1_H02E0601 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: M2 E1_H02W0601 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N3_V06N0203 F4 +arc: V00B0100 F5 +arc: W3_H06W0103 Q2 +word: SLICEC.K1.INIT 1111111100001111 +word: SLICEC.K0.INIT 1111111111111110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R23C61:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 + +.tile R23C62:PLC2 +arc: N1_V02N0201 E1_H01W0000 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H01W0000 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 N1_V02S0301 +arc: B2 V01N0001 +arc: B3 Q3 +arc: CE1 V02N0201 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: V00B0000 Q4 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C63:PLC2 +arc: E1_H02E0201 V01N0001 +arc: V00B0000 N1_V02S0201 +arc: W1_H02W0201 N1_V02S0201 +arc: A4 H02E0501 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B4 H00L0000 +arc: B7 H01E0101 +arc: C4 E1_H01E0101 +arc: C7 N1_V02S0201 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D4 V01N0001 +arc: D7 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 F1 +arc: V00T0000 Q0 +arc: V01S0100 F1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 0000111100001101 +word: SLICEC.K0.INIT 1111000011100000 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R23C64:PLC2 +arc: H00R0000 W1_H02E0601 +arc: V00B0000 H02E0401 +arc: A0 H00R0000 +arc: B0 N1_V02S0301 +arc: C0 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 1100111111011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C65:PLC2 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0501 N1_V01S0100 + +.tile R23C66:PLC2 +arc: H00L0000 V02N0201 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D5 E1_H02W0001 +arc: F5 F5_SLICE +arc: LSR1 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: V00B0100 F5 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 1111000011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C67:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: N1_V02N0001 H06E0003 + +.tile R23C68:PLC2 +arc: W1_H02W0001 E1_H01W0000 +arc: W3_H06W0003 E1_H01W0000 + +.tile R23C69:PLC2 +arc: B0 W1_H02E0301 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C70:PLC2 +arc: N1_V02N0301 H06E0003 + +.tile R23C71:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 V01N0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0301 S1_V02N0301 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R23C72:PLC2 +arc: H00R0100 H02E0501 +arc: V00T0000 V02N0601 +arc: A0 F7 +arc: B0 V02N0301 +arc: C0 H00R0100 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0701 F7 +arc: V01S0000 F7 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111111100100111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R23C73:PLC2 +arc: E3_H06E0203 H01E0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0601 H01E0001 + +.tile R23C75:PLC2 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H06E0303 + +.tile R23C76:PLC2 +arc: N1_V02N0401 H06E0203 + +.tile R23C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R24C58:PLC2 +arc: N1_V02N0601 S1_V02N0301 + +.tile R24C60:PLC2 +arc: N1_V02N0001 E1_H02W0001 + +.tile R24C62:PLC2 +arc: E1_H02E0001 V06S0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: W1_H02W0001 V06S0003 +arc: CE0 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R24C63:PLC2 +arc: C3 N1_V01S0100 +arc: D3 H02E0001 +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F3 +arc: N1_V02N0101 F3 +arc: V01S0000 F3 +arc: W1_H02W0101 F3 +word: SLICEB.K1.INIT 0000111100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R24C64:PLC2 +arc: W1_H02W0501 V06S0303 + +.tile R24C66:PLC2 +arc: N1_V02N0201 E3_H06W0103 + +.tile R24C69:PLC2 +arc: N1_V02N0201 H06W0103 + +.tile R24C70:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V06S0003 + +.tile R24C71:PLC2 +arc: H00R0000 H02W0601 +arc: V00B0000 V02S0001 +arc: A2 V00B0000 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B0 V02S0101 +arc: B3 Q3 +arc: B4 V01S0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 Q7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q6 +arc: V01S0000 Q4 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C72:PLC2 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 H01E0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0601 N1_V01S0000 +arc: A0 H00L0000 +arc: A4 H02E0501 +arc: A6 H00R0000 +arc: B4 N1_V01S0000 +arc: B6 N1_V01S0000 +arc: C4 E1_H01E0101 +arc: C6 H01E0001 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D4 W1_H02E0001 +arc: D6 F0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00R0000 F4 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F1 +arc: N1_V02N0601 F6 +arc: W3_H06W0103 F1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEC.K0.INIT 0000000011111110 +word: SLICED.K0.INIT 1010101010100010 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ + +.tile R25C47:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R25C50:PLC2 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0103 + +.tile R25C52:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: S1_V02S0501 N1_V02S0501 +arc: W1_H02W0501 N1_V02S0501 + +.tile R25C53:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 N3_V06S0103 +arc: B5 V01S0000 +arc: C5 V02N0001 +arc: CLK0 G_HPBX0000 +arc: F5 F5_SLICE +arc: LSR0 V00B0100 +arc: M0 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: V00B0100 F5 +word: SLICEC.K1.INIT 1100111111001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C62:PLC2 +arc: N1_V02N0201 N3_V06S0103 + +.tile R25C63:PLC2 +arc: N1_V02N0201 N1_V01S0000 + +.tile R25C71:PLC2 +arc: N1_V02N0301 N3_V06S0003 + +.tile R26C18:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R26C48:PLC2 +arc: S3_V06S0303 H06W0303 + +.tile R26C49:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R26C51:PLC2 +arc: W3_H06W0303 E1_H01W0100 + +.tile R26C52:PLC2 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 H02W0401 +arc: A0 V02S0501 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0000111110101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C53:PLC2 +arc: N1_V02N0001 H02E0001 +arc: W1_H02W0401 N1_V01S0000 + +.tile R26C58:PLC2 +arc: N1_V02N0301 W3_H06E0003 + +.tile R27C17:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R27C50:PLC2 +arc: S3_V06S0303 N3_V06S0303 +arc: B4 N1_V02S0501 +arc: C4 N1_V02S0201 +arc: D4 E1_H02W0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0401 F4 +arc: F4 F4_SLICE +arc: S3_V06S0203 F4 +word: SLICEC.K0.INIT 1111000011111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R27C51:PLC2 +arc: S1_V02S0401 H01E0001 + +.tile R27C52:PLC2 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N1_V01S0000 +arc: W1_H02W0001 N1_V01S0000 + +.tile R27C53:PLC2 +arc: S3_V06S0003 N3_V06S0303 + +.tile R28C49:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R28C51:PLC2 +arc: H00R0000 H02W0401 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0000 V02S0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R28C52:PLC2 +arc: A4 V02N0101 +arc: D4 V02S0601 +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: S1_V02S0601 F4 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 0101010100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R29C51:PLC2 +arc: H00R0000 V02S0601 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: A0 V02N0501 +arc: A2 V00B0000 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B3 Q3 +arc: B4 V01S0000 +arc: CE1 H00R0000 +arc: CE2 V02S0601 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q6 +arc: V01S0000 Q4 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C52:PLC2 +arc: H00R0000 V02S0601 +arc: V00T0000 N1_V02S0401 +arc: A0 H00L0000 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F1 +arc: S3_V06S0103 F1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1010101010100000 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C38:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R2C49:PLC2 +arc: N1_V02N0701 S1_V02N0601 + +.tile R2C51:PLC2 +arc: N1_V02N0501 S1_V02N0501 + +.tile R2C67:PLC2 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0701 S3_V06N0203 + +.tile R30C50:PLC2 +arc: E1_H02E0501 V06S0303 + +.tile R30C51:PLC2 +arc: N1_V02N0501 H02E0501 + +.tile R31C47:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R31C50:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R31C53:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R32C18:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R32C48:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R32C49:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R32C52:PLC2 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 + +.tile R33C17:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R33C50:PLC2 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 + +.tile R33C53:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R35C52:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R37C47:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R37C50:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R37C53:PLC2 +arc: S1_V02S0701 N3_V06S0203 + +.tile R38C18:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R38C48:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R38C49:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R38C52:PLC2 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 + +.tile R39C17:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R39C48:PLC2 +arc: S1_V02S0601 S3_V06N0303 + +.tile R39C49:PLC2 +arc: S1_V02S0601 S3_V06N0303 + +.tile R39C50:PLC2 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 + +.tile R39C53:PLC2 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0701 N1_V02S0701 + +.tile R3C18:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R3C41:PLC2 +arc: N1_V02N0701 S1_V02N0701 + +.tile R3C60:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R3C75:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 + +.tile R3C76:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R40C12:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R40C18:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R40C24:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R40C30:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R40C36:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R40C3:PLC2 +arc: S1_V02S0701 H06W0203 + +.tile R40C42:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R40C47:PLC2 +arc: E1_H02E0501 V06S0303 + +.tile R40C48:PLC2 +arc: E1_H02E0401 V02N0401 +arc: S1_V02S0101 H06W0103 +arc: B0 S1_V02N0101 +arc: C0 V02N0401 +arc: CE0 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0000000011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C49:PLC2 +arc: B0 S1_V02N0301 +arc: C0 H02E0401 +arc: CE0 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: F0 F0_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 0000000011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C50:PLC2 +arc: E1_H02E0501 V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 V06S0303 + +.tile R40C51:PLC2 +arc: W3_H06W0103 E1_H01W0100 +arc: B0 S1_V02N0301 +arc: C0 S1_V02N0601 +arc: CE0 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: F0 F0_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 0011000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R40C52:PLC2 +arc: C1 V02N0401 +arc: D1 N1_V02S0201 +arc: F1 F1_SLICE +arc: H01W0100 F1 +arc: S1_V02S0101 F1 +arc: W1_H02W0101 F1 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R40C6:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R41C11:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R41C17:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R41C23:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R41C29:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R41C35:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R41C3:PLC2 +arc: W1_H02W0701 V02S0701 + +.tile R41C41:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R41C46:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: S1_V02S0601 E3_H06W0303 + +.tile R41C47:PLC2 +arc: V00T0100 S1_V02N0501 +arc: A0 H02W0701 +arc: C0 H02E0601 +arc: CE0 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0000000010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C48:PLC2 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0701 N1_V02S0601 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0701 V01N0101 +arc: A0 H02W0501 +arc: A2 V01N0101 +arc: B3 V01N0001 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B6 V00T0000 +arc: B7 V02N0701 +word: SLICED.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R41C49:PLC2 +arc: H00R0000 V02N0601 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0401 +arc: W1_H02W0501 V06S0303 +arc: A2 V00B0000 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: A6 H00R0000 +arc: B0 S1_V02N0101 +arc: B1 V01N0001 +arc: B5 V02N0701 +arc: B7 V02N0501 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 1001100110011100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R41C4:PLC2 +arc: W3_H06W0203 E1_H01W0000 + +.tile R41C50:PLC2 +arc: H00L0000 V02N0201 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A2 V00B0000 +arc: B3 V01N0001 +arc: B4 S1_V02N0701 +arc: B5 V02N0501 +arc: B6 V00T0000 +arc: B7 V02N0701 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEA.K0.INIT 0101010101011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R41C51:PLC2 +arc: H00L0000 V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H00L0000 +arc: A2 V00B0000 +arc: A3 V01N0101 +arc: A4 V00T0000 +arc: B1 V01N0001 +arc: B5 V02N0701 +arc: B6 S1_V02N0701 +arc: B7 V02N0501 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0101010101011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R41C52:PLC2 +arc: E1_H02E0101 V02S0101 +arc: N1_V02N0401 N3_V06S0203 +arc: C6 V02N0201 +arc: D6 F0 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: V01S0000 F6 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000001111 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R41C53:PLC2 +arc: H00L0000 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0701 +arc: V00T0100 N1_V02S0701 +arc: B0 V02N0101 +arc: C0 H02E0601 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: LSR0 V00T0100 +arc: M1 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0011001100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R41C59:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile R41C5:PLC2 +arc: H01W0000 E3_H06W0103 + +.tile R41C65:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 + +.tile R41C71:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 + +.tile R41C77:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R41C83:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R42C11:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R42C17:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R42C23:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R42C29:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R42C35:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R42C41:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R42C46:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 V02S0601 + +.tile R42C47:PLC2 +arc: N1_V02N0201 H02E0201 +arc: V00T0100 V02N0501 +arc: B0 E1_H01W0100 +arc: C0 H02E0601 +arc: CE0 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0000000011001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C48:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 W1_H02E0201 +arc: W1_H02W0101 N1_V02S0101 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 E1_H02W0301 +arc: B2 V02N0301 +arc: B3 Q3 +arc: B4 H00L0000 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: CE1 H00R0100 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F4 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F6 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F2 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C49:PLC2 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H01E0101 +arc: W1_H02W0101 V06N0103 +arc: A0 H02W0701 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0501 +arc: A3 H00L0100 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 S1_V02N0301 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 V02N0701 +arc: B5 V02S0701 +arc: B6 V01S0000 +arc: B7 V02N0501 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0100 F0 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F5 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0000 Q6 +arc: V01S0100 F0 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C4:PLC2 +arc: W3_H06W0203 E1_H01W0000 + +.tile R42C50:PLC2 +arc: E1_H02E0501 V06S0303 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02N0301 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 V06N0203 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 H02W0501 +arc: A5 Q5 +arc: A6 H02W0501 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 V01S0000 +arc: B7 V00B0100 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 F2 +arc: N1_V02N0201 F0 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: V00T0000 Q0 +arc: V01S0000 Q6 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C51:PLC2 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: W1_H02W0501 V02N0501 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q2 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F0 +arc: N1_V02N0201 F2 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F5 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0100 F6 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C52:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 N1_V02S0101 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 F1 +arc: LSR1 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 F0 +arc: V00T0000 Q0 +arc: W3_H06W0103 F1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C53:PLC2 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: V00B0000 V02S0201 +arc: B0 H02E0301 +arc: C0 H02W0401 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R42C54:PLC2 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 + +.tile R42C59:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R42C5:PLC2 +arc: H01W0000 E3_H06W0103 + +.tile R42C65:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R42C71:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R42C77:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R42C83:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R43C47:PLC2 +arc: N1_V02N0501 N3_V06S0303 + +.tile R43C48:PLC2 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 S1_V02N0701 + +.tile R43C49:PLC2 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 + +.tile R43C50:PLC2 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 N1_V01S0100 + +.tile R43C51:PLC2 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 N1_V01S0100 + +.tile R44C18:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R44C48:PLC2 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 V01N0101 + +.tile R44C49:PLC2 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0501 N3_V06S0303 + +.tile R44C50:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 V01N0101 +arc: W1_H02W0501 V02N0501 + +.tile R44C51:PLC2 +arc: N1_V02N0201 H02W0201 + +.tile R44C52:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: S1_V02S0401 N3_V06S0203 +arc: W1_H02W0201 N3_V06S0103 + +.tile R45C17:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R45C46:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V01N0101 + +.tile R45C47:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 + +.tile R45C48:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: H00R0000 W1_H02E0601 +arc: V00B0000 V02N0001 +arc: V00T0000 W1_H02E0201 +arc: A2 E1_H02W0701 +arc: A3 W1_H02E0501 +arc: A4 W1_H02E0701 +arc: A5 V00T0000 +arc: A6 H02W0701 +arc: A7 E1_H02W0501 +arc: B0 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 H02W0301 +arc: B4 E1_H02W0101 +arc: B5 V02N0501 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: E1_H01E0101 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F2 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F5 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R45C49:PLC2 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 E1_H02W0401 +arc: N3_V06N0103 H01E0101 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 H00L0000 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 W1_H02E0701 +arc: A4 V00B0000 +arc: A5 E1_H02W0501 +arc: A6 H02E0501 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 W1_H02E0301 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 H02E0101 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: N3_V06N0303 F5 +arc: V01S0000 F1 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R45C50:PLC2 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0301 N3_V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 H00R0000 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: B0 E1_H02W0101 +arc: B1 W1_H02E0301 +arc: B2 W1_H02E0301 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: N1_V01N0101 F0 +arc: N1_V02N0301 F1 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R45C51:PLC2 +arc: N1_V02N0501 H01E0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 + +.tile R45C52:PLC2 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 V02N0701 + +.tile R45C53:PLC2 +arc: W1_H02W0401 V02N0401 + +.tile R47C50:PLC2 +arc: N1_V02N0501 H02W0501 + +.tile R47C51:PLC2 +arc: W1_H02W0501 V02S0501 + +.tile R4C18:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R4C49:PLC2 +arc: N1_V02N0601 S3_V06N0303 + +.tile R4C51:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R50C18:PLC2 +arc: S3_V06S0003 N3_V06S0303 + +.tile R51C17:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R56C18:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R57C17:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R5C41:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R62C18:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R63C17:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R68C18:PLC2 +arc: S1_V02S0701 N3_V06S0203 + +.tile R69C17:PLC2 +arc: V01S0100 N3_V06S0303 + +.tile R7C37:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R7C39:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R7C63:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R8C38:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R8C67:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 + +.tile R9C18:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R9C60:PLC2 +arc: N3_V06N0303 S1_V02N0601 + +.tile R9C75:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 + +.tile R9C76:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile TAP_R17C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R18C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R19C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R20C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R20C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R21C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R21C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R23C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R24C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R25C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R28C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R29C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R40C51:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R41C51:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R42C51:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile_group MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 MIB_R22C65:MIB_DSP5 MIB_R22C65:MIB2_DSP5 MIB_R22C66:MIB_DSP6 MIB_R22C66:MIB2_DSP6 MIB_R22C67:MIB_DSP7 MIB_R22C67:MIB2_DSP7 MIB_R22C68:MIB_DSP8 MIB_R22C68:MIB2_DSP8 +enum: MULT18_4.REG_INPUTA_CLK NONE +enum: MULT18_4.REG_INPUTA_CE CE0 +enum: MULT18_4.REG_INPUTA_RST RST0 +enum: MULT18_4.REG_INPUTB_CLK NONE +enum: MULT18_4.REG_INPUTB_CE CE0 +enum: MULT18_4.REG_INPUTB_RST RST0 +enum: MULT18_4.REG_INPUTC_CLK NONE +enum: MULT18_4.REG_PIPELINE_CLK NONE +enum: MULT18_4.REG_PIPELINE_CE CE0 +enum: MULT18_4.REG_PIPELINE_RST RST0 +enum: MULT18_4.REG_OUTPUT_CLK NONE +enum: MULT18_4.REG_OUTPUT_RST RST0 +enum: MULT18_4.CLK0_DIV ENABLED +enum: MULT18_4.CLK1_DIV ENABLED +enum: MULT18_4.CLK2_DIV ENABLED +enum: MULT18_4.CLK3_DIV ENABLED +enum: MULT18_4.GSR ENABLED +enum: MULT18_4.SOURCEB_MODE B_SHIFT +enum: MULT18_4.RESETMODE SYNC +enum: MULT18_4.MODE MULT18X18D +enum: MULT18_4.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_4.CLK0MUX CLK0 +enum: MULT18_4.CLK1MUX CLK1 +enum: MULT18_4.CLK2MUX CLK2 +enum: MULT18_4.CLK3MUX CLK3 +enum: MULT18_4.CE0MUX CE0 +enum: MULT18_4.CE1MUX CE1 +enum: MULT18_4.CE2MUX CE2 +enum: MULT18_4.CE3MUX CE3 +enum: MULT18_4.RST0MUX RST0 +enum: MULT18_4.RST1MUX RST1 +enum: MULT18_4.RST2MUX RST2 +enum: MULT18_4.RST3MUX RST3 + +.tile_group MIB_R22C69:MIB_DSP0 MIB_R22C69:MIB2_DSP0 MIB_R22C70:MIB_DSP1 MIB_R22C70:MIB2_DSP1 MIB_R22C71:MIB_DSP2 MIB_R22C71:MIB2_DSP2 MIB_R22C72:MIB_DSP3 MIB_R22C72:MIB2_DSP3 MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 +enum: MULT18_1.REG_INPUTA_CLK NONE +enum: MULT18_1.REG_INPUTA_CE CE0 +enum: MULT18_1.REG_INPUTA_RST RST0 +enum: MULT18_1.REG_INPUTB_CLK NONE +enum: MULT18_1.REG_INPUTB_CE CE0 +enum: MULT18_1.REG_INPUTB_RST RST0 +enum: MULT18_1.REG_INPUTC_CLK NONE +enum: MULT18_1.REG_PIPELINE_CLK NONE +enum: MULT18_1.REG_PIPELINE_CE CE0 +enum: MULT18_1.REG_PIPELINE_RST RST0 +enum: MULT18_1.REG_OUTPUT_CLK NONE +enum: MULT18_1.CLK0_DIV ENABLED +enum: MULT18_1.CLK1_DIV ENABLED +enum: MULT18_1.CLK2_DIV ENABLED +enum: MULT18_1.CLK3_DIV ENABLED +enum: MULT18_1.GSR ENABLED +enum: MULT18_1.SOURCEB_MODE B_SHIFT +enum: MULT18_1.RESETMODE SYNC +enum: MULT18_1.MODE MULT18X18D +enum: MULT18_1.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_1.CLK0MUX CLK0 +enum: MULT18_1.CLK1MUX CLK1 +enum: MULT18_1.CLK2MUX CLK2 +enum: MULT18_1.CLK3MUX CLK3 +enum: MULT18_1.CE0MUX CE0 +enum: MULT18_1.CE1MUX CE1 +enum: MULT18_1.CE2MUX CE2 +enum: MULT18_1.CE3MUX CE3 +enum: MULT18_1.RST0MUX RST0 +enum: MULT18_1.RST1MUX RST1 +enum: MULT18_1.RST2MUX RST2 +enum: MULT18_1.RST3MUX RST3 + +.tile_group MIB_R46C51:MIB_DSP0 MIB_R46C51:MIB2_DSP0 MIB_R46C52:MIB_DSP1 MIB_R46C52:MIB2_DSP1 MIB_R46C53:MIB_DSP2 MIB_R46C53:MIB2_DSP2 MIB_R46C54:MIB_DSP3 MIB_R46C54:MIB2_DSP3 MIB_R46C55:MIB_DSP4 MIB_R46C55:MIB2_DSP4 +enum: MULT18_0.REG_INPUTA_CLK NONE +enum: MULT18_0.REG_INPUTA_CE CE0 +enum: MULT18_0.REG_INPUTA_RST RST0 +enum: MULT18_0.REG_INPUTB_CLK NONE +enum: MULT18_0.REG_INPUTB_CE CE0 +enum: MULT18_0.REG_INPUTB_RST RST0 +enum: MULT18_0.REG_INPUTC_CLK NONE +enum: MULT18_0.REG_PIPELINE_CLK NONE +enum: MULT18_0.REG_PIPELINE_CE CE0 +enum: MULT18_0.REG_PIPELINE_RST RST0 +enum: MULT18_0.REG_OUTPUT_CLK NONE +enum: MULT18_0.REG_OUTPUT_RST RST0 +enum: MULT18_0.CLK0_DIV ENABLED +enum: MULT18_0.CLK1_DIV ENABLED +enum: MULT18_0.CLK2_DIV ENABLED +enum: MULT18_0.CLK3_DIV ENABLED +enum: MULT18_0.GSR ENABLED +enum: MULT18_0.SOURCEB_MODE B_SHIFT +enum: MULT18_0.RESETMODE SYNC +enum: MULT18_0.MODE MULT18X18D +enum: MULT18_0.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_0.CLK0MUX CLK0 +enum: MULT18_0.CLK1MUX CLK1 +enum: MULT18_0.CLK2MUX CLK2 +enum: MULT18_0.CLK3MUX CLK3 +enum: MULT18_0.CE0MUX CE0 +enum: MULT18_0.CE1MUX CE1 +enum: MULT18_0.CE2MUX CE2 +enum: MULT18_0.CE3MUX CE3 +enum: MULT18_0.RST0MUX RST0 +enum: MULT18_0.RST1MUX RST1 +enum: MULT18_0.RST2MUX RST2 +enum: MULT18_0.RST3MUX RST3 + +.tile_group MIB_R22C17:MIB_DSP4 MIB_R22C17:MIB2_DSP4 MIB_R22C18:MIB_DSP5 MIB_R22C18:MIB2_DSP5 MIB_R22C19:MIB_DSP6 MIB_R22C19:MIB2_DSP6 MIB_R22C20:MIB_DSP7 MIB_R22C20:MIB2_DSP7 MIB_R22C21:MIB_DSP8 MIB_R22C21:MIB2_DSP8 +enum: MULT18_5.REG_INPUTA_CLK NONE +enum: MULT18_5.REG_INPUTA_CE CE0 +enum: MULT18_5.REG_INPUTA_RST RST0 +enum: MULT18_5.REG_INPUTB_CLK NONE +enum: MULT18_5.REG_INPUTB_CE CE0 +enum: MULT18_5.REG_INPUTB_RST RST0 +enum: MULT18_5.REG_INPUTC_CLK NONE +enum: MULT18_5.REG_PIPELINE_CLK NONE +enum: MULT18_5.REG_PIPELINE_CE CE0 +enum: MULT18_5.REG_PIPELINE_RST RST0 +enum: MULT18_5.REG_OUTPUT_CLK NONE +enum: MULT18_5.CLK0_DIV ENABLED +enum: MULT18_5.CLK1_DIV ENABLED +enum: MULT18_5.CLK2_DIV ENABLED +enum: MULT18_5.CLK3_DIV ENABLED +enum: MULT18_5.GSR ENABLED +enum: MULT18_5.SOURCEB_MODE B_SHIFT +enum: MULT18_5.RESETMODE SYNC +enum: MULT18_5.MODE MULT18X18D +enum: MULT18_5.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_5.CLK0MUX CLK0 +enum: MULT18_5.CLK1MUX CLK1 +enum: MULT18_5.CLK2MUX CLK2 +enum: MULT18_5.CLK3MUX CLK3 +enum: MULT18_5.CE0MUX CE0 +enum: MULT18_5.CE1MUX CE1 +enum: MULT18_5.CE2MUX CE2 +enum: MULT18_5.CE3MUX CE3 +enum: MULT18_5.RST0MUX RST0 +enum: MULT18_5.RST1MUX RST1 +enum: MULT18_5.RST2MUX RST2 +enum: MULT18_5.RST3MUX RST3 + +.tile_group MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 MIB_R22C65:MIB_DSP5 MIB_R22C65:MIB2_DSP5 MIB_R22C66:MIB_DSP6 MIB_R22C66:MIB2_DSP6 MIB_R22C67:MIB_DSP7 MIB_R22C67:MIB2_DSP7 MIB_R22C68:MIB_DSP8 MIB_R22C68:MIB2_DSP8 +enum: MULT18_5.REG_INPUTA_CLK NONE +enum: MULT18_5.REG_INPUTA_CE CE0 +enum: MULT18_5.REG_INPUTA_RST RST0 +enum: MULT18_5.REG_INPUTB_CLK NONE +enum: MULT18_5.REG_INPUTB_CE CE0 +enum: MULT18_5.REG_INPUTB_RST RST0 +enum: MULT18_5.REG_INPUTC_CLK NONE +enum: MULT18_5.REG_PIPELINE_CLK NONE +enum: MULT18_5.REG_PIPELINE_CE CE0 +enum: MULT18_5.REG_PIPELINE_RST RST0 +enum: MULT18_5.REG_OUTPUT_CLK NONE +enum: MULT18_5.CLK0_DIV ENABLED +enum: MULT18_5.CLK1_DIV ENABLED +enum: MULT18_5.CLK2_DIV ENABLED +enum: MULT18_5.CLK3_DIV ENABLED +enum: MULT18_5.GSR ENABLED +enum: MULT18_5.SOURCEB_MODE B_SHIFT +enum: MULT18_5.RESETMODE SYNC +enum: MULT18_5.MODE MULT18X18D +enum: MULT18_5.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_5.CLK0MUX CLK0 +enum: MULT18_5.CLK1MUX CLK1 +enum: MULT18_5.CLK2MUX CLK2 +enum: MULT18_5.CLK3MUX CLK3 +enum: MULT18_5.CE0MUX CE0 +enum: MULT18_5.CE1MUX CE1 +enum: MULT18_5.CE2MUX CE2 +enum: MULT18_5.CE3MUX CE3 +enum: MULT18_5.RST0MUX RST0 +enum: MULT18_5.RST1MUX RST1 +enum: MULT18_5.RST2MUX RST2 +enum: MULT18_5.RST3MUX RST3 + +.tile_group MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 MIB_R22C74:MIB_DSP5 MIB_R22C74:MIB2_DSP5 MIB_R22C75:MIB_DSP6 MIB_R22C75:MIB2_DSP6 MIB_R22C76:MIB_DSP7 MIB_R22C76:MIB2_DSP7 MIB_R22C77:MIB_DSP8 MIB_R22C77:MIB2_DSP8 +enum: MULT18_4.REG_INPUTA_CLK NONE +enum: MULT18_4.REG_INPUTA_CE CE0 +enum: MULT18_4.REG_INPUTA_RST RST0 +enum: MULT18_4.REG_INPUTB_CLK NONE +enum: MULT18_4.REG_INPUTB_CE CE0 +enum: MULT18_4.REG_INPUTB_RST RST0 +enum: MULT18_4.REG_INPUTC_CLK NONE +enum: MULT18_4.REG_PIPELINE_CLK NONE +enum: MULT18_4.REG_PIPELINE_CE CE0 +enum: MULT18_4.REG_PIPELINE_RST RST0 +enum: MULT18_4.REG_OUTPUT_CLK NONE +enum: MULT18_4.REG_OUTPUT_RST RST0 +enum: MULT18_4.CLK0_DIV ENABLED +enum: MULT18_4.CLK1_DIV ENABLED +enum: MULT18_4.CLK2_DIV ENABLED +enum: MULT18_4.CLK3_DIV ENABLED +enum: MULT18_4.GSR ENABLED +enum: MULT18_4.SOURCEB_MODE B_SHIFT +enum: MULT18_4.RESETMODE SYNC +enum: MULT18_4.MODE MULT18X18D +enum: MULT18_4.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_4.CLK0MUX CLK0 +enum: MULT18_4.CLK1MUX CLK1 +enum: MULT18_4.CLK2MUX CLK2 +enum: MULT18_4.CLK3MUX CLK3 +enum: MULT18_4.CE0MUX CE0 +enum: MULT18_4.CE1MUX CE1 +enum: MULT18_4.CE2MUX CE2 +enum: MULT18_4.CE3MUX CE3 +enum: MULT18_4.RST0MUX RST0 +enum: MULT18_4.RST1MUX RST1 +enum: MULT18_4.RST2MUX RST2 +enum: MULT18_4.RST3MUX RST3 + +.tile_group MIB_R22C22:MIB_DSP0 MIB_R22C22:MIB2_DSP0 MIB_R22C23:MIB_DSP1 MIB_R22C23:MIB2_DSP1 MIB_R22C24:MIB_DSP2 MIB_R22C24:MIB2_DSP2 MIB_R22C25:MIB_DSP3 MIB_R22C25:MIB2_DSP3 MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 +enum: MULT18_0.REG_INPUTA_CLK NONE +enum: MULT18_0.REG_INPUTA_CE CE0 +enum: MULT18_0.REG_INPUTA_RST RST0 +enum: MULT18_0.REG_INPUTB_CLK NONE +enum: MULT18_0.REG_INPUTB_CE CE0 +enum: MULT18_0.REG_INPUTB_RST RST0 +enum: MULT18_0.REG_INPUTC_CLK NONE +enum: MULT18_0.REG_PIPELINE_CLK NONE +enum: MULT18_0.REG_PIPELINE_CE CE0 +enum: MULT18_0.REG_PIPELINE_RST RST0 +enum: MULT18_0.REG_OUTPUT_CLK NONE +enum: MULT18_0.REG_OUTPUT_RST RST0 +enum: MULT18_0.CLK0_DIV ENABLED +enum: MULT18_0.CLK1_DIV ENABLED +enum: MULT18_0.CLK2_DIV ENABLED +enum: MULT18_0.CLK3_DIV ENABLED +enum: MULT18_0.GSR ENABLED +enum: MULT18_0.SOURCEB_MODE B_SHIFT +enum: MULT18_0.RESETMODE SYNC +enum: MULT18_0.MODE MULT18X18D +enum: MULT18_0.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_0.CLK0MUX CLK0 +enum: MULT18_0.CLK1MUX CLK1 +enum: MULT18_0.CLK2MUX CLK2 +enum: MULT18_0.CLK3MUX CLK3 +enum: MULT18_0.CE0MUX CE0 +enum: MULT18_0.CE1MUX CE1 +enum: MULT18_0.CE2MUX CE2 +enum: MULT18_0.CE3MUX CE3 +enum: MULT18_0.RST0MUX RST0 +enum: MULT18_0.RST1MUX RST1 +enum: MULT18_0.RST2MUX RST2 +enum: MULT18_0.RST3MUX RST3 + +.tile_group MIB_R46C46:MIB_DSP4 MIB_R46C46:MIB2_DSP4 MIB_R46C47:MIB_DSP5 MIB_R46C47:MIB2_DSP5 MIB_R46C48:MIB_DSP6 MIB_R46C48:MIB2_DSP6 MIB_R46C49:MIB_DSP7 MIB_R46C49:MIB2_DSP7 MIB_R46C50:MIB_DSP8 MIB_R46C50:MIB2_DSP8 +enum: MULT18_5.REG_INPUTA_CLK NONE +enum: MULT18_5.REG_INPUTA_CE CE0 +enum: MULT18_5.REG_INPUTA_RST RST0 +enum: MULT18_5.REG_INPUTB_CLK NONE +enum: MULT18_5.REG_INPUTB_CE CE0 +enum: MULT18_5.REG_INPUTB_RST RST0 +enum: MULT18_5.REG_INPUTC_CLK NONE +enum: MULT18_5.REG_PIPELINE_CLK NONE +enum: MULT18_5.REG_PIPELINE_CE CE0 +enum: MULT18_5.REG_PIPELINE_RST RST0 +enum: MULT18_5.REG_OUTPUT_CLK NONE +enum: MULT18_5.CLK0_DIV ENABLED +enum: MULT18_5.CLK1_DIV ENABLED +enum: MULT18_5.CLK2_DIV ENABLED +enum: MULT18_5.CLK3_DIV ENABLED +enum: MULT18_5.GSR ENABLED +enum: MULT18_5.SOURCEB_MODE B_SHIFT +enum: MULT18_5.RESETMODE SYNC +enum: MULT18_5.MODE MULT18X18D +enum: MULT18_5.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_5.CLK0MUX CLK0 +enum: MULT18_5.CLK1MUX CLK1 +enum: MULT18_5.CLK2MUX CLK2 +enum: MULT18_5.CLK3MUX CLK3 +enum: MULT18_5.CE0MUX CE0 +enum: MULT18_5.CE1MUX CE1 +enum: MULT18_5.CE2MUX CE2 +enum: MULT18_5.CE3MUX CE3 +enum: MULT18_5.RST0MUX RST0 +enum: MULT18_5.RST1MUX RST1 +enum: MULT18_5.RST2MUX RST2 +enum: MULT18_5.RST3MUX RST3 + diff --git a/synth/ecp5/p2/top.json b/synth/ecp5/p2/top.json new file mode 100644 index 0000000..6451055 --- /dev/null +++ b/synth/ecp5/p2/top.json @@ -0,0 +1,44888 @@ +{ + "creator": "Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)", + "modules": { + "$__ABC9_DELAY": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000011", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.1-7.10" + }, + "parameter_default_values": { + "DELAY": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + "$specify$7970": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000000000000", + "T_FALL_MIN": "00000000000000000000000000000000", + "T_FALL_TYP": "00000000000000000000000000000000", + "T_RISE_MAX": "00000000000000000000000000000000", + "T_RISE_MIN": "00000000000000000000000000000000", + "T_RISE_TYP": "00000000000000000000000000000000" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:5.5-5.22" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 3 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + } + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.29-2.30" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.39-2.40" + } + } + } + }, + "$__ABC9_SCC_BREAKER": { + "attributes": { + "dynports": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.1-11.10" + }, + "parameter_default_values": { + "WIDTH": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "offset": -1, + "upto": 1, + "bits": [ 2, 3 ] + }, + "O": { + "direction": "output", + "offset": -1, + "upto": 1, + "bits": [ 4, 5 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2, 3 ], + "offset": -1, + "upto": 1, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.47-9.48" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4, 5 ], + "offset": -1, + "upto": 1, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.69-9.70" + } + } + } + }, + "$__DFF_N__$abc9_flop": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000010", + "blackbox": "00000000000000000000000000000001", + "abc9_flop": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.1-20.10" + }, + "ports": { + "C": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "input", + "bits": [ 4 ] + }, + "n1": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "C": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.36-14.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.39-14.40" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.42-14.43" + } + }, + "n1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.52-14.54" + } + } + } + }, + "$__DFF_P__$abc9_flop": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "abc9_flop": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.1-29.10" + }, + "ports": { + "C": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "input", + "bits": [ 4 ] + }, + "n1": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "C": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.36-23.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.39-23.40" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.42-23.43" + } + }, + "n1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.52-23.54" + } + } + } + }, + "$paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\\CCU2C": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000100", + "blackbox": "00000000000000000000000000000001", + "hdlname": "CCU2C", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:3.1-61.10" + }, + "parameter_default_values": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "ports": { + "CIN": { + "direction": "input", + "bits": [ 2 ] + }, + "A0": { + "direction": "input", + "bits": [ 3 ] + }, + "B0": { + "direction": "input", + "bits": [ 4 ] + }, + "C0": { + "direction": "input", + "bits": [ 5 ] + }, + "D0": { + "direction": "input", + "bits": [ 6 ] + }, + "A1": { + "direction": "input", + "bits": [ 7 ] + }, + "B1": { + "direction": "input", + "bits": [ 8 ] + }, + "C1": { + "direction": "input", + "bits": [ 9 ] + }, + "D1": { + "direction": "input", + "bits": [ 10 ] + }, + "S0": { + "direction": "output", + "bits": [ 11 ] + }, + "S1": { + "direction": "output", + "bits": [ 12 ] + }, + "COUT": { + "direction": "output", + "bits": [ 13 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.9-6.11" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.25-6.27" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.13-6.15" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.29-6.31" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.17-6.19" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.33-6.35" + } + }, + "CIN": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:5.9-5.12" + } + }, + "COUT": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "D0": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.21-6.23" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.37-6.39" + } + }, + "S0": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.9-7.11" + } + }, + "S1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.13-7.15" + } + } + } + }, + "\\$__ABC9_LUT5": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000000010", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.1-30.10" + }, + "ports": { + "M0": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "C": { + "direction": "input", + "bits": [ 4 ] + }, + "B": { + "direction": "input", + "bits": [ 5 ] + }, + "A": { + "direction": "input", + "bits": [ 6 ] + }, + "Z": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + "$specify$319": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000010010111", + "T_FALL_MIN": "00000000000000000000000010010111", + "T_FALL_TYP": "00000000000000000000000010010111", + "T_RISE_MAX": "00000000000000000000000010010111", + "T_RISE_MIN": "00000000000000000000000010010111", + "T_RISE_TYP": "00000000000000000000000010010111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:24.9-24.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + }, + "$specify$320": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000011101111", + "T_FALL_MIN": "00000000000000000000000011101111", + "T_FALL_TYP": "00000000000000000000000011101111", + "T_RISE_MAX": "00000000000000000000000011101111", + "T_RISE_MIN": "00000000000000000000000011101111", + "T_RISE_TYP": "00000000000000000000000011101111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:25.9-25.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 3 ] + } + }, + "$specify$321": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000101110101", + "T_FALL_MIN": "00000000000000000000000101110101", + "T_FALL_TYP": "00000000000000000000000101110101", + "T_RISE_MAX": "00000000000000000000000101110101", + "T_RISE_MIN": "00000000000000000000000101110101", + "T_RISE_TYP": "00000000000000000000000101110101" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:26.9-26.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 4 ] + } + }, + "$specify$322": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000111011101", + "T_FALL_MIN": "00000000000000000000000111011101", + "T_FALL_TYP": "00000000000000000000000111011101", + "T_RISE_MAX": "00000000000000000000000111011101", + "T_RISE_MIN": "00000000000000000000000111011101", + "T_RISE_TYP": "00000000000000000000000111011101" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:27.9-27.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 5 ] + } + }, + "$specify$323": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000111011101", + "T_FALL_MIN": "00000000000000000000000111011101", + "T_FALL_TYP": "00000000000000000000000111011101", + "T_RISE_MAX": "00000000000000000000000111011101", + "T_RISE_MIN": "00000000000000000000000111011101", + "T_RISE_TYP": "00000000000000000000000111011101" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:28.9-28.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 6 ] + } + } + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.42-22.43" + } + }, + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.39-22.40" + } + }, + "C": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.36-22.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.33-22.34" + } + }, + "M0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.29-22.31" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.52-22.53" + } + } + } + }, + "\\$__ABC9_LUT6": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000000100", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.1-45.10" + }, + "ports": { + "M1": { + "direction": "input", + "bits": [ 2 ] + }, + "M0": { + "direction": "input", + "bits": [ 3 ] + }, + "D": { + "direction": "input", + "bits": [ 4 ] + }, + "C": { + "direction": "input", + "bits": [ 5 ] + }, + "B": { + "direction": "input", + "bits": [ 6 ] + }, + "A": { + "direction": "input", + "bits": [ 7 ] + }, + "Z": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + "$specify$324": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000010010100", + "T_FALL_MIN": "00000000000000000000000010010100", + "T_FALL_TYP": "00000000000000000000000010010100", + "T_RISE_MAX": "00000000000000000000000010010100", + "T_RISE_MIN": "00000000000000000000000010010100", + "T_RISE_TYP": "00000000000000000000000010010100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:38.9-38.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + }, + "$specify$325": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000100100100", + "T_FALL_MIN": "00000000000000000000000100100100", + "T_FALL_TYP": "00000000000000000000000100100100", + "T_RISE_MAX": "00000000000000000000000100100100", + "T_RISE_MIN": "00000000000000000000000100100100", + "T_RISE_TYP": "00000000000000000000000100100100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:39.9-39.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 3 ] + } + }, + "$specify$326": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000101111100", + "T_FALL_MIN": "00000000000000000000000101111100", + "T_FALL_TYP": "00000000000000000000000101111100", + "T_RISE_MAX": "00000000000000000000000101111100", + "T_RISE_MIN": "00000000000000000000000101111100", + "T_RISE_TYP": "00000000000000000000000101111100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:40.9-40.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 4 ] + } + }, + "$specify$327": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001000000010", + "T_FALL_MIN": "00000000000000000000001000000010", + "T_FALL_TYP": "00000000000000000000001000000010", + "T_RISE_MAX": "00000000000000000000001000000010", + "T_RISE_MIN": "00000000000000000000001000000010", + "T_RISE_TYP": "00000000000000000000001000000010" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:41.9-41.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 5 ] + } + }, + "$specify$328": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001001101010", + "T_FALL_MIN": "00000000000000000000001001101010", + "T_FALL_TYP": "00000000000000000000001001101010", + "T_RISE_MAX": "00000000000000000000001001101010", + "T_RISE_MIN": "00000000000000000000001001101010", + "T_RISE_TYP": "00000000000000000000001001101010" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:42.9-42.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 6 ] + } + }, + "$specify$329": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001001101010", + "T_FALL_MIN": "00000000000000000000001001101010", + "T_FALL_TYP": "00000000000000000000001001101010", + "T_RISE_MAX": "00000000000000000000001001101010", + "T_RISE_MIN": "00000000000000000000001001101010", + "T_RISE_TYP": "00000000000000000000001001101010" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:43.9-43.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 7 ] + } + } + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.46-36.47" + } + }, + "B": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.43-36.44" + } + }, + "C": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.40-36.41" + } + }, + "D": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.37-36.38" + } + }, + "M0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.33-36.35" + } + }, + "M1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.29-36.31" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.56-36.57" + } + } + } + }, + "\\$__ABC9_LUT7": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000001000", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.1-61.10" + }, + "ports": { + "M2": { + "direction": "input", + "bits": [ 2 ] + }, + "M1": { + "direction": "input", + "bits": [ 3 ] + }, + "M0": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "C": { + "direction": "input", + "bits": [ 6 ] + }, + "B": { + "direction": "input", + "bits": [ 7 ] + }, + "A": { + "direction": "input", + "bits": [ 8 ] + }, + "Z": { + "direction": "output", + "bits": [ 9 ] + } + }, + "cells": { + "$specify$330": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000010010100", + "T_FALL_MIN": "00000000000000000000000010010100", + "T_FALL_TYP": "00000000000000000000000010010100", + "T_RISE_MAX": "00000000000000000000000010010100", + "T_RISE_MIN": "00000000000000000000000010010100", + "T_RISE_TYP": "00000000000000000000000010010100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:53.9-53.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + }, + "$specify$331": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000100100001", + "T_FALL_MIN": "00000000000000000000000100100001", + "T_FALL_TYP": "00000000000000000000000100100001", + "T_RISE_MAX": "00000000000000000000000100100001", + "T_RISE_MIN": "00000000000000000000000100100001", + "T_RISE_TYP": "00000000000000000000000100100001" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:54.9-54.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 3 ] + } + }, + "$specify$332": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000110110001", + "T_FALL_MIN": "00000000000000000000000110110001", + "T_FALL_TYP": "00000000000000000000000110110001", + "T_RISE_MAX": "00000000000000000000000110110001", + "T_RISE_MIN": "00000000000000000000000110110001", + "T_RISE_TYP": "00000000000000000000000110110001" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:55.9-55.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 4 ] + } + }, + "$specify$333": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001000001001", + "T_FALL_MIN": "00000000000000000000001000001001", + "T_FALL_TYP": "00000000000000000000001000001001", + "T_RISE_MAX": "00000000000000000000001000001001", + "T_RISE_MIN": "00000000000000000000001000001001", + "T_RISE_TYP": "00000000000000000000001000001001" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:56.9-56.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 5 ] + } + }, + "$specify$334": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001010001111", + "T_FALL_MIN": "00000000000000000000001010001111", + "T_FALL_TYP": "00000000000000000000001010001111", + "T_RISE_MAX": "00000000000000000000001010001111", + "T_RISE_MIN": "00000000000000000000001010001111", + "T_RISE_TYP": "00000000000000000000001010001111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:57.9-57.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 6 ] + } + }, + "$specify$335": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001011110111", + "T_FALL_MIN": "00000000000000000000001011110111", + "T_FALL_TYP": "00000000000000000000001011110111", + "T_RISE_MAX": "00000000000000000000001011110111", + "T_RISE_MIN": "00000000000000000000001011110111", + "T_RISE_TYP": "00000000000000000000001011110111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:58.9-58.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 7 ] + } + }, + "$specify$336": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001011110111", + "T_FALL_MIN": "00000000000000000000001011110111", + "T_FALL_TYP": "00000000000000000000001011110111", + "T_RISE_MAX": "00000000000000000000001011110111", + "T_RISE_MIN": "00000000000000000000001011110111", + "T_RISE_TYP": "00000000000000000000001011110111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:59.9-59.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 8 ] + } + } + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.50-51.51" + } + }, + "B": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.47-51.48" + } + }, + "C": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.44-51.45" + } + }, + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.41-51.42" + } + }, + "M0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.37-51.39" + } + }, + "M1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.33-51.35" + } + }, + "M2": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.29-51.31" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.60-51.61" + } + } + } + }, + "ALU54B": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:489.1-1007.10" + }, + "parameter_default_values": { + "CLK0_DIV": "ENABLED", + "CLK1_DIV": "ENABLED", + "CLK2_DIV": "ENABLED", + "CLK3_DIV": "ENABLED", + "FORCE_ZERO_BARREL_SHIFT": "DISABLED", + "GSR": "ENABLED", + "LEGACY": "DISABLED", + "MASK01": "0x00000000000000 ", + "MASKPAT": "0x00000000000000 ", + "MASKPAT_SOURCE": "STATIC", + "MCPAT": "0x00000000000000 ", + "MCPAT_SOURCE": "STATIC", + "MULT9_MODE": "DISABLED", + "REG_FLAG_CE": "CE0", + "REG_FLAG_CLK": "NONE", + "REG_FLAG_RST": "RST0", + "REG_INPUTC0_CE": "CE0", + "REG_INPUTC0_CLK": "NONE", + "REG_INPUTC0_RST": "RST0", + "REG_INPUTC1_CE": "CE0", + "REG_INPUTC1_CLK": "NONE", + "REG_INPUTC1_RST": "RST0", + "REG_INPUTCFB_CE": "CE0", + "REG_INPUTCFB_CLK": "NONE", + "REG_INPUTCFB_RST": "RST0", + "REG_OPCODEIN_0_CE": "CE0", + "REG_OPCODEIN_0_CLK": "NONE", + "REG_OPCODEIN_0_RST": "RST0", + "REG_OPCODEIN_1_CE": "CE0", + "REG_OPCODEIN_1_CLK": "NONE", + "REG_OPCODEIN_1_RST": "RST0", + "REG_OPCODEOP0_0_CE": "CE0", + "REG_OPCODEOP0_0_CLK": "NONE", + "REG_OPCODEOP0_0_RST": "RST0", + "REG_OPCODEOP0_1_CE": "CE0", + "REG_OPCODEOP0_1_CLK": "NONE", + "REG_OPCODEOP0_1_RST": "RST0", + "REG_OPCODEOP1_0_CLK": "NONE", + "REG_OPCODEOP1_1_CLK": "NONE", + "REG_OUTPUT0_CE": "CE0", + "REG_OUTPUT0_CLK": "NONE", + "REG_OUTPUT0_RST": "RST0", + "REG_OUTPUT1_CE": "CE0", + "REG_OUTPUT1_CLK": "NONE", + "REG_OUTPUT1_RST": "RST0", + "RESETMODE": "SYNC", + "RNDPAT": "0x00000000000000 " + }, + "ports": { + "CE3": { + "direction": "input", + "bits": [ 2 ] + }, + "CE2": { + "direction": "input", + "bits": [ 3 ] + }, + "CE1": { + "direction": "input", + "bits": [ 4 ] + }, + "CE0": { + "direction": "input", + "bits": [ 5 ] + }, + "CLK3": { + "direction": "input", + "bits": [ 6 ] + }, + "CLK2": { + "direction": "input", + "bits": [ 7 ] + }, + "CLK1": { + "direction": "input", + "bits": [ 8 ] + }, + "CLK0": { + "direction": "input", + "bits": [ 9 ] + }, + "RST3": { + "direction": "input", + "bits": [ 10 ] + }, + "RST2": { + "direction": "input", + "bits": [ 11 ] + }, + "RST1": { + "direction": "input", + "bits": [ 12 ] + }, + "RST0": { + "direction": "input", + "bits": [ 13 ] + }, + "SIGNEDIA": { + "direction": "input", + "bits": [ 14 ] + }, + "SIGNEDIB": { + "direction": "input", + "bits": [ 15 ] + }, + "SIGNEDCIN": { + "direction": "input", + "bits": [ 16 ] + }, + "A35": { + "direction": "input", + "bits": [ 17 ] + }, + "A34": { + "direction": "input", + "bits": [ 18 ] + }, + "A33": { + "direction": "input", + "bits": [ 19 ] + }, + "A32": { + "direction": "input", + "bits": [ 20 ] + }, + "A31": { + "direction": "input", + "bits": [ 21 ] + }, + "A30": { + "direction": "input", + "bits": [ 22 ] + }, + "A29": { + "direction": "input", + "bits": [ 23 ] + }, + "A28": { + "direction": "input", + "bits": [ 24 ] + }, + "A27": { + "direction": "input", + "bits": [ 25 ] + }, + "A26": { + "direction": "input", + "bits": [ 26 ] + }, + "A25": { + "direction": "input", + "bits": [ 27 ] + }, + "A24": { + "direction": "input", + "bits": [ 28 ] + }, + "A23": { + "direction": "input", + "bits": [ 29 ] + }, + "A22": { + "direction": "input", + "bits": [ 30 ] + }, + "A21": { + "direction": "input", + "bits": [ 31 ] + }, + "A20": { + "direction": "input", + "bits": [ 32 ] + }, + "A19": { + "direction": "input", + "bits": [ 33 ] + }, + "A18": { + "direction": "input", + "bits": [ 34 ] + }, + "A17": { + "direction": "input", + "bits": [ 35 ] + }, + "A16": { + "direction": "input", + "bits": [ 36 ] + }, + "A15": { + "direction": "input", + "bits": [ 37 ] + }, + "A14": { + "direction": "input", + "bits": [ 38 ] + }, + "A13": { + "direction": "input", + "bits": [ 39 ] + }, + "A12": { + "direction": "input", + "bits": [ 40 ] + }, + "A11": { + "direction": "input", + "bits": [ 41 ] + }, + "A10": { + "direction": "input", + "bits": [ 42 ] + }, + "A9": { + "direction": "input", + "bits": [ 43 ] + }, + "A8": { + "direction": "input", + "bits": [ 44 ] + }, + "A7": { + "direction": "input", + "bits": [ 45 ] + }, + "A6": { + "direction": "input", + "bits": [ 46 ] + }, + "A5": { + "direction": "input", + "bits": [ 47 ] + }, + "A4": { + "direction": "input", + "bits": [ 48 ] + }, + "A3": { + "direction": "input", + "bits": [ 49 ] + }, + "A2": { + "direction": "input", + "bits": [ 50 ] + }, + "A1": { + "direction": "input", + "bits": [ 51 ] + }, + "A0": { + "direction": "input", + "bits": [ 52 ] + }, + "B35": { + "direction": "input", + "bits": [ 53 ] + }, + "B34": { + "direction": "input", + "bits": [ 54 ] + }, + "B33": { + "direction": "input", + "bits": [ 55 ] + }, + "B32": { + "direction": "input", + "bits": [ 56 ] + }, + "B31": { + "direction": "input", + "bits": [ 57 ] + }, + "B30": { + "direction": "input", + "bits": [ 58 ] + }, + "B29": { + "direction": "input", + "bits": [ 59 ] + }, + "B28": { + "direction": "input", + "bits": [ 60 ] + }, + "B27": { + "direction": "input", + "bits": [ 61 ] + }, + "B26": { + "direction": "input", + "bits": [ 62 ] + }, + "B25": { + "direction": "input", + "bits": [ 63 ] + }, + "B24": { + "direction": "input", + "bits": [ 64 ] + }, + "B23": { + "direction": "input", + "bits": [ 65 ] + }, + "B22": { + "direction": "input", + "bits": [ 66 ] + }, + "B21": { + "direction": "input", + "bits": [ 67 ] + }, + "B20": { + "direction": "input", + "bits": [ 68 ] + }, + "B19": { + "direction": "input", + "bits": [ 69 ] + }, + "B18": { + "direction": "input", + "bits": [ 70 ] + }, + "B17": { + "direction": "input", + "bits": [ 71 ] + }, + "B16": { + "direction": "input", + "bits": [ 72 ] + }, + "B15": { + "direction": "input", + "bits": [ 73 ] + }, + "B14": { + "direction": "input", + "bits": [ 74 ] + }, + "B13": { + "direction": "input", + "bits": [ 75 ] + }, + "B12": { + "direction": "input", + "bits": [ 76 ] + }, + "B11": { + "direction": "input", + "bits": [ 77 ] + }, + "B10": { + "direction": "input", + "bits": [ 78 ] + }, + "B9": { + "direction": "input", + "bits": [ 79 ] + }, + "B8": { + "direction": "input", + "bits": [ 80 ] + }, + "B7": { + "direction": "input", + "bits": [ 81 ] + }, + "B6": { + "direction": "input", + "bits": [ 82 ] + }, + "B5": { + "direction": "input", + "bits": [ 83 ] + }, + "B4": { + "direction": "input", + "bits": [ 84 ] + }, + "B3": { + "direction": "input", + "bits": [ 85 ] + }, + "B2": { + "direction": "input", + "bits": [ 86 ] + }, + "B1": { + "direction": "input", + "bits": [ 87 ] + }, + "B0": { + "direction": "input", + "bits": [ 88 ] + }, + "C53": { + "direction": "input", + "bits": [ 89 ] + }, + "C52": { + "direction": "input", + "bits": [ 90 ] + }, + "C51": { + "direction": "input", + "bits": [ 91 ] + }, + "C50": { + "direction": "input", + "bits": [ 92 ] + }, + "C49": { + "direction": "input", + "bits": [ 93 ] + }, + "C48": { + "direction": "input", + "bits": [ 94 ] + }, + "C47": { + "direction": "input", + "bits": [ 95 ] + }, + "C46": { + "direction": "input", + "bits": [ 96 ] + }, + "C45": { + "direction": "input", + "bits": [ 97 ] + }, + "C44": { + "direction": "input", + "bits": [ 98 ] + }, + "C43": { + "direction": "input", + "bits": [ 99 ] + }, + "C42": { + "direction": "input", + "bits": [ 100 ] + }, + "C41": { + "direction": "input", + "bits": [ 101 ] + }, + "C40": { + "direction": "input", + "bits": [ 102 ] + }, + "C39": { + "direction": "input", + "bits": [ 103 ] + }, + "C38": { + "direction": "input", + "bits": [ 104 ] + }, + "C37": { + "direction": "input", + "bits": [ 105 ] + }, + "C36": { + "direction": "input", + "bits": [ 106 ] + }, + "C35": { + "direction": "input", + "bits": [ 107 ] + }, + "C34": { + "direction": "input", + "bits": [ 108 ] + }, + "C33": { + "direction": "input", + "bits": [ 109 ] + }, + "C32": { + "direction": "input", + "bits": [ 110 ] + }, + "C31": { + "direction": "input", + "bits": [ 111 ] + }, + "C30": { + "direction": "input", + "bits": [ 112 ] + }, + "C29": { + "direction": "input", + "bits": [ 113 ] + }, + "C28": { + "direction": "input", + "bits": [ 114 ] + }, + "C27": { + "direction": "input", + "bits": [ 115 ] + }, + "C26": { + "direction": "input", + "bits": [ 116 ] + }, + "C25": { + "direction": "input", + "bits": [ 117 ] + }, + "C24": { + "direction": "input", + "bits": [ 118 ] + }, + "C23": { + "direction": "input", + "bits": [ 119 ] + }, + "C22": { + "direction": "input", + "bits": [ 120 ] + }, + "C21": { + "direction": "input", + "bits": [ 121 ] + }, + "C20": { + "direction": "input", + "bits": [ 122 ] + }, + "C19": { + "direction": "input", + "bits": [ 123 ] + }, + "C18": { + "direction": "input", + "bits": [ 124 ] + }, + "C17": { + "direction": "input", + "bits": [ 125 ] + }, + "C16": { + "direction": "input", + "bits": [ 126 ] + }, + "C15": { + "direction": "input", + "bits": [ 127 ] + }, + "C14": { + "direction": "input", + "bits": [ 128 ] + }, + "C13": { + "direction": "input", + "bits": [ 129 ] + }, + "C12": { + "direction": "input", + "bits": [ 130 ] + }, + "C11": { + "direction": "input", + "bits": [ 131 ] + }, + "C10": { + "direction": "input", + "bits": [ 132 ] + }, + "C9": { + "direction": "input", + "bits": [ 133 ] + }, + "C8": { + "direction": "input", + "bits": [ 134 ] + }, + "C7": { + "direction": "input", + "bits": [ 135 ] + }, + "C6": { + "direction": "input", + "bits": [ 136 ] + }, + "C5": { + "direction": "input", + "bits": [ 137 ] + }, + "C4": { + "direction": "input", + "bits": [ 138 ] + }, + "C3": { + "direction": "input", + "bits": [ 139 ] + }, + "C2": { + "direction": "input", + "bits": [ 140 ] + }, + "C1": { + "direction": "input", + "bits": [ 141 ] + }, + "C0": { + "direction": "input", + "bits": [ 142 ] + }, + "CFB53": { + "direction": "input", + "bits": [ 143 ] + }, + "CFB52": { + "direction": "input", + "bits": [ 144 ] + }, + "CFB51": { + "direction": "input", + "bits": [ 145 ] + }, + "CFB50": { + "direction": "input", + "bits": [ 146 ] + }, + "CFB49": { + "direction": "input", + "bits": [ 147 ] + }, + "CFB48": { + "direction": "input", + "bits": [ 148 ] + }, + "CFB47": { + "direction": "input", + "bits": [ 149 ] + }, + "CFB46": { + "direction": "input", + "bits": [ 150 ] + }, + "CFB45": { + "direction": "input", + "bits": [ 151 ] + }, + "CFB44": { + "direction": "input", + "bits": [ 152 ] + }, + "CFB43": { + "direction": "input", + "bits": [ 153 ] + }, + "CFB42": { + "direction": "input", + "bits": [ 154 ] + }, + "CFB41": { + "direction": "input", + "bits": [ 155 ] + }, + "CFB40": { + "direction": "input", + "bits": [ 156 ] + }, + "CFB39": { + "direction": "input", + "bits": [ 157 ] + }, + "CFB38": { + "direction": "input", + "bits": [ 158 ] + }, + "CFB37": { + "direction": "input", + "bits": [ 159 ] + }, + "CFB36": { + "direction": "input", + "bits": [ 160 ] + }, + "CFB35": { + "direction": "input", + "bits": [ 161 ] + }, + "CFB34": { + "direction": "input", + "bits": [ 162 ] + }, + "CFB33": { + "direction": "input", + "bits": [ 163 ] + }, + "CFB32": { + "direction": "input", + "bits": [ 164 ] + }, + "CFB31": { + "direction": "input", + "bits": [ 165 ] + }, + "CFB30": { + "direction": "input", + "bits": [ 166 ] + }, + "CFB29": { + "direction": "input", + "bits": [ 167 ] + }, + "CFB28": { + "direction": "input", + "bits": [ 168 ] + }, + "CFB27": { + "direction": "input", + "bits": [ 169 ] + }, + "CFB26": { + "direction": "input", + "bits": [ 170 ] + }, + "CFB25": { + "direction": "input", + "bits": [ 171 ] + }, + "CFB24": { + "direction": "input", + "bits": [ 172 ] + }, + "CFB23": { + "direction": "input", + "bits": [ 173 ] + }, + "CFB22": { + "direction": "input", + "bits": [ 174 ] + }, + "CFB21": { + "direction": "input", + "bits": [ 175 ] + }, + "CFB20": { + "direction": "input", + "bits": [ 176 ] + }, + "CFB19": { + "direction": "input", + "bits": [ 177 ] + }, + "CFB18": { + "direction": "input", + "bits": [ 178 ] + }, + "CFB17": { + "direction": "input", + "bits": [ 179 ] + }, + "CFB16": { + "direction": "input", + "bits": [ 180 ] + }, + "CFB15": { + "direction": "input", + "bits": [ 181 ] + }, + "CFB14": { + "direction": "input", + "bits": [ 182 ] + }, + "CFB13": { + "direction": "input", + "bits": [ 183 ] + }, + "CFB12": { + "direction": "input", + "bits": [ 184 ] + }, + "CFB11": { + "direction": "input", + "bits": [ 185 ] + }, + "CFB10": { + "direction": "input", + "bits": [ 186 ] + }, + "CFB9": { + "direction": "input", + "bits": [ 187 ] + }, + "CFB8": { + "direction": "input", + "bits": [ 188 ] + }, + "CFB7": { + "direction": "input", + "bits": [ 189 ] + }, + "CFB6": { + "direction": "input", + "bits": [ 190 ] + }, + "CFB5": { + "direction": "input", + "bits": [ 191 ] + }, + "CFB4": { + "direction": "input", + "bits": [ 192 ] + }, + "CFB3": { + "direction": "input", + "bits": [ 193 ] + }, + "CFB2": { + "direction": "input", + "bits": [ 194 ] + }, + "CFB1": { + "direction": "input", + "bits": [ 195 ] + }, + "CFB0": { + "direction": "input", + "bits": [ 196 ] + }, + "MA35": { + "direction": "input", + "bits": [ 197 ] + }, + "MA34": { + "direction": "input", + "bits": [ 198 ] + }, + "MA33": { + "direction": "input", + "bits": [ 199 ] + }, + "MA32": { + "direction": "input", + "bits": [ 200 ] + }, + "MA31": { + "direction": "input", + "bits": [ 201 ] + }, + "MA30": { + "direction": "input", + "bits": [ 202 ] + }, + "MA29": { + "direction": "input", + "bits": [ 203 ] + }, + "MA28": { + "direction": "input", + "bits": [ 204 ] + }, + "MA27": { + "direction": "input", + "bits": [ 205 ] + }, + "MA26": { + "direction": "input", + "bits": [ 206 ] + }, + "MA25": { + "direction": "input", + "bits": [ 207 ] + }, + "MA24": { + "direction": "input", + "bits": [ 208 ] + }, + "MA23": { + "direction": "input", + "bits": [ 209 ] + }, + "MA22": { + "direction": "input", + "bits": [ 210 ] + }, + "MA21": { + "direction": "input", + "bits": [ 211 ] + }, + "MA20": { + "direction": "input", + "bits": [ 212 ] + }, + "MA19": { + "direction": "input", + "bits": [ 213 ] + }, + "MA18": { + "direction": "input", + "bits": [ 214 ] + }, + "MA17": { + "direction": "input", + "bits": [ 215 ] + }, + "MA16": { + "direction": "input", + "bits": [ 216 ] + }, + "MA15": { + "direction": "input", + "bits": [ 217 ] + }, + "MA14": { + "direction": "input", + "bits": [ 218 ] + }, + "MA13": { + "direction": "input", + "bits": [ 219 ] + }, + "MA12": { + "direction": "input", + "bits": [ 220 ] + }, + "MA11": { + "direction": "input", + "bits": [ 221 ] + }, + "MA10": { + "direction": "input", + "bits": [ 222 ] + }, + "MA9": { + "direction": "input", + "bits": [ 223 ] + }, + "MA8": { + "direction": "input", + "bits": [ 224 ] + }, + "MA7": { + "direction": "input", + "bits": [ 225 ] + }, + "MA6": { + "direction": "input", + "bits": [ 226 ] + }, + "MA5": { + "direction": "input", + "bits": [ 227 ] + }, + "MA4": { + "direction": "input", + "bits": [ 228 ] + }, + "MA3": { + "direction": "input", + "bits": [ 229 ] + }, + "MA2": { + "direction": "input", + "bits": [ 230 ] + }, + "MA1": { + "direction": "input", + "bits": [ 231 ] + }, + "MA0": { + "direction": "input", + "bits": [ 232 ] + }, + "MB35": { + "direction": "input", + "bits": [ 233 ] + }, + "MB34": { + "direction": "input", + "bits": [ 234 ] + }, + "MB33": { + "direction": "input", + "bits": [ 235 ] + }, + "MB32": { + "direction": "input", + "bits": [ 236 ] + }, + "MB31": { + "direction": "input", + "bits": [ 237 ] + }, + "MB30": { + "direction": "input", + "bits": [ 238 ] + }, + "MB29": { + "direction": "input", + "bits": [ 239 ] + }, + "MB28": { + "direction": "input", + "bits": [ 240 ] + }, + "MB27": { + "direction": "input", + "bits": [ 241 ] + }, + "MB26": { + "direction": "input", + "bits": [ 242 ] + }, + "MB25": { + "direction": "input", + "bits": [ 243 ] + }, + "MB24": { + "direction": "input", + "bits": [ 244 ] + }, + "MB23": { + "direction": "input", + "bits": [ 245 ] + }, + "MB22": { + "direction": "input", + "bits": [ 246 ] + }, + "MB21": { + "direction": "input", + "bits": [ 247 ] + }, + "MB20": { + "direction": "input", + "bits": [ 248 ] + }, + "MB19": { + "direction": "input", + "bits": [ 249 ] + }, + "MB18": { + "direction": "input", + "bits": [ 250 ] + }, + "MB17": { + "direction": "input", + "bits": [ 251 ] + }, + "MB16": { + "direction": "input", + "bits": [ 252 ] + }, + "MB15": { + "direction": "input", + "bits": [ 253 ] + }, + "MB14": { + "direction": "input", + "bits": [ 254 ] + }, + "MB13": { + "direction": "input", + "bits": [ 255 ] + }, + "MB12": { + "direction": "input", + "bits": [ 256 ] + }, + "MB11": { + "direction": "input", + "bits": [ 257 ] + }, + "MB10": { + "direction": "input", + "bits": [ 258 ] + }, + "MB9": { + "direction": "input", + "bits": [ 259 ] + }, + "MB8": { + "direction": "input", + "bits": [ 260 ] + }, + "MB7": { + "direction": "input", + "bits": [ 261 ] + }, + "MB6": { + "direction": "input", + "bits": [ 262 ] + }, + "MB5": { + "direction": "input", + "bits": [ 263 ] + }, + "MB4": { + "direction": "input", + "bits": [ 264 ] + }, + "MB3": { + "direction": "input", + "bits": [ 265 ] + }, + "MB2": { + "direction": "input", + "bits": [ 266 ] + }, + "MB1": { + "direction": "input", + "bits": [ 267 ] + }, + "MB0": { + "direction": "input", + "bits": [ 268 ] + }, + "CIN53": { + "direction": "input", + "bits": [ 269 ] + }, + "CIN52": { + "direction": "input", + "bits": [ 270 ] + }, + "CIN51": { + "direction": "input", + "bits": [ 271 ] + }, + "CIN50": { + "direction": "input", + "bits": [ 272 ] + }, + "CIN49": { + "direction": "input", + "bits": [ 273 ] + }, + "CIN48": { + "direction": "input", + "bits": [ 274 ] + }, + "CIN47": { + "direction": "input", + "bits": [ 275 ] + }, + "CIN46": { + "direction": "input", + "bits": [ 276 ] + }, + "CIN45": { + "direction": "input", + "bits": [ 277 ] + }, + "CIN44": { + "direction": "input", + "bits": [ 278 ] + }, + "CIN43": { + "direction": "input", + "bits": [ 279 ] + }, + "CIN42": { + "direction": "input", + "bits": [ 280 ] + }, + "CIN41": { + "direction": "input", + "bits": [ 281 ] + }, + "CIN40": { + "direction": "input", + "bits": [ 282 ] + }, + "CIN39": { + "direction": "input", + "bits": [ 283 ] + }, + "CIN38": { + "direction": "input", + "bits": [ 284 ] + }, + "CIN37": { + "direction": "input", + "bits": [ 285 ] + }, + "CIN36": { + "direction": "input", + "bits": [ 286 ] + }, + "CIN35": { + "direction": "input", + "bits": [ 287 ] + }, + "CIN34": { + "direction": "input", + "bits": [ 288 ] + }, + "CIN33": { + "direction": "input", + "bits": [ 289 ] + }, + "CIN32": { + "direction": "input", + "bits": [ 290 ] + }, + "CIN31": { + "direction": "input", + "bits": [ 291 ] + }, + "CIN30": { + "direction": "input", + "bits": [ 292 ] + }, + "CIN29": { + "direction": "input", + "bits": [ 293 ] + }, + "CIN28": { + "direction": "input", + "bits": [ 294 ] + }, + "CIN27": { + "direction": "input", + "bits": [ 295 ] + }, + "CIN26": { + "direction": "input", + "bits": [ 296 ] + }, + "CIN25": { + "direction": "input", + "bits": [ 297 ] + }, + "CIN24": { + "direction": "input", + "bits": [ 298 ] + }, + "CIN23": { + "direction": "input", + "bits": [ 299 ] + }, + "CIN22": { + "direction": "input", + "bits": [ 300 ] + }, + "CIN21": { + "direction": "input", + "bits": [ 301 ] + }, + "CIN20": { + "direction": "input", + "bits": [ 302 ] + }, + "CIN19": { + "direction": "input", + "bits": [ 303 ] + }, + "CIN18": { + "direction": "input", + "bits": [ 304 ] + }, + "CIN17": { + "direction": "input", + "bits": [ 305 ] + }, + "CIN16": { + "direction": "input", + "bits": [ 306 ] + }, + "CIN15": { + "direction": "input", + "bits": [ 307 ] + }, + "CIN14": { + "direction": "input", + "bits": [ 308 ] + }, + "CIN13": { + "direction": "input", + "bits": [ 309 ] + }, + "CIN12": { + "direction": "input", + "bits": [ 310 ] + }, + "CIN11": { + "direction": "input", + "bits": [ 311 ] + }, + "CIN10": { + "direction": "input", + "bits": [ 312 ] + }, + "CIN9": { + "direction": "input", + "bits": [ 313 ] + }, + "CIN8": { + "direction": "input", + "bits": [ 314 ] + }, + "CIN7": { + "direction": "input", + "bits": [ 315 ] + }, + "CIN6": { + "direction": "input", + "bits": [ 316 ] + }, + "CIN5": { + "direction": "input", + "bits": [ 317 ] + }, + "CIN4": { + "direction": "input", + "bits": [ 318 ] + }, + "CIN3": { + "direction": "input", + "bits": [ 319 ] + }, + "CIN2": { + "direction": "input", + "bits": [ 320 ] + }, + "CIN1": { + "direction": "input", + "bits": [ 321 ] + }, + "CIN0": { + "direction": "input", + "bits": [ 322 ] + }, + "OP10": { + "direction": "input", + "bits": [ 323 ] + }, + "OP9": { + "direction": "input", + "bits": [ 324 ] + }, + "OP8": { + "direction": "input", + "bits": [ 325 ] + }, + "OP7": { + "direction": "input", + "bits": [ 326 ] + }, + "OP6": { + "direction": "input", + "bits": [ 327 ] + }, + "OP5": { + "direction": "input", + "bits": [ 328 ] + }, + "OP4": { + "direction": "input", + "bits": [ 329 ] + }, + "OP3": { + "direction": "input", + "bits": [ 330 ] + }, + "OP2": { + "direction": "input", + "bits": [ 331 ] + }, + "OP1": { + "direction": "input", + "bits": [ 332 ] + }, + "OP0": { + "direction": "input", + "bits": [ 333 ] + }, + "R53": { + "direction": "output", + "bits": [ 334 ] + }, + "R52": { + "direction": "output", + "bits": [ 335 ] + }, + "R51": { + "direction": "output", + "bits": [ 336 ] + }, + "R50": { + "direction": "output", + "bits": [ 337 ] + }, + "R49": { + "direction": "output", + "bits": [ 338 ] + }, + "R48": { + "direction": "output", + "bits": [ 339 ] + }, + "R47": { + "direction": "output", + "bits": [ 340 ] + }, + "R46": { + "direction": "output", + "bits": [ 341 ] + }, + "R45": { + "direction": "output", + "bits": [ 342 ] + }, + "R44": { + "direction": "output", + "bits": [ 343 ] + }, + "R43": { + "direction": "output", + "bits": [ 344 ] + }, + "R42": { + "direction": "output", + "bits": [ 345 ] + }, + "R41": { + "direction": "output", + "bits": [ 346 ] + }, + "R40": { + "direction": "output", + "bits": [ 347 ] + }, + "R39": { + "direction": "output", + "bits": [ 348 ] + }, + "R38": { + "direction": "output", + "bits": [ 349 ] + }, + "R37": { + "direction": "output", + "bits": [ 350 ] + }, + "R36": { + "direction": "output", + "bits": [ 351 ] + }, + "R35": { + "direction": "output", + "bits": [ 352 ] + }, + "R34": { + "direction": "output", + "bits": [ 353 ] + }, + "R33": { + "direction": "output", + "bits": [ 354 ] + }, + "R32": { + "direction": "output", + "bits": [ 355 ] + }, + "R31": { + "direction": "output", + "bits": [ 356 ] + }, + "R30": { + "direction": "output", + "bits": [ 357 ] + }, + "R29": { + "direction": "output", + "bits": [ 358 ] + }, + "R28": { + "direction": "output", + "bits": [ 359 ] + }, + "R27": { + "direction": "output", + "bits": [ 360 ] + }, + "R26": { + "direction": "output", + "bits": [ 361 ] + }, + "R25": { + "direction": "output", + "bits": [ 362 ] + }, + "R24": { + "direction": "output", + "bits": [ 363 ] + }, + "R23": { + "direction": "output", + "bits": [ 364 ] + }, + "R22": { + "direction": "output", + "bits": [ 365 ] + }, + "R21": { + "direction": "output", + "bits": [ 366 ] + }, + "R20": { + "direction": "output", + "bits": [ 367 ] + }, + "R19": { + "direction": "output", + "bits": [ 368 ] + }, + "R18": { + "direction": "output", + "bits": [ 369 ] + }, + "R17": { + "direction": "output", + "bits": [ 370 ] + }, + "R16": { + "direction": "output", + "bits": [ 371 ] + }, + "R15": { + "direction": "output", + "bits": [ 372 ] + }, + "R14": { + "direction": "output", + "bits": [ 373 ] + }, + "R13": { + "direction": "output", + "bits": [ 374 ] + }, + "R12": { + "direction": "output", + "bits": [ 375 ] + }, + "R11": { + "direction": "output", + "bits": [ 376 ] + }, + "R10": { + "direction": "output", + "bits": [ 377 ] + }, + "R9": { + "direction": "output", + "bits": [ 378 ] + }, + "R8": { + "direction": "output", + "bits": [ 379 ] + }, + "R7": { + "direction": "output", + "bits": [ 380 ] + }, + "R6": { + "direction": "output", + "bits": [ 381 ] + }, + "R5": { + "direction": "output", + "bits": [ 382 ] + }, + "R4": { + "direction": "output", + "bits": [ 383 ] + }, + "R3": { + "direction": "output", + "bits": [ 384 ] + }, + "R2": { + "direction": "output", + "bits": [ 385 ] + }, + "R1": { + "direction": "output", + "bits": [ 386 ] + }, + "R0": { + "direction": "output", + "bits": [ 387 ] + }, + "CO53": { + "direction": "output", + "bits": [ 388 ] + }, + "CO52": { + "direction": "output", + "bits": [ 389 ] + }, + "CO51": { + "direction": "output", + "bits": [ 390 ] + }, + "CO50": { + "direction": "output", + "bits": [ 391 ] + }, + "CO49": { + "direction": "output", + "bits": [ 392 ] + }, + "CO48": { + "direction": "output", + "bits": [ 393 ] + }, + "CO47": { + "direction": "output", + "bits": [ 394 ] + }, + "CO46": { + "direction": "output", + "bits": [ 395 ] + }, + "CO45": { + "direction": "output", + "bits": [ 396 ] + }, + "CO44": { + "direction": "output", + "bits": [ 397 ] + }, + "CO43": { + "direction": "output", + "bits": [ 398 ] + }, + "CO42": { + "direction": "output", + "bits": [ 399 ] + }, + "CO41": { + "direction": "output", + "bits": [ 400 ] + }, + "CO40": { + "direction": "output", + "bits": [ 401 ] + }, + "CO39": { + "direction": "output", + "bits": [ 402 ] + }, + "CO38": { + "direction": "output", + "bits": [ 403 ] + }, + "CO37": { + "direction": "output", + "bits": [ 404 ] + }, + "CO36": { + "direction": "output", + "bits": [ 405 ] + }, + "CO35": { + "direction": "output", + "bits": [ 406 ] + }, + "CO34": { + "direction": "output", + "bits": [ 407 ] + }, + "CO33": { + "direction": "output", + "bits": [ 408 ] + }, + "CO32": { + "direction": "output", + "bits": [ 409 ] + }, + "CO31": { + "direction": "output", + "bits": [ 410 ] + }, + "CO30": { + "direction": "output", + "bits": [ 411 ] + }, + "CO29": { + "direction": "output", + "bits": [ 412 ] + }, + "CO28": { + "direction": "output", + "bits": [ 413 ] + }, + "CO27": { + "direction": "output", + "bits": [ 414 ] + }, + "CO26": { + "direction": "output", + "bits": [ 415 ] + }, + "CO25": { + "direction": "output", + "bits": [ 416 ] + }, + "CO24": { + "direction": "output", + "bits": [ 417 ] + }, + "CO23": { + "direction": "output", + "bits": [ 418 ] + }, + "CO22": { + "direction": "output", + "bits": [ 419 ] + }, + "CO21": { + "direction": "output", + "bits": [ 420 ] + }, + "CO20": { + "direction": "output", + "bits": [ 421 ] + }, + "CO19": { + "direction": "output", + "bits": [ 422 ] + }, + "CO18": { + "direction": "output", + "bits": [ 423 ] + }, + "CO17": { + "direction": "output", + "bits": [ 424 ] + }, + "CO16": { + "direction": "output", + "bits": [ 425 ] + }, + "CO15": { + "direction": "output", + "bits": [ 426 ] + }, + "CO14": { + "direction": "output", + "bits": [ 427 ] + }, + "CO13": { + "direction": "output", + "bits": [ 428 ] + }, + "CO12": { + "direction": "output", + "bits": [ 429 ] + }, + "CO11": { + "direction": "output", + "bits": [ 430 ] + }, + "CO10": { + "direction": "output", + "bits": [ 431 ] + }, + "CO9": { + "direction": "output", + "bits": [ 432 ] + }, + "CO8": { + "direction": "output", + "bits": [ 433 ] + }, + "CO7": { + "direction": "output", + "bits": [ 434 ] + }, + "CO6": { + "direction": "output", + "bits": [ 435 ] + }, + "CO5": { + "direction": "output", + "bits": [ 436 ] + }, + "CO4": { + "direction": "output", + "bits": [ 437 ] + }, + "CO3": { + "direction": "output", + "bits": [ 438 ] + }, + "CO2": { + "direction": "output", + "bits": [ 439 ] + }, + "CO1": { + "direction": "output", + "bits": [ 440 ] + }, + "CO0": { + "direction": "output", + "bits": [ 441 ] + }, + "EQZ": { + "direction": "output", + "bits": [ 442 ] + }, + "EQZM": { + "direction": "output", + "bits": [ 443 ] + }, + "EQOM": { + "direction": "output", + "bits": [ 444 ] + }, + "EQPAT": { + "direction": "output", + "bits": [ 445 ] + }, + "EQPATB": { + "direction": "output", + "bits": [ 446 ] + }, + "OVER": { + "direction": "output", + "bits": [ 447 ] + }, + "UNDER": { + "direction": "output", + "bits": [ 448 ] + }, + "OVERUNDER": { + "direction": "output", + "bits": [ 449 ] + }, + "SIGNEDR": { + "direction": "output", + "bits": [ 450 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:608.11-608.13" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:607.11-607.13" + } + }, + "A10": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:598.11-598.14" + } + }, + "A11": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:597.11-597.14" + } + }, + "A12": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:596.11-596.14" + } + }, + "A13": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:595.11-595.14" + } + }, + "A14": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:594.11-594.14" + } + }, + "A15": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:593.11-593.14" + } + }, + "A16": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:592.11-592.14" + } + }, + "A17": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:591.11-591.14" + } + }, + "A18": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:590.11-590.14" + } + }, + "A19": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:589.11-589.14" + } + }, + "A2": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:606.11-606.13" + } + }, + "A20": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:588.11-588.14" + } + }, + "A21": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:587.11-587.14" + } + }, + "A22": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:586.11-586.14" + } + }, + "A23": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:585.11-585.14" + } + }, + "A24": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:584.11-584.14" + } + }, + "A25": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:583.11-583.14" + } + }, + "A26": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:582.11-582.14" + } + }, + "A27": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:581.11-581.14" + } + }, + "A28": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:580.11-580.14" + } + }, + "A29": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:579.11-579.14" + } + }, + "A3": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:605.11-605.13" + } + }, + "A30": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:578.11-578.14" + } + }, + "A31": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:577.11-577.14" + } + }, + "A32": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:576.11-576.14" + } + }, + "A33": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:575.11-575.14" + } + }, + "A34": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:574.11-574.14" + } + }, + "A35": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:573.11-573.14" + } + }, + "A4": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:604.11-604.13" + } + }, + "A5": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:603.11-603.13" + } + }, + "A6": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:602.11-602.13" + } + }, + "A7": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:601.11-601.13" + } + }, + "A8": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:600.11-600.13" + } + }, + "A9": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:599.11-599.13" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:644.11-644.13" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:643.11-643.13" + } + }, + "B10": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:634.11-634.14" + } + }, + "B11": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:633.11-633.14" + } + }, + "B12": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:632.11-632.14" + } + }, + "B13": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:631.11-631.14" + } + }, + "B14": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:630.11-630.14" + } + }, + "B15": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:629.11-629.14" + } + }, + "B16": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:628.11-628.14" + } + }, + "B17": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:627.11-627.14" + } + }, + "B18": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:626.11-626.14" + } + }, + "B19": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:625.11-625.14" + } + }, + "B2": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:642.11-642.13" + } + }, + "B20": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:624.11-624.14" + } + }, + "B21": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:623.11-623.14" + } + }, + "B22": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:622.11-622.14" + } + }, + "B23": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:621.11-621.14" + } + }, + "B24": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:620.11-620.14" + } + }, + "B25": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:619.11-619.14" + } + }, + "B26": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:618.11-618.14" + } + }, + "B27": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:617.11-617.14" + } + }, + "B28": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:616.11-616.14" + } + }, + "B29": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:615.11-615.14" + } + }, + "B3": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:641.11-641.13" + } + }, + "B30": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:614.11-614.14" + } + }, + "B31": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:613.11-613.14" + } + }, + "B32": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:612.11-612.14" + } + }, + "B33": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:611.11-611.14" + } + }, + "B34": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:610.11-610.14" + } + }, + "B35": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:609.11-609.14" + } + }, + "B4": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:640.11-640.13" + } + }, + "B5": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:639.11-639.13" + } + }, + "B6": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:638.11-638.13" + } + }, + "B7": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:637.11-637.13" + } + }, + "B8": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:636.11-636.13" + } + }, + "B9": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:635.11-635.13" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:698.11-698.13" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:697.11-697.13" + } + }, + "C10": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:688.11-688.14" + } + }, + "C11": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:687.11-687.14" + } + }, + "C12": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:686.11-686.14" + } + }, + "C13": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:685.11-685.14" + } + }, + "C14": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:684.11-684.14" + } + }, + "C15": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:683.11-683.14" + } + }, + "C16": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:682.11-682.14" + } + }, + "C17": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:681.11-681.14" + } + }, + "C18": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:680.11-680.14" + } + }, + "C19": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:679.11-679.14" + } + }, + "C2": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:696.11-696.13" + } + }, + "C20": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:678.11-678.14" + } + }, + "C21": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:677.11-677.14" + } + }, + "C22": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:676.11-676.14" + } + }, + "C23": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:675.11-675.14" + } + }, + "C24": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:674.11-674.14" + } + }, + "C25": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:673.11-673.14" + } + }, + "C26": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:672.11-672.14" + } + }, + "C27": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:671.11-671.14" + } + }, + "C28": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:670.11-670.14" + } + }, + "C29": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:669.11-669.14" + } + }, + "C3": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:695.11-695.13" + } + }, + "C30": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:668.11-668.14" + } + }, + "C31": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:667.11-667.14" + } + }, + "C32": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:666.11-666.14" + } + }, + "C33": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:665.11-665.14" + } + }, + "C34": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:664.11-664.14" + } + }, + "C35": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:663.11-663.14" + } + }, + "C36": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:662.11-662.14" + } + }, + "C37": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:661.11-661.14" + } + }, + "C38": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:660.11-660.14" + } + }, + "C39": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:659.11-659.14" + } + }, + "C4": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:694.11-694.13" + } + }, + "C40": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:658.11-658.14" + } + }, + "C41": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:657.11-657.14" + } + }, + "C42": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:656.11-656.14" + } + }, + "C43": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:655.11-655.14" + } + }, + "C44": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:654.11-654.14" + } + }, + "C45": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:653.11-653.14" + } + }, + "C46": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:652.11-652.14" + } + }, + "C47": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:651.11-651.14" + } + }, + "C48": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:650.11-650.14" + } + }, + "C49": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:649.11-649.14" + } + }, + "C5": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:693.11-693.13" + } + }, + "C50": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:648.11-648.14" + } + }, + "C51": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:647.11-647.14" + } + }, + "C52": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:646.11-646.14" + } + }, + "C53": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:645.11-645.14" + } + }, + "C6": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:692.11-692.13" + } + }, + "C7": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:691.11-691.13" + } + }, + "C8": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:690.11-690.13" + } + }, + "C9": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:689.11-689.13" + } + }, + "CE0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:561.11-561.14" + } + }, + "CE1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:560.11-560.14" + } + }, + "CE2": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:559.11-559.14" + } + }, + "CE3": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:558.11-558.14" + } + }, + "CFB0": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:752.11-752.15" + } + }, + "CFB1": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:751.11-751.15" + } + }, + "CFB10": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:742.11-742.16" + } + }, + "CFB11": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:741.11-741.16" + } + }, + "CFB12": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:740.11-740.16" + } + }, + "CFB13": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:739.11-739.16" + } + }, + "CFB14": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:738.11-738.16" + } + }, + "CFB15": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:737.11-737.16" + } + }, + "CFB16": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:736.11-736.16" + } + }, + "CFB17": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:735.11-735.16" + } + }, + "CFB18": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:734.11-734.16" + } + }, + "CFB19": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:733.11-733.16" + } + }, + "CFB2": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:750.11-750.15" + } + }, + "CFB20": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:732.11-732.16" + } + }, + "CFB21": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:731.11-731.16" + } + }, + "CFB22": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:730.11-730.16" + } + }, + "CFB23": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:729.11-729.16" + } + }, + "CFB24": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:728.11-728.16" + } + }, + "CFB25": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:727.11-727.16" + } + }, + "CFB26": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:726.11-726.16" + } + }, + "CFB27": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:725.11-725.16" + } + }, + "CFB28": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:724.11-724.16" + } + }, + "CFB29": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:723.11-723.16" + } + }, + "CFB3": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:749.11-749.15" + } + }, + "CFB30": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:722.11-722.16" + } + }, + "CFB31": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:721.11-721.16" + } + }, + "CFB32": { + "hide_name": 0, + "bits": [ 164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:720.11-720.16" + } + }, + "CFB33": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:719.11-719.16" + } + }, + "CFB34": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:718.11-718.16" + } + }, + "CFB35": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:717.11-717.16" + } + }, + "CFB36": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:716.11-716.16" + } + }, + "CFB37": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:715.11-715.16" + } + }, + "CFB38": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:714.11-714.16" + } + }, + "CFB39": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:713.11-713.16" + } + }, + "CFB4": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:748.11-748.15" + } + }, + "CFB40": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:712.11-712.16" + } + }, + "CFB41": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:711.11-711.16" + } + }, + "CFB42": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:710.11-710.16" + } + }, + "CFB43": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:709.11-709.16" + } + }, + "CFB44": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:708.11-708.16" + } + }, + "CFB45": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:707.11-707.16" + } + }, + "CFB46": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:706.11-706.16" + } + }, + "CFB47": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:705.11-705.16" + } + }, + "CFB48": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:704.11-704.16" + } + }, + "CFB49": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:703.11-703.16" + } + }, + "CFB5": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:747.11-747.15" + } + }, + "CFB50": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:702.11-702.16" + } + }, + "CFB51": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:701.11-701.16" + } + }, + "CFB52": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:700.11-700.16" + } + }, + "CFB53": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:699.11-699.16" + } + }, + "CFB6": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:746.11-746.15" + } + }, + "CFB7": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:745.11-745.15" + } + }, + "CFB8": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:744.11-744.15" + } + }, + "CFB9": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:743.11-743.15" + } + }, + "CIN0": { + "hide_name": 0, + "bits": [ 322 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:878.11-878.15" + } + }, + "CIN1": { + "hide_name": 0, + "bits": [ 321 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:877.11-877.15" + } + }, + "CIN10": { + "hide_name": 0, + "bits": [ 312 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:868.11-868.16" + } + }, + "CIN11": { + "hide_name": 0, + "bits": [ 311 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:867.11-867.16" + } + }, + "CIN12": { + "hide_name": 0, + "bits": [ 310 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:866.11-866.16" + } + }, + "CIN13": { + "hide_name": 0, + "bits": [ 309 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:865.11-865.16" + } + }, + "CIN14": { + "hide_name": 0, + "bits": [ 308 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:864.11-864.16" + } + }, + "CIN15": { + "hide_name": 0, + "bits": [ 307 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:863.11-863.16" + } + }, + "CIN16": { + "hide_name": 0, + "bits": [ 306 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:862.11-862.16" + } + }, + "CIN17": { + "hide_name": 0, + "bits": [ 305 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:861.11-861.16" + } + }, + "CIN18": { + "hide_name": 0, + "bits": [ 304 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:860.11-860.16" + } + }, + "CIN19": { + "hide_name": 0, + "bits": [ 303 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:859.11-859.16" + } + }, + "CIN2": { + "hide_name": 0, + "bits": [ 320 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:876.11-876.15" + } + }, + "CIN20": { + "hide_name": 0, + "bits": [ 302 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:858.11-858.16" + } + }, + "CIN21": { + "hide_name": 0, + "bits": [ 301 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:857.11-857.16" + } + }, + "CIN22": { + "hide_name": 0, + "bits": [ 300 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:856.11-856.16" + } + }, + "CIN23": { + "hide_name": 0, + "bits": [ 299 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:855.11-855.16" + } + }, + "CIN24": { + "hide_name": 0, + "bits": [ 298 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:854.11-854.16" + } + }, + "CIN25": { + "hide_name": 0, + "bits": [ 297 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:853.11-853.16" + } + }, + "CIN26": { + "hide_name": 0, + "bits": [ 296 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:852.11-852.16" + } + }, + "CIN27": { + "hide_name": 0, + "bits": [ 295 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:851.11-851.16" + } + }, + "CIN28": { + "hide_name": 0, + "bits": [ 294 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:850.11-850.16" + } + }, + "CIN29": { + "hide_name": 0, + "bits": [ 293 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:849.11-849.16" + } + }, + "CIN3": { + "hide_name": 0, + "bits": [ 319 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:875.11-875.15" + } + }, + "CIN30": { + "hide_name": 0, + "bits": [ 292 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:848.11-848.16" + } + }, + "CIN31": { + "hide_name": 0, + "bits": [ 291 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:847.11-847.16" + } + }, + "CIN32": { + "hide_name": 0, + "bits": [ 290 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:846.11-846.16" + } + }, + "CIN33": { + "hide_name": 0, + "bits": [ 289 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:845.11-845.16" + } + }, + "CIN34": { + "hide_name": 0, + "bits": [ 288 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:844.11-844.16" + } + }, + "CIN35": { + "hide_name": 0, + "bits": [ 287 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:843.11-843.16" + } + }, + "CIN36": { + "hide_name": 0, + "bits": [ 286 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:842.11-842.16" + } + }, + "CIN37": { + "hide_name": 0, + "bits": [ 285 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:841.11-841.16" + } + }, + "CIN38": { + "hide_name": 0, + "bits": [ 284 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:840.11-840.16" + } + }, + "CIN39": { + "hide_name": 0, + "bits": [ 283 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:839.11-839.16" + } + }, + "CIN4": { + "hide_name": 0, + "bits": [ 318 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:874.11-874.15" + } + }, + "CIN40": { + "hide_name": 0, + "bits": [ 282 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:838.11-838.16" + } + }, + "CIN41": { + "hide_name": 0, + "bits": [ 281 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:837.11-837.16" + } + }, + "CIN42": { + "hide_name": 0, + "bits": [ 280 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:836.11-836.16" + } + }, + "CIN43": { + "hide_name": 0, + "bits": [ 279 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:835.11-835.16" + } + }, + "CIN44": { + "hide_name": 0, + "bits": [ 278 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:834.11-834.16" + } + }, + "CIN45": { + "hide_name": 0, + "bits": [ 277 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:833.11-833.16" + } + }, + "CIN46": { + "hide_name": 0, + "bits": [ 276 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:832.11-832.16" + } + }, + "CIN47": { + "hide_name": 0, + "bits": [ 275 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:831.11-831.16" + } + }, + "CIN48": { + "hide_name": 0, + "bits": [ 274 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:830.11-830.16" + } + }, + "CIN49": { + "hide_name": 0, + "bits": [ 273 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:829.11-829.16" + } + }, + "CIN5": { + "hide_name": 0, + "bits": [ 317 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:873.11-873.15" + } + }, + "CIN50": { + "hide_name": 0, + "bits": [ 272 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:828.11-828.16" + } + }, + "CIN51": { + "hide_name": 0, + "bits": [ 271 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:827.11-827.16" + } + }, + "CIN52": { + "hide_name": 0, + "bits": [ 270 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:826.11-826.16" + } + }, + "CIN53": { + "hide_name": 0, + "bits": [ 269 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:825.11-825.16" + } + }, + "CIN6": { + "hide_name": 0, + "bits": [ 316 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:872.11-872.15" + } + }, + "CIN7": { + "hide_name": 0, + "bits": [ 315 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:871.11-871.15" + } + }, + "CIN8": { + "hide_name": 0, + "bits": [ 314 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:870.11-870.15" + } + }, + "CIN9": { + "hide_name": 0, + "bits": [ 313 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:869.11-869.15" + } + }, + "CLK0": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:565.11-565.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:564.11-564.15" + } + }, + "CLK2": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:563.11-563.15" + } + }, + "CLK3": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:562.11-562.15" + } + }, + "CO0": { + "hide_name": 0, + "bits": [ 441 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:997.12-997.15" + } + }, + "CO1": { + "hide_name": 0, + "bits": [ 440 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:996.12-996.15" + } + }, + "CO10": { + "hide_name": 0, + "bits": [ 431 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:987.12-987.16" + } + }, + "CO11": { + "hide_name": 0, + "bits": [ 430 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:986.12-986.16" + } + }, + "CO12": { + "hide_name": 0, + "bits": [ 429 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:985.12-985.16" + } + }, + "CO13": { + "hide_name": 0, + "bits": [ 428 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:984.12-984.16" + } + }, + "CO14": { + "hide_name": 0, + "bits": [ 427 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:983.12-983.16" + } + }, + "CO15": { + "hide_name": 0, + "bits": [ 426 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:982.12-982.16" + } + }, + "CO16": { + "hide_name": 0, + "bits": [ 425 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:981.12-981.16" + } + }, + "CO17": { + "hide_name": 0, + "bits": [ 424 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:980.12-980.16" + } + }, + "CO18": { + "hide_name": 0, + "bits": [ 423 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:979.12-979.16" + } + }, + "CO19": { + "hide_name": 0, + "bits": [ 422 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:978.12-978.16" + } + }, + "CO2": { + "hide_name": 0, + "bits": [ 439 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:995.12-995.15" + } + }, + "CO20": { + "hide_name": 0, + "bits": [ 421 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:977.12-977.16" + } + }, + "CO21": { + "hide_name": 0, + "bits": [ 420 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:976.12-976.16" + } + }, + "CO22": { + "hide_name": 0, + "bits": [ 419 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:975.12-975.16" + } + }, + "CO23": { + "hide_name": 0, + "bits": [ 418 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:974.12-974.16" + } + }, + "CO24": { + "hide_name": 0, + "bits": [ 417 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:973.12-973.16" + } + }, + "CO25": { + "hide_name": 0, + "bits": [ 416 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:972.12-972.16" + } + }, + "CO26": { + "hide_name": 0, + "bits": [ 415 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:971.12-971.16" + } + }, + "CO27": { + "hide_name": 0, + "bits": [ 414 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:970.12-970.16" + } + }, + "CO28": { + "hide_name": 0, + "bits": [ 413 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:969.12-969.16" + } + }, + "CO29": { + "hide_name": 0, + "bits": [ 412 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:968.12-968.16" + } + }, + "CO3": { + "hide_name": 0, + "bits": [ 438 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:994.12-994.15" + } + }, + "CO30": { + "hide_name": 0, + "bits": [ 411 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:967.12-967.16" + } + }, + "CO31": { + "hide_name": 0, + "bits": [ 410 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:966.12-966.16" + } + }, + "CO32": { + "hide_name": 0, + "bits": [ 409 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:965.12-965.16" + } + }, + "CO33": { + "hide_name": 0, + "bits": [ 408 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:964.12-964.16" + } + }, + "CO34": { + "hide_name": 0, + "bits": [ 407 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:963.12-963.16" + } + }, + "CO35": { + "hide_name": 0, + "bits": [ 406 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:962.12-962.16" + } + }, + "CO36": { + "hide_name": 0, + "bits": [ 405 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:961.12-961.16" + } + }, + "CO37": { + "hide_name": 0, + "bits": [ 404 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:960.12-960.16" + } + }, + "CO38": { + "hide_name": 0, + "bits": [ 403 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:959.12-959.16" + } + }, + "CO39": { + "hide_name": 0, + "bits": [ 402 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:958.12-958.16" + } + }, + "CO4": { + "hide_name": 0, + "bits": [ 437 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:993.12-993.15" + } + }, + "CO40": { + "hide_name": 0, + "bits": [ 401 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:957.12-957.16" + } + }, + "CO41": { + "hide_name": 0, + "bits": [ 400 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:956.12-956.16" + } + }, + "CO42": { + "hide_name": 0, + "bits": [ 399 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:955.12-955.16" + } + }, + "CO43": { + "hide_name": 0, + "bits": [ 398 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:954.12-954.16" + } + }, + "CO44": { + "hide_name": 0, + "bits": [ 397 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:953.12-953.16" + } + }, + "CO45": { + "hide_name": 0, + "bits": [ 396 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:952.12-952.16" + } + }, + "CO46": { + "hide_name": 0, + "bits": [ 395 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:951.12-951.16" + } + }, + "CO47": { + "hide_name": 0, + "bits": [ 394 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:950.12-950.16" + } + }, + "CO48": { + "hide_name": 0, + "bits": [ 393 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:949.12-949.16" + } + }, + "CO49": { + "hide_name": 0, + "bits": [ 392 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:948.12-948.16" + } + }, + "CO5": { + "hide_name": 0, + "bits": [ 436 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:992.12-992.15" + } + }, + "CO50": { + "hide_name": 0, + "bits": [ 391 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:947.12-947.16" + } + }, + "CO51": { + "hide_name": 0, + "bits": [ 390 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:946.12-946.16" + } + }, + "CO52": { + "hide_name": 0, + "bits": [ 389 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:945.12-945.16" + } + }, + "CO53": { + "hide_name": 0, + "bits": [ 388 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:944.12-944.16" + } + }, + "CO6": { + "hide_name": 0, + "bits": [ 435 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:991.12-991.15" + } + }, + "CO7": { + "hide_name": 0, + "bits": [ 434 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:990.12-990.15" + } + }, + "CO8": { + "hide_name": 0, + "bits": [ 433 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:989.12-989.15" + } + }, + "CO9": { + "hide_name": 0, + "bits": [ 432 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:988.12-988.15" + } + }, + "EQOM": { + "hide_name": 0, + "bits": [ 444 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1000.12-1000.16" + } + }, + "EQPAT": { + "hide_name": 0, + "bits": [ 445 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1001.12-1001.17" + } + }, + "EQPATB": { + "hide_name": 0, + "bits": [ 446 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1002.12-1002.18" + } + }, + "EQZ": { + "hide_name": 0, + "bits": [ 442 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:998.12-998.15" + } + }, + "EQZM": { + "hide_name": 0, + "bits": [ 443 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:999.12-999.16" + } + }, + "MA0": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:788.11-788.14" + } + }, + "MA1": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:787.11-787.14" + } + }, + "MA10": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:778.11-778.15" + } + }, + "MA11": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:777.11-777.15" + } + }, + "MA12": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:776.11-776.15" + } + }, + "MA13": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:775.11-775.15" + } + }, + "MA14": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:774.11-774.15" + } + }, + "MA15": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:773.11-773.15" + } + }, + "MA16": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:772.11-772.15" + } + }, + "MA17": { + "hide_name": 0, + "bits": [ 215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:771.11-771.15" + } + }, + "MA18": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:770.11-770.15" + } + }, + "MA19": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:769.11-769.15" + } + }, + "MA2": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:786.11-786.14" + } + }, + "MA20": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:768.11-768.15" + } + }, + "MA21": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:767.11-767.15" + } + }, + "MA22": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:766.11-766.15" + } + }, + "MA23": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:765.11-765.15" + } + }, + "MA24": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:764.11-764.15" + } + }, + "MA25": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:763.11-763.15" + } + }, + "MA26": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:762.11-762.15" + } + }, + "MA27": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:761.11-761.15" + } + }, + "MA28": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:760.11-760.15" + } + }, + "MA29": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:759.11-759.15" + } + }, + "MA3": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:785.11-785.14" + } + }, + "MA30": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:758.11-758.15" + } + }, + "MA31": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:757.11-757.15" + } + }, + "MA32": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:756.11-756.15" + } + }, + "MA33": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:755.11-755.15" + } + }, + "MA34": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:754.11-754.15" + } + }, + "MA35": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:753.11-753.15" + } + }, + "MA4": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:784.11-784.14" + } + }, + "MA5": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:783.11-783.14" + } + }, + "MA6": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:782.11-782.14" + } + }, + "MA7": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:781.11-781.14" + } + }, + "MA8": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:780.11-780.14" + } + }, + "MA9": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:779.11-779.14" + } + }, + "MB0": { + "hide_name": 0, + "bits": [ 268 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:824.11-824.14" + } + }, + "MB1": { + "hide_name": 0, + "bits": [ 267 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:823.11-823.14" + } + }, + "MB10": { + "hide_name": 0, + "bits": [ 258 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:814.11-814.15" + } + }, + "MB11": { + "hide_name": 0, + "bits": [ 257 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:813.11-813.15" + } + }, + "MB12": { + "hide_name": 0, + "bits": [ 256 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:812.11-812.15" + } + }, + "MB13": { + "hide_name": 0, + "bits": [ 255 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:811.11-811.15" + } + }, + "MB14": { + "hide_name": 0, + "bits": [ 254 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:810.11-810.15" + } + }, + "MB15": { + "hide_name": 0, + "bits": [ 253 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:809.11-809.15" + } + }, + "MB16": { + "hide_name": 0, + "bits": [ 252 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:808.11-808.15" + } + }, + "MB17": { + "hide_name": 0, + "bits": [ 251 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:807.11-807.15" + } + }, + "MB18": { + "hide_name": 0, + "bits": [ 250 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:806.11-806.15" + } + }, + "MB19": { + "hide_name": 0, + "bits": [ 249 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:805.11-805.15" + } + }, + "MB2": { + "hide_name": 0, + "bits": [ 266 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:822.11-822.14" + } + }, + "MB20": { + "hide_name": 0, + "bits": [ 248 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:804.11-804.15" + } + }, + "MB21": { + "hide_name": 0, + "bits": [ 247 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:803.11-803.15" + } + }, + "MB22": { + "hide_name": 0, + "bits": [ 246 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:802.11-802.15" + } + }, + "MB23": { + "hide_name": 0, + "bits": [ 245 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:801.11-801.15" + } + }, + "MB24": { + "hide_name": 0, + "bits": [ 244 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:800.11-800.15" + } + }, + "MB25": { + "hide_name": 0, + "bits": [ 243 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:799.11-799.15" + } + }, + "MB26": { + "hide_name": 0, + "bits": [ 242 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:798.11-798.15" + } + }, + "MB27": { + "hide_name": 0, + "bits": [ 241 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:797.11-797.15" + } + }, + "MB28": { + "hide_name": 0, + "bits": [ 240 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:796.11-796.15" + } + }, + "MB29": { + "hide_name": 0, + "bits": [ 239 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:795.11-795.15" + } + }, + "MB3": { + "hide_name": 0, + "bits": [ 265 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:821.11-821.14" + } + }, + "MB30": { + "hide_name": 0, + "bits": [ 238 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:794.11-794.15" + } + }, + "MB31": { + "hide_name": 0, + "bits": [ 237 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:793.11-793.15" + } + }, + "MB32": { + "hide_name": 0, + "bits": [ 236 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:792.11-792.15" + } + }, + "MB33": { + "hide_name": 0, + "bits": [ 235 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:791.11-791.15" + } + }, + "MB34": { + "hide_name": 0, + "bits": [ 234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:790.11-790.15" + } + }, + "MB35": { + "hide_name": 0, + "bits": [ 233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:789.11-789.15" + } + }, + "MB4": { + "hide_name": 0, + "bits": [ 264 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:820.11-820.14" + } + }, + "MB5": { + "hide_name": 0, + "bits": [ 263 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:819.11-819.14" + } + }, + "MB6": { + "hide_name": 0, + "bits": [ 262 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:818.11-818.14" + } + }, + "MB7": { + "hide_name": 0, + "bits": [ 261 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:817.11-817.14" + } + }, + "MB8": { + "hide_name": 0, + "bits": [ 260 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:816.11-816.14" + } + }, + "MB9": { + "hide_name": 0, + "bits": [ 259 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:815.11-815.14" + } + }, + "OP0": { + "hide_name": 0, + "bits": [ 333 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:889.11-889.14" + } + }, + "OP1": { + "hide_name": 0, + "bits": [ 332 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:888.11-888.14" + } + }, + "OP10": { + "hide_name": 0, + "bits": [ 323 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:879.11-879.15" + } + }, + "OP2": { + "hide_name": 0, + "bits": [ 331 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:887.11-887.14" + } + }, + "OP3": { + "hide_name": 0, + "bits": [ 330 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:886.11-886.14" + } + }, + "OP4": { + "hide_name": 0, + "bits": [ 329 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:885.11-885.14" + } + }, + "OP5": { + "hide_name": 0, + "bits": [ 328 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:884.11-884.14" + } + }, + "OP6": { + "hide_name": 0, + "bits": [ 327 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:883.11-883.14" + } + }, + "OP7": { + "hide_name": 0, + "bits": [ 326 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:882.11-882.14" + } + }, + "OP8": { + "hide_name": 0, + "bits": [ 325 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:881.11-881.14" + } + }, + "OP9": { + "hide_name": 0, + "bits": [ 324 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:880.11-880.14" + } + }, + "OVER": { + "hide_name": 0, + "bits": [ 447 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1003.12-1003.16" + } + }, + "OVERUNDER": { + "hide_name": 0, + "bits": [ 449 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1005.12-1005.21" + } + }, + "R0": { + "hide_name": 0, + "bits": [ 387 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:943.12-943.14" + } + }, + "R1": { + "hide_name": 0, + "bits": [ 386 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:942.12-942.14" + } + }, + "R10": { + "hide_name": 0, + "bits": [ 377 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:933.12-933.15" + } + }, + "R11": { + "hide_name": 0, + "bits": [ 376 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:932.12-932.15" + } + }, + "R12": { + "hide_name": 0, + "bits": [ 375 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:931.12-931.15" + } + }, + "R13": { + "hide_name": 0, + "bits": [ 374 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:930.12-930.15" + } + }, + "R14": { + "hide_name": 0, + "bits": [ 373 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:929.12-929.15" + } + }, + "R15": { + "hide_name": 0, + "bits": [ 372 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:928.12-928.15" + } + }, + "R16": { + "hide_name": 0, + "bits": [ 371 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:927.12-927.15" + } + }, + "R17": { + "hide_name": 0, + "bits": [ 370 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:926.12-926.15" + } + }, + "R18": { + "hide_name": 0, + "bits": [ 369 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:925.12-925.15" + } + }, + "R19": { + "hide_name": 0, + "bits": [ 368 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:924.12-924.15" + } + }, + "R2": { + "hide_name": 0, + "bits": [ 385 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:941.12-941.14" + } + }, + "R20": { + "hide_name": 0, + "bits": [ 367 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:923.12-923.15" + } + }, + "R21": { + "hide_name": 0, + "bits": [ 366 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:922.12-922.15" + } + }, + "R22": { + "hide_name": 0, + "bits": [ 365 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:921.12-921.15" + } + }, + "R23": { + "hide_name": 0, + "bits": [ 364 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:920.12-920.15" + } + }, + "R24": { + "hide_name": 0, + "bits": [ 363 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:919.12-919.15" + } + }, + "R25": { + "hide_name": 0, + "bits": [ 362 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:918.12-918.15" + } + }, + "R26": { + "hide_name": 0, + "bits": [ 361 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:917.12-917.15" + } + }, + "R27": { + "hide_name": 0, + "bits": [ 360 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:916.12-916.15" + } + }, + "R28": { + "hide_name": 0, + "bits": [ 359 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:915.12-915.15" + } + }, + "R29": { + "hide_name": 0, + "bits": [ 358 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:914.12-914.15" + } + }, + "R3": { + "hide_name": 0, + "bits": [ 384 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:940.12-940.14" + } + }, + "R30": { + "hide_name": 0, + "bits": [ 357 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:913.12-913.15" + } + }, + "R31": { + "hide_name": 0, + "bits": [ 356 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:912.12-912.15" + } + }, + "R32": { + "hide_name": 0, + "bits": [ 355 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:911.12-911.15" + } + }, + "R33": { + "hide_name": 0, + "bits": [ 354 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:910.12-910.15" + } + }, + "R34": { + "hide_name": 0, + "bits": [ 353 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:909.12-909.15" + } + }, + "R35": { + "hide_name": 0, + "bits": [ 352 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:908.12-908.15" + } + }, + "R36": { + "hide_name": 0, + "bits": [ 351 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:907.12-907.15" + } + }, + "R37": { + "hide_name": 0, + "bits": [ 350 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:906.12-906.15" + } + }, + "R38": { + "hide_name": 0, + "bits": [ 349 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:905.12-905.15" + } + }, + "R39": { + "hide_name": 0, + "bits": [ 348 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:904.12-904.15" + } + }, + "R4": { + "hide_name": 0, + "bits": [ 383 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:939.12-939.14" + } + }, + "R40": { + "hide_name": 0, + "bits": [ 347 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:903.12-903.15" + } + }, + "R41": { + "hide_name": 0, + "bits": [ 346 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:902.12-902.15" + } + }, + "R42": { + "hide_name": 0, + "bits": [ 345 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:901.12-901.15" + } + }, + "R43": { + "hide_name": 0, + "bits": [ 344 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:900.12-900.15" + } + }, + "R44": { + "hide_name": 0, + "bits": [ 343 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:899.12-899.15" + } + }, + "R45": { + "hide_name": 0, + "bits": [ 342 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:898.12-898.15" + } + }, + "R46": { + "hide_name": 0, + "bits": [ 341 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:897.12-897.15" + } + }, + "R47": { + "hide_name": 0, + "bits": [ 340 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:896.12-896.15" + } + }, + "R48": { + "hide_name": 0, + "bits": [ 339 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:895.12-895.15" + } + }, + "R49": { + "hide_name": 0, + "bits": [ 338 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:894.12-894.15" + } + }, + "R5": { + "hide_name": 0, + "bits": [ 382 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:938.12-938.14" + } + }, + "R50": { + "hide_name": 0, + "bits": [ 337 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:893.12-893.15" + } + }, + "R51": { + "hide_name": 0, + "bits": [ 336 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:892.12-892.15" + } + }, + "R52": { + "hide_name": 0, + "bits": [ 335 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:891.12-891.15" + } + }, + "R53": { + "hide_name": 0, + "bits": [ 334 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:890.12-890.15" + } + }, + "R6": { + "hide_name": 0, + "bits": [ 381 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:937.12-937.14" + } + }, + "R7": { + "hide_name": 0, + "bits": [ 380 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:936.12-936.14" + } + }, + "R8": { + "hide_name": 0, + "bits": [ 379 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:935.12-935.14" + } + }, + "R9": { + "hide_name": 0, + "bits": [ 378 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:934.12-934.14" + } + }, + "RST0": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:569.11-569.15" + } + }, + "RST1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:568.11-568.15" + } + }, + "RST2": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:567.11-567.15" + } + }, + "RST3": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:566.11-566.15" + } + }, + "SIGNEDCIN": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:572.11-572.20" + } + }, + "SIGNEDIA": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:570.11-570.19" + } + }, + "SIGNEDIB": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:571.11-571.19" + } + }, + "SIGNEDR": { + "hide_name": 0, + "bits": [ 450 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1006.12-1006.19" + } + }, + "UNDER": { + "hide_name": 0, + "bits": [ 448 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1004.12-1004.17" + } + } + } + }, + "BB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + }, + "B": { + "direction": "inout", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.68-10.69" + } + }, + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.20-10.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.34-10.35" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.23-10.24" + } + } + } + }, + "BBPD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + }, + "B": { + "direction": "inout", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.68-12.69" + } + }, + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.20-12.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.34-12.35" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.23-12.24" + } + } + } + }, + "BBPU": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + }, + "B": { + "direction": "inout", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.68-11.69" + } + }, + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.20-11.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.34-11.35" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.23-11.24" + } + } + } + }, + "CCU2C": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "abc9_box_id": "00000000000000000000000000000101", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:3.1-61.10" + }, + "parameter_default_values": { + "INIT0": "0000000000000000", + "INIT1": "0000000000000000", + "INJECT1_0": "YES", + "INJECT1_1": "YES" + }, + "ports": { + "CIN": { + "direction": "input", + "bits": [ 2 ] + }, + "A0": { + "direction": "input", + "bits": [ 3 ] + }, + "B0": { + "direction": "input", + "bits": [ 4 ] + }, + "C0": { + "direction": "input", + "bits": [ 5 ] + }, + "D0": { + "direction": "input", + "bits": [ 6 ] + }, + "A1": { + "direction": "input", + "bits": [ 7 ] + }, + "B1": { + "direction": "input", + "bits": [ 8 ] + }, + "C1": { + "direction": "input", + "bits": [ 9 ] + }, + "D1": { + "direction": "input", + "bits": [ 10 ] + }, + "S0": { + "direction": "output", + "bits": [ 11 ] + }, + "S1": { + "direction": "output", + "bits": [ 12 ] + }, + "COUT": { + "direction": "output", + "bits": [ 13 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.9-6.11" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.25-6.27" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.13-6.15" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.29-6.31" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.17-6.19" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.33-6.35" + } + }, + "CIN": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:5.9-5.12" + } + }, + "COUT": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "D0": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.21-6.23" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.37-6.39" + } + }, + "S0": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.9-7.11" + } + }, + "S1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.13-7.15" + } + } + } + }, + "CLKDIVF": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1010.1-1017.10" + }, + "parameter_default_values": { + "DIV": "2.0", + "GSR": "DISABLED" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "ALIGNWD": { + "direction": "input", + "bits": [ 4 ] + }, + "CDIVX": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "ALIGNWD": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1015.11-1015.18" + } + }, + "CDIVX": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1016.12-1016.17" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1013.11-1013.15" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1014.11-1014.14" + } + } + } + }, + "DCCA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1043.1-1047.10" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "CE": { + "direction": "input", + "bits": [ 3 ] + }, + "CLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "CE": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1045.11-1045.13" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1044.11-1044.15" + } + }, + "CLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1046.12-1046.16" + } + } + } + }, + "DCSC": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1032.1-1040.10" + }, + "parameter_default_values": { + "DCSMODE": "POS" + }, + "ports": { + "CLK1": { + "direction": "input", + "bits": [ 2 ] + }, + "CLK0": { + "direction": "input", + "bits": [ 3 ] + }, + "SEL1": { + "direction": "input", + "bits": [ 4 ] + }, + "SEL0": { + "direction": "input", + "bits": [ 5 ] + }, + "MODESEL": { + "direction": "input", + "bits": [ 6 ] + }, + "DCSOUT": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "CLK0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1035.11-1035.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1034.11-1034.15" + } + }, + "DCSOUT": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1039.12-1039.18" + } + }, + "MODESEL": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1038.11-1038.18" + } + }, + "SEL0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1037.11-1037.15" + } + }, + "SEL1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1036.11-1036.15" + } + } + } + }, + "DCUA": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1456.1-2032.10" + }, + "parameter_default_values": { + "CH0_AUTO_CALIB_EN": "DONTCARE", + "CH0_AUTO_FACQ_EN": "DONTCARE", + "CH0_BAND_THRESHOLD": "DONTCARE", + "CH0_CALIB_CK_MODE": "DONTCARE", + "CH0_CC_MATCH_1": "DONTCARE", + "CH0_CC_MATCH_2": "DONTCARE", + "CH0_CC_MATCH_3": "DONTCARE", + "CH0_CC_MATCH_4": "DONTCARE", + "CH0_CDR_CNT4SEL": "DONTCARE", + "CH0_CDR_CNT8SEL": "DONTCARE", + "CH0_CDR_MAX_RATE": "DONTCARE", + "CH0_CTC_BYPASS": "DONTCARE", + "CH0_DCOATDCFG": "DONTCARE", + "CH0_DCOATDDLY": "DONTCARE", + "CH0_DCOBYPSATD": "DONTCARE", + "CH0_DCOCALDIV": "DONTCARE", + "CH0_DCOCTLGI": "DONTCARE", + "CH0_DCODISBDAVOID": "DONTCARE", + "CH0_DCOFLTDAC": "DONTCARE", + "CH0_DCOFTNRG": "DONTCARE", + "CH0_DCOIOSTUNE": "DONTCARE", + "CH0_DCOITUNE": "DONTCARE", + "CH0_DCOITUNE4LSB": "DONTCARE", + "CH0_DCOIUPDNX2": "DONTCARE", + "CH0_DCONUOFLSB": "DONTCARE", + "CH0_DCOSCALEI": "DONTCARE", + "CH0_DCOSTARTVAL": "DONTCARE", + "CH0_DCOSTEP": "DONTCARE", + "CH0_DEC_BYPASS": "DONTCARE", + "CH0_ENABLE_CG_ALIGN": "DONTCARE", + "CH0_ENC_BYPASS": "DONTCARE", + "CH0_FF_RX_F_CLK_DIS": "DONTCARE", + "CH0_FF_RX_H_CLK_EN": "DONTCARE", + "CH0_FF_TX_F_CLK_DIS": "DONTCARE", + "CH0_FF_TX_H_CLK_EN": "DONTCARE", + "CH0_GE_AN_ENABLE": "DONTCARE", + "CH0_INVERT_RX": "DONTCARE", + "CH0_INVERT_TX": "DONTCARE", + "CH0_LDR_CORE2TX_SEL": "DONTCARE", + "CH0_LDR_RX2CORE_SEL": "DONTCARE", + "CH0_LEQ_OFFSET_SEL": "DONTCARE", + "CH0_LEQ_OFFSET_TRIM": "DONTCARE", + "CH0_LSM_DISABLE": "DONTCARE", + "CH0_MATCH_2_ENABLE": "DONTCARE", + "CH0_MATCH_4_ENABLE": "DONTCARE", + "CH0_MIN_IPG_CNT": "DONTCARE", + "CH0_PCIE_EI_EN": "DONTCARE", + "CH0_PCIE_MODE": "DONTCARE", + "CH0_PCS_DET_TIME_SEL": "DONTCARE", + "CH0_PDEN_SEL": "DONTCARE", + "CH0_PRBS_ENABLE": "DONTCARE", + "CH0_PRBS_LOCK": "DONTCARE", + "CH0_PRBS_SELECTION": "DONTCARE", + "CH0_PROTOCOL": "DONTCARE", + "CH0_RATE_MODE_RX": "DONTCARE", + "CH0_RATE_MODE_TX": "DONTCARE", + "CH0_RCV_DCC_EN": "DONTCARE", + "CH0_REG_BAND_OFFSET": "DONTCARE", + "CH0_REG_BAND_SEL": "DONTCARE", + "CH0_REG_IDAC_EN": "DONTCARE", + "CH0_REG_IDAC_SEL": "DONTCARE", + "CH0_REQ_EN": "DONTCARE", + "CH0_REQ_LVL_SET": "DONTCARE", + "CH0_RIO_MODE": "DONTCARE", + "CH0_RLOS_SEL": "DONTCARE", + "CH0_RPWDNB": "DONTCARE", + "CH0_RTERM_RX": "DONTCARE", + "CH0_RTERM_TX": "DONTCARE", + "CH0_RXIN_CM": "DONTCARE", + "CH0_RXTERM_CM": "DONTCARE", + "CH0_RX_DCO_CK_DIV": "DONTCARE", + "CH0_RX_DIV11_SEL": "DONTCARE", + "CH0_RX_GEAR_BYPASS": "DONTCARE", + "CH0_RX_GEAR_MODE": "DONTCARE", + "CH0_RX_LOS_CEQ": "DONTCARE", + "CH0_RX_LOS_EN": "DONTCARE", + "CH0_RX_LOS_HYST_EN": "DONTCARE", + "CH0_RX_LOS_LVL": "DONTCARE", + "CH0_RX_RATE_SEL": "DONTCARE", + "CH0_RX_SB_BYPASS": "DONTCARE", + "CH0_SB_BYPASS": "DONTCARE", + "CH0_SEL_SD_RX_CLK": "DONTCARE", + "CH0_TDRV_DAT_SEL": "DONTCARE", + "CH0_TDRV_POST_EN": "DONTCARE", + "CH0_TDRV_PRE_EN": "DONTCARE", + "CH0_TDRV_SLICE0_CUR": "DONTCARE", + "CH0_TDRV_SLICE0_SEL": "DONTCARE", + "CH0_TDRV_SLICE1_CUR": "DONTCARE", + "CH0_TDRV_SLICE1_SEL": "DONTCARE", + "CH0_TDRV_SLICE2_CUR": "DONTCARE", + "CH0_TDRV_SLICE2_SEL": "DONTCARE", + "CH0_TDRV_SLICE3_CUR": "DONTCARE", + "CH0_TDRV_SLICE3_SEL": "DONTCARE", + "CH0_TDRV_SLICE4_CUR": "DONTCARE", + "CH0_TDRV_SLICE4_SEL": "DONTCARE", + "CH0_TDRV_SLICE5_CUR": "DONTCARE", + "CH0_TDRV_SLICE5_SEL": "DONTCARE", + "CH0_TPWDNB": "DONTCARE", + "CH0_TXAMPLITUDE": "DONTCARE", + "CH0_TXDEPOST": "DONTCARE", + "CH0_TXDEPRE": "DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 138 ] + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 139 ] + }, + "D_SCAN_ENABLE": { + "direction": "input", + "bits": [ 140 ] + }, + "D_SCAN_IN_0": { + "direction": "input", + "bits": [ 141 ] + }, + "D_SCAN_IN_1": { + "direction": "input", + "bits": [ 142 ] + }, + "D_SCAN_IN_2": { + "direction": "input", + "bits": [ 143 ] + }, + "D_SCAN_IN_3": { + "direction": "input", + "bits": [ 144 ] + }, + "D_SCAN_IN_4": { + "direction": "input", + "bits": [ 145 ] + }, + "D_SCAN_IN_5": { + "direction": "input", + "bits": [ 146 ] + }, + "D_SCAN_IN_6": { + "direction": "input", + "bits": [ 147 ] + }, + "D_SCAN_IN_7": { + "direction": "input", + "bits": [ 148 ] + }, + "D_SCAN_MODE": { + "direction": "input", + "bits": [ 149 ] + }, + "D_SCAN_RESET": { + "direction": "input", + "bits": [ 150 ] + }, + "D_CIN0": { + "direction": "input", + "bits": [ 151 ] + }, + "D_CIN1": { + "direction": "input", + "bits": [ 152 ] + }, + "D_CIN2": { + "direction": "input", + "bits": [ 153 ] + }, + "D_CIN3": { + "direction": "input", + "bits": [ 154 ] + }, + "D_CIN4": { + "direction": "input", + "bits": [ 155 ] + }, + "D_CIN5": { + "direction": "input", + "bits": [ 156 ] + }, + "D_CIN6": { + "direction": "input", + "bits": [ 157 ] + }, + "D_CIN7": { + "direction": "input", + "bits": [ 158 ] + }, + "D_CIN8": { + "direction": "input", + "bits": [ 159 ] + }, + "D_CIN9": { + "direction": "input", + "bits": [ 160 ] + }, + "D_CIN10": { + "direction": "input", + "bits": [ 161 ] + }, + "D_CIN11": { + "direction": "input", + "bits": [ 162 ] + }, + "CH0_HDOUTP": { + "direction": "output", + "bits": [ 163 ] + }, + "CH1_HDOUTP": { + "direction": "output", + "bits": [ 164 ] + }, + "CH0_HDOUTN": { + "direction": "output", + "bits": [ 165 ] + }, + "CH1_HDOUTN": { + "direction": "output", + "bits": [ 166 ] + }, + "D_TXBIT_CLKP_TO_ND": { + "direction": "output", + "bits": [ 167 ] + }, + "D_TXBIT_CLKN_TO_ND": { + "direction": "output", + "bits": [ 168 ] + }, + "D_SYNC_PULSE2ND": { + "direction": "output", + "bits": [ 169 ] + }, + "D_TXPLL_LOL_TO_ND": { + "direction": "output", + "bits": [ 170 ] + }, + "CH0_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 171 ] + }, + "CH1_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 172 ] + }, + "CH0_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 173 ] + }, + "CH1_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 174 ] + }, + "CH0_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 175 ] + }, + "CH1_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 176 ] + }, + "CH0_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 177 ] + }, + "CH1_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 178 ] + }, + "CH0_FF_RX_PCLK": { + "direction": "output", + "bits": [ 179 ] + }, + "CH1_FF_RX_PCLK": { + "direction": "output", + "bits": [ 180 ] + }, + "CH0_FF_TX_PCLK": { + "direction": "output", + "bits": [ 181 ] + }, + "CH1_FF_TX_PCLK": { + "direction": "output", + "bits": [ 182 ] + }, + "CH0_FF_RX_D_0": { + "direction": "output", + "bits": [ 183 ] + }, + "CH1_FF_RX_D_0": { + "direction": "output", + "bits": [ 184 ] + }, + "CH0_FF_RX_D_1": { + "direction": "output", + "bits": [ 185 ] + }, + "CH1_FF_RX_D_1": { + "direction": "output", + "bits": [ 186 ] + }, + "CH0_FF_RX_D_2": { + "direction": "output", + "bits": [ 187 ] + }, + "CH1_FF_RX_D_2": { + "direction": "output", + "bits": [ 188 ] + }, + "CH0_FF_RX_D_3": { + "direction": "output", + "bits": [ 189 ] + }, + "CH1_FF_RX_D_3": { + "direction": "output", + "bits": [ 190 ] + }, + "CH0_FF_RX_D_4": { + "direction": "output", + "bits": [ 191 ] + }, + "CH1_FF_RX_D_4": { + "direction": "output", + "bits": [ 192 ] + }, + "CH0_FF_RX_D_5": { + "direction": "output", + "bits": [ 193 ] + }, + "CH1_FF_RX_D_5": { + "direction": "output", + "bits": [ 194 ] + }, + "CH0_FF_RX_D_6": { + "direction": "output", + "bits": [ 195 ] + }, + "CH1_FF_RX_D_6": { + "direction": "output", + "bits": [ 196 ] + }, + "CH0_FF_RX_D_7": { + "direction": "output", + "bits": [ 197 ] + }, + "CH1_FF_RX_D_7": { + "direction": "output", + "bits": [ 198 ] + }, + "CH0_FF_RX_D_8": { + "direction": "output", + "bits": [ 199 ] + }, + "CH1_FF_RX_D_8": { + "direction": "output", + "bits": [ 200 ] + }, + "CH0_FF_RX_D_9": { + "direction": "output", + "bits": [ 201 ] + }, + "CH1_FF_RX_D_9": { + "direction": "output", + "bits": [ 202 ] + }, + "CH0_FF_RX_D_10": { + "direction": "output", + "bits": [ 203 ] + }, + "CH1_FF_RX_D_10": { + "direction": "output", + "bits": [ 204 ] + }, + "CH0_FF_RX_D_11": { + "direction": "output", + "bits": [ 205 ] + }, + "CH1_FF_RX_D_11": { + "direction": "output", + "bits": [ 206 ] + }, + "CH0_FF_RX_D_12": { + "direction": "output", + "bits": [ 207 ] + }, + "CH1_FF_RX_D_12": { + "direction": "output", + "bits": [ 208 ] + }, + "CH0_FF_RX_D_13": { + "direction": "output", + "bits": [ 209 ] + }, + "CH1_FF_RX_D_13": { + "direction": "output", + "bits": [ 210 ] + }, + "CH0_FF_RX_D_14": { + "direction": "output", + "bits": [ 211 ] + }, + "CH1_FF_RX_D_14": { + "direction": "output", + "bits": [ 212 ] + }, + "CH0_FF_RX_D_15": { + "direction": "output", + "bits": [ 213 ] + }, + "CH1_FF_RX_D_15": { + "direction": "output", + "bits": [ 214 ] + }, + "CH0_FF_RX_D_16": { + "direction": "output", + "bits": [ 215 ] + }, + "CH1_FF_RX_D_16": { + "direction": "output", + "bits": [ 216 ] + }, + "CH0_FF_RX_D_17": { + "direction": "output", + "bits": [ 217 ] + }, + "CH1_FF_RX_D_17": { + "direction": "output", + "bits": [ 218 ] + }, + "CH0_FF_RX_D_18": { + "direction": "output", + "bits": [ 219 ] + }, + "CH1_FF_RX_D_18": { + "direction": "output", + "bits": [ 220 ] + }, + "CH0_FF_RX_D_19": { + "direction": "output", + "bits": [ 221 ] + }, + "CH1_FF_RX_D_19": { + "direction": "output", + "bits": [ 222 ] + }, + "CH0_FF_RX_D_20": { + "direction": "output", + "bits": [ 223 ] + }, + "CH1_FF_RX_D_20": { + "direction": "output", + "bits": [ 224 ] + }, + "CH0_FF_RX_D_21": { + "direction": "output", + "bits": [ 225 ] + }, + "CH1_FF_RX_D_21": { + "direction": "output", + "bits": [ 226 ] + }, + "CH0_FF_RX_D_22": { + "direction": "output", + "bits": [ 227 ] + }, + "CH1_FF_RX_D_22": { + "direction": "output", + "bits": [ 228 ] + }, + "CH0_FF_RX_D_23": { + "direction": "output", + "bits": [ 229 ] + }, + "CH1_FF_RX_D_23": { + "direction": "output", + "bits": [ 230 ] + }, + "CH0_FFS_PCIE_DONE": { + "direction": "output", + "bits": [ 231 ] + }, + "CH1_FFS_PCIE_DONE": { + "direction": "output", + "bits": [ 232 ] + }, + "CH0_FFS_PCIE_CON": { + "direction": "output", + "bits": [ 233 ] + }, + "CH1_FFS_PCIE_CON": { + "direction": "output", + "bits": [ 234 ] + }, + "CH0_FFS_RLOS": { + "direction": "output", + "bits": [ 235 ] + }, + "CH1_FFS_RLOS": { + "direction": "output", + "bits": [ 236 ] + }, + "CH0_FFS_LS_SYNC_STATUS": { + "direction": "output", + "bits": [ 237 ] + }, + "CH1_FFS_LS_SYNC_STATUS": { + "direction": "output", + "bits": [ 238 ] + }, + "CH0_FFS_CC_UNDERRUN": { + "direction": "output", + "bits": [ 239 ] + }, + "CH1_FFS_CC_UNDERRUN": { + "direction": "output", + "bits": [ 240 ] + }, + "CH0_FFS_CC_OVERRUN": { + "direction": "output", + "bits": [ 241 ] + }, + "CH1_FFS_CC_OVERRUN": { + "direction": "output", + "bits": [ 242 ] + }, + "CH0_FFS_RXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 243 ] + }, + "CH1_FFS_RXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 244 ] + }, + "CH0_FFS_TXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 245 ] + }, + "CH1_FFS_TXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 246 ] + }, + "CH0_FFS_RLOL": { + "direction": "output", + "bits": [ 247 ] + }, + "CH1_FFS_RLOL": { + "direction": "output", + "bits": [ 248 ] + }, + "CH0_FFS_SKP_ADDED": { + "direction": "output", + "bits": [ 249 ] + }, + "CH1_FFS_SKP_ADDED": { + "direction": "output", + "bits": [ 250 ] + }, + "CH0_FFS_SKP_DELETED": { + "direction": "output", + "bits": [ 251 ] + }, + "CH1_FFS_SKP_DELETED": { + "direction": "output", + "bits": [ 252 ] + }, + "CH0_LDR_RX2CORE": { + "direction": "output", + "bits": [ 253 ] + }, + "CH1_LDR_RX2CORE": { + "direction": "output", + "bits": [ 254 ] + }, + "D_SCIRDATA0": { + "direction": "output", + "bits": [ 255 ] + }, + "D_SCIRDATA1": { + "direction": "output", + "bits": [ 256 ] + }, + "D_SCIRDATA2": { + "direction": "output", + "bits": [ 257 ] + }, + "D_SCIRDATA3": { + "direction": "output", + "bits": [ 258 ] + }, + "D_SCIRDATA4": { + "direction": "output", + "bits": [ 259 ] + }, + "D_SCIRDATA5": { + "direction": "output", + "bits": [ 260 ] + }, + "D_SCIRDATA6": { + "direction": "output", + "bits": [ 261 ] + }, + "D_SCIRDATA7": { + "direction": "output", + "bits": [ 262 ] + }, + "D_SCIINT": { + "direction": "output", + "bits": [ 263 ] + }, + "D_SCAN_OUT_0": { + "direction": "output", + "bits": [ 264 ] + }, + "D_SCAN_OUT_1": { + "direction": "output", + "bits": [ 265 ] + }, + "D_SCAN_OUT_2": { + "direction": "output", + "bits": [ 266 ] + }, + "D_SCAN_OUT_3": { + "direction": "output", + "bits": [ 267 ] + }, + "D_SCAN_OUT_4": { + "direction": "output", + "bits": [ 268 ] + }, + "D_SCAN_OUT_5": { + "direction": "output", + "bits": [ 269 ] + }, + "D_SCAN_OUT_6": { + "direction": "output", + "bits": [ 270 ] + }, + "D_SCAN_OUT_7": { + "direction": "output", + "bits": [ 271 ] + }, + "D_COUT0": { + "direction": "output", + "bits": [ 272 ] + }, + "D_COUT1": { + "direction": "output", + "bits": [ 273 ] + }, + "D_COUT2": { + "direction": "output", + "bits": [ 274 ] + }, + "D_COUT3": { + "direction": "output", + "bits": [ 275 ] + }, + "D_COUT4": { + "direction": "output", + "bits": [ 276 ] + }, + "D_COUT5": { + "direction": "output", + "bits": [ 277 ] + }, + "D_COUT6": { + "direction": "output", + "bits": [ 278 ] + }, + "D_COUT7": { + "direction": "output", + "bits": [ 279 ] + }, + "D_COUT8": { + "direction": "output", + "bits": [ 280 ] + }, + "D_COUT9": { + "direction": "output", + "bits": [ 281 ] + }, + "D_COUT10": { + "direction": "output", + "bits": [ 282 ] + }, + "D_COUT11": { + "direction": "output", + "bits": [ 283 ] + }, + "D_COUT12": { + "direction": "output", + "bits": [ 284 ] + }, + "D_COUT13": { + "direction": "output", + "bits": [ 285 ] + }, + "D_COUT14": { + "direction": "output", + "bits": [ 286 ] + }, + "D_COUT15": { + "direction": "output", + "bits": [ 287 ] + }, + "D_COUT16": { + "direction": "output", + "bits": [ 288 ] + }, + "D_COUT17": { + "direction": "output", + "bits": [ 289 ] + }, + "D_COUT18": { + "direction": "output", + "bits": [ 290 ] + }, + "D_COUT19": { + "direction": "output", + "bits": [ 291 ] + }, + "D_REFCLKI": { + "direction": "input", + "bits": [ 292 ] + }, + "D_FFS_PLOL": { + "direction": "output", + "bits": [ 293 ] + } + }, + "cells": { + }, + "netnames": { + "CH0_FFC_CDR_EN_BITSLIP": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1876.11-1876.33" + } + }, + "CH0_FFC_DIV11_MODE_RX": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1826.11-1826.32" + } + }, + "CH0_FFC_DIV11_MODE_TX": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1832.11-1832.32" + } + }, + "CH0_FFC_EI_EN": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1804.11-1804.24" + } + }, + "CH0_FFC_ENABLE_CGALIGN": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1812.11-1812.33" + } + }, + "CH0_FFC_FB_LOOPBACK": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1816.11-1816.30" + } + }, + "CH0_FFC_LANE_RX_RST": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1838.11-1838.30" + } + }, + "CH0_FFC_LANE_TX_RST": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1836.11-1836.30" + } + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1834.11-1834.33" + } + }, + "CH0_FFC_PCIE_CT": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1808.11-1808.26" + } + }, + "CH0_FFC_PCIE_DET_EN": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1806.11-1806.30" + } + }, + "CH0_FFC_PFIFO_CLR": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1820.11-1820.28" + } + }, + "CH0_FFC_RATE_MODE_RX": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1822.11-1822.31" + } + }, + "CH0_FFC_RATE_MODE_TX": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1824.11-1824.31" + } + }, + "CH0_FFC_RRST": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1840.11-1840.23" + } + }, + "CH0_FFC_RXPWDNB": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1844.11-1844.26" + } + }, + "CH0_FFC_RX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1828.11-1828.31" + } + }, + "CH0_FFC_SB_INV_RX": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1810.11-1810.28" + } + }, + "CH0_FFC_SB_PFIFO_LP": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1818.11-1818.30" + } + }, + "CH0_FFC_SIGNAL_DETECT": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1814.11-1814.32" + } + }, + "CH0_FFC_TXPWDNB": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1842.11-1842.26" + } + }, + "CH0_FFC_TX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1830.11-1830.31" + } + }, + "CH0_FFS_CC_OVERRUN": { + "hide_name": 0, + "bits": [ 241 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1979.12-1979.30" + } + }, + "CH0_FFS_CC_UNDERRUN": { + "hide_name": 0, + "bits": [ 239 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1977.12-1977.31" + } + }, + "CH0_FFS_LS_SYNC_STATUS": { + "hide_name": 0, + "bits": [ 237 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1975.12-1975.34" + } + }, + "CH0_FFS_PCIE_CON": { + "hide_name": 0, + "bits": [ 233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1971.12-1971.28" + } + }, + "CH0_FFS_PCIE_DONE": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1969.12-1969.29" + } + }, + "CH0_FFS_RLOL": { + "hide_name": 0, + "bits": [ 247 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1985.12-1985.24" + } + }, + "CH0_FFS_RLOS": { + "hide_name": 0, + "bits": [ 235 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1973.12-1973.24" + } + }, + "CH0_FFS_RXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 243 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1981.12-1981.34" + } + }, + "CH0_FFS_SKP_ADDED": { + "hide_name": 0, + "bits": [ 249 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1987.12-1987.29" + } + }, + "CH0_FFS_SKP_DELETED": { + "hide_name": 0, + "bits": [ 251 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1989.12-1989.31" + } + }, + "CH0_FFS_TXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 245 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1983.12-1983.34" + } + }, + "CH0_FF_EBRD_CLK": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1754.11-1754.26" + } + }, + "CH0_FF_RXI_CLK": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1750.11-1750.25" + } + }, + "CH0_FF_RX_D_0": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1921.12-1921.25" + } + }, + "CH0_FF_RX_D_1": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1923.12-1923.25" + } + }, + "CH0_FF_RX_D_10": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1941.12-1941.26" + } + }, + "CH0_FF_RX_D_11": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1943.12-1943.26" + } + }, + "CH0_FF_RX_D_12": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1945.12-1945.26" + } + }, + "CH0_FF_RX_D_13": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1947.12-1947.26" + } + }, + "CH0_FF_RX_D_14": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1949.12-1949.26" + } + }, + "CH0_FF_RX_D_15": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1951.12-1951.26" + } + }, + "CH0_FF_RX_D_16": { + "hide_name": 0, + "bits": [ 215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1953.12-1953.26" + } + }, + "CH0_FF_RX_D_17": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1955.12-1955.26" + } + }, + "CH0_FF_RX_D_18": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1957.12-1957.26" + } + }, + "CH0_FF_RX_D_19": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1959.12-1959.26" + } + }, + "CH0_FF_RX_D_2": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1925.12-1925.25" + } + }, + "CH0_FF_RX_D_20": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1961.12-1961.26" + } + }, + "CH0_FF_RX_D_21": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1963.12-1963.26" + } + }, + "CH0_FF_RX_D_22": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1965.12-1965.26" + } + }, + "CH0_FF_RX_D_23": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1967.12-1967.26" + } + }, + "CH0_FF_RX_D_3": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1927.12-1927.25" + } + }, + "CH0_FF_RX_D_4": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1929.12-1929.25" + } + }, + "CH0_FF_RX_D_5": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1931.12-1931.25" + } + }, + "CH0_FF_RX_D_6": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1933.12-1933.25" + } + }, + "CH0_FF_RX_D_7": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1935.12-1935.25" + } + }, + "CH0_FF_RX_D_8": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1937.12-1937.25" + } + }, + "CH0_FF_RX_D_9": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1939.12-1939.25" + } + }, + "CH0_FF_RX_F_CLK": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1909.12-1909.27" + } + }, + "CH0_FF_RX_H_CLK": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1911.12-1911.27" + } + }, + "CH0_FF_RX_PCLK": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1917.12-1917.26" + } + }, + "CH0_FF_TXI_CLK": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1752.11-1752.25" + } + }, + "CH0_FF_TX_D_0": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1756.11-1756.24" + } + }, + "CH0_FF_TX_D_1": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1758.11-1758.24" + } + }, + "CH0_FF_TX_D_10": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1776.11-1776.25" + } + }, + "CH0_FF_TX_D_11": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1778.11-1778.25" + } + }, + "CH0_FF_TX_D_12": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1780.11-1780.25" + } + }, + "CH0_FF_TX_D_13": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1782.11-1782.25" + } + }, + "CH0_FF_TX_D_14": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1784.11-1784.25" + } + }, + "CH0_FF_TX_D_15": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1786.11-1786.25" + } + }, + "CH0_FF_TX_D_16": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1788.11-1788.25" + } + }, + "CH0_FF_TX_D_17": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1790.11-1790.25" + } + }, + "CH0_FF_TX_D_18": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1792.11-1792.25" + } + }, + "CH0_FF_TX_D_19": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1794.11-1794.25" + } + }, + "CH0_FF_TX_D_2": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1760.11-1760.24" + } + }, + "CH0_FF_TX_D_20": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1796.11-1796.25" + } + }, + "CH0_FF_TX_D_21": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1798.11-1798.25" + } + }, + "CH0_FF_TX_D_22": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1800.11-1800.25" + } + }, + "CH0_FF_TX_D_23": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1802.11-1802.25" + } + }, + "CH0_FF_TX_D_3": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1762.11-1762.24" + } + }, + "CH0_FF_TX_D_4": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1764.11-1764.24" + } + }, + "CH0_FF_TX_D_5": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1766.11-1766.24" + } + }, + "CH0_FF_TX_D_6": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1768.11-1768.24" + } + }, + "CH0_FF_TX_D_7": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1770.11-1770.24" + } + }, + "CH0_FF_TX_D_8": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1772.11-1772.24" + } + }, + "CH0_FF_TX_D_9": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1774.11-1774.24" + } + }, + "CH0_FF_TX_F_CLK": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1913.12-1913.27" + } + }, + "CH0_FF_TX_H_CLK": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1915.12-1915.27" + } + }, + "CH0_FF_TX_PCLK": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1919.12-1919.26" + } + }, + "CH0_HDINN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1741.11-1741.20" + } + }, + "CH0_HDINP": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1737.11-1737.20" + } + }, + "CH0_HDOUTN": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1903.12-1903.22" + } + }, + "CH0_HDOUTP": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1901.12-1901.22" + } + }, + "CH0_LDR_CORE2TX": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1846.11-1846.26" + } + }, + "CH0_LDR_RX2CORE": { + "hide_name": 0, + "bits": [ 253 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1991.12-1991.27" + } + }, + "CH0_RX_REFCLK": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1748.11-1748.24" + } + }, + "CH0_SCIEN": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1864.11-1864.20" + } + }, + "CH0_SCISEL": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1866.11-1866.21" + } + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1877.11-1877.33" + } + }, + "CH1_FFC_DIV11_MODE_RX": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1827.11-1827.32" + } + }, + "CH1_FFC_DIV11_MODE_TX": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1833.11-1833.32" + } + }, + "CH1_FFC_EI_EN": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1805.11-1805.24" + } + }, + "CH1_FFC_ENABLE_CGALIGN": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1813.11-1813.33" + } + }, + "CH1_FFC_FB_LOOPBACK": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1817.11-1817.30" + } + }, + "CH1_FFC_LANE_RX_RST": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1839.11-1839.30" + } + }, + "CH1_FFC_LANE_TX_RST": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1837.11-1837.30" + } + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1835.11-1835.33" + } + }, + "CH1_FFC_PCIE_CT": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1809.11-1809.26" + } + }, + "CH1_FFC_PCIE_DET_EN": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1807.11-1807.30" + } + }, + "CH1_FFC_PFIFO_CLR": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1821.11-1821.28" + } + }, + "CH1_FFC_RATE_MODE_RX": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1823.11-1823.31" + } + }, + "CH1_FFC_RATE_MODE_TX": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1825.11-1825.31" + } + }, + "CH1_FFC_RRST": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1841.11-1841.23" + } + }, + "CH1_FFC_RXPWDNB": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1845.11-1845.26" + } + }, + "CH1_FFC_RX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1829.11-1829.31" + } + }, + "CH1_FFC_SB_INV_RX": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1811.11-1811.28" + } + }, + "CH1_FFC_SB_PFIFO_LP": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1819.11-1819.30" + } + }, + "CH1_FFC_SIGNAL_DETECT": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1815.11-1815.32" + } + }, + "CH1_FFC_TXPWDNB": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1843.11-1843.26" + } + }, + "CH1_FFC_TX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1831.11-1831.31" + } + }, + "CH1_FFS_CC_OVERRUN": { + "hide_name": 0, + "bits": [ 242 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1980.12-1980.30" + } + }, + "CH1_FFS_CC_UNDERRUN": { + "hide_name": 0, + "bits": [ 240 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1978.12-1978.31" + } + }, + "CH1_FFS_LS_SYNC_STATUS": { + "hide_name": 0, + "bits": [ 238 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1976.12-1976.34" + } + }, + "CH1_FFS_PCIE_CON": { + "hide_name": 0, + "bits": [ 234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1972.12-1972.28" + } + }, + "CH1_FFS_PCIE_DONE": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1970.12-1970.29" + } + }, + "CH1_FFS_RLOL": { + "hide_name": 0, + "bits": [ 248 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1986.12-1986.24" + } + }, + "CH1_FFS_RLOS": { + "hide_name": 0, + "bits": [ 236 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1974.12-1974.24" + } + }, + "CH1_FFS_RXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 244 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1982.12-1982.34" + } + }, + "CH1_FFS_SKP_ADDED": { + "hide_name": 0, + "bits": [ 250 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1988.12-1988.29" + } + }, + "CH1_FFS_SKP_DELETED": { + "hide_name": 0, + "bits": [ 252 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1990.12-1990.31" + } + }, + "CH1_FFS_TXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 246 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1984.12-1984.34" + } + }, + "CH1_FF_EBRD_CLK": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1755.11-1755.26" + } + }, + "CH1_FF_RXI_CLK": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1751.11-1751.25" + } + }, + "CH1_FF_RX_D_0": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1922.12-1922.25" + } + }, + "CH1_FF_RX_D_1": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1924.12-1924.25" + } + }, + "CH1_FF_RX_D_10": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1942.12-1942.26" + } + }, + "CH1_FF_RX_D_11": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1944.12-1944.26" + } + }, + "CH1_FF_RX_D_12": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1946.12-1946.26" + } + }, + "CH1_FF_RX_D_13": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1948.12-1948.26" + } + }, + "CH1_FF_RX_D_14": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1950.12-1950.26" + } + }, + "CH1_FF_RX_D_15": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1952.12-1952.26" + } + }, + "CH1_FF_RX_D_16": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1954.12-1954.26" + } + }, + "CH1_FF_RX_D_17": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1956.12-1956.26" + } + }, + "CH1_FF_RX_D_18": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1958.12-1958.26" + } + }, + "CH1_FF_RX_D_19": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1960.12-1960.26" + } + }, + "CH1_FF_RX_D_2": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1926.12-1926.25" + } + }, + "CH1_FF_RX_D_20": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1962.12-1962.26" + } + }, + "CH1_FF_RX_D_21": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1964.12-1964.26" + } + }, + "CH1_FF_RX_D_22": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1966.12-1966.26" + } + }, + "CH1_FF_RX_D_23": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1968.12-1968.26" + } + }, + "CH1_FF_RX_D_3": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1928.12-1928.25" + } + }, + "CH1_FF_RX_D_4": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1930.12-1930.25" + } + }, + "CH1_FF_RX_D_5": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1932.12-1932.25" + } + }, + "CH1_FF_RX_D_6": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1934.12-1934.25" + } + }, + "CH1_FF_RX_D_7": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1936.12-1936.25" + } + }, + "CH1_FF_RX_D_8": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1938.12-1938.25" + } + }, + "CH1_FF_RX_D_9": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1940.12-1940.25" + } + }, + "CH1_FF_RX_F_CLK": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1910.12-1910.27" + } + }, + "CH1_FF_RX_H_CLK": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1912.12-1912.27" + } + }, + "CH1_FF_RX_PCLK": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1918.12-1918.26" + } + }, + "CH1_FF_TXI_CLK": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1753.11-1753.25" + } + }, + "CH1_FF_TX_D_0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1757.11-1757.24" + } + }, + "CH1_FF_TX_D_1": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1759.11-1759.24" + } + }, + "CH1_FF_TX_D_10": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1777.11-1777.25" + } + }, + "CH1_FF_TX_D_11": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1779.11-1779.25" + } + }, + "CH1_FF_TX_D_12": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1781.11-1781.25" + } + }, + "CH1_FF_TX_D_13": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1783.11-1783.25" + } + }, + "CH1_FF_TX_D_14": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1785.11-1785.25" + } + }, + "CH1_FF_TX_D_15": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1787.11-1787.25" + } + }, + "CH1_FF_TX_D_16": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1789.11-1789.25" + } + }, + "CH1_FF_TX_D_17": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1791.11-1791.25" + } + }, + "CH1_FF_TX_D_18": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1793.11-1793.25" + } + }, + "CH1_FF_TX_D_19": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1795.11-1795.25" + } + }, + "CH1_FF_TX_D_2": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1761.11-1761.24" + } + }, + "CH1_FF_TX_D_20": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1797.11-1797.25" + } + }, + "CH1_FF_TX_D_21": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1799.11-1799.25" + } + }, + "CH1_FF_TX_D_22": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1801.11-1801.25" + } + }, + "CH1_FF_TX_D_23": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1803.11-1803.25" + } + }, + "CH1_FF_TX_D_3": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1763.11-1763.24" + } + }, + "CH1_FF_TX_D_4": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1765.11-1765.24" + } + }, + "CH1_FF_TX_D_5": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1767.11-1767.24" + } + }, + "CH1_FF_TX_D_6": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1769.11-1769.24" + } + }, + "CH1_FF_TX_D_7": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1771.11-1771.24" + } + }, + "CH1_FF_TX_D_8": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1773.11-1773.24" + } + }, + "CH1_FF_TX_D_9": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1775.11-1775.24" + } + }, + "CH1_FF_TX_F_CLK": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1914.12-1914.27" + } + }, + "CH1_FF_TX_H_CLK": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1916.12-1916.27" + } + }, + "CH1_FF_TX_PCLK": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1920.12-1920.26" + } + }, + "CH1_HDINN": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1743.11-1743.20" + } + }, + "CH1_HDINP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1739.11-1739.20" + } + }, + "CH1_HDOUTN": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1904.12-1904.22" + } + }, + "CH1_HDOUTP": { + "hide_name": 0, + "bits": [ 164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1902.12-1902.22" + } + }, + "CH1_LDR_CORE2TX": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1847.11-1847.26" + } + }, + "CH1_LDR_RX2CORE": { + "hide_name": 0, + "bits": [ 254 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1992.12-1992.27" + } + }, + "CH1_RX_REFCLK": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1749.11-1749.24" + } + }, + "CH1_SCIEN": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1865.11-1865.20" + } + }, + "CH1_SCISEL": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1867.11-1867.21" + } + }, + "D_CIN0": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1889.11-1889.17" + } + }, + "D_CIN1": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1890.11-1890.17" + } + }, + "D_CIN10": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1899.11-1899.18" + } + }, + "D_CIN11": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1900.11-1900.18" + } + }, + "D_CIN2": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1891.11-1891.17" + } + }, + "D_CIN3": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1892.11-1892.17" + } + }, + "D_CIN4": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1893.11-1893.17" + } + }, + "D_CIN5": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1894.11-1894.17" + } + }, + "D_CIN6": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1895.11-1895.17" + } + }, + "D_CIN7": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1896.11-1896.17" + } + }, + "D_CIN8": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1897.11-1897.17" + } + }, + "D_CIN9": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1898.11-1898.17" + } + }, + "D_COUT0": { + "hide_name": 0, + "bits": [ 272 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2010.12-2010.19" + } + }, + "D_COUT1": { + "hide_name": 0, + "bits": [ 273 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2011.12-2011.19" + } + }, + "D_COUT10": { + "hide_name": 0, + "bits": [ 282 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2020.12-2020.20" + } + }, + "D_COUT11": { + "hide_name": 0, + "bits": [ 283 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2021.12-2021.20" + } + }, + "D_COUT12": { + "hide_name": 0, + "bits": [ 284 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2022.12-2022.20" + } + }, + "D_COUT13": { + "hide_name": 0, + "bits": [ 285 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2023.12-2023.20" + } + }, + "D_COUT14": { + "hide_name": 0, + "bits": [ 286 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2024.12-2024.20" + } + }, + "D_COUT15": { + "hide_name": 0, + "bits": [ 287 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2025.12-2025.20" + } + }, + "D_COUT16": { + "hide_name": 0, + "bits": [ 288 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2026.12-2026.20" + } + }, + "D_COUT17": { + "hide_name": 0, + "bits": [ 289 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2027.12-2027.20" + } + }, + "D_COUT18": { + "hide_name": 0, + "bits": [ 290 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2028.12-2028.20" + } + }, + "D_COUT19": { + "hide_name": 0, + "bits": [ 291 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2029.12-2029.20" + } + }, + "D_COUT2": { + "hide_name": 0, + "bits": [ 274 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2012.12-2012.19" + } + }, + "D_COUT3": { + "hide_name": 0, + "bits": [ 275 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2013.12-2013.19" + } + }, + "D_COUT4": { + "hide_name": 0, + "bits": [ 276 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2014.12-2014.19" + } + }, + "D_COUT5": { + "hide_name": 0, + "bits": [ 277 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2015.12-2015.19" + } + }, + "D_COUT6": { + "hide_name": 0, + "bits": [ 278 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2016.12-2016.19" + } + }, + "D_COUT7": { + "hide_name": 0, + "bits": [ 279 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2017.12-2017.19" + } + }, + "D_COUT8": { + "hide_name": 0, + "bits": [ 280 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2018.12-2018.19" + } + }, + "D_COUT9": { + "hide_name": 0, + "bits": [ 281 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2019.12-2019.19" + } + }, + "D_CYAWSTN": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1870.11-1870.20" + } + }, + "D_FFC_DUAL_RST": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1872.11-1872.25" + } + }, + "D_FFC_MACROPDB": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1874.11-1874.25" + } + }, + "D_FFC_MACRO_RST": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1873.11-1873.26" + } + }, + "D_FFC_SYNC_TOGGLE": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1871.11-1871.28" + } + }, + "D_FFC_TRST": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1875.11-1875.21" + } + }, + "D_FFS_PLOL": { + "hide_name": 0, + "bits": [ 293 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2031.12-2031.22" + } + }, + "D_REFCLKI": { + "hide_name": 0, + "bits": [ 292 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2030.11-2030.20" + } + }, + "D_SCAN_ENABLE": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1878.11-1878.24" + } + }, + "D_SCAN_IN_0": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1879.11-1879.22" + } + }, + "D_SCAN_IN_1": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1880.11-1880.22" + } + }, + "D_SCAN_IN_2": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1881.11-1881.22" + } + }, + "D_SCAN_IN_3": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1882.11-1882.22" + } + }, + "D_SCAN_IN_4": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1883.11-1883.22" + } + }, + "D_SCAN_IN_5": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1884.11-1884.22" + } + }, + "D_SCAN_IN_6": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1885.11-1885.22" + } + }, + "D_SCAN_IN_7": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1886.11-1886.22" + } + }, + "D_SCAN_MODE": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1887.11-1887.22" + } + }, + "D_SCAN_OUT_0": { + "hide_name": 0, + "bits": [ 264 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2002.12-2002.24" + } + }, + "D_SCAN_OUT_1": { + "hide_name": 0, + "bits": [ 265 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2003.12-2003.24" + } + }, + "D_SCAN_OUT_2": { + "hide_name": 0, + "bits": [ 266 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2004.12-2004.24" + } + }, + "D_SCAN_OUT_3": { + "hide_name": 0, + "bits": [ 267 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2005.12-2005.24" + } + }, + "D_SCAN_OUT_4": { + "hide_name": 0, + "bits": [ 268 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2006.12-2006.24" + } + }, + "D_SCAN_OUT_5": { + "hide_name": 0, + "bits": [ 269 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2007.12-2007.24" + } + }, + "D_SCAN_OUT_6": { + "hide_name": 0, + "bits": [ 270 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2008.12-2008.24" + } + }, + "D_SCAN_OUT_7": { + "hide_name": 0, + "bits": [ 271 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2009.12-2009.24" + } + }, + "D_SCAN_RESET": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1888.11-1888.23" + } + }, + "D_SCIADDR0": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1856.11-1856.21" + } + }, + "D_SCIADDR1": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1857.11-1857.21" + } + }, + "D_SCIADDR2": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1858.11-1858.21" + } + }, + "D_SCIADDR3": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1859.11-1859.21" + } + }, + "D_SCIADDR4": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1860.11-1860.21" + } + }, + "D_SCIADDR5": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1861.11-1861.21" + } + }, + "D_SCIENAUX": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1862.11-1862.21" + } + }, + "D_SCIINT": { + "hide_name": 0, + "bits": [ 263 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2001.12-2001.20" + } + }, + "D_SCIRD": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1868.11-1868.18" + } + }, + "D_SCIRDATA0": { + "hide_name": 0, + "bits": [ 255 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1993.12-1993.23" + } + }, + "D_SCIRDATA1": { + "hide_name": 0, + "bits": [ 256 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1994.12-1994.23" + } + }, + "D_SCIRDATA2": { + "hide_name": 0, + "bits": [ 257 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1995.12-1995.23" + } + }, + "D_SCIRDATA3": { + "hide_name": 0, + "bits": [ 258 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1996.12-1996.23" + } + }, + "D_SCIRDATA4": { + "hide_name": 0, + "bits": [ 259 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1997.12-1997.23" + } + }, + "D_SCIRDATA5": { + "hide_name": 0, + "bits": [ 260 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1998.12-1998.23" + } + }, + "D_SCIRDATA6": { + "hide_name": 0, + "bits": [ 261 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1999.12-1999.23" + } + }, + "D_SCIRDATA7": { + "hide_name": 0, + "bits": [ 262 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2000.12-2000.23" + } + }, + "D_SCISELAUX": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1863.11-1863.22" + } + }, + "D_SCIWDATA0": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1848.11-1848.22" + } + }, + "D_SCIWDATA1": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1849.11-1849.22" + } + }, + "D_SCIWDATA2": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1850.11-1850.22" + } + }, + "D_SCIWDATA3": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1851.11-1851.22" + } + }, + "D_SCIWDATA4": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1852.11-1852.22" + } + }, + "D_SCIWDATA5": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1853.11-1853.22" + } + }, + "D_SCIWDATA6": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1854.11-1854.22" + } + }, + "D_SCIWDATA7": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1855.11-1855.22" + } + }, + "D_SCIWSTN": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1869.11-1869.20" + } + }, + "D_SYNC_ND": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1746.11-1746.20" + } + }, + "D_SYNC_PULSE2ND": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1907.12-1907.27" + } + }, + "D_TXBIT_CLKN_FROM_ND": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1745.11-1745.31" + } + }, + "D_TXBIT_CLKN_TO_ND": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1906.12-1906.30" + } + }, + "D_TXBIT_CLKP_FROM_ND": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1744.11-1744.31" + } + }, + "D_TXBIT_CLKP_TO_ND": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1905.12-1905.30" + } + }, + "D_TXPLL_LOL_FROM_ND": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1747.11-1747.30" + } + }, + "D_TXPLL_LOL_TO_ND": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1908.12-1908.29" + } + } + } + }, + "DDRDLLA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1139.1-1156.10" + }, + "parameter_default_values": { + "FORCE_MAX_DELAY": "NO", + "GSR": "ENABLED" + }, + "ports": { + "CLK": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "UDDCNTLN": { + "direction": "input", + "bits": [ 4 ] + }, + "FREEZE": { + "direction": "input", + "bits": [ 5 ] + }, + "DDRDEL": { + "direction": "output", + "bits": [ 6 ] + }, + "LOCK": { + "direction": "output", + "bits": [ 7 ] + }, + "DCNTL7": { + "direction": "output", + "bits": [ 8 ] + }, + "DCNTL6": { + "direction": "output", + "bits": [ 9 ] + }, + "DCNTL5": { + "direction": "output", + "bits": [ 10 ] + }, + "DCNTL4": { + "direction": "output", + "bits": [ 11 ] + }, + "DCNTL3": { + "direction": "output", + "bits": [ 12 ] + }, + "DCNTL2": { + "direction": "output", + "bits": [ 13 ] + }, + "DCNTL1": { + "direction": "output", + "bits": [ 14 ] + }, + "DCNTL0": { + "direction": "output", + "bits": [ 15 ] + } + }, + "cells": { + }, + "netnames": { + "CLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1142.11-1142.14" + } + }, + "DCNTL0": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1155.12-1155.18" + } + }, + "DCNTL1": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1154.12-1154.18" + } + }, + "DCNTL2": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1153.12-1153.18" + } + }, + "DCNTL3": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1152.12-1152.18" + } + }, + "DCNTL4": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1151.12-1151.18" + } + }, + "DCNTL5": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1150.12-1150.18" + } + }, + "DCNTL6": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1149.12-1149.18" + } + }, + "DCNTL7": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1148.12-1148.18" + } + }, + "DDRDEL": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1146.12-1146.18" + } + }, + "FREEZE": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1145.11-1145.17" + } + }, + "LOCK": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1147.12-1147.16" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1143.11-1143.14" + } + }, + "UDDCNTLN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1144.11-1144.19" + } + } + } + }, + "DELAYF": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1065.1-1074.10" + }, + "parameter_default_values": { + "DEL_MODE": "USER_DEFINED", + "DEL_VALUE": "00000000000000000000000000000000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "LOADN": { + "direction": "input", + "bits": [ 3 ] + }, + "MOVE": { + "direction": "input", + "bits": [ 4 ] + }, + "DIRECTION": { + "direction": "input", + "bits": [ 5 ] + }, + "Z": { + "direction": "output", + "bits": [ 6 ] + }, + "CFLAG": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1068.11-1068.12" + } + }, + "CFLAG": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1073.12-1073.17" + } + }, + "DIRECTION": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1071.11-1071.20" + } + }, + "LOADN": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1069.11-1069.16" + } + }, + "MOVE": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1070.11-1070.15" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1072.12-1072.13" + } + } + } + }, + "DELAYG": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1077.1-1082.10" + }, + "parameter_default_values": { + "DEL_MODE": "USER_DEFINED", + "DEL_VALUE": "00000000000000000000000000000000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "Z": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1080.11-1080.12" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1081.12-1081.13" + } + } + } + }, + "DLLDELD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1159.1-1167.10" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "DDRDEL": { + "direction": "input", + "bits": [ 3 ] + }, + "LOADN": { + "direction": "input", + "bits": [ 4 ] + }, + "MOVE": { + "direction": "input", + "bits": [ 5 ] + }, + "DIRECTION": { + "direction": "input", + "bits": [ 6 ] + }, + "Z": { + "direction": "output", + "bits": [ 7 ] + }, + "CFLAG": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1160.11-1160.12" + } + }, + "CFLAG": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1166.12-1166.17" + } + }, + "DDRDEL": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1161.11-1161.17" + } + }, + "DIRECTION": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1164.11-1164.20" + } + }, + "LOADN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1162.11-1162.16" + } + }, + "MOVE": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1163.11-1163.15" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1165.12-1165.13" + } + } + } + }, + "DP16KD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:5.1-219.10" + }, + "parameter_default_values": { + "ADA0MUX": "ADA0", + "ADA10MUX": "ADA10", + "ADA11MUX": "ADA11", + "ADA12MUX": "ADA12", + "ADA13MUX": "ADA13", + "ADA1MUX": "ADA1", + "ADA2MUX": "ADA2", + "ADA3MUX": "ADA3", + "ADA4MUX": "ADA4", + "ADA5MUX": "ADA5", + "ADA6MUX": "ADA6", + "ADA7MUX": "ADA7", + "ADA8MUX": "ADA8", + "ADA9MUX": "ADA9", + "ADB0MUX": "ADB0", + "ADB10MUX": "ADB10", + "ADB11MUX": "ADB11", + "ADB12MUX": "ADB12", + "ADB13MUX": "ADB13", + "ADB1MUX": "ADB1", + "ADB2MUX": "ADB2", + "ADB3MUX": "ADB3", + "ADB4MUX": "ADB4", + "ADB5MUX": "ADB5", + "ADB6MUX": "ADB6", + "ADB7MUX": "ADB7", + "ADB8MUX": "ADB8", + "ADB9MUX": "ADB9", + "ASYNC_RESET_RELEASE": "SYNC", + "CEAMUX": "CEA", + "CEBMUX": "CEB", + "CLKAMUX": "CLKA", + "CLKBMUX": "CLKB", + "CSA0MUX": "CSA0", + "CSA1MUX": "CSA1", + "CSA2MUX": "CSA2", + "CSB0MUX": "CSB0", + "CSB1MUX": "CSB1", + "CSB2MUX": "CSB2", + "CSDECODE_A": "0b000", + "CSDECODE_B": "0b000", + "DATA_WIDTH_A": "00000000000000000000000000010010", + "DATA_WIDTH_B": "00000000000000000000000000010010", + "DIA0MUX": "DIA0", + "DIA10MUX": "DIA10", + "DIA11MUX": "DIA11", + "DIA12MUX": "DIA12", + "DIA13MUX": "DIA13", + "DIA14MUX": "DIA14", + "DIA15MUX": "DIA15", + "DIA16MUX": "DIA16", + "DIA17MUX": "DIA17", + "DIA1MUX": "DIA1", + "DIA2MUX": "DIA2", + "DIA3MUX": "DIA3", + "DIA4MUX": "DIA4", + "DIA5MUX": "DIA5", + "DIA6MUX": "DIA6", + "DIA7MUX": "DIA7", + "DIA8MUX": "DIA8", + "DIA9MUX": "DIA9", + "DIB0MUX": "DIB0", + "DIB10MUX": "DIB10", + "DIB11MUX": "DIB11", + "DIB12MUX": "DIB12", + "DIB13MUX": "DIB13", + "DIB14MUX": "DIB14", + "DIB15MUX": "DIB15", + "DIB16MUX": "DIB16", + "DIB17MUX": "DIB17", + "DIB1MUX": "DIB1", + "DIB2MUX": "DIB2", + "DIB3MUX": "DIB3", + "DIB4MUX": "DIB4", + "DIB5MUX": "DIB5", + "DIB6MUX": "DIB6", + "DIB7MUX": "DIB7", + "DIB8MUX": "DIB8", + "DIB9MUX": "DIB9", + "DOA0MUX": "DOA0", + "DOA10MUX": "DOA10", + "DOA11MUX": "DOA11", + "DOA12MUX": "DOA12", + "DOA13MUX": "DOA13", + "DOA14MUX": "DOA14", + "DOA15MUX": "DOA15", + "DOA16MUX": "DOA16", + "DOA17MUX": "DOA17", + "DOA1MUX": "DOA1", + "DOA2MUX": "DOA2", + "DOA3MUX": "DOA3", + "DOA4MUX": "DOA4", + "DOA5MUX": "DOA5", + "DOA6MUX": "DOA6", + "DOA7MUX": "DOA7", + "DOA8MUX": "DOA8", + "DOA9MUX": "DOA9", + "DOB0MUX": "DOB0", + "DOB10MUX": "DOB10", + "DOB11MUX": "DOB11", + "DOB12MUX": "DOB12", + "DOB13MUX": "DOB13", + "DOB14MUX": "DOB14", + "DOB15MUX": "DOB15", + "DOB16MUX": "DOB16", + "DOB17MUX": "DOB17", + "DOB1MUX": "DOB1", + "DOB2MUX": "DOB2", + "DOB3MUX": "DOB3", + "DOB4MUX": "DOB4", + "DOB5MUX": "DOB5", + "DOB6MUX": "DOB6", + "DOB7MUX": "DOB7", + "DOB8MUX": "DOB8", + "DOB9MUX": "DOB9", + "GSR": "ENABLED", + "INITVAL_00": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_01": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_02": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_03": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_04": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_05": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_06": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_07": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_08": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_09": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_10": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_11": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_12": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_13": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_14": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_15": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_16": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_17": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_18": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_19": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_20": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_21": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_22": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_23": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_24": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_25": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_26": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_27": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_28": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_29": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_30": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_31": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_32": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_33": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_34": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_35": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_36": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_37": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_38": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_39": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INIT_DATA": "STATIC", + "OCEAMUX": "OCEA", + "OCEBMUX": "OCEB", + "REGMODE_A": "NOREG", + "REGMODE_B": "NOREG", + "RESETMODE": "SYNC", + "RSTAMUX": "RSTA", + "RSTBMUX": "RSTB", + "WEAMUX": "WEA", + "WEBMUX": "WEB", + "WID": "00000000000000000000000000000000", + "WRITEMODE_A": "NORMAL", + "WRITEMODE_B": "NORMAL" + }, + "ports": { + "DIA17": { + "direction": "input", + "bits": [ 2 ] + }, + "DIA16": { + "direction": "input", + "bits": [ 3 ] + }, + "DIA15": { + "direction": "input", + "bits": [ 4 ] + }, + "DIA14": { + "direction": "input", + "bits": [ 5 ] + }, + "DIA13": { + "direction": "input", + "bits": [ 6 ] + }, + "DIA12": { + "direction": "input", + "bits": [ 7 ] + }, + "DIA11": { + "direction": "input", + "bits": [ 8 ] + }, + "DIA10": { + "direction": "input", + "bits": [ 9 ] + }, + "DIA9": { + "direction": "input", + "bits": [ 10 ] + }, + "DIA8": { + "direction": "input", + "bits": [ 11 ] + }, + "DIA7": { + "direction": "input", + "bits": [ 12 ] + }, + "DIA6": { + "direction": "input", + "bits": [ 13 ] + }, + "DIA5": { + "direction": "input", + "bits": [ 14 ] + }, + "DIA4": { + "direction": "input", + "bits": [ 15 ] + }, + "DIA3": { + "direction": "input", + "bits": [ 16 ] + }, + "DIA2": { + "direction": "input", + "bits": [ 17 ] + }, + "DIA1": { + "direction": "input", + "bits": [ 18 ] + }, + "DIA0": { + "direction": "input", + "bits": [ 19 ] + }, + "ADA13": { + "direction": "input", + "bits": [ 20 ] + }, + "ADA12": { + "direction": "input", + "bits": [ 21 ] + }, + "ADA11": { + "direction": "input", + "bits": [ 22 ] + }, + "ADA10": { + "direction": "input", + "bits": [ 23 ] + }, + "ADA9": { + "direction": "input", + "bits": [ 24 ] + }, + "ADA8": { + "direction": "input", + "bits": [ 25 ] + }, + "ADA7": { + "direction": "input", + "bits": [ 26 ] + }, + "ADA6": { + "direction": "input", + "bits": [ 27 ] + }, + "ADA5": { + "direction": "input", + "bits": [ 28 ] + }, + "ADA4": { + "direction": "input", + "bits": [ 29 ] + }, + "ADA3": { + "direction": "input", + "bits": [ 30 ] + }, + "ADA2": { + "direction": "input", + "bits": [ 31 ] + }, + "ADA1": { + "direction": "input", + "bits": [ 32 ] + }, + "ADA0": { + "direction": "input", + "bits": [ 33 ] + }, + "CEA": { + "direction": "input", + "bits": [ 34 ] + }, + "OCEA": { + "direction": "input", + "bits": [ 35 ] + }, + "CLKA": { + "direction": "input", + "bits": [ 36 ] + }, + "WEA": { + "direction": "input", + "bits": [ 37 ] + }, + "RSTA": { + "direction": "input", + "bits": [ 38 ] + }, + "CSA2": { + "direction": "input", + "bits": [ 39 ] + }, + "CSA1": { + "direction": "input", + "bits": [ 40 ] + }, + "CSA0": { + "direction": "input", + "bits": [ 41 ] + }, + "DOA17": { + "direction": "output", + "bits": [ 42 ] + }, + "DOA16": { + "direction": "output", + "bits": [ 43 ] + }, + "DOA15": { + "direction": "output", + "bits": [ 44 ] + }, + "DOA14": { + "direction": "output", + "bits": [ 45 ] + }, + "DOA13": { + "direction": "output", + "bits": [ 46 ] + }, + "DOA12": { + "direction": "output", + "bits": [ 47 ] + }, + "DOA11": { + "direction": "output", + "bits": [ 48 ] + }, + "DOA10": { + "direction": "output", + "bits": [ 49 ] + }, + "DOA9": { + "direction": "output", + "bits": [ 50 ] + }, + "DOA8": { + "direction": "output", + "bits": [ 51 ] + }, + "DOA7": { + "direction": "output", + "bits": [ 52 ] + }, + "DOA6": { + "direction": "output", + "bits": [ 53 ] + }, + "DOA5": { + "direction": "output", + "bits": [ 54 ] + }, + "DOA4": { + "direction": "output", + "bits": [ 55 ] + }, + "DOA3": { + "direction": "output", + "bits": [ 56 ] + }, + "DOA2": { + "direction": "output", + "bits": [ 57 ] + }, + "DOA1": { + "direction": "output", + "bits": [ 58 ] + }, + "DOA0": { + "direction": "output", + "bits": [ 59 ] + }, + "DIB17": { + "direction": "input", + "bits": [ 60 ] + }, + "DIB16": { + "direction": "input", + "bits": [ 61 ] + }, + "DIB15": { + "direction": "input", + "bits": [ 62 ] + }, + "DIB14": { + "direction": "input", + "bits": [ 63 ] + }, + "DIB13": { + "direction": "input", + "bits": [ 64 ] + }, + "DIB12": { + "direction": "input", + "bits": [ 65 ] + }, + "DIB11": { + "direction": "input", + "bits": [ 66 ] + }, + "DIB10": { + "direction": "input", + "bits": [ 67 ] + }, + "DIB9": { + "direction": "input", + "bits": [ 68 ] + }, + "DIB8": { + "direction": "input", + "bits": [ 69 ] + }, + "DIB7": { + "direction": "input", + "bits": [ 70 ] + }, + "DIB6": { + "direction": "input", + "bits": [ 71 ] + }, + "DIB5": { + "direction": "input", + "bits": [ 72 ] + }, + "DIB4": { + "direction": "input", + "bits": [ 73 ] + }, + "DIB3": { + "direction": "input", + "bits": [ 74 ] + }, + "DIB2": { + "direction": "input", + "bits": [ 75 ] + }, + "DIB1": { + "direction": "input", + "bits": [ 76 ] + }, + "DIB0": { + "direction": "input", + "bits": [ 77 ] + }, + "ADB13": { + "direction": "input", + "bits": [ 78 ] + }, + "ADB12": { + "direction": "input", + "bits": [ 79 ] + }, + "ADB11": { + "direction": "input", + "bits": [ 80 ] + }, + "ADB10": { + "direction": "input", + "bits": [ 81 ] + }, + "ADB9": { + "direction": "input", + "bits": [ 82 ] + }, + "ADB8": { + "direction": "input", + "bits": [ 83 ] + }, + "ADB7": { + "direction": "input", + "bits": [ 84 ] + }, + "ADB6": { + "direction": "input", + "bits": [ 85 ] + }, + "ADB5": { + "direction": "input", + "bits": [ 86 ] + }, + "ADB4": { + "direction": "input", + "bits": [ 87 ] + }, + "ADB3": { + "direction": "input", + "bits": [ 88 ] + }, + "ADB2": { + "direction": "input", + "bits": [ 89 ] + }, + "ADB1": { + "direction": "input", + "bits": [ 90 ] + }, + "ADB0": { + "direction": "input", + "bits": [ 91 ] + }, + "CEB": { + "direction": "input", + "bits": [ 92 ] + }, + "OCEB": { + "direction": "input", + "bits": [ 93 ] + }, + "CLKB": { + "direction": "input", + "bits": [ 94 ] + }, + "WEB": { + "direction": "input", + "bits": [ 95 ] + }, + "RSTB": { + "direction": "input", + "bits": [ 96 ] + }, + "CSB2": { + "direction": "input", + "bits": [ 97 ] + }, + "CSB1": { + "direction": "input", + "bits": [ 98 ] + }, + "CSB0": { + "direction": "input", + "bits": [ 99 ] + }, + "DOB17": { + "direction": "output", + "bits": [ 100 ] + }, + "DOB16": { + "direction": "output", + "bits": [ 101 ] + }, + "DOB15": { + "direction": "output", + "bits": [ 102 ] + }, + "DOB14": { + "direction": "output", + "bits": [ 103 ] + }, + "DOB13": { + "direction": "output", + "bits": [ 104 ] + }, + "DOB12": { + "direction": "output", + "bits": [ 105 ] + }, + "DOB11": { + "direction": "output", + "bits": [ 106 ] + }, + "DOB10": { + "direction": "output", + "bits": [ 107 ] + }, + "DOB9": { + "direction": "output", + "bits": [ 108 ] + }, + "DOB8": { + "direction": "output", + "bits": [ 109 ] + }, + "DOB7": { + "direction": "output", + "bits": [ 110 ] + }, + "DOB6": { + "direction": "output", + "bits": [ 111 ] + }, + "DOB5": { + "direction": "output", + "bits": [ 112 ] + }, + "DOB4": { + "direction": "output", + "bits": [ 113 ] + }, + "DOB3": { + "direction": "output", + "bits": [ 114 ] + }, + "DOB2": { + "direction": "output", + "bits": [ 115 ] + }, + "DOB1": { + "direction": "output", + "bits": [ 116 ] + }, + "DOB0": { + "direction": "output", + "bits": [ 117 ] + } + }, + "cells": { + }, + "netnames": { + "ADA0": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.91-7.95" + } + }, + "ADA1": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.85-7.89" + } + }, + "ADA10": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.30-7.35" + } + }, + "ADA11": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.23-7.28" + } + }, + "ADA12": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.16-7.21" + } + }, + "ADA13": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.9-7.14" + } + }, + "ADA2": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.79-7.83" + } + }, + "ADA3": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.73-7.77" + } + }, + "ADA4": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.67-7.71" + } + }, + "ADA5": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.61-7.65" + } + }, + "ADA6": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.55-7.59" + } + }, + "ADA7": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.49-7.53" + } + }, + "ADA8": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.43-7.47" + } + }, + "ADA9": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.37-7.41" + } + }, + "ADB0": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.91-13.95" + } + }, + "ADB1": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.85-13.89" + } + }, + "ADB10": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.30-13.35" + } + }, + "ADB11": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.23-13.28" + } + }, + "ADB12": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.16-13.21" + } + }, + "ADB13": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.9-13.14" + } + }, + "ADB2": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.79-13.83" + } + }, + "ADB3": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.73-13.77" + } + }, + "ADB4": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.67-13.71" + } + }, + "ADB5": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.61-13.65" + } + }, + "ADB6": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.55-13.59" + } + }, + "ADB7": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.49-13.53" + } + }, + "ADB8": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.43-13.47" + } + }, + "ADB9": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.37-13.41" + } + }, + "CEA": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.9-8.12" + } + }, + "CEB": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.9-14.12" + } + }, + "CLKA": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.20-8.24" + } + }, + "CLKB": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.20-14.24" + } + }, + "CSA0": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:9.21-9.25" + } + }, + "CSA1": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:9.15-9.19" + } + }, + "CSA2": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:9.9-9.13" + } + }, + "CSB0": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:15.21-15.25" + } + }, + "CSB1": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:15.15-15.19" + } + }, + "CSB2": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:15.9-15.13" + } + }, + "DIA0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.119-6.123" + } + }, + "DIA1": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.113-6.117" + } + }, + "DIA10": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.58-6.63" + } + }, + "DIA11": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.51-6.56" + } + }, + "DIA12": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.44-6.49" + } + }, + "DIA13": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.37-6.42" + } + }, + "DIA14": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.30-6.35" + } + }, + "DIA15": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.23-6.28" + } + }, + "DIA16": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.16-6.21" + } + }, + "DIA17": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.9-6.14" + } + }, + "DIA2": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.107-6.111" + } + }, + "DIA3": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.101-6.105" + } + }, + "DIA4": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.95-6.99" + } + }, + "DIA5": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.89-6.93" + } + }, + "DIA6": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.83-6.87" + } + }, + "DIA7": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.77-6.81" + } + }, + "DIA8": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.71-6.75" + } + }, + "DIA9": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.65-6.69" + } + }, + "DIB0": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.119-12.123" + } + }, + "DIB1": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.113-12.117" + } + }, + "DIB10": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.58-12.63" + } + }, + "DIB11": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.51-12.56" + } + }, + "DIB12": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.44-12.49" + } + }, + "DIB13": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.37-12.42" + } + }, + "DIB14": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.30-12.35" + } + }, + "DIB15": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.23-12.28" + } + }, + "DIB16": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.16-12.21" + } + }, + "DIB17": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.9-12.14" + } + }, + "DIB2": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.107-12.111" + } + }, + "DIB3": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.101-12.105" + } + }, + "DIB4": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.95-12.99" + } + }, + "DIB5": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.89-12.93" + } + }, + "DIB6": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.83-12.87" + } + }, + "DIB7": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.77-12.81" + } + }, + "DIB8": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.71-12.75" + } + }, + "DIB9": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.65-12.69" + } + }, + "DOA0": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.120-10.124" + } + }, + "DOA1": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.114-10.118" + } + }, + "DOA10": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.59-10.64" + } + }, + "DOA11": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.52-10.57" + } + }, + "DOA12": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.45-10.50" + } + }, + "DOA13": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.38-10.43" + } + }, + "DOA14": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.31-10.36" + } + }, + "DOA15": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.24-10.29" + } + }, + "DOA16": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.17-10.22" + } + }, + "DOA17": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.10-10.15" + } + }, + "DOA2": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.108-10.112" + } + }, + "DOA3": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.102-10.106" + } + }, + "DOA4": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.96-10.100" + } + }, + "DOA5": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.90-10.94" + } + }, + "DOA6": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.84-10.88" + } + }, + "DOA7": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.78-10.82" + } + }, + "DOA8": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.72-10.76" + } + }, + "DOA9": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.66-10.70" + } + }, + "DOB0": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.120-16.124" + } + }, + "DOB1": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.114-16.118" + } + }, + "DOB10": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.59-16.64" + } + }, + "DOB11": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.52-16.57" + } + }, + "DOB12": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.45-16.50" + } + }, + "DOB13": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.38-16.43" + } + }, + "DOB14": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.31-16.36" + } + }, + "DOB15": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.24-16.29" + } + }, + "DOB16": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.17-16.22" + } + }, + "DOB17": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.10-16.15" + } + }, + "DOB2": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.108-16.112" + } + }, + "DOB3": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.102-16.106" + } + }, + "DOB4": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.96-16.100" + } + }, + "DOB5": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.90-16.94" + } + }, + "DOB6": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.84-16.88" + } + }, + "DOB7": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.78-16.82" + } + }, + "DOB8": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.72-16.76" + } + }, + "DOB9": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.66-16.70" + } + }, + "OCEA": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.14-8.18" + } + }, + "OCEB": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.14-14.18" + } + }, + "RSTA": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.31-8.35" + } + }, + "RSTB": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.31-14.35" + } + }, + "WEA": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.26-8.29" + } + }, + "WEB": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.26-14.29" + } + } + } + }, + "DPR16X4C": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000110", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:174.1-233.10" + }, + "parameter_default_values": { + "INITVAL": "0x0000000000000000 " + }, + "ports": { + "DI": { + "direction": "input", + "bits": [ 2, 3, 4, 5 ] + }, + "WCK": { + "direction": "input", + "bits": [ 6 ] + }, + "WRE": { + "direction": "input", + "bits": [ 7 ] + }, + "RAD": { + "direction": "input", + "bits": [ 8, 9, 10, 11 ] + }, + "WAD": { + "direction": "input", + "bits": [ 12, 13, 14, 15 ] + }, + "DO": { + "direction": "output", + "bits": [ 16, 17, 18, 19 ] + } + }, + "cells": { + }, + "netnames": { + "DI": { + "hide_name": 0, + "bits": [ 2, 3, 4, 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:175.15-175.17" + } + }, + "DO": { + "hide_name": 0, + "bits": [ 16, 17, 18, 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:179.16-179.18" + } + }, + "RAD": { + "hide_name": 0, + "bits": [ 8, 9, 10, 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:177.15-177.18" + } + }, + "WAD": { + "hide_name": 0, + "bits": [ 12, 13, 14, 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:178.15-178.18" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:176.9-176.12" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:176.14-176.17" + } + } + } + }, + "DQSBUFM": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1091.1-1136.10" + }, + "parameter_default_values": { + "DQS_LI_DEL_ADJ": "FACTORYONLY", + "DQS_LI_DEL_VAL": "00000000000000000000000000000100", + "DQS_LO_DEL_ADJ": "FACTORYONLY", + "DQS_LO_DEL_VAL": "00000000000000000000000000000000", + "GSR": "ENABLED" + }, + "ports": { + "DQSI": { + "direction": "input", + "bits": [ 2 ] + }, + "READ1": { + "direction": "input", + "bits": [ 3 ] + }, + "READ0": { + "direction": "input", + "bits": [ 4 ] + }, + "READCLKSEL2": { + "direction": "input", + "bits": [ 5 ] + }, + "READCLKSEL1": { + "direction": "input", + "bits": [ 6 ] + }, + "READCLKSEL0": { + "direction": "input", + "bits": [ 7 ] + }, + "DDRDEL": { + "direction": "input", + "bits": [ 8 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 9 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "RST": { + "direction": "input", + "bits": [ 11 ] + }, + "DYNDELAY7": { + "direction": "input", + "bits": [ 12 ] + }, + "DYNDELAY6": { + "direction": "input", + "bits": [ 13 ] + }, + "DYNDELAY5": { + "direction": "input", + "bits": [ 14 ] + }, + "DYNDELAY4": { + "direction": "input", + "bits": [ 15 ] + }, + "DYNDELAY3": { + "direction": "input", + "bits": [ 16 ] + }, + "DYNDELAY2": { + "direction": "input", + "bits": [ 17 ] + }, + "DYNDELAY1": { + "direction": "input", + "bits": [ 18 ] + }, + "DYNDELAY0": { + "direction": "input", + "bits": [ 19 ] + }, + "PAUSE": { + "direction": "input", + "bits": [ 20 ] + }, + "RDLOADN": { + "direction": "input", + "bits": [ 21 ] + }, + "RDMOVE": { + "direction": "input", + "bits": [ 22 ] + }, + "RDDIRECTION": { + "direction": "input", + "bits": [ 23 ] + }, + "WRLOADN": { + "direction": "input", + "bits": [ 24 ] + }, + "WRMOVE": { + "direction": "input", + "bits": [ 25 ] + }, + "WRDIRECTION": { + "direction": "input", + "bits": [ 26 ] + }, + "DQSR90": { + "direction": "output", + "bits": [ 27 ] + }, + "DQSW": { + "direction": "output", + "bits": [ 28 ] + }, + "DQSW270": { + "direction": "output", + "bits": [ 29 ] + }, + "RDPNTR2": { + "direction": "output", + "bits": [ 30 ] + }, + "RDPNTR1": { + "direction": "output", + "bits": [ 31 ] + }, + "RDPNTR0": { + "direction": "output", + "bits": [ 32 ] + }, + "WRPNTR2": { + "direction": "output", + "bits": [ 33 ] + }, + "WRPNTR1": { + "direction": "output", + "bits": [ 34 ] + }, + "WRPNTR0": { + "direction": "output", + "bits": [ 35 ] + }, + "DATAVALID": { + "direction": "output", + "bits": [ 36 ] + }, + "BURSTDET": { + "direction": "output", + "bits": [ 37 ] + }, + "RDCFLAG": { + "direction": "output", + "bits": [ 38 ] + }, + "WRCFLAG": { + "direction": "output", + "bits": [ 39 ] + } + }, + "cells": { + }, + "netnames": { + "BURSTDET": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1133.12-1133.20" + } + }, + "DATAVALID": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1132.12-1132.21" + } + }, + "DDRDEL": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1104.11-1104.17" + } + }, + "DQSI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1098.11-1098.15" + } + }, + "DQSR90": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1123.12-1123.18" + } + }, + "DQSW": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1124.12-1124.16" + } + }, + "DQSW270": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1125.12-1125.19" + } + }, + "DYNDELAY0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1115.11-1115.20" + } + }, + "DYNDELAY1": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1114.11-1114.20" + } + }, + "DYNDELAY2": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1113.11-1113.20" + } + }, + "DYNDELAY3": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1112.11-1112.20" + } + }, + "DYNDELAY4": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1111.11-1111.20" + } + }, + "DYNDELAY5": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1110.11-1110.20" + } + }, + "DYNDELAY6": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1109.11-1109.20" + } + }, + "DYNDELAY7": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1108.11-1108.20" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1105.11-1105.15" + } + }, + "PAUSE": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1116.11-1116.16" + } + }, + "RDCFLAG": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1134.12-1134.19" + } + }, + "RDDIRECTION": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1119.11-1119.22" + } + }, + "RDLOADN": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1117.11-1117.18" + } + }, + "RDMOVE": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1118.11-1118.17" + } + }, + "RDPNTR0": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1128.12-1128.19" + } + }, + "RDPNTR1": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1127.12-1127.19" + } + }, + "RDPNTR2": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1126.12-1126.19" + } + }, + "READ0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1100.11-1100.16" + } + }, + "READ1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1099.11-1099.16" + } + }, + "READCLKSEL0": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1103.11-1103.22" + } + }, + "READCLKSEL1": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1102.11-1102.22" + } + }, + "READCLKSEL2": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1101.11-1101.22" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1107.11-1107.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1106.11-1106.15" + } + }, + "WRCFLAG": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1135.12-1135.19" + } + }, + "WRDIRECTION": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1122.11-1122.22" + } + }, + "WRLOADN": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1120.11-1120.18" + } + }, + "WRMOVE": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1121.11-1121.17" + } + }, + "WRPNTR0": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1131.12-1131.19" + } + }, + "WRPNTR1": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1130.12-1130.19" + } + }, + "WRPNTR2": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1129.12-1129.19" + } + } + } + }, + "DTR": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1399.1-1410.10" + }, + "parameter_default_values": { + "DTR_TEMP": "00000000000000000000000000011001" + }, + "ports": { + "STARTPULSE": { + "direction": "input", + "bits": [ 2 ] + }, + "DTROUT7": { + "direction": "output", + "bits": [ 3 ] + }, + "DTROUT6": { + "direction": "output", + "bits": [ 4 ] + }, + "DTROUT5": { + "direction": "output", + "bits": [ 5 ] + }, + "DTROUT4": { + "direction": "output", + "bits": [ 6 ] + }, + "DTROUT3": { + "direction": "output", + "bits": [ 7 ] + }, + "DTROUT2": { + "direction": "output", + "bits": [ 8 ] + }, + "DTROUT1": { + "direction": "output", + "bits": [ 9 ] + }, + "DTROUT0": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "DTROUT0": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1409.12-1409.19" + } + }, + "DTROUT1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1408.12-1408.19" + } + }, + "DTROUT2": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1407.12-1407.19" + } + }, + "DTROUT3": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1406.12-1406.19" + } + }, + "DTROUT4": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1405.12-1405.19" + } + }, + "DTROUT5": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1404.12-1404.19" + } + }, + "DTROUT6": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1403.12-1403.19" + } + }, + "DTROUT7": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1402.12-1402.19" + } + }, + "STARTPULSE": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1401.11-1401.21" + } + } + } + }, + "ECLKBRIDGECS": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1057.1-1062.10" + }, + "ports": { + "CLK0": { + "direction": "input", + "bits": [ 2 ] + }, + "CLK1": { + "direction": "input", + "bits": [ 3 ] + }, + "SEL": { + "direction": "input", + "bits": [ 4 ] + }, + "ECSOUT": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CLK0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1058.11-1058.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1059.11-1059.15" + } + }, + "ECSOUT": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1061.12-1061.18" + } + }, + "SEL": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1060.11-1060.14" + } + } + } + }, + "ECLKSYNCB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1050.1-1054.10" + }, + "ports": { + "ECLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "STOP": { + "direction": "input", + "bits": [ 3 ] + }, + "ECLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "ECLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1051.11-1051.16" + } + }, + "ECLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1053.12-1053.17" + } + }, + "STOP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1052.11-1052.15" + } + } + } + }, + "EHXPLLL": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1336.1-1396.10" + }, + "parameter_default_values": { + "CLKFB_DIV": "00000000000000000000000000000001", + "CLKI_DIV": "00000000000000000000000000000001", + "CLKOP_CPHASE": "00000000000000000000000000000000", + "CLKOP_DIV": "00000000000000000000000000001000", + "CLKOP_ENABLE": "ENABLED", + "CLKOP_FPHASE": "00000000000000000000000000000000", + "CLKOP_TRIM_DELAY": "00000000000000000000000000000000", + "CLKOP_TRIM_POL": "RISING", + "CLKOS2_CPHASE": "00000000000000000000000000000000", + "CLKOS2_DIV": "00000000000000000000000000001000", + "CLKOS2_ENABLE": "DISABLED", + "CLKOS2_FPHASE": "00000000000000000000000000000000", + "CLKOS3_CPHASE": "00000000000000000000000000000000", + "CLKOS3_DIV": "00000000000000000000000000001000", + "CLKOS3_ENABLE": "DISABLED", + "CLKOS3_FPHASE": "00000000000000000000000000000000", + "CLKOS_CPHASE": "00000000000000000000000000000000", + "CLKOS_DIV": "00000000000000000000000000001000", + "CLKOS_ENABLE": "DISABLED", + "CLKOS_FPHASE": "00000000000000000000000000000000", + "CLKOS_TRIM_DELAY": "00000000000000000000000000000000", + "CLKOS_TRIM_POL": "RISING", + "DPHASE_SOURCE": "DISABLED", + "FEEDBK_PATH": "CLKOP", + "INTFB_WAKE": "DISABLED", + "INT_LOCK_STICKY": "ENABLED", + "OUTDIVIDER_MUXA": "DIVA", + "OUTDIVIDER_MUXB": "DIVB", + "OUTDIVIDER_MUXC": "DIVC", + "OUTDIVIDER_MUXD": "DIVD", + "PLLRST_ENA": "DISABLED", + "PLL_LOCK_DELAY": "00000000000000000000000011001000", + "PLL_LOCK_MODE": "00000000000000000000000000000000", + "REFIN_RESET": "DISABLED", + "STDBY_ENABLE": "DISABLED", + "SYNC_ENABLE": "DISABLED" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "CLKFB": { + "direction": "input", + "bits": [ 3 ] + }, + "PHASESEL1": { + "direction": "input", + "bits": [ 4 ] + }, + "PHASESEL0": { + "direction": "input", + "bits": [ 5 ] + }, + "PHASEDIR": { + "direction": "input", + "bits": [ 6 ] + }, + "PHASESTEP": { + "direction": "input", + "bits": [ 7 ] + }, + "PHASELOADREG": { + "direction": "input", + "bits": [ 8 ] + }, + "STDBY": { + "direction": "input", + "bits": [ 9 ] + }, + "PLLWAKESYNC": { + "direction": "input", + "bits": [ 10 ] + }, + "RST": { + "direction": "input", + "bits": [ 11 ] + }, + "ENCLKOP": { + "direction": "input", + "bits": [ 12 ] + }, + "ENCLKOS": { + "direction": "input", + "bits": [ 13 ] + }, + "ENCLKOS2": { + "direction": "input", + "bits": [ 14 ] + }, + "ENCLKOS3": { + "direction": "input", + "bits": [ 15 ] + }, + "CLKOP": { + "direction": "output", + "bits": [ 16 ] + }, + "CLKOS": { + "direction": "output", + "bits": [ 17 ] + }, + "CLKOS2": { + "direction": "output", + "bits": [ 18 ] + }, + "CLKOS3": { + "direction": "output", + "bits": [ 19 ] + }, + "LOCK": { + "direction": "output", + "bits": [ 20 ] + }, + "INTLOCK": { + "direction": "output", + "bits": [ 21 ] + }, + "REFCLK": { + "direction": "output", + "bits": [ 22 ] + }, + "CLKINTFB": { + "direction": "output", + "bits": [ 23 ] + } + }, + "cells": { + }, + "netnames": { + "CLKFB": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1375.11-1375.16" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1374.11-1374.15" + } + }, + "CLKINTFB": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1395.12-1395.20" + } + }, + "CLKOP": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1388.12-1388.17" + } + }, + "CLKOS": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1389.12-1389.17" + } + }, + "CLKOS2": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1390.12-1390.18" + } + }, + "CLKOS3": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1391.12-1391.18" + } + }, + "ENCLKOP": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1384.11-1384.18" + } + }, + "ENCLKOS": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1385.11-1385.18" + } + }, + "ENCLKOS2": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1386.11-1386.19" + } + }, + "ENCLKOS3": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1387.11-1387.19" + } + }, + "INTLOCK": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1393.12-1393.19" + } + }, + "LOCK": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1392.12-1392.16" + } + }, + "PHASEDIR": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1378.11-1378.19" + } + }, + "PHASELOADREG": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1380.11-1380.23" + } + }, + "PHASESEL0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1377.11-1377.20" + } + }, + "PHASESEL1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1376.11-1376.20" + } + }, + "PHASESTEP": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1379.11-1379.20" + } + }, + "PLLWAKESYNC": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1382.11-1382.22" + } + }, + "REFCLK": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1394.12-1394.18" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1383.11-1383.14" + } + }, + "STDBY": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1381.11-1381.16" + } + } + } + }, + "EXTREFB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1419.1-1428.10" + }, + "parameter_default_values": { + "REFCK_DCBIAS_EN": "DONTCARE", + "REFCK_PWDNB": "DONTCARE", + "REFCK_RTERM": "DONTCARE" + }, + "ports": { + "REFCLKP": { + "direction": "input", + "bits": [ 2 ] + }, + "REFCLKN": { + "direction": "input", + "bits": [ 3 ] + }, + "REFCLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "REFCLKN": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1426.11-1426.18" + } + }, + "REFCLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1427.12-1427.19" + } + }, + "REFCLKP": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1424.11-1424.18" + } + } + } + }, + "FD1P3AX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SP": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.33-2.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.26-2.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.44-2.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.29-2.31" + } + } + } + }, + "FD1P3AY": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SP": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.33-3.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.26-3.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.44-3.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.29-3.31" + } + } + } + }, + "FD1P3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.33-4.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.26-4.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.22-4.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.44-4.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.29-4.31" + } + } + } + }, + "FD1P3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.22-5.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.33-5.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.26-5.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.44-5.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.29-5.31" + } + } + } + }, + "FD1P3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.22-6.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.33-6.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.26-6.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.44-6.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.29-6.31" + } + } + } + }, + "FD1P3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.33-7.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.26-7.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.22-7.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.44-7.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.29-7.31" + } + } + } + }, + "FD1S3AX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "CK": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.33-8.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.26-8.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.44-8.45" + } + } + } + }, + "FD1S3AY": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "CK": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.33-9.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.26-9.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.44-9.45" + } + } + } + }, + "FD1S3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.33-10.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.26-10.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.22-10.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.44-10.45" + } + } + } + }, + "FD1S3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.22-11.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.33-11.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.26-11.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.44-11.45" + } + } + } + }, + "FD1S3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.22-12.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.33-12.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.26-12.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.44-12.45" + } + } + } + }, + "FD1S3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.33-13.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.26-13.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.22-13.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.44-13.45" + } + } + } + }, + "GSR": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:4.1-6.10" + }, + "ports": { + "GSR": { + "direction": "input", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "GSR": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:5.11-5.14" + } + } + } + }, + "IB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.45-2.46" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.59-2.60" + } + } + } + }, + "IBPD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.45-4.46" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.59-4.60" + } + } + } + }, + "IBPU": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.45-3.46" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.59-3.60" + } + } + } + }, + "IDDR71B": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1194.1-1208.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 3 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 4 ] + }, + "RST": { + "direction": "input", + "bits": [ 5 ] + }, + "ALIGNWD": { + "direction": "input", + "bits": [ 6 ] + }, + "Q6": { + "direction": "output", + "bits": [ 7 ] + }, + "Q5": { + "direction": "output", + "bits": [ 8 ] + }, + "Q4": { + "direction": "output", + "bits": [ 9 ] + }, + "Q3": { + "direction": "output", + "bits": [ 10 ] + }, + "Q2": { + "direction": "output", + "bits": [ 11 ] + }, + "Q1": { + "direction": "output", + "bits": [ 12 ] + }, + "Q0": { + "direction": "output", + "bits": [ 13 ] + } + }, + "cells": { + }, + "netnames": { + "ALIGNWD": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1200.11-1200.18" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1196.11-1196.12" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1198.11-1198.15" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1207.12-1207.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1206.12-1206.14" + } + }, + "Q2": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1205.12-1205.14" + } + }, + "Q3": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1204.12-1204.14" + } + }, + "Q4": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1203.12-1203.14" + } + }, + "Q5": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1202.12-1202.14" + } + }, + "Q6": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1201.12-1201.14" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1199.11-1199.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1197.11-1197.15" + } + } + } + }, + "IDDRX1F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1170.1-1177.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 3 ] + }, + "RST": { + "direction": "input", + "bits": [ 4 ] + }, + "Q0": { + "direction": "output", + "bits": [ 5 ] + }, + "Q1": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1172.11-1172.12" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1175.12-1175.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1176.12-1176.14" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1174.11-1174.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1173.11-1173.15" + } + } + } + }, + "IDDRX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1211.1-1229.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 3 ] + }, + "DQSR90": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "RST": { + "direction": "input", + "bits": [ 6 ] + }, + "RDPNTR2": { + "direction": "input", + "bits": [ 7 ] + }, + "RDPNTR1": { + "direction": "input", + "bits": [ 8 ] + }, + "RDPNTR0": { + "direction": "input", + "bits": [ 9 ] + }, + "WRPNTR2": { + "direction": "input", + "bits": [ 10 ] + }, + "WRPNTR1": { + "direction": "input", + "bits": [ 11 ] + }, + "WRPNTR0": { + "direction": "input", + "bits": [ 12 ] + }, + "Q3": { + "direction": "output", + "bits": [ 13 ] + }, + "Q2": { + "direction": "output", + "bits": [ 14 ] + }, + "Q1": { + "direction": "output", + "bits": [ 15 ] + }, + "Q0": { + "direction": "output", + "bits": [ 16 ] + }, + "QWL": { + "direction": "output", + "bits": [ 17 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1216.11-1216.12" + } + }, + "DQSR90": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1215.11-1215.17" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1214.11-1214.15" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1227.12-1227.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1226.12-1226.14" + } + }, + "Q2": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1225.12-1225.14" + } + }, + "Q3": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1224.12-1224.14" + } + }, + "QWL": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1228.12-1228.15" + } + }, + "RDPNTR0": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1220.11-1220.18" + } + }, + "RDPNTR1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1219.11-1219.18" + } + }, + "RDPNTR2": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1218.11-1218.18" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1217.11-1217.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1213.11-1213.15" + } + }, + "WRPNTR0": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1223.11-1223.18" + } + }, + "WRPNTR1": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1222.11-1222.18" + } + }, + "WRPNTR2": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1221.11-1221.18" + } + } + } + }, + "IDDRX2F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1180.1-1191.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 3 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 4 ] + }, + "RST": { + "direction": "input", + "bits": [ 5 ] + }, + "ALIGNWD": { + "direction": "input", + "bits": [ 6 ] + }, + "Q3": { + "direction": "output", + "bits": [ 7 ] + }, + "Q2": { + "direction": "output", + "bits": [ 8 ] + }, + "Q1": { + "direction": "output", + "bits": [ 9 ] + }, + "Q0": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "ALIGNWD": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1186.11-1186.18" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1182.11-1182.12" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1184.11-1184.15" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1190.12-1190.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1189.12-1189.14" + } + }, + "Q2": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1188.12-1188.14" + } + }, + "Q3": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1187.12-1187.14" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1185.11-1185.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1183.11-1183.15" + } + } + } + }, + "IFS1P3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.27-26.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.23-26.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.47-26.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.34-26.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.30-26.32" + } + } + } + }, + "IFS1P3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.23-27.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.27-27.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.47-27.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.34-27.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.30-27.32" + } + } + } + }, + "IFS1P3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.23-28.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.27-28.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.47-28.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.34-28.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.30-28.32" + } + } + } + }, + "IFS1P3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.27-29.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.23-29.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.47-29.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.34-29.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.30-29.32" + } + } + } + }, + "ILVDS": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "AN": { + "direction": "input", + "bits": [ 3 ] + }, + "Z": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.20-13.21" + } + }, + "AN": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.23-13.25" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.59-13.60" + } + } + } + }, + "INV": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:348.1-350.10" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "Z": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:348.18-348.19" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:348.28-348.29" + } + } + } + }, + "JTAGG": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1431.1-1453.10" + }, + "parameter_default_values": { + "ER1": "ENABLED", + "ER2": "ENABLED" + }, + "ports": { + "TCK": { + "direction": "input", + "bits": [ 2 ] + }, + "TMS": { + "direction": "input", + "bits": [ 3 ] + }, + "TDI": { + "direction": "input", + "bits": [ 4 ] + }, + "JTDO2": { + "direction": "input", + "bits": [ 5 ] + }, + "JTDO1": { + "direction": "input", + "bits": [ 6 ] + }, + "TDO": { + "direction": "output", + "bits": [ 7 ] + }, + "JTDI": { + "direction": "output", + "bits": [ 8 ] + }, + "JTCK": { + "direction": "output", + "bits": [ 9 ] + }, + "JRTI2": { + "direction": "output", + "bits": [ 10 ] + }, + "JRTI1": { + "direction": "output", + "bits": [ 11 ] + }, + "JSHIFT": { + "direction": "output", + "bits": [ 12 ] + }, + "JUPDATE": { + "direction": "output", + "bits": [ 13 ] + }, + "JRSTN": { + "direction": "output", + "bits": [ 14 ] + }, + "JCE2": { + "direction": "output", + "bits": [ 15 ] + }, + "JCE1": { + "direction": "output", + "bits": [ 16 ] + } + }, + "cells": { + }, + "netnames": { + "JCE1": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1452.12-1452.16" + } + }, + "JCE2": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1451.12-1451.16" + } + }, + "JRSTN": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1450.12-1450.17" + } + }, + "JRTI1": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1447.12-1447.17" + } + }, + "JRTI2": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1446.12-1446.17" + } + }, + "JSHIFT": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1448.12-1448.18" + } + }, + "JTCK": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1445.12-1445.16" + } + }, + "JTDI": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1444.12-1444.16" + } + }, + "JTDO1": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1441.11-1441.16" + } + }, + "JTDO2": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1440.11-1440.16" + } + }, + "JUPDATE": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1449.12-1449.19" + } + }, + "TCK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1435.11-1435.14" + } + }, + "TDI": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1439.11-1439.14" + } + }, + "TDO": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1443.12-1443.15" + } + }, + "TMS": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1437.11-1437.14" + } + } + } + }, + "L6MUX21": { + "attributes": { + "abc9_box_id": "00000000000000000000000000001001", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.1-72.10" + }, + "ports": { + "D0": { + "direction": "input", + "bits": [ 2 ] + }, + "D1": { + "direction": "input", + "bits": [ 3 ] + }, + "SD": { + "direction": "input", + "bits": [ 4 ] + }, + "Z": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.23-65.25" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.27-65.29" + } + }, + "SD": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.31-65.33" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.42-65.43" + } + } + } + }, + "LUT2": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.1-242.10" + }, + "parameter_default_values": { + "INIT": "0000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "B": { + "direction": "input", + "bits": [ 3 ] + }, + "Z": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.19-238.20" + } + }, + "B": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.22-238.23" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.32-238.33" + } + } + } + }, + "LUT4": { + "attributes": { + "abc9_lut": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.1-16.10" + }, + "parameter_default_values": { + "INIT": "0000000000000000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "B": { + "direction": "input", + "bits": [ 3 ] + }, + "C": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "Z": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.19-4.20" + } + }, + "B": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.22-4.23" + } + }, + "C": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.25-4.26" + } + }, + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.28-4.29" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.38-4.39" + } + } + } + }, + "MULT18X18D": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:216.1-486.10" + }, + "parameter_default_values": { + "CAS_MATCH_REG": "FALSE", + "CLK0_DIV": "ENABLED", + "CLK1_DIV": "ENABLED", + "CLK2_DIV": "ENABLED", + "CLK3_DIV": "ENABLED", + "GSR": "ENABLED", + "HIGHSPEED_CLK": "NONE", + "MULT_BYPASS": "DISABLED", + "REG_INPUTA_CE": "CE0", + "REG_INPUTA_CLK": "NONE", + "REG_INPUTA_RST": "RST0", + "REG_INPUTB_CE": "CE0", + "REG_INPUTB_CLK": "NONE", + "REG_INPUTB_RST": "RST0", + "REG_INPUTC_CE": "CE0", + "REG_INPUTC_CLK": "NONE", + "REG_INPUTC_RST": "RST0", + "REG_OUTPUT_CE": "CE0", + "REG_OUTPUT_CLK": "NONE", + "REG_OUTPUT_RST": "RST0", + "REG_PIPELINE_CE": "CE0", + "REG_PIPELINE_CLK": "NONE", + "REG_PIPELINE_RST": "RST0", + "RESETMODE": "SYNC", + "SOURCEB_MODE": "B_SHIFT" + }, + "ports": { + "A17": { + "direction": "input", + "bits": [ 2 ] + }, + "A16": { + "direction": "input", + "bits": [ 3 ] + }, + "A15": { + "direction": "input", + "bits": [ 4 ] + }, + "A14": { + "direction": "input", + "bits": [ 5 ] + }, + "A13": { + "direction": "input", + "bits": [ 6 ] + }, + "A12": { + "direction": "input", + "bits": [ 7 ] + }, + "A11": { + "direction": "input", + "bits": [ 8 ] + }, + "A10": { + "direction": "input", + "bits": [ 9 ] + }, + "A9": { + "direction": "input", + "bits": [ 10 ] + }, + "A8": { + "direction": "input", + "bits": [ 11 ] + }, + "A7": { + "direction": "input", + "bits": [ 12 ] + }, + "A6": { + "direction": "input", + "bits": [ 13 ] + }, + "A5": { + "direction": "input", + "bits": [ 14 ] + }, + "A4": { + "direction": "input", + "bits": [ 15 ] + }, + "A3": { + "direction": "input", + "bits": [ 16 ] + }, + "A2": { + "direction": "input", + "bits": [ 17 ] + }, + "A1": { + "direction": "input", + "bits": [ 18 ] + }, + "A0": { + "direction": "input", + "bits": [ 19 ] + }, + "B17": { + "direction": "input", + "bits": [ 20 ] + }, + "B16": { + "direction": "input", + "bits": [ 21 ] + }, + "B15": { + "direction": "input", + "bits": [ 22 ] + }, + "B14": { + "direction": "input", + "bits": [ 23 ] + }, + "B13": { + "direction": "input", + "bits": [ 24 ] + }, + "B12": { + "direction": "input", + "bits": [ 25 ] + }, + "B11": { + "direction": "input", + "bits": [ 26 ] + }, + "B10": { + "direction": "input", + "bits": [ 27 ] + }, + "B9": { + "direction": "input", + "bits": [ 28 ] + }, + "B8": { + "direction": "input", + "bits": [ 29 ] + }, + "B7": { + "direction": "input", + "bits": [ 30 ] + }, + "B6": { + "direction": "input", + "bits": [ 31 ] + }, + "B5": { + "direction": "input", + "bits": [ 32 ] + }, + "B4": { + "direction": "input", + "bits": [ 33 ] + }, + "B3": { + "direction": "input", + "bits": [ 34 ] + }, + "B2": { + "direction": "input", + "bits": [ 35 ] + }, + "B1": { + "direction": "input", + "bits": [ 36 ] + }, + "B0": { + "direction": "input", + "bits": [ 37 ] + }, + "C17": { + "direction": "input", + "bits": [ 38 ] + }, + "C16": { + "direction": "input", + "bits": [ 39 ] + }, + "C15": { + "direction": "input", + "bits": [ 40 ] + }, + "C14": { + "direction": "input", + "bits": [ 41 ] + }, + "C13": { + "direction": "input", + "bits": [ 42 ] + }, + "C12": { + "direction": "input", + "bits": [ 43 ] + }, + "C11": { + "direction": "input", + "bits": [ 44 ] + }, + "C10": { + "direction": "input", + "bits": [ 45 ] + }, + "C9": { + "direction": "input", + "bits": [ 46 ] + }, + "C8": { + "direction": "input", + "bits": [ 47 ] + }, + "C7": { + "direction": "input", + "bits": [ 48 ] + }, + "C6": { + "direction": "input", + "bits": [ 49 ] + }, + "C5": { + "direction": "input", + "bits": [ 50 ] + }, + "C4": { + "direction": "input", + "bits": [ 51 ] + }, + "C3": { + "direction": "input", + "bits": [ 52 ] + }, + "C2": { + "direction": "input", + "bits": [ 53 ] + }, + "C1": { + "direction": "input", + "bits": [ 54 ] + }, + "C0": { + "direction": "input", + "bits": [ 55 ] + }, + "SIGNEDA": { + "direction": "input", + "bits": [ 56 ] + }, + "SIGNEDB": { + "direction": "input", + "bits": [ 57 ] + }, + "SOURCEA": { + "direction": "input", + "bits": [ 58 ] + }, + "SOURCEB": { + "direction": "input", + "bits": [ 59 ] + }, + "CLK3": { + "direction": "input", + "bits": [ 60 ] + }, + "CLK2": { + "direction": "input", + "bits": [ 61 ] + }, + "CLK1": { + "direction": "input", + "bits": [ 62 ] + }, + "CLK0": { + "direction": "input", + "bits": [ 63 ] + }, + "CE3": { + "direction": "input", + "bits": [ 64 ] + }, + "CE2": { + "direction": "input", + "bits": [ 65 ] + }, + "CE1": { + "direction": "input", + "bits": [ 66 ] + }, + "CE0": { + "direction": "input", + "bits": [ 67 ] + }, + "RST3": { + "direction": "input", + "bits": [ 68 ] + }, + "RST2": { + "direction": "input", + "bits": [ 69 ] + }, + "RST1": { + "direction": "input", + "bits": [ 70 ] + }, + "RST0": { + "direction": "input", + "bits": [ 71 ] + }, + "SRIA17": { + "direction": "input", + "bits": [ 72 ] + }, + "SRIA16": { + "direction": "input", + "bits": [ 73 ] + }, + "SRIA15": { + "direction": "input", + "bits": [ 74 ] + }, + "SRIA14": { + "direction": "input", + "bits": [ 75 ] + }, + "SRIA13": { + "direction": "input", + "bits": [ 76 ] + }, + "SRIA12": { + "direction": "input", + "bits": [ 77 ] + }, + "SRIA11": { + "direction": "input", + "bits": [ 78 ] + }, + "SRIA10": { + "direction": "input", + "bits": [ 79 ] + }, + "SRIA9": { + "direction": "input", + "bits": [ 80 ] + }, + "SRIA8": { + "direction": "input", + "bits": [ 81 ] + }, + "SRIA7": { + "direction": "input", + "bits": [ 82 ] + }, + "SRIA6": { + "direction": "input", + "bits": [ 83 ] + }, + "SRIA5": { + "direction": "input", + "bits": [ 84 ] + }, + "SRIA4": { + "direction": "input", + "bits": [ 85 ] + }, + "SRIA3": { + "direction": "input", + "bits": [ 86 ] + }, + "SRIA2": { + "direction": "input", + "bits": [ 87 ] + }, + "SRIA1": { + "direction": "input", + "bits": [ 88 ] + }, + "SRIA0": { + "direction": "input", + "bits": [ 89 ] + }, + "SRIB17": { + "direction": "input", + "bits": [ 90 ] + }, + "SRIB16": { + "direction": "input", + "bits": [ 91 ] + }, + "SRIB15": { + "direction": "input", + "bits": [ 92 ] + }, + "SRIB14": { + "direction": "input", + "bits": [ 93 ] + }, + "SRIB13": { + "direction": "input", + "bits": [ 94 ] + }, + "SRIB12": { + "direction": "input", + "bits": [ 95 ] + }, + "SRIB11": { + "direction": "input", + "bits": [ 96 ] + }, + "SRIB10": { + "direction": "input", + "bits": [ 97 ] + }, + "SRIB9": { + "direction": "input", + "bits": [ 98 ] + }, + "SRIB8": { + "direction": "input", + "bits": [ 99 ] + }, + "SRIB7": { + "direction": "input", + "bits": [ 100 ] + }, + "SRIB6": { + "direction": "input", + "bits": [ 101 ] + }, + "SRIB5": { + "direction": "input", + "bits": [ 102 ] + }, + "SRIB4": { + "direction": "input", + "bits": [ 103 ] + }, + "SRIB3": { + "direction": "input", + "bits": [ 104 ] + }, + "SRIB2": { + "direction": "input", + "bits": [ 105 ] + }, + "SRIB1": { + "direction": "input", + "bits": [ 106 ] + }, + "SRIB0": { + "direction": "input", + "bits": [ 107 ] + }, + "SROA17": { + "direction": "output", + "bits": [ 108 ] + }, + "SROA16": { + "direction": "output", + "bits": [ 109 ] + }, + "SROA15": { + "direction": "output", + "bits": [ 110 ] + }, + "SROA14": { + "direction": "output", + "bits": [ 111 ] + }, + "SROA13": { + "direction": "output", + "bits": [ 112 ] + }, + "SROA12": { + "direction": "output", + "bits": [ 113 ] + }, + "SROA11": { + "direction": "output", + "bits": [ 114 ] + }, + "SROA10": { + "direction": "output", + "bits": [ 115 ] + }, + "SROA9": { + "direction": "output", + "bits": [ 116 ] + }, + "SROA8": { + "direction": "output", + "bits": [ 117 ] + }, + "SROA7": { + "direction": "output", + "bits": [ 118 ] + }, + "SROA6": { + "direction": "output", + "bits": [ 119 ] + }, + "SROA5": { + "direction": "output", + "bits": [ 120 ] + }, + "SROA4": { + "direction": "output", + "bits": [ 121 ] + }, + "SROA3": { + "direction": "output", + "bits": [ 122 ] + }, + "SROA2": { + "direction": "output", + "bits": [ 123 ] + }, + "SROA1": { + "direction": "output", + "bits": [ 124 ] + }, + "SROA0": { + "direction": "output", + "bits": [ 125 ] + }, + "SROB17": { + "direction": "output", + "bits": [ 126 ] + }, + "SROB16": { + "direction": "output", + "bits": [ 127 ] + }, + "SROB15": { + "direction": "output", + "bits": [ 128 ] + }, + "SROB14": { + "direction": "output", + "bits": [ 129 ] + }, + "SROB13": { + "direction": "output", + "bits": [ 130 ] + }, + "SROB12": { + "direction": "output", + "bits": [ 131 ] + }, + "SROB11": { + "direction": "output", + "bits": [ 132 ] + }, + "SROB10": { + "direction": "output", + "bits": [ 133 ] + }, + "SROB9": { + "direction": "output", + "bits": [ 134 ] + }, + "SROB8": { + "direction": "output", + "bits": [ 135 ] + }, + "SROB7": { + "direction": "output", + "bits": [ 136 ] + }, + "SROB6": { + "direction": "output", + "bits": [ 137 ] + }, + "SROB5": { + "direction": "output", + "bits": [ 138 ] + }, + "SROB4": { + "direction": "output", + "bits": [ 139 ] + }, + "SROB3": { + "direction": "output", + "bits": [ 140 ] + }, + "SROB2": { + "direction": "output", + "bits": [ 141 ] + }, + "SROB1": { + "direction": "output", + "bits": [ 142 ] + }, + "SROB0": { + "direction": "output", + "bits": [ 143 ] + }, + "ROA17": { + "direction": "output", + "bits": [ 144 ] + }, + "ROA16": { + "direction": "output", + "bits": [ 145 ] + }, + "ROA15": { + "direction": "output", + "bits": [ 146 ] + }, + "ROA14": { + "direction": "output", + "bits": [ 147 ] + }, + "ROA13": { + "direction": "output", + "bits": [ 148 ] + }, + "ROA12": { + "direction": "output", + "bits": [ 149 ] + }, + "ROA11": { + "direction": "output", + "bits": [ 150 ] + }, + "ROA10": { + "direction": "output", + "bits": [ 151 ] + }, + "ROA9": { + "direction": "output", + "bits": [ 152 ] + }, + "ROA8": { + "direction": "output", + "bits": [ 153 ] + }, + "ROA7": { + "direction": "output", + "bits": [ 154 ] + }, + "ROA6": { + "direction": "output", + "bits": [ 155 ] + }, + "ROA5": { + "direction": "output", + "bits": [ 156 ] + }, + "ROA4": { + "direction": "output", + "bits": [ 157 ] + }, + "ROA3": { + "direction": "output", + "bits": [ 158 ] + }, + "ROA2": { + "direction": "output", + "bits": [ 159 ] + }, + "ROA1": { + "direction": "output", + "bits": [ 160 ] + }, + "ROA0": { + "direction": "output", + "bits": [ 161 ] + }, + "ROB17": { + "direction": "output", + "bits": [ 162 ] + }, + "ROB16": { + "direction": "output", + "bits": [ 163 ] + }, + "ROB15": { + "direction": "output", + "bits": [ 164 ] + }, + "ROB14": { + "direction": "output", + "bits": [ 165 ] + }, + "ROB13": { + "direction": "output", + "bits": [ 166 ] + }, + "ROB12": { + "direction": "output", + "bits": [ 167 ] + }, + "ROB11": { + "direction": "output", + "bits": [ 168 ] + }, + "ROB10": { + "direction": "output", + "bits": [ 169 ] + }, + "ROB9": { + "direction": "output", + "bits": [ 170 ] + }, + "ROB8": { + "direction": "output", + "bits": [ 171 ] + }, + "ROB7": { + "direction": "output", + "bits": [ 172 ] + }, + "ROB6": { + "direction": "output", + "bits": [ 173 ] + }, + "ROB5": { + "direction": "output", + "bits": [ 174 ] + }, + "ROB4": { + "direction": "output", + "bits": [ 175 ] + }, + "ROB3": { + "direction": "output", + "bits": [ 176 ] + }, + "ROB2": { + "direction": "output", + "bits": [ 177 ] + }, + "ROB1": { + "direction": "output", + "bits": [ 178 ] + }, + "ROB0": { + "direction": "output", + "bits": [ 179 ] + }, + "ROC17": { + "direction": "output", + "bits": [ 180 ] + }, + "ROC16": { + "direction": "output", + "bits": [ 181 ] + }, + "ROC15": { + "direction": "output", + "bits": [ 182 ] + }, + "ROC14": { + "direction": "output", + "bits": [ 183 ] + }, + "ROC13": { + "direction": "output", + "bits": [ 184 ] + }, + "ROC12": { + "direction": "output", + "bits": [ 185 ] + }, + "ROC11": { + "direction": "output", + "bits": [ 186 ] + }, + "ROC10": { + "direction": "output", + "bits": [ 187 ] + }, + "ROC9": { + "direction": "output", + "bits": [ 188 ] + }, + "ROC8": { + "direction": "output", + "bits": [ 189 ] + }, + "ROC7": { + "direction": "output", + "bits": [ 190 ] + }, + "ROC6": { + "direction": "output", + "bits": [ 191 ] + }, + "ROC5": { + "direction": "output", + "bits": [ 192 ] + }, + "ROC4": { + "direction": "output", + "bits": [ 193 ] + }, + "ROC3": { + "direction": "output", + "bits": [ 194 ] + }, + "ROC2": { + "direction": "output", + "bits": [ 195 ] + }, + "ROC1": { + "direction": "output", + "bits": [ 196 ] + }, + "ROC0": { + "direction": "output", + "bits": [ 197 ] + }, + "P35": { + "direction": "output", + "bits": [ 198 ] + }, + "P34": { + "direction": "output", + "bits": [ 199 ] + }, + "P33": { + "direction": "output", + "bits": [ 200 ] + }, + "P32": { + "direction": "output", + "bits": [ 201 ] + }, + "P31": { + "direction": "output", + "bits": [ 202 ] + }, + "P30": { + "direction": "output", + "bits": [ 203 ] + }, + "P29": { + "direction": "output", + "bits": [ 204 ] + }, + "P28": { + "direction": "output", + "bits": [ 205 ] + }, + "P27": { + "direction": "output", + "bits": [ 206 ] + }, + "P26": { + "direction": "output", + "bits": [ 207 ] + }, + "P25": { + "direction": "output", + "bits": [ 208 ] + }, + "P24": { + "direction": "output", + "bits": [ 209 ] + }, + "P23": { + "direction": "output", + "bits": [ 210 ] + }, + "P22": { + "direction": "output", + "bits": [ 211 ] + }, + "P21": { + "direction": "output", + "bits": [ 212 ] + }, + "P20": { + "direction": "output", + "bits": [ 213 ] + }, + "P19": { + "direction": "output", + "bits": [ 214 ] + }, + "P18": { + "direction": "output", + "bits": [ 215 ] + }, + "P17": { + "direction": "output", + "bits": [ 216 ] + }, + "P16": { + "direction": "output", + "bits": [ 217 ] + }, + "P15": { + "direction": "output", + "bits": [ 218 ] + }, + "P14": { + "direction": "output", + "bits": [ 219 ] + }, + "P13": { + "direction": "output", + "bits": [ 220 ] + }, + "P12": { + "direction": "output", + "bits": [ 221 ] + }, + "P11": { + "direction": "output", + "bits": [ 222 ] + }, + "P10": { + "direction": "output", + "bits": [ 223 ] + }, + "P9": { + "direction": "output", + "bits": [ 224 ] + }, + "P8": { + "direction": "output", + "bits": [ 225 ] + }, + "P7": { + "direction": "output", + "bits": [ 226 ] + }, + "P6": { + "direction": "output", + "bits": [ 227 ] + }, + "P5": { + "direction": "output", + "bits": [ 228 ] + }, + "P4": { + "direction": "output", + "bits": [ 229 ] + }, + "P3": { + "direction": "output", + "bits": [ 230 ] + }, + "P2": { + "direction": "output", + "bits": [ 231 ] + }, + "P1": { + "direction": "output", + "bits": [ 232 ] + }, + "P0": { + "direction": "output", + "bits": [ 233 ] + }, + "SIGNEDP": { + "direction": "output", + "bits": [ 234 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:270.11-270.13" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:269.11-269.13" + } + }, + "A10": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:260.11-260.14" + } + }, + "A11": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:259.11-259.14" + } + }, + "A12": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:258.11-258.14" + } + }, + "A13": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:257.11-257.14" + } + }, + "A14": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:256.11-256.14" + } + }, + "A15": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:255.11-255.14" + } + }, + "A16": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:254.11-254.14" + } + }, + "A17": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:253.11-253.14" + } + }, + "A2": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:268.11-268.13" + } + }, + "A3": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:267.11-267.13" + } + }, + "A4": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:266.11-266.13" + } + }, + "A5": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:265.11-265.13" + } + }, + "A6": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:264.11-264.13" + } + }, + "A7": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:263.11-263.13" + } + }, + "A8": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:262.11-262.13" + } + }, + "A9": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:261.11-261.13" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:288.11-288.13" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:287.11-287.13" + } + }, + "B10": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:278.11-278.14" + } + }, + "B11": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:277.11-277.14" + } + }, + "B12": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:276.11-276.14" + } + }, + "B13": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:275.11-275.14" + } + }, + "B14": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:274.11-274.14" + } + }, + "B15": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:273.11-273.14" + } + }, + "B16": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:272.11-272.14" + } + }, + "B17": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:271.11-271.14" + } + }, + "B2": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:286.11-286.13" + } + }, + "B3": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:285.11-285.13" + } + }, + "B4": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:284.11-284.13" + } + }, + "B5": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:283.11-283.13" + } + }, + "B6": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:282.11-282.13" + } + }, + "B7": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:281.11-281.13" + } + }, + "B8": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:280.11-280.13" + } + }, + "B9": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:279.11-279.13" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:306.11-306.13" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:305.11-305.13" + } + }, + "C10": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:296.11-296.14" + } + }, + "C11": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:295.11-295.14" + } + }, + "C12": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:294.11-294.14" + } + }, + "C13": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:293.11-293.14" + } + }, + "C14": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:292.11-292.14" + } + }, + "C15": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:291.11-291.14" + } + }, + "C16": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:290.11-290.14" + } + }, + "C17": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:289.11-289.14" + } + }, + "C2": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:304.11-304.13" + } + }, + "C3": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:303.11-303.13" + } + }, + "C4": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:302.11-302.13" + } + }, + "C5": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:301.11-301.13" + } + }, + "C6": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:300.11-300.13" + } + }, + "C7": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:299.11-299.13" + } + }, + "C8": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:298.11-298.13" + } + }, + "C9": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:297.11-297.13" + } + }, + "CE0": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:318.11-318.14" + } + }, + "CE1": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:317.11-317.14" + } + }, + "CE2": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:316.11-316.14" + } + }, + "CE3": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:315.11-315.14" + } + }, + "CLK0": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:314.11-314.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:313.11-313.15" + } + }, + "CLK2": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:312.11-312.15" + } + }, + "CLK3": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:311.11-311.15" + } + }, + "P0": { + "hide_name": 0, + "bits": [ 233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:484.12-484.14" + } + }, + "P1": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:483.12-483.14" + } + }, + "P10": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:474.12-474.15" + } + }, + "P11": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:473.12-473.15" + } + }, + "P12": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:472.12-472.15" + } + }, + "P13": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:471.12-471.15" + } + }, + "P14": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:470.12-470.15" + } + }, + "P15": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:469.12-469.15" + } + }, + "P16": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:468.12-468.15" + } + }, + "P17": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:467.12-467.15" + } + }, + "P18": { + "hide_name": 0, + "bits": [ 215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:466.12-466.15" + } + }, + "P19": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:465.12-465.15" + } + }, + "P2": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:482.12-482.14" + } + }, + "P20": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:464.12-464.15" + } + }, + "P21": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:463.12-463.15" + } + }, + "P22": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:462.12-462.15" + } + }, + "P23": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:461.12-461.15" + } + }, + "P24": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:460.12-460.15" + } + }, + "P25": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:459.12-459.15" + } + }, + "P26": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:458.12-458.15" + } + }, + "P27": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:457.12-457.15" + } + }, + "P28": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:456.12-456.15" + } + }, + "P29": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:455.12-455.15" + } + }, + "P3": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:481.12-481.14" + } + }, + "P30": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:454.12-454.15" + } + }, + "P31": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:453.12-453.15" + } + }, + "P32": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:452.12-452.15" + } + }, + "P33": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:451.12-451.15" + } + }, + "P34": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:450.12-450.15" + } + }, + "P35": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:449.12-449.15" + } + }, + "P4": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:480.12-480.14" + } + }, + "P5": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:479.12-479.14" + } + }, + "P6": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:478.12-478.14" + } + }, + "P7": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:477.12-477.14" + } + }, + "P8": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:476.12-476.14" + } + }, + "P9": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:475.12-475.14" + } + }, + "ROA0": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:412.12-412.16" + } + }, + "ROA1": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:411.12-411.16" + } + }, + "ROA10": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:402.12-402.17" + } + }, + "ROA11": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:401.12-401.17" + } + }, + "ROA12": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:400.12-400.17" + } + }, + "ROA13": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:399.12-399.17" + } + }, + "ROA14": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:398.12-398.17" + } + }, + "ROA15": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:397.12-397.17" + } + }, + "ROA16": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:396.12-396.17" + } + }, + "ROA17": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:395.12-395.17" + } + }, + "ROA2": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:410.12-410.16" + } + }, + "ROA3": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:409.12-409.16" + } + }, + "ROA4": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:408.12-408.16" + } + }, + "ROA5": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:407.12-407.16" + } + }, + "ROA6": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:406.12-406.16" + } + }, + "ROA7": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:405.12-405.16" + } + }, + "ROA8": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:404.12-404.16" + } + }, + "ROA9": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:403.12-403.16" + } + }, + "ROB0": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:430.12-430.16" + } + }, + "ROB1": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:429.12-429.16" + } + }, + "ROB10": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:420.12-420.17" + } + }, + "ROB11": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:419.12-419.17" + } + }, + "ROB12": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:418.12-418.17" + } + }, + "ROB13": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:417.12-417.17" + } + }, + "ROB14": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:416.12-416.17" + } + }, + "ROB15": { + "hide_name": 0, + "bits": [ 164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:415.12-415.17" + } + }, + "ROB16": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:414.12-414.17" + } + }, + "ROB17": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:413.12-413.17" + } + }, + "ROB2": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:428.12-428.16" + } + }, + "ROB3": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:427.12-427.16" + } + }, + "ROB4": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:426.12-426.16" + } + }, + "ROB5": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:425.12-425.16" + } + }, + "ROB6": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:424.12-424.16" + } + }, + "ROB7": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:423.12-423.16" + } + }, + "ROB8": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:422.12-422.16" + } + }, + "ROB9": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:421.12-421.16" + } + }, + "ROC0": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:448.12-448.16" + } + }, + "ROC1": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:447.12-447.16" + } + }, + "ROC10": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:438.12-438.17" + } + }, + "ROC11": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:437.12-437.17" + } + }, + "ROC12": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:436.12-436.17" + } + }, + "ROC13": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:435.12-435.17" + } + }, + "ROC14": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:434.12-434.17" + } + }, + "ROC15": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:433.12-433.17" + } + }, + "ROC16": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:432.12-432.17" + } + }, + "ROC17": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:431.12-431.17" + } + }, + "ROC2": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:446.12-446.16" + } + }, + "ROC3": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:445.12-445.16" + } + }, + "ROC4": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:444.12-444.16" + } + }, + "ROC5": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:443.12-443.16" + } + }, + "ROC6": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:442.12-442.16" + } + }, + "ROC7": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:441.12-441.16" + } + }, + "ROC8": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:440.12-440.16" + } + }, + "ROC9": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:439.12-439.16" + } + }, + "RST0": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:322.11-322.15" + } + }, + "RST1": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:321.11-321.15" + } + }, + "RST2": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:320.11-320.15" + } + }, + "RST3": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:319.11-319.15" + } + }, + "SIGNEDA": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:307.11-307.18" + } + }, + "SIGNEDB": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:308.11-308.18" + } + }, + "SIGNEDP": { + "hide_name": 0, + "bits": [ 234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:485.12-485.19" + } + }, + "SOURCEA": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:309.11-309.18" + } + }, + "SOURCEB": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:310.11-310.18" + } + }, + "SRIA0": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:340.11-340.16" + } + }, + "SRIA1": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:339.11-339.16" + } + }, + "SRIA10": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:330.11-330.17" + } + }, + "SRIA11": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:329.11-329.17" + } + }, + "SRIA12": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:328.11-328.17" + } + }, + "SRIA13": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:327.11-327.17" + } + }, + "SRIA14": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:326.11-326.17" + } + }, + "SRIA15": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:325.11-325.17" + } + }, + "SRIA16": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:324.11-324.17" + } + }, + "SRIA17": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:323.11-323.17" + } + }, + "SRIA2": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:338.11-338.16" + } + }, + "SRIA3": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:337.11-337.16" + } + }, + "SRIA4": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:336.11-336.16" + } + }, + "SRIA5": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:335.11-335.16" + } + }, + "SRIA6": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:334.11-334.16" + } + }, + "SRIA7": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:333.11-333.16" + } + }, + "SRIA8": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:332.11-332.16" + } + }, + "SRIA9": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:331.11-331.16" + } + }, + "SRIB0": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:358.11-358.16" + } + }, + "SRIB1": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:357.11-357.16" + } + }, + "SRIB10": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:348.11-348.17" + } + }, + "SRIB11": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:347.11-347.17" + } + }, + "SRIB12": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:346.11-346.17" + } + }, + "SRIB13": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:345.11-345.17" + } + }, + "SRIB14": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:344.11-344.17" + } + }, + "SRIB15": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:343.11-343.17" + } + }, + "SRIB16": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:342.11-342.17" + } + }, + "SRIB17": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:341.11-341.17" + } + }, + "SRIB2": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:356.11-356.16" + } + }, + "SRIB3": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:355.11-355.16" + } + }, + "SRIB4": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:354.11-354.16" + } + }, + "SRIB5": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:353.11-353.16" + } + }, + "SRIB6": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:352.11-352.16" + } + }, + "SRIB7": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:351.11-351.16" + } + }, + "SRIB8": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:350.11-350.16" + } + }, + "SRIB9": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:349.11-349.16" + } + }, + "SROA0": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:376.12-376.17" + } + }, + "SROA1": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:375.12-375.17" + } + }, + "SROA10": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:366.12-366.18" + } + }, + "SROA11": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:365.12-365.18" + } + }, + "SROA12": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:364.12-364.18" + } + }, + "SROA13": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:363.12-363.18" + } + }, + "SROA14": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:362.12-362.18" + } + }, + "SROA15": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:361.12-361.18" + } + }, + "SROA16": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:360.12-360.18" + } + }, + "SROA17": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:359.12-359.18" + } + }, + "SROA2": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:374.12-374.17" + } + }, + "SROA3": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:373.12-373.17" + } + }, + "SROA4": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:372.12-372.17" + } + }, + "SROA5": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:371.12-371.17" + } + }, + "SROA6": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:370.12-370.17" + } + }, + "SROA7": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:369.12-369.17" + } + }, + "SROA8": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:368.12-368.17" + } + }, + "SROA9": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:367.12-367.17" + } + }, + "SROB0": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:394.12-394.17" + } + }, + "SROB1": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:393.12-393.17" + } + }, + "SROB10": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:384.12-384.18" + } + }, + "SROB11": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:383.12-383.18" + } + }, + "SROB12": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:382.12-382.18" + } + }, + "SROB13": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:381.12-381.18" + } + }, + "SROB14": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:380.12-380.18" + } + }, + "SROB15": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:379.12-379.18" + } + }, + "SROB16": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:378.12-378.18" + } + }, + "SROB17": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:377.12-377.18" + } + }, + "SROB2": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:392.12-392.17" + } + }, + "SROB3": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:391.12-391.17" + } + }, + "SROB4": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:390.12-390.17" + } + }, + "SROB5": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:389.12-389.17" + } + }, + "SROB6": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:388.12-388.17" + } + }, + "SROB7": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:387.12-387.17" + } + }, + "SROB8": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:386.12-386.17" + } + }, + "SROB9": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:385.12-385.17" + } + } + } + }, + "OB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.20-5.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.59-5.60" + } + } + } + }, + "OBCO": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "OT": { + "direction": "output", + "bits": [ 3 ] + }, + "OC": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.20-9.21" + } + }, + "OC": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.38-9.40" + } + }, + "OT": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.34-9.36" + } + } + } + }, + "OBZ": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.20-6.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.59-6.60" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.23-6.24" + } + } + } + }, + "OBZPD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.20-8.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.59-8.60" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.23-8.24" + } + } + } + }, + "OBZPU": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.20-7.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.59-7.60" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.23-7.24" + } + } + } + }, + "ODDR71B": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1255.1-1268.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 3 ] + }, + "RST": { + "direction": "input", + "bits": [ 4 ] + }, + "D6": { + "direction": "input", + "bits": [ 5 ] + }, + "D5": { + "direction": "input", + "bits": [ 6 ] + }, + "D4": { + "direction": "input", + "bits": [ 7 ] + }, + "D3": { + "direction": "input", + "bits": [ 8 ] + }, + "D2": { + "direction": "input", + "bits": [ 9 ] + }, + "D1": { + "direction": "input", + "bits": [ 10 ] + }, + "D0": { + "direction": "input", + "bits": [ 11 ] + }, + "Q": { + "direction": "output", + "bits": [ 12 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1266.11-1266.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1265.11-1265.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1264.11-1264.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1263.11-1263.13" + } + }, + "D4": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1262.11-1262.13" + } + }, + "D5": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1261.11-1261.13" + } + }, + "D6": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1260.11-1260.13" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1258.11-1258.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1267.12-1267.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1259.11-1259.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1257.11-1257.15" + } + } + } + }, + "ODDRX1F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1232.1-1239.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "D0": { + "direction": "input", + "bits": [ 4 ] + }, + "D1": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1236.11-1236.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1237.11-1237.13" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1238.12-1238.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1235.11-1235.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1234.11-1234.15" + } + } + } + }, + "ODDRX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1308.1-1319.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D3": { + "direction": "input", + "bits": [ 2 ] + }, + "D2": { + "direction": "input", + "bits": [ 3 ] + }, + "D1": { + "direction": "input", + "bits": [ 4 ] + }, + "D0": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW270": { + "direction": "input", + "bits": [ 6 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 7 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 8 ] + }, + "RST": { + "direction": "input", + "bits": [ 9 ] + }, + "Q": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1313.11-1313.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1312.11-1312.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1311.11-1311.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1310.11-1310.13" + } + }, + "DQSW270": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1314.11-1314.18" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1316.11-1316.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1318.12-1318.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1317.11-1317.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1315.11-1315.15" + } + } + } + }, + "ODDRX2DQSB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1322.1-1333.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D3": { + "direction": "input", + "bits": [ 2 ] + }, + "D2": { + "direction": "input", + "bits": [ 3 ] + }, + "D1": { + "direction": "input", + "bits": [ 4 ] + }, + "D0": { + "direction": "input", + "bits": [ 5 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 6 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 7 ] + }, + "DQSW": { + "direction": "input", + "bits": [ 8 ] + }, + "RST": { + "direction": "input", + "bits": [ 9 ] + }, + "Q": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1327.11-1327.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1326.11-1326.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1325.11-1325.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1324.11-1324.13" + } + }, + "DQSW": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1330.11-1330.15" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1329.11-1329.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1332.12-1332.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1331.11-1331.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1328.11-1328.15" + } + } + } + }, + "ODDRX2F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1242.1-1252.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 3 ] + }, + "RST": { + "direction": "input", + "bits": [ 4 ] + }, + "D3": { + "direction": "input", + "bits": [ 5 ] + }, + "D2": { + "direction": "input", + "bits": [ 6 ] + }, + "D1": { + "direction": "input", + "bits": [ 7 ] + }, + "D0": { + "direction": "input", + "bits": [ 8 ] + }, + "Q": { + "direction": "output", + "bits": [ 9 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1250.11-1250.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1249.11-1249.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1248.11-1248.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1247.11-1247.13" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1245.11-1245.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1251.12-1251.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1246.11-1246.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1244.11-1244.15" + } + } + } + }, + "OFS1P3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.27-31.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.23-31.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.47-31.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.34-31.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.30-31.32" + } + } + } + }, + "OFS1P3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.23-32.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.27-32.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.47-32.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.34-32.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.30-32.32" + } + } + } + }, + "OFS1P3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.23-33.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.27-33.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.47-33.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.34-33.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.30-33.32" + } + } + } + }, + "OFS1P3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.27-34.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.23-34.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.47-34.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.34-34.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.30-34.32" + } + } + } + }, + "OLVDS": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "Z": { + "direction": "output", + "bits": [ 3 ] + }, + "ZN": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.20-14.21" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.59-14.60" + } + }, + "ZN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.69-14.71" + } + } + } + }, + "OSCG": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1413.1-1416.10" + }, + "parameter_default_values": { + "DIV": "00000000000000000000000010000000" + }, + "ports": { + "OSC": { + "direction": "output", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "OSC": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1415.12-1415.15" + } + } + } + }, + "OSHX2A": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1271.1-1279.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D1": { + "direction": "input", + "bits": [ 2 ] + }, + "D0": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "RST": { + "direction": "input", + "bits": [ 6 ] + }, + "Q": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1274.11-1274.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1273.11-1273.13" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1276.11-1276.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1278.12-1278.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1277.11-1277.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1275.11-1275.15" + } + } + } + }, + "PCSCLKDIV": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1020.1-1029.10" + }, + "parameter_default_values": { + "GSR": "DISABLED" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "SEL2": { + "direction": "input", + "bits": [ 4 ] + }, + "SEL1": { + "direction": "input", + "bits": [ 5 ] + }, + "SEL0": { + "direction": "input", + "bits": [ 6 ] + }, + "CDIV1": { + "direction": "output", + "bits": [ 7 ] + }, + "CDIVX": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "CDIV1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1027.12-1027.17" + } + }, + "CDIVX": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1028.12-1028.17" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1022.11-1022.15" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1023.11-1023.14" + } + }, + "SEL0": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1026.11-1026.15" + } + }, + "SEL1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1025.11-1025.15" + } + }, + "SEL2": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1024.11-1024.15" + } + } + } + }, + "PDPW16KD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:21.1-213.10" + }, + "parameter_default_values": { + "ASYNC_RESET_RELEASE": "SYNC", + "CLKRMUX": "CLKR", + "CLKWMUX": "CLKW", + "CSDECODE_R": "0b000", + "CSDECODE_W": "0b000", + "DATA_WIDTH_R": "00000000000000000000000000100100", + "DATA_WIDTH_W": "00000000000000000000000000100100", + "GSR": "ENABLED", + "INITVAL_00": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_01": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_02": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_03": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_04": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_05": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_06": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_07": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_08": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_09": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_10": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_11": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_12": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_13": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_14": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_15": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_16": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_17": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_18": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_19": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_20": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_21": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_22": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_23": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_24": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_25": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_26": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_27": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_28": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_29": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_30": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_31": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_32": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_33": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_34": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_35": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_36": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_37": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_38": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_39": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INIT_DATA": "STATIC", + "REGMODE": "NOREG", + "RESETMODE": "SYNC" + }, + "ports": { + "DI35": { + "direction": "input", + "bits": [ 2 ] + }, + "DI34": { + "direction": "input", + "bits": [ 3 ] + }, + "DI33": { + "direction": "input", + "bits": [ 4 ] + }, + "DI32": { + "direction": "input", + "bits": [ 5 ] + }, + "DI31": { + "direction": "input", + "bits": [ 6 ] + }, + "DI30": { + "direction": "input", + "bits": [ 7 ] + }, + "DI29": { + "direction": "input", + "bits": [ 8 ] + }, + "DI28": { + "direction": "input", + "bits": [ 9 ] + }, + "DI27": { + "direction": "input", + "bits": [ 10 ] + }, + "DI26": { + "direction": "input", + "bits": [ 11 ] + }, + "DI25": { + "direction": "input", + "bits": [ 12 ] + }, + "DI24": { + "direction": "input", + "bits": [ 13 ] + }, + "DI23": { + "direction": "input", + "bits": [ 14 ] + }, + "DI22": { + "direction": "input", + "bits": [ 15 ] + }, + "DI21": { + "direction": "input", + "bits": [ 16 ] + }, + "DI20": { + "direction": "input", + "bits": [ 17 ] + }, + "DI19": { + "direction": "input", + "bits": [ 18 ] + }, + "DI18": { + "direction": "input", + "bits": [ 19 ] + }, + "DI17": { + "direction": "input", + "bits": [ 20 ] + }, + "DI16": { + "direction": "input", + "bits": [ 21 ] + }, + "DI15": { + "direction": "input", + "bits": [ 22 ] + }, + "DI14": { + "direction": "input", + "bits": [ 23 ] + }, + "DI13": { + "direction": "input", + "bits": [ 24 ] + }, + "DI12": { + "direction": "input", + "bits": [ 25 ] + }, + "DI11": { + "direction": "input", + "bits": [ 26 ] + }, + "DI10": { + "direction": "input", + "bits": [ 27 ] + }, + "DI9": { + "direction": "input", + "bits": [ 28 ] + }, + "DI8": { + "direction": "input", + "bits": [ 29 ] + }, + "DI7": { + "direction": "input", + "bits": [ 30 ] + }, + "DI6": { + "direction": "input", + "bits": [ 31 ] + }, + "DI5": { + "direction": "input", + "bits": [ 32 ] + }, + "DI4": { + "direction": "input", + "bits": [ 33 ] + }, + "DI3": { + "direction": "input", + "bits": [ 34 ] + }, + "DI2": { + "direction": "input", + "bits": [ 35 ] + }, + "DI1": { + "direction": "input", + "bits": [ 36 ] + }, + "DI0": { + "direction": "input", + "bits": [ 37 ] + }, + "ADW8": { + "direction": "input", + "bits": [ 38 ] + }, + "ADW7": { + "direction": "input", + "bits": [ 39 ] + }, + "ADW6": { + "direction": "input", + "bits": [ 40 ] + }, + "ADW5": { + "direction": "input", + "bits": [ 41 ] + }, + "ADW4": { + "direction": "input", + "bits": [ 42 ] + }, + "ADW3": { + "direction": "input", + "bits": [ 43 ] + }, + "ADW2": { + "direction": "input", + "bits": [ 44 ] + }, + "ADW1": { + "direction": "input", + "bits": [ 45 ] + }, + "ADW0": { + "direction": "input", + "bits": [ 46 ] + }, + "BE3": { + "direction": "input", + "bits": [ 47 ] + }, + "BE2": { + "direction": "input", + "bits": [ 48 ] + }, + "BE1": { + "direction": "input", + "bits": [ 49 ] + }, + "BE0": { + "direction": "input", + "bits": [ 50 ] + }, + "CEW": { + "direction": "input", + "bits": [ 51 ] + }, + "CLKW": { + "direction": "input", + "bits": [ 52 ] + }, + "CSW2": { + "direction": "input", + "bits": [ 53 ] + }, + "CSW1": { + "direction": "input", + "bits": [ 54 ] + }, + "CSW0": { + "direction": "input", + "bits": [ 55 ] + }, + "ADR13": { + "direction": "input", + "bits": [ 56 ] + }, + "ADR12": { + "direction": "input", + "bits": [ 57 ] + }, + "ADR11": { + "direction": "input", + "bits": [ 58 ] + }, + "ADR10": { + "direction": "input", + "bits": [ 59 ] + }, + "ADR9": { + "direction": "input", + "bits": [ 60 ] + }, + "ADR8": { + "direction": "input", + "bits": [ 61 ] + }, + "ADR7": { + "direction": "input", + "bits": [ 62 ] + }, + "ADR6": { + "direction": "input", + "bits": [ 63 ] + }, + "ADR5": { + "direction": "input", + "bits": [ 64 ] + }, + "ADR4": { + "direction": "input", + "bits": [ 65 ] + }, + "ADR3": { + "direction": "input", + "bits": [ 66 ] + }, + "ADR2": { + "direction": "input", + "bits": [ 67 ] + }, + "ADR1": { + "direction": "input", + "bits": [ 68 ] + }, + "ADR0": { + "direction": "input", + "bits": [ 69 ] + }, + "CER": { + "direction": "input", + "bits": [ 70 ] + }, + "OCER": { + "direction": "input", + "bits": [ 71 ] + }, + "CLKR": { + "direction": "input", + "bits": [ 72 ] + }, + "CSR2": { + "direction": "input", + "bits": [ 73 ] + }, + "CSR1": { + "direction": "input", + "bits": [ 74 ] + }, + "CSR0": { + "direction": "input", + "bits": [ 75 ] + }, + "RST": { + "direction": "input", + "bits": [ 76 ] + }, + "DO35": { + "direction": "output", + "bits": [ 77 ] + }, + "DO34": { + "direction": "output", + "bits": [ 78 ] + }, + "DO33": { + "direction": "output", + "bits": [ 79 ] + }, + "DO32": { + "direction": "output", + "bits": [ 80 ] + }, + "DO31": { + "direction": "output", + "bits": [ 81 ] + }, + "DO30": { + "direction": "output", + "bits": [ 82 ] + }, + "DO29": { + "direction": "output", + "bits": [ 83 ] + }, + "DO28": { + "direction": "output", + "bits": [ 84 ] + }, + "DO27": { + "direction": "output", + "bits": [ 85 ] + }, + "DO26": { + "direction": "output", + "bits": [ 86 ] + }, + "DO25": { + "direction": "output", + "bits": [ 87 ] + }, + "DO24": { + "direction": "output", + "bits": [ 88 ] + }, + "DO23": { + "direction": "output", + "bits": [ 89 ] + }, + "DO22": { + "direction": "output", + "bits": [ 90 ] + }, + "DO21": { + "direction": "output", + "bits": [ 91 ] + }, + "DO20": { + "direction": "output", + "bits": [ 92 ] + }, + "DO19": { + "direction": "output", + "bits": [ 93 ] + }, + "DO18": { + "direction": "output", + "bits": [ 94 ] + }, + "DO17": { + "direction": "output", + "bits": [ 95 ] + }, + "DO16": { + "direction": "output", + "bits": [ 96 ] + }, + "DO15": { + "direction": "output", + "bits": [ 97 ] + }, + "DO14": { + "direction": "output", + "bits": [ 98 ] + }, + "DO13": { + "direction": "output", + "bits": [ 99 ] + }, + "DO12": { + "direction": "output", + "bits": [ 100 ] + }, + "DO11": { + "direction": "output", + "bits": [ 101 ] + }, + "DO10": { + "direction": "output", + "bits": [ 102 ] + }, + "DO9": { + "direction": "output", + "bits": [ 103 ] + }, + "DO8": { + "direction": "output", + "bits": [ 104 ] + }, + "DO7": { + "direction": "output", + "bits": [ 105 ] + }, + "DO6": { + "direction": "output", + "bits": [ 106 ] + }, + "DO5": { + "direction": "output", + "bits": [ 107 ] + }, + "DO4": { + "direction": "output", + "bits": [ 108 ] + }, + "DO3": { + "direction": "output", + "bits": [ 109 ] + }, + "DO2": { + "direction": "output", + "bits": [ 110 ] + }, + "DO1": { + "direction": "output", + "bits": [ 111 ] + }, + "DO0": { + "direction": "output", + "bits": [ 112 ] + } + }, + "cells": { + }, + "netnames": { + "ADR0": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:169.11-169.15" + } + }, + "ADR1": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:168.11-168.15" + } + }, + "ADR10": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:159.11-159.16" + } + }, + "ADR11": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:158.11-158.16" + } + }, + "ADR12": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:157.11-157.16" + } + }, + "ADR13": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:156.11-156.16" + } + }, + "ADR2": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:167.11-167.15" + } + }, + "ADR3": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:166.11-166.15" + } + }, + "ADR4": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:165.11-165.15" + } + }, + "ADR5": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:164.11-164.15" + } + }, + "ADR6": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:163.11-163.15" + } + }, + "ADR7": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:162.11-162.15" + } + }, + "ADR8": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:161.11-161.15" + } + }, + "ADR9": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:160.11-160.15" + } + }, + "ADW0": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:146.11-146.15" + } + }, + "ADW1": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:145.11-145.15" + } + }, + "ADW2": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:144.11-144.15" + } + }, + "ADW3": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:143.11-143.15" + } + }, + "ADW4": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:142.11-142.15" + } + }, + "ADW5": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:141.11-141.15" + } + }, + "ADW6": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:140.11-140.15" + } + }, + "ADW7": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:139.11-139.15" + } + }, + "ADW8": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:138.11-138.15" + } + }, + "BE0": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:150.11-150.14" + } + }, + "BE1": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:149.11-149.14" + } + }, + "BE2": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:148.11-148.14" + } + }, + "BE3": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:147.11-147.14" + } + }, + "CER": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:170.11-170.14" + } + }, + "CEW": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:151.11-151.14" + } + }, + "CLKR": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:172.11-172.15" + } + }, + "CLKW": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:152.11-152.15" + } + }, + "CSR0": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:175.11-175.15" + } + }, + "CSR1": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:174.11-174.15" + } + }, + "CSR2": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:173.11-173.15" + } + }, + "CSW0": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:155.11-155.15" + } + }, + "CSW1": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:154.11-154.15" + } + }, + "CSW2": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:153.11-153.15" + } + }, + "DI0": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:137.11-137.14" + } + }, + "DI1": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:136.11-136.14" + } + }, + "DI10": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:127.11-127.15" + } + }, + "DI11": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:126.11-126.15" + } + }, + "DI12": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:125.11-125.15" + } + }, + "DI13": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:124.11-124.15" + } + }, + "DI14": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:123.11-123.15" + } + }, + "DI15": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:122.11-122.15" + } + }, + "DI16": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:121.11-121.15" + } + }, + "DI17": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:120.11-120.15" + } + }, + "DI18": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:119.11-119.15" + } + }, + "DI19": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:118.11-118.15" + } + }, + "DI2": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:135.11-135.14" + } + }, + "DI20": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:117.11-117.15" + } + }, + "DI21": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:116.11-116.15" + } + }, + "DI22": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:115.11-115.15" + } + }, + "DI23": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:114.11-114.15" + } + }, + "DI24": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:113.11-113.15" + } + }, + "DI25": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:112.11-112.15" + } + }, + "DI26": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:111.11-111.15" + } + }, + "DI27": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:110.11-110.15" + } + }, + "DI28": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:109.11-109.15" + } + }, + "DI29": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:108.11-108.15" + } + }, + "DI3": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:134.11-134.14" + } + }, + "DI30": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:107.11-107.15" + } + }, + "DI31": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:106.11-106.15" + } + }, + "DI32": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:105.11-105.15" + } + }, + "DI33": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:104.11-104.15" + } + }, + "DI34": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:103.11-103.15" + } + }, + "DI35": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:102.11-102.15" + } + }, + "DI4": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:133.11-133.14" + } + }, + "DI5": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:132.11-132.14" + } + }, + "DI6": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:131.11-131.14" + } + }, + "DI7": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:130.11-130.14" + } + }, + "DI8": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:129.11-129.14" + } + }, + "DI9": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:128.11-128.14" + } + }, + "DO0": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:212.12-212.15" + } + }, + "DO1": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:211.12-211.15" + } + }, + "DO10": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:202.12-202.16" + } + }, + "DO11": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:201.12-201.16" + } + }, + "DO12": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:200.12-200.16" + } + }, + "DO13": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:199.12-199.16" + } + }, + "DO14": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:198.12-198.16" + } + }, + "DO15": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:197.12-197.16" + } + }, + "DO16": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:196.12-196.16" + } + }, + "DO17": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:195.12-195.16" + } + }, + "DO18": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:194.12-194.16" + } + }, + "DO19": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:193.12-193.16" + } + }, + "DO2": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:210.12-210.15" + } + }, + "DO20": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:192.12-192.16" + } + }, + "DO21": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:191.12-191.16" + } + }, + "DO22": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:190.12-190.16" + } + }, + "DO23": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:189.12-189.16" + } + }, + "DO24": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:188.12-188.16" + } + }, + "DO25": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:187.12-187.16" + } + }, + "DO26": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:186.12-186.16" + } + }, + "DO27": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:185.12-185.16" + } + }, + "DO28": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:184.12-184.16" + } + }, + "DO29": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:183.12-183.16" + } + }, + "DO3": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:209.12-209.15" + } + }, + "DO30": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:182.12-182.16" + } + }, + "DO31": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:181.12-181.16" + } + }, + "DO32": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:180.12-180.16" + } + }, + "DO33": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:179.12-179.16" + } + }, + "DO34": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:178.12-178.16" + } + }, + "DO35": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:177.12-177.16" + } + }, + "DO4": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:208.12-208.15" + } + }, + "DO5": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:207.12-207.15" + } + }, + "DO6": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:206.12-206.15" + } + }, + "DO7": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:205.12-205.15" + } + }, + "DO8": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:204.12-204.15" + } + }, + "DO9": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:203.12-203.15" + } + }, + "OCER": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:171.11-171.15" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:176.11-176.14" + } + } + } + }, + "PFUMX": { + "attributes": { + "abc9_box_id": "00000000000000000000000000001000", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.1-124.10" + }, + "ports": { + "ALUT": { + "direction": "input", + "bits": [ 2 ] + }, + "BLUT": { + "direction": "input", + "bits": [ 3 ] + }, + "C0": { + "direction": "input", + "bits": [ 4 ] + }, + "Z": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "ALUT": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.21-117.25" + } + }, + "BLUT": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.27-117.31" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.33-117.35" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.44-117.45" + } + } + } + }, + "PUR": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:9.1-12.10" + }, + "parameter_default_values": { + "RST_PULSE": "00000000000000000000000000000001" + }, + "ports": { + "PUR": { + "direction": "input", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "PUR": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:11.11-11.14" + } + } + } + }, + "SGSR": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:15.1-18.10" + }, + "ports": { + "GSR": { + "direction": "input", + "bits": [ 2 ] + }, + "CLK": { + "direction": "input", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "CLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:17.11-17.14" + } + }, + "GSR": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:16.11-16.14" + } + } + } + }, + "TRELLIS_COMB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:354.1-395.10" + }, + "parameter_default_values": { + "CCU2_INJECT1": "NO", + "INITVAL": "0000000000000000", + "IS_Z1": "0", + "MODE": "LOGIC", + "WREMUX": "WRE" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "B": { + "direction": "input", + "bits": [ 3 ] + }, + "C": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "M": { + "direction": "input", + "bits": [ 6 ] + }, + "FCI": { + "direction": "input", + "bits": [ 7 ] + }, + "F1": { + "direction": "input", + "bits": [ 8 ] + }, + "FXA": { + "direction": "input", + "bits": [ 9 ] + }, + "FXB": { + "direction": "input", + "bits": [ 10 ] + }, + "WD": { + "direction": "input", + "bits": [ 11 ] + }, + "WAD0": { + "direction": "input", + "bits": [ 12 ] + }, + "WAD1": { + "direction": "input", + "bits": [ 13 ] + }, + "WAD2": { + "direction": "input", + "bits": [ 14 ] + }, + "WAD3": { + "direction": "input", + "bits": [ 15 ] + }, + "WRE": { + "direction": "input", + "bits": [ 16 ] + }, + "WCK": { + "direction": "input", + "bits": [ 17 ] + }, + "F": { + "direction": "output", + "bits": [ 18 ] + }, + "FCO": { + "direction": "output", + "bits": [ 19 ] + }, + "OFX": { + "direction": "output", + "bits": [ 20 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.8-355.9" + } + }, + "B": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.11-355.12" + } + }, + "C": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.14-355.15" + } + }, + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.17-355.18" + } + }, + "F": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:360.9-360.10" + } + }, + "F1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.13-356.15" + } + }, + "FCI": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.8-356.11" + } + }, + "FCO": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:360.12-360.15" + } + }, + "FXA": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.17-356.20" + } + }, + "FXB": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.22-356.25" + } + }, + "M": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.20-355.21" + } + }, + "OFX": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:360.17-360.20" + } + }, + "WAD0": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.8-358.12" + } + }, + "WAD1": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.14-358.18" + } + }, + "WAD2": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.20-358.24" + } + }, + "WAD3": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.26-358.30" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:359.13-359.16" + } + }, + "WD": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:357.8-357.10" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:359.8-359.11" + } + } + } + }, + "TRELLIS_DPR16X4": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000111", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:128.1-169.10" + }, + "parameter_default_values": { + "INITVAL": "0000000000000000000000000000000000000000000000000000000000000000", + "WCKMUX": "WCK", + "WREMUX": "WRE" + }, + "ports": { + "DI": { + "direction": "input", + "bits": [ 2, 3, 4, 5 ] + }, + "WAD": { + "direction": "input", + "bits": [ 6, 7, 8, 9 ] + }, + "WRE": { + "direction": "input", + "bits": [ 10 ] + }, + "WCK": { + "direction": "input", + "bits": [ 11 ] + }, + "RAD": { + "direction": "input", + "bits": [ 12, 13, 14, 15 ] + }, + "DO": { + "direction": "output", + "bits": [ 16, 17, 18, 19 ] + } + }, + "cells": { + }, + "netnames": { + "DI": { + "hide_name": 0, + "bits": [ 2, 3, 4, 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:129.15-129.17" + } + }, + "DO": { + "hide_name": 0, + "bits": [ 16, 17, 18, 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:134.15-134.17" + } + }, + "RAD": { + "hide_name": 0, + "bits": [ 12, 13, 14, 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:133.15-133.18" + } + }, + "WAD": { + "hide_name": 0, + "bits": [ 6, 7, 8, 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:130.15-130.18" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:132.15-132.18" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:131.15-131.18" + } + } + } + }, + "TRELLIS_FF": { + "attributes": { + "abc9_flop": "1", + "abc9_box": "0", + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.1-314.10" + }, + "parameter_default_values": { + "CEMUX": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110001", + "CLKMUX": "CLK", + "GSR": "ENABLED", + "LSRMODE": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000101001101010010", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "ports": { + "CLK": { + "direction": "input", + "bits": [ 2 ] + }, + "LSR": { + "direction": "input", + "bits": [ 3 ] + }, + "CE": { + "direction": "input", + "bits": [ 4 ] + }, + "DI": { + "direction": "input", + "bits": [ 5 ] + }, + "M": { + "direction": "input", + "bits": [ 6 ] + }, + "Q": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "CE": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.35-249.37" + } + }, + "CLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.25-249.28" + } + }, + "DI": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.39-249.41" + } + }, + "LSR": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.30-249.33" + } + }, + "M": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.43-249.44" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.57-249.58" + } + } + } + }, + "TRELLIS_IO": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:318.1-344.10" + }, + "parameter_default_values": { + "DIR": "INPUT" + }, + "ports": { + "B": { + "direction": "inout", + "bits": [ 2 ] + }, + "I": { + "direction": "input", + "bits": [ 3 ] + }, + "T": { + "direction": "input", + "bits": [ 4 ] + }, + "O": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:320.8-320.9" + } + }, + "I": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:321.8-321.9" + } + }, + "O": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:323.9-323.10" + } + }, + "T": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:322.8-322.9" + } + } + } + }, + "TRELLIS_RAM16X2": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:76.1-113.10" + }, + "parameter_default_values": { + "INITVAL_0": "0000000000000000", + "INITVAL_1": "0000000000000000", + "WCKMUX": "WCK", + "WREMUX": "WRE" + }, + "ports": { + "DI0": { + "direction": "input", + "bits": [ 2 ] + }, + "DI1": { + "direction": "input", + "bits": [ 3 ] + }, + "WAD0": { + "direction": "input", + "bits": [ 4 ] + }, + "WAD1": { + "direction": "input", + "bits": [ 5 ] + }, + "WAD2": { + "direction": "input", + "bits": [ 6 ] + }, + "WAD3": { + "direction": "input", + "bits": [ 7 ] + }, + "WRE": { + "direction": "input", + "bits": [ 8 ] + }, + "WCK": { + "direction": "input", + "bits": [ 9 ] + }, + "RAD0": { + "direction": "input", + "bits": [ 10 ] + }, + "RAD1": { + "direction": "input", + "bits": [ 11 ] + }, + "RAD2": { + "direction": "input", + "bits": [ 12 ] + }, + "RAD3": { + "direction": "input", + "bits": [ 13 ] + }, + "DO0": { + "direction": "output", + "bits": [ 14 ] + }, + "DO1": { + "direction": "output", + "bits": [ 15 ] + } + }, + "cells": { + }, + "netnames": { + "DI0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:77.8-77.11" + } + }, + "DI1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:77.13-77.16" + } + }, + "DO0": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:81.9-81.12" + } + }, + "DO1": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:81.14-81.17" + } + }, + "RAD0": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.8-80.12" + } + }, + "RAD1": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.14-80.18" + } + }, + "RAD2": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.20-80.24" + } + }, + "RAD3": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.26-80.30" + } + }, + "WAD0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.8-78.12" + } + }, + "WAD1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.14-78.18" + } + }, + "WAD2": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.20-78.24" + } + }, + "WAD3": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.26-78.30" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:79.13-79.16" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:79.8-79.11" + } + } + } + }, + "TSHX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1282.1-1292.10" + }, + "parameter_default_values": { + "GSR": "ENABLED", + "REGSET": "SET" + }, + "ports": { + "T1": { + "direction": "input", + "bits": [ 2 ] + }, + "T0": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW270": { + "direction": "input", + "bits": [ 6 ] + }, + "RST": { + "direction": "input", + "bits": [ 7 ] + }, + "Q": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "DQSW270": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1289.11-1289.18" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1288.11-1288.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1291.12-1291.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1290.11-1290.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1287.11-1287.15" + } + }, + "T0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1286.11-1286.13" + } + }, + "T1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1285.11-1285.13" + } + } + } + }, + "TSHX2DQSA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1295.1-1305.10" + }, + "parameter_default_values": { + "GSR": "ENABLED", + "REGSET": "SET" + }, + "ports": { + "T1": { + "direction": "input", + "bits": [ 2 ] + }, + "T0": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW": { + "direction": "input", + "bits": [ 6 ] + }, + "RST": { + "direction": "input", + "bits": [ 7 ] + }, + "Q": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "DQSW": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1302.11-1302.15" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1301.11-1301.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1304.12-1304.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1303.11-1303.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1300.11-1300.15" + } + }, + "T0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1299.11-1299.13" + } + }, + "T1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1298.11-1298.13" + } + } + } + }, + "USRMCLK": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1085.1-1088.10" + }, + "ports": { + "USRMCLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "USRMCLKTS": { + "direction": "input", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "USRMCLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1086.11-1086.19" + } + }, + "USRMCLKTS": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1087.11-1087.20" + } + } + } + }, + "VHI": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:402.1-404.10" + }, + "ports": { + "Z": { + "direction": "output", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "Z": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:402.19-402.20" + } + } + } + }, + "VLO": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:398.1-400.10" + }, + "ports": { + "Z": { + "direction": "output", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "Z": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:398.19-398.20" + } + } + } + }, + "top": { + "attributes": { + "dynports": "00000000000000000000000000000001", + "top": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:1.1-78.10" + }, + "ports": { + "clk": { + "direction": "input", + "bits": [ 2 ] + }, + "rst": { + "direction": "input", + "bits": [ 3 ] + }, + "start": { + "direction": "input", + "bits": [ 4 ] + }, + "y_bus": { + "direction": "output", + "signed": 1, + "bits": [ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 ] + }, + "busy": { + "direction": "output", + "bits": [ 37 ] + }, + "done": { + "direction": "output", + "bits": [ 38 ] + } + }, + "cells": { + "busy_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 39 ], + "B": [ 40 ], + "C": [ 41 ], + "D": [ 42 ], + "Z": [ 37 ] + } + }, + "done_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 43 ], + "B": [ 44 ], + "C": [ 45 ], + "D": [ 46 ], + "Z": [ 38 ] + } + }, + "start_LUT4_B": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 39 ], + "Z": [ 47 ] + } + }, + "start_LUT4_B_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 40 ], + "Z": [ 48 ] + } + }, + "u_layer": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:66.7-76.6", + "module": "$paramod$7e825ade20b59feb4977cf1a7ec311a8b49c589f\\layer", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "layer", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:1.1-81.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron", + "module": "$paramod$d5562b26b0d20b9e83064f78f90a77e852659143\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 49 ], + "LSR": [ 50 ], + "Q": [ 51 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 52 ], + "LSR": [ 50 ], + "Q": [ 53 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 54 ], + "LSR": [ 50 ], + "Q": [ 55 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 56 ], + "LSR": [ 50 ], + "Q": [ 57 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 58 ], + "LSR": [ 50 ], + "Q": [ 59 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 60 ], + "LSR": [ 50 ], + "Q": [ 61 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 62 ], + "LSR": [ 50 ], + "Q": [ 63 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 64 ], + "LSR": [ 50 ], + "Q": [ 65 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 66 ], + "LSR": [ 50 ], + "Q": [ 67 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 68 ], + "LSR": [ 50 ], + "Q": [ 69 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 70 ], + "LSR": [ 50 ], + "Q": [ 71 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 72 ], + "LSR": [ 50 ], + "Q": [ 73 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 74 ], + "LSR": [ 50 ], + "Q": [ 75 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 76 ], + "LSR": [ 50 ], + "Q": [ 77 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 78 ], + "LSR": [ 50 ], + "Q": [ 79 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 80 ], + "LSR": [ 50 ], + "Q": [ 81 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 82 ], + "LSR": [ 50 ], + "Q": [ 83 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 84 ], + "LSR": [ 50 ], + "Q": [ 85 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 86 ], + "LSR": [ 50 ], + "Q": [ 87 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 88 ], + "LSR": [ 50 ], + "Q": [ 89 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 90 ], + "LSR": [ 50 ], + "Q": [ 91 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 92 ], + "LSR": [ 50 ], + "Q": [ 93 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_29": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 94 ], + "LSR": [ 50 ], + "Q": [ 95 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 96 ], + "LSR": [ 50 ], + "Q": [ 97 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_30": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 98 ], + "LSR": [ 50 ], + "Q": [ 99 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_31": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 100 ], + "LSR": [ 50 ], + "Q": [ 101 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 102 ], + "LSR": [ 50 ], + "Q": [ 103 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 104 ], + "LSR": [ 50 ], + "Q": [ 105 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 106 ], + "LSR": [ 50 ], + "Q": [ 107 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 108 ], + "LSR": [ 50 ], + "Q": [ 109 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 110 ], + "LSR": [ 50 ], + "Q": [ 111 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 112 ], + "LSR": [ 50 ], + "Q": [ 113 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 93 ], + "A1": [ 95 ], + "B0": [ 114 ], + "B1": [ 114 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 115 ], + "COUT": [ 116 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 92 ], + "S1": [ 94 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 105 ], + "A1": [ 107 ], + "B0": [ 114 ], + "B1": [ 114 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 117 ], + "COUT": [ 118 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 104 ], + "S1": [ 106 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 67 ], + "A1": [ 69 ], + "B0": [ 119 ], + "B1": [ 120 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 121 ], + "COUT": [ 122 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 66 ], + "S1": [ 68 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 123 ], + "A1": [ 124 ], + "B0": [ 125 ], + "B1": [ 126 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 127 ], + "COUT": [ 128 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 119 ], + "S1": [ 120 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 57 ], + "A1": [ 59 ], + "B0": [ 114 ], + "B1": [ 114 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 129 ], + "COUT": [ 130 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 56 ], + "S1": [ 58 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 71 ], + "A1": [ 73 ], + "B0": [ 131 ], + "B1": [ 132 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 122 ], + "COUT": [ 133 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 70 ], + "S1": [ 72 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 134 ], + "A1": [ 135 ], + "B0": [ 136 ], + "B1": [ 137 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 128 ], + "COUT": [ 138 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 131 ], + "S1": [ 132 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 97 ], + "A1": [ 103 ], + "B0": [ 114 ], + "B1": [ 114 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 139 ], + "COUT": [ 117 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 96 ], + "S1": [ 102 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 77 ], + "A1": [ 79 ], + "B0": [ 140 ], + "B1": [ 141 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 133 ], + "COUT": [ 142 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 76 ], + "S1": [ 78 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 143 ], + "A1": [ 144 ], + "B0": [ 145 ], + "B1": [ 146 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 138 ], + "COUT": [ 147 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 140 ], + "S1": [ 141 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 51 ], + "A1": [ 61 ], + "B0": [ 148 ], + "B1": [ 149 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 150 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 49 ], + "S1": [ 60 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 151 ], + "A1": [ 152 ], + "B0": [ 153 ], + "B1": [ 154 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 155 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 148 ], + "S1": [ 149 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 109 ], + "A1": [ 111 ], + "B0": [ 114 ], + "B1": [ 114 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 118 ], + "COUT": [ 156 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 108 ], + "S1": [ 110 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 99 ], + "A1": [ 101 ], + "B0": [ 114 ], + "B1": [ 114 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 116 ], + "COUT": [ 157 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 98 ], + "S1": [ 100 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 53 ], + "A1": [ 75 ], + "B0": [ 114 ], + "B1": [ 114 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 157 ], + "COUT": [ 139 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 52 ], + "S1": [ 74 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 85 ], + "A1": [ 87 ], + "B0": [ 158 ], + "B1": [ 159 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 160 ], + "COUT": [ 161 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 84 ], + "S1": [ 86 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 162 ], + "A1": [ 163 ], + "B0": [ 164 ], + "B1": [ 165 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 166 ], + "COUT": [ 167 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 158 ], + "S1": [ 159 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_6": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 113 ], + "A1": [ 55 ], + "B0": [ 114 ], + "B1": [ 114 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 156 ], + "COUT": [ 129 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 112 ], + "S1": [ 54 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 81 ], + "A1": [ 83 ], + "B0": [ 168 ], + "B1": [ 169 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 142 ], + "COUT": [ 160 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 80 ], + "S1": [ 82 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 170 ], + "A1": [ 171 ], + "B0": [ 172 ], + "B1": [ 173 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 147 ], + "COUT": [ 166 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 168 ], + "S1": [ 169 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 89 ], + "A1": [ 91 ], + "B0": [ 174 ], + "B1": [ 175 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 161 ], + "COUT": [ 115 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 88 ], + "S1": [ 90 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 176 ], + "A1": [ 177 ], + "B0": [ 178 ], + "B1": [ 179 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 167 ], + "COUT": [ 180 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 174 ], + "S1": [ 175 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 177 ], + "A1": [ "0" ], + "B0": [ 179 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 180 ], + "COUT": [ 181 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 114 ], + "S1": [ 182 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 63 ], + "A1": [ 65 ], + "B0": [ 183 ], + "B1": [ 184 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 150 ], + "COUT": [ 121 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 62 ], + "S1": [ 64 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 185 ], + "A1": [ 186 ], + "B0": [ 187 ], + "B1": [ 188 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 155 ], + "COUT": [ 127 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 183 ], + "S1": [ 184 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 189 ], + "LSR": [ 3 ], + "Q": [ 42 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 42 ], + "D": [ 190 ], + "Z": [ 189 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 190 ], + "LSR": [ 191 ], + "Q": [ 46 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 192 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 193 ], + "COUT": [ 194 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 195 ], + "S1": [ 190 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 196 ], + "B1": [ 197 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 198 ], + "COUT": [ 199 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 200 ], + "S1": [ 201 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 202 ], + "B1": [ 203 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 198 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 204 ], + "S1": [ 205 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 206 ], + "B1": [ 207 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 199 ], + "COUT": [ 193 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 208 ], + "S1": [ 209 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 202 ], + "Z": [ 210 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 42 ], + "D": [ 190 ], + "Z": [ 211 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 42 ], + "D": [ 190 ], + "Z": [ 212 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 42 ], + "Z": [ 50 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 42 ], + "Z": [ 191 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 212 ], + "CLK": [ 2 ], + "DI": [ 210 ], + "LSR": [ 50 ], + "Q": [ 202 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 212 ], + "CLK": [ 2 ], + "DI": [ 205 ], + "LSR": [ 50 ], + "Q": [ 203 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 212 ], + "CLK": [ 2 ], + "DI": [ 200 ], + "LSR": [ 50 ], + "Q": [ 196 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 212 ], + "CLK": [ 2 ], + "DI": [ 201 ], + "LSR": [ 50 ], + "Q": [ 197 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 212 ], + "CLK": [ 2 ], + "DI": [ 208 ], + "LSR": [ 50 ], + "Q": [ 206 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 212 ], + "CLK": [ 2 ], + "DI": [ 209 ], + "LSR": [ 50 ], + "Q": [ 207 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 212 ], + "CLK": [ 2 ], + "DI": [ 195 ], + "LSR": [ 50 ], + "Q": [ 192 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8", + "module": "$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ 213 ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 153 ], + "P1": [ 154 ], + "P10": [ 172 ], + "P11": [ 173 ], + "P12": [ 164 ], + "P13": [ 165 ], + "P14": [ 178 ], + "P15": [ 179 ], + "P16": [ 214 ], + "P17": [ 215 ], + "P18": [ 216 ], + "P19": [ 217 ], + "P2": [ 187 ], + "P20": [ 218 ], + "P21": [ 219 ], + "P22": [ 220 ], + "P23": [ 221 ], + "P24": [ 222 ], + "P25": [ 223 ], + "P26": [ 224 ], + "P27": [ 225 ], + "P28": [ 226 ], + "P29": [ 227 ], + "P3": [ 188 ], + "P30": [ 228 ], + "P31": [ 229 ], + "P32": [ 230 ], + "P33": [ 231 ], + "P34": [ 232 ], + "P35": [ 233 ], + "P4": [ 125 ], + "P5": [ 126 ], + "P6": [ 136 ], + "P7": [ 137 ], + "P8": [ 145 ], + "P9": [ 146 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ 213 ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 151 ], + "P1": [ 152 ], + "P10": [ 170 ], + "P11": [ 171 ], + "P12": [ 162 ], + "P13": [ 163 ], + "P14": [ 176 ], + "P15": [ 177 ], + "P16": [ 234 ], + "P17": [ 235 ], + "P18": [ 236 ], + "P19": [ 237 ], + "P2": [ 185 ], + "P20": [ 238 ], + "P21": [ 239 ], + "P22": [ 240 ], + "P23": [ 241 ], + "P24": [ 242 ], + "P25": [ 243 ], + "P26": [ 244 ], + "P27": [ 245 ], + "P28": [ 246 ], + "P29": [ 247 ], + "P3": [ 186 ], + "P30": [ 248 ], + "P31": [ 249 ], + "P32": [ 250 ], + "P33": [ 251 ], + "P34": [ 252 ], + "P35": [ 253 ], + "P4": [ 123 ], + "P5": [ 124 ], + "P6": [ 134 ], + "P7": [ 135 ], + "P8": [ 143 ], + "P9": [ 144 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 254 ], + "LSR": [ 255 ], + "Q": [ 213 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100111111011101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 206 ], + "B": [ 50 ], + "C": [ 208 ], + "D": [ 212 ], + "Z": [ 254 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1110111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 209 ], + "B": [ 195 ], + "C": [ 212 ], + "D": [ 256 ], + "Z": [ 255 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100001110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 192 ], + "B": [ 207 ], + "C": [ 50 ], + "D": [ 212 ], + "Z": [ 256 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 211 ], + "CLK": [ 2 ], + "DI": [ 257 ], + "LSR": [ 3 ], + "Q": [ 5 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 211 ], + "CLK": [ 2 ], + "DI": [ 258 ], + "LSR": [ 3 ], + "Q": [ 6 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 211 ], + "CLK": [ 2 ], + "DI": [ 259 ], + "LSR": [ 3 ], + "Q": [ 7 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 211 ], + "CLK": [ 2 ], + "DI": [ 260 ], + "LSR": [ 3 ], + "Q": [ 8 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 211 ], + "CLK": [ 2 ], + "DI": [ 261 ], + "LSR": [ 3 ], + "Q": [ 9 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 211 ], + "CLK": [ 2 ], + "DI": [ 262 ], + "LSR": [ 3 ], + "Q": [ 10 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 211 ], + "CLK": [ 2 ], + "DI": [ 263 ], + "LSR": [ 3 ], + "Q": [ 11 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 211 ], + "CLK": [ 2 ], + "DI": [ "0" ], + "LSR": [ 3 ], + "Q": [ 12 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 70 ], + "C": [ 58 ], + "D": [ 264 ], + "Z": [ 263 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 64 ], + "C": [ 58 ], + "D": [ 264 ], + "Z": [ 260 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 62 ], + "C": [ 58 ], + "D": [ 264 ], + "Z": [ 259 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 66 ], + "C": [ 58 ], + "D": [ 264 ], + "Z": [ 261 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 68 ], + "C": [ 58 ], + "D": [ 264 ], + "Z": [ 262 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 49 ], + "C": [ 58 ], + "D": [ 264 ], + "Z": [ 257 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 60 ], + "C": [ 58 ], + "D": [ 264 ], + "Z": [ 258 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 56 ], + "D": [ 265 ], + "Z": [ 264 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 112 ], + "A1": [ 54 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 266 ], + "COUT": [ 265 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 267 ], + "S1": [ 268 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 108 ], + "A1": [ 110 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 269 ], + "COUT": [ 266 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 270 ], + "S1": [ 271 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 104 ], + "A1": [ 106 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 272 ], + "COUT": [ 269 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 273 ], + "S1": [ 274 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 96 ], + "A1": [ 102 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 275 ], + "COUT": [ 272 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 276 ], + "S1": [ 277 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 52 ], + "A1": [ 74 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 278 ], + "COUT": [ 275 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 279 ], + "S1": [ 280 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 98 ], + "A1": [ 100 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 281 ], + "COUT": [ 278 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 282 ], + "S1": [ 283 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 92 ], + "A1": [ 94 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 284 ], + "COUT": [ 281 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 285 ], + "S1": [ 286 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 88 ], + "A1": [ 90 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 287 ], + "COUT": [ 284 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 288 ], + "S1": [ 289 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 84 ], + "A1": [ 86 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 290 ], + "COUT": [ 287 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 291 ], + "S1": [ 292 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 80 ], + "A1": [ 82 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 293 ], + "COUT": [ 290 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 294 ], + "S1": [ 295 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 76 ], + "A1": [ 78 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 296 ], + "COUT": [ 293 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 297 ], + "S1": [ 298 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 70 ], + "A1": [ 72 ], + "B0": [ "1" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 299 ], + "COUT": [ 296 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 300 ], + "S1": [ 301 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 66 ], + "A1": [ 68 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 302 ], + "COUT": [ 299 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 303 ], + "S1": [ 304 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 62 ], + "A1": [ 64 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 305 ], + "COUT": [ 302 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 306 ], + "S1": [ 307 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 49 ], + "A1": [ 60 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ "1" ], + "COUT": [ 305 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 308 ], + "S1": [ 309 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron", + "module": "$paramod$d5562b26b0d20b9e83064f78f90a77e852659143\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 310 ], + "LSR": [ 48 ], + "Q": [ 311 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 312 ], + "LSR": [ 48 ], + "Q": [ 313 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 314 ], + "LSR": [ 48 ], + "Q": [ 315 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 316 ], + "LSR": [ 48 ], + "Q": [ 317 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 318 ], + "LSR": [ 48 ], + "Q": [ 319 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 320 ], + "LSR": [ 48 ], + "Q": [ 321 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 322 ], + "LSR": [ 48 ], + "Q": [ 323 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 324 ], + "LSR": [ 48 ], + "Q": [ 325 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 326 ], + "LSR": [ 48 ], + "Q": [ 327 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 328 ], + "LSR": [ 48 ], + "Q": [ 329 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 330 ], + "LSR": [ 48 ], + "Q": [ 331 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 332 ], + "LSR": [ 48 ], + "Q": [ 333 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 334 ], + "LSR": [ 48 ], + "Q": [ 335 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 336 ], + "LSR": [ 48 ], + "Q": [ 337 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 338 ], + "LSR": [ 48 ], + "Q": [ 339 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 340 ], + "LSR": [ 48 ], + "Q": [ 341 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 342 ], + "LSR": [ 48 ], + "Q": [ 343 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 344 ], + "LSR": [ 48 ], + "Q": [ 345 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 346 ], + "LSR": [ 48 ], + "Q": [ 347 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 348 ], + "LSR": [ 48 ], + "Q": [ 349 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 350 ], + "LSR": [ 48 ], + "Q": [ 351 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 352 ], + "LSR": [ 48 ], + "Q": [ 353 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_29": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 354 ], + "LSR": [ 48 ], + "Q": [ 355 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 356 ], + "LSR": [ 48 ], + "Q": [ 357 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_30": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 358 ], + "LSR": [ 48 ], + "Q": [ 359 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_31": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 360 ], + "LSR": [ 48 ], + "Q": [ 361 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 362 ], + "LSR": [ 48 ], + "Q": [ 363 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 364 ], + "LSR": [ 48 ], + "Q": [ 365 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 366 ], + "LSR": [ 48 ], + "Q": [ 367 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 368 ], + "LSR": [ 48 ], + "Q": [ 369 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 370 ], + "LSR": [ 48 ], + "Q": [ 371 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 372 ], + "LSR": [ 48 ], + "Q": [ 373 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 338 ], + "A1": [ 374 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ "1" ], + "COUT": [ 375 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 376 ], + "S1": [ 377 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 378 ], + "Z": [ 374 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 379 ], + "A1": [ 380 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 375 ], + "COUT": [ 381 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 382 ], + "S1": [ 383 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 384 ], + "A1": [ 385 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 381 ], + "COUT": [ 386 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 387 ], + "S1": [ 388 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 389 ], + "A1": [ 390 ], + "B0": [ "1" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 386 ], + "COUT": [ 391 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 392 ], + "S1": [ 393 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 394 ], + "A1": [ 395 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 391 ], + "COUT": [ 396 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 397 ], + "S1": [ 398 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 399 ], + "A1": [ 400 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 396 ], + "COUT": [ 401 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 402 ], + "S1": [ 403 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 404 ], + "A1": [ 405 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 401 ], + "COUT": [ 406 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 407 ], + "S1": [ 408 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 409 ], + "A1": [ 410 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 406 ], + "COUT": [ 411 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 412 ], + "S1": [ 413 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 414 ], + "A1": [ 415 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 411 ], + "COUT": [ 416 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 417 ], + "S1": [ 418 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 419 ], + "A1": [ 420 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 416 ], + "COUT": [ 421 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 422 ], + "S1": [ 423 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 424 ], + "A1": [ 425 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 421 ], + "COUT": [ 426 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 427 ], + "S1": [ 428 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 429 ], + "A1": [ 430 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 426 ], + "COUT": [ 431 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 432 ], + "S1": [ 433 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 434 ], + "A1": [ 435 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 431 ], + "COUT": [ 436 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 437 ], + "S1": [ 438 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 439 ], + "A1": [ 440 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 436 ], + "COUT": [ 441 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 442 ], + "S1": [ 443 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 444 ], + "A1": [ 445 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 441 ], + "COUT": [ 446 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 447 ], + "S1": [ 448 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 449 ], + "A1": [ 450 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 446 ], + "COUT": [ 451 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 452 ], + "S1": [ 453 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 339 ], + "A1": [ 341 ], + "B0": [ 454 ], + "B1": [ 455 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 456 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 338 ], + "S1": [ 378 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 457 ], + "A1": [ 458 ], + "B0": [ 459 ], + "B1": [ 460 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 461 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 454 ], + "S1": [ 455 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 343 ], + "A1": [ 345 ], + "B0": [ 462 ], + "B1": [ 463 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 456 ], + "COUT": [ 464 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 465 ], + "S1": [ 466 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 467 ], + "A1": [ 468 ], + "B0": [ 469 ], + "B1": [ 470 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 461 ], + "COUT": [ 471 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 462 ], + "S1": [ 463 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 472 ], + "A1": [ 473 ], + "B0": [ 474 ], + "B1": [ 475 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 471 ], + "COUT": [ 476 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 477 ], + "S1": [ 478 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 479 ], + "A1": [ 480 ], + "B0": [ 481 ], + "B1": [ 482 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 476 ], + "COUT": [ 483 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 484 ], + "S1": [ 485 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 486 ], + "A1": [ 487 ], + "B0": [ 488 ], + "B1": [ 489 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 483 ], + "COUT": [ 490 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 491 ], + "S1": [ 492 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 493 ], + "A1": [ 494 ], + "B0": [ 495 ], + "B1": [ 496 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 490 ], + "COUT": [ 497 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 498 ], + "S1": [ 499 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 500 ], + "A1": [ 501 ], + "B0": [ 502 ], + "B1": [ 503 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 497 ], + "COUT": [ 504 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 505 ], + "S1": [ 506 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 507 ], + "A1": [ 508 ], + "B0": [ 509 ], + "B1": [ 510 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 504 ], + "COUT": [ 511 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 512 ], + "S1": [ 513 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 508 ], + "A1": [ "0" ], + "B0": [ 510 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 511 ], + "COUT": [ 514 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 515 ], + "S1": [ 516 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S0_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 378 ], + "B1": [ 465 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 517 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 518 ], + "S1": [ 379 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 466 ], + "B1": [ 519 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 517 ], + "COUT": [ 520 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 380 ], + "S1": [ 384 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 311 ], + "A1": [ 313 ], + "B0": [ 477 ], + "B1": [ 478 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 464 ], + "COUT": [ 521 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 519 ], + "S1": [ 522 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 522 ], + "B1": [ 523 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 520 ], + "COUT": [ 524 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 385 ], + "S1": [ 389 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 347 ], + "A1": [ 349 ], + "B0": [ 484 ], + "B1": [ 485 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 521 ], + "COUT": [ 525 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 523 ], + "S1": [ 526 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 526 ], + "B1": [ 527 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 524 ], + "COUT": [ 528 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 390 ], + "S1": [ 394 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 351 ], + "A1": [ 353 ], + "B0": [ 491 ], + "B1": [ 492 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 525 ], + "COUT": [ 529 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 527 ], + "S1": [ 530 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 530 ], + "B1": [ 531 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 528 ], + "COUT": [ 532 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 395 ], + "S1": [ 399 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 355 ], + "A1": [ 359 ], + "B0": [ 498 ], + "B1": [ 499 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 529 ], + "COUT": [ 533 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 531 ], + "S1": [ 534 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 534 ], + "B1": [ 535 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 532 ], + "COUT": [ 536 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 400 ], + "S1": [ 404 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 361 ], + "A1": [ 335 ], + "B0": [ 505 ], + "B1": [ 506 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 533 ], + "COUT": [ 537 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 535 ], + "S1": [ 538 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 538 ], + "B1": [ 539 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 536 ], + "COUT": [ 540 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 405 ], + "S1": [ 409 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 357 ], + "A1": [ 363 ], + "B0": [ 512 ], + "B1": [ 513 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 537 ], + "COUT": [ 541 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 539 ], + "S1": [ 542 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 542 ], + "B1": [ 543 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 540 ], + "COUT": [ 544 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 410 ], + "S1": [ 414 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 365 ], + "A1": [ 367 ], + "B0": [ 515 ], + "B1": [ 515 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 541 ], + "COUT": [ 545 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 543 ], + "S1": [ 546 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 546 ], + "B1": [ 547 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 544 ], + "COUT": [ 548 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 415 ], + "S1": [ 419 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 369 ], + "A1": [ 371 ], + "B0": [ 515 ], + "B1": [ 515 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 545 ], + "COUT": [ 549 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 547 ], + "S1": [ 550 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 550 ], + "B1": [ 551 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 548 ], + "COUT": [ 552 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 420 ], + "S1": [ 424 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 373 ], + "A1": [ 315 ], + "B0": [ 515 ], + "B1": [ 515 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 549 ], + "COUT": [ 553 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 551 ], + "S1": [ 554 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 554 ], + "B1": [ 555 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 552 ], + "COUT": [ 556 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 425 ], + "S1": [ 429 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 317 ], + "A1": [ 319 ], + "B0": [ 515 ], + "B1": [ 515 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 553 ], + "COUT": [ 557 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 555 ], + "S1": [ 558 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 558 ], + "B1": [ 559 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 556 ], + "COUT": [ 560 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 430 ], + "S1": [ 434 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 321 ], + "A1": [ 323 ], + "B0": [ 515 ], + "B1": [ 515 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 557 ], + "COUT": [ 561 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 559 ], + "S1": [ 562 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 562 ], + "B1": [ 563 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 560 ], + "COUT": [ 564 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 435 ], + "S1": [ 439 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 325 ], + "A1": [ 327 ], + "B0": [ 515 ], + "B1": [ 515 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 561 ], + "COUT": [ 565 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 563 ], + "S1": [ 566 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 566 ], + "B1": [ 567 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 564 ], + "COUT": [ 568 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 440 ], + "S1": [ 444 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 329 ], + "A1": [ 331 ], + "B0": [ 515 ], + "B1": [ 515 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 565 ], + "COUT": [ 569 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 567 ], + "S1": [ 570 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 570 ], + "B1": [ 571 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 568 ], + "COUT": [ 572 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 445 ], + "S1": [ 449 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 333 ], + "A1": [ 337 ], + "B0": [ 515 ], + "B1": [ 515 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 569 ], + "COUT": [ 573 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 571 ], + "S1": [ 574 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 574 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 572 ], + "COUT": [ 575 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 450 ], + "S1": [ 576 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 577 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 578 ], + "COUT": [ 579 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 580 ], + "S1": [ 581 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_S0_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 582 ], + "B1": [ 583 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 584 ], + "COUT": [ 585 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 586 ], + "S1": [ 587 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_S0_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 588 ], + "B1": [ 589 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 585 ], + "COUT": [ 578 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 590 ], + "S1": [ 591 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_S0_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 592 ], + "B1": [ 593 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 584 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 594 ], + "S1": [ 595 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_S0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 592 ], + "Z": [ 596 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 581 ], + "D": [ 378 ], + "Z": [ 340 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 570 ], + "D": [ 445 ], + "Z": [ 330 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 567 ], + "D": [ 444 ], + "Z": [ 328 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_10": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 527 ], + "D": [ 394 ], + "Z": [ 350 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_11": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 530 ], + "D": [ 395 ], + "Z": [ 352 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_12": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 531 ], + "D": [ 399 ], + "Z": [ 354 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_13": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 534 ], + "D": [ 400 ], + "Z": [ 358 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_14": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 535 ], + "D": [ 404 ], + "Z": [ 360 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_15": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 538 ], + "D": [ 405 ], + "Z": [ 334 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_16": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 539 ], + "D": [ 409 ], + "Z": [ 356 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_17": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 542 ], + "D": [ 410 ], + "Z": [ 362 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_18": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 543 ], + "D": [ 414 ], + "Z": [ 364 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_19": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 546 ], + "D": [ 415 ], + "Z": [ 366 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 466 ], + "D": [ 380 ], + "Z": [ 344 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_20": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 547 ], + "D": [ 419 ], + "Z": [ 368 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_21": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 550 ], + "D": [ 420 ], + "Z": [ 370 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_22": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 551 ], + "D": [ 424 ], + "Z": [ 372 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_23": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 554 ], + "D": [ 425 ], + "Z": [ 314 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_24": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 555 ], + "D": [ 429 ], + "Z": [ 316 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_25": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 558 ], + "D": [ 430 ], + "Z": [ 318 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_26": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 559 ], + "D": [ 434 ], + "Z": [ 320 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_27": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 562 ], + "D": [ 435 ], + "Z": [ 322 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_28": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 563 ], + "D": [ 439 ], + "Z": [ 324 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_29": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 566 ], + "D": [ 440 ], + "Z": [ 326 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 465 ], + "D": [ 379 ], + "Z": [ 342 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 571 ], + "D": [ 449 ], + "Z": [ 332 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 574 ], + "D": [ 450 ], + "Z": [ 336 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 519 ], + "D": [ 384 ], + "Z": [ 310 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_7": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 522 ], + "D": [ 385 ], + "Z": [ 312 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_8": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 523 ], + "D": [ 389 ], + "Z": [ 346 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z_LUT4_Z_9": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 581 ], + "C": [ 526 ], + "D": [ 390 ], + "Z": [ 348 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 338 ], + "C": [ 450 ], + "D": [ 453 ], + "Z": [ 597 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 389 ], + "C": [ 450 ], + "D": [ 453 ], + "Z": [ 598 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 380 ], + "C": [ 450 ], + "D": [ 453 ], + "Z": [ 599 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 379 ], + "C": [ 450 ], + "D": [ 453 ], + "Z": [ 600 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000001100001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 378 ], + "C": [ 450 ], + "D": [ 453 ], + "Z": [ 601 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 384 ], + "C": [ 450 ], + "D": [ 453 ], + "Z": [ 602 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 385 ], + "C": [ 450 ], + "D": [ 453 ], + "Z": [ 603 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 604 ], + "LSR": [ 3 ], + "Q": [ 40 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 40 ], + "D": [ 581 ], + "Z": [ 604 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 581 ], + "LSR": [ 605 ], + "Q": [ 44 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 40 ], + "Z": [ 605 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 606 ], + "CLK": [ 2 ], + "DI": [ 580 ], + "LSR": [ 48 ], + "Q": [ 577 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 606 ], + "CLK": [ 2 ], + "DI": [ 596 ], + "LSR": [ 48 ], + "Q": [ 592 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 606 ], + "CLK": [ 2 ], + "DI": [ 595 ], + "LSR": [ 48 ], + "Q": [ 593 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 606 ], + "CLK": [ 2 ], + "DI": [ 586 ], + "LSR": [ 48 ], + "Q": [ 582 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 606 ], + "CLK": [ 2 ], + "DI": [ 587 ], + "LSR": [ 48 ], + "Q": [ 583 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 606 ], + "CLK": [ 2 ], + "DI": [ 590 ], + "LSR": [ 48 ], + "Q": [ 588 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 606 ], + "CLK": [ 2 ], + "DI": [ 591 ], + "LSR": [ 48 ], + "Q": [ 589 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_CE_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 40 ], + "D": [ 581 ], + "Z": [ 606 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8", + "module": "$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 459 ], + "P1": [ 460 ], + "P10": [ 495 ], + "P11": [ 496 ], + "P12": [ 502 ], + "P13": [ 503 ], + "P14": [ 509 ], + "P15": [ 510 ], + "P16": [ 607 ], + "P17": [ 608 ], + "P18": [ 609 ], + "P19": [ 610 ], + "P2": [ 469 ], + "P20": [ 611 ], + "P21": [ 612 ], + "P22": [ 613 ], + "P23": [ 614 ], + "P24": [ 615 ], + "P25": [ 616 ], + "P26": [ 617 ], + "P27": [ 618 ], + "P28": [ 619 ], + "P29": [ 620 ], + "P3": [ 470 ], + "P30": [ 621 ], + "P31": [ 622 ], + "P32": [ 623 ], + "P33": [ 624 ], + "P34": [ 625 ], + "P35": [ 626 ], + "P4": [ 474 ], + "P5": [ 475 ], + "P6": [ 481 ], + "P7": [ 482 ], + "P8": [ 488 ], + "P9": [ 489 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 457 ], + "P1": [ 458 ], + "P10": [ 493 ], + "P11": [ 494 ], + "P12": [ 500 ], + "P13": [ 501 ], + "P14": [ 507 ], + "P15": [ 508 ], + "P16": [ 627 ], + "P17": [ 628 ], + "P18": [ 629 ], + "P19": [ 630 ], + "P2": [ 467 ], + "P20": [ 631 ], + "P21": [ 632 ], + "P22": [ 633 ], + "P23": [ 634 ], + "P24": [ 635 ], + "P25": [ 636 ], + "P26": [ 637 ], + "P27": [ 638 ], + "P28": [ 639 ], + "P29": [ 640 ], + "P3": [ 468 ], + "P30": [ 641 ], + "P31": [ 642 ], + "P32": [ 643 ], + "P33": [ 644 ], + "P34": [ 645 ], + "P35": [ 646 ], + "P4": [ 472 ], + "P5": [ 473 ], + "P6": [ 479 ], + "P7": [ 480 ], + "P8": [ 486 ], + "P9": [ 487 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 647 ], + "CLK": [ 2 ], + "DI": [ 598 ], + "LSR": [ 3 ], + "Q": [ 19 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 647 ], + "CLK": [ 2 ], + "DI": [ 597 ], + "LSR": [ 3 ], + "Q": [ 13 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 647 ], + "CLK": [ 2 ], + "DI": [ 601 ], + "LSR": [ 3 ], + "Q": [ 14 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 647 ], + "CLK": [ 2 ], + "DI": [ 600 ], + "LSR": [ 3 ], + "Q": [ 15 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 647 ], + "CLK": [ 2 ], + "DI": [ 599 ], + "LSR": [ 3 ], + "Q": [ 16 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 647 ], + "CLK": [ 2 ], + "DI": [ 602 ], + "LSR": [ 3 ], + "Q": [ 17 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 647 ], + "CLK": [ 2 ], + "DI": [ 603 ], + "LSR": [ 3 ], + "Q": [ 18 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 647 ], + "CLK": [ 2 ], + "DI": [ "0" ], + "LSR": [ 3 ], + "Q": [ 20 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_CE_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 40 ], + "D": [ 581 ], + "Z": [ 647 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron", + "module": "$paramod$d5562b26b0d20b9e83064f78f90a77e852659143\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 648 ], + "LSR": [ 47 ], + "Q": [ 649 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 650 ], + "LSR": [ 47 ], + "Q": [ 651 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 652 ], + "LSR": [ 47 ], + "Q": [ 653 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 654 ], + "LSR": [ 47 ], + "Q": [ 655 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 656 ], + "LSR": [ 47 ], + "Q": [ 657 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 658 ], + "LSR": [ 47 ], + "Q": [ 659 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 660 ], + "LSR": [ 47 ], + "Q": [ 661 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 662 ], + "LSR": [ 47 ], + "Q": [ 663 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 664 ], + "LSR": [ 47 ], + "Q": [ 665 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 666 ], + "LSR": [ 47 ], + "Q": [ 667 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 668 ], + "LSR": [ 47 ], + "Q": [ 669 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 670 ], + "LSR": [ 47 ], + "Q": [ 671 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 672 ], + "LSR": [ 47 ], + "Q": [ 673 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 674 ], + "LSR": [ 47 ], + "Q": [ 675 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 676 ], + "LSR": [ 47 ], + "Q": [ 677 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 678 ], + "LSR": [ 47 ], + "Q": [ 679 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 680 ], + "LSR": [ 47 ], + "Q": [ 681 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 682 ], + "LSR": [ 47 ], + "Q": [ 683 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 684 ], + "LSR": [ 47 ], + "Q": [ 685 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 686 ], + "LSR": [ 47 ], + "Q": [ 687 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 688 ], + "LSR": [ 47 ], + "Q": [ 689 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 690 ], + "LSR": [ 47 ], + "Q": [ 691 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_29": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 692 ], + "LSR": [ 47 ], + "Q": [ 693 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 694 ], + "LSR": [ 47 ], + "Q": [ 695 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_30": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 696 ], + "LSR": [ 47 ], + "Q": [ 697 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_31": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 698 ], + "LSR": [ 47 ], + "Q": [ 699 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 700 ], + "LSR": [ 47 ], + "Q": [ 701 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 702 ], + "LSR": [ 47 ], + "Q": [ 703 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 704 ], + "LSR": [ 47 ], + "Q": [ 705 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 706 ], + "LSR": [ 47 ], + "Q": [ 707 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 708 ], + "LSR": [ 47 ], + "Q": [ 709 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 710 ], + "LSR": [ 47 ], + "Q": [ 711 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 707 ], + "A1": [ 703 ], + "B0": [ 712 ], + "B1": [ 712 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 713 ], + "COUT": [ 714 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 706 ], + "S1": [ 702 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 663 ], + "A1": [ 709 ], + "B0": [ 715 ], + "B1": [ 716 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 717 ], + "COUT": [ 718 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 662 ], + "S1": [ 708 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 675 ], + "A1": [ 677 ], + "B0": [ 719 ], + "B1": [ 720 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 721 ], + "COUT": [ 717 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 674 ], + "S1": [ 676 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 722 ], + "A1": [ 723 ], + "B0": [ 724 ], + "B1": [ 725 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 726 ], + "COUT": [ 727 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 719 ], + "S1": [ 720 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 699 ], + "A1": [ 649 ], + "B0": [ 728 ], + "B1": [ 729 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 730 ], + "COUT": [ 731 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 698 ], + "S1": [ 648 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 732 ], + "A1": [ 733 ], + "B0": [ 734 ], + "B1": [ 735 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 736 ], + "COUT": [ 737 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 728 ], + "S1": [ 729 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 687 ], + "A1": [ 701 ], + "B0": [ 712 ], + "B1": [ 712 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 738 ], + "COUT": [ 713 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 686 ], + "S1": [ 700 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 659 ], + "A1": [ 661 ], + "B0": [ 712 ], + "B1": [ 712 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 739 ], + "COUT": [ 740 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 658 ], + "S1": [ 660 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 695 ], + "A1": [ 693 ], + "B0": [ 741 ], + "B1": [ 742 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 743 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 694 ], + "S1": [ 692 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 744 ], + "A1": [ 745 ], + "B0": [ 746 ], + "B1": [ 747 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 748 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 741 ], + "S1": [ 742 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 697 ], + "A1": [ 691 ], + "B0": [ 749 ], + "B1": [ 750 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 743 ], + "COUT": [ 730 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 696 ], + "S1": [ 690 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 751 ], + "A1": [ 752 ], + "B0": [ 753 ], + "B1": [ 754 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 748 ], + "COUT": [ 736 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 749 ], + "S1": [ 750 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 755 ], + "A1": [ 756 ], + "B0": [ 757 ], + "B1": [ 758 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 727 ], + "COUT": [ 759 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 715 ], + "S1": [ 716 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 756 ], + "A1": [ "0" ], + "B0": [ 758 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 759 ], + "COUT": [ 760 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 712 ], + "S1": [ 761 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 689 ], + "A1": [ 683 ], + "B0": [ 762 ], + "B1": [ 763 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 764 ], + "COUT": [ 721 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 688 ], + "S1": [ 682 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 765 ], + "A1": [ 766 ], + "B0": [ 767 ], + "B1": [ 768 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 769 ], + "COUT": [ 726 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 762 ], + "S1": [ 763 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 667 ], + "A1": [ 705 ], + "B0": [ 712 ], + "B1": [ 712 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 714 ], + "COUT": [ 770 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 666 ], + "S1": [ 704 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 651 ], + "A1": [ 673 ], + "B0": [ 771 ], + "B1": [ 772 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 731 ], + "COUT": [ 773 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 650 ], + "S1": [ 672 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 774 ], + "A1": [ 775 ], + "B0": [ 776 ], + "B1": [ 777 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 737 ], + "COUT": [ 778 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 771 ], + "S1": [ 772 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 679 ], + "A1": [ 681 ], + "B0": [ 712 ], + "B1": [ 712 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 718 ], + "COUT": [ 738 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 678 ], + "S1": [ 680 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 711 ], + "A1": [ 653 ], + "B0": [ 712 ], + "B1": [ 712 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 770 ], + "COUT": [ 779 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 710 ], + "S1": [ 652 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 669 ], + "A1": [ 671 ], + "B0": [ 712 ], + "B1": [ 712 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 740 ], + "COUT": [ 780 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 668 ], + "S1": [ 670 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 655 ], + "A1": [ 657 ], + "B0": [ 712 ], + "B1": [ 712 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 779 ], + "COUT": [ 739 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 654 ], + "S1": [ 656 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 665 ], + "A1": [ 685 ], + "B0": [ 781 ], + "B1": [ 782 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 773 ], + "COUT": [ 764 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 664 ], + "S1": [ 684 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 783 ], + "A1": [ 784 ], + "B0": [ 785 ], + "B1": [ 786 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 778 ], + "COUT": [ 769 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 781 ], + "S1": [ 782 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 787 ], + "LSR": [ 3 ], + "Q": [ 39 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 39 ], + "D": [ 788 ], + "Z": [ 787 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 788 ], + "LSR": [ 789 ], + "Q": [ 43 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 790 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 791 ], + "COUT": [ 792 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 793 ], + "S1": [ 788 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 794 ], + "B1": [ 795 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 796 ], + "COUT": [ 791 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 797 ], + "S1": [ 798 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 799 ], + "B1": [ 800 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 801 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 802 ], + "S1": [ 803 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 804 ], + "B1": [ 805 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 801 ], + "COUT": [ 796 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 806 ], + "S1": [ 807 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 799 ], + "Z": [ 808 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 39 ], + "D": [ 788 ], + "Z": [ 809 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 39 ], + "D": [ 788 ], + "Z": [ 810 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 39 ], + "Z": [ 789 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 809 ], + "CLK": [ 2 ], + "DI": [ 807 ], + "LSR": [ 47 ], + "Q": [ 805 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 809 ], + "CLK": [ 2 ], + "DI": [ 797 ], + "LSR": [ 47 ], + "Q": [ 794 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 809 ], + "CLK": [ 2 ], + "DI": [ 808 ], + "LSR": [ 47 ], + "Q": [ 799 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 809 ], + "CLK": [ 2 ], + "DI": [ 803 ], + "LSR": [ 47 ], + "Q": [ 800 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 809 ], + "CLK": [ 2 ], + "DI": [ 806 ], + "LSR": [ 47 ], + "Q": [ 804 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 809 ], + "CLK": [ 2 ], + "DI": [ 793 ], + "LSR": [ 47 ], + "Q": [ 790 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 809 ], + "CLK": [ 2 ], + "DI": [ 798 ], + "LSR": [ 47 ], + "Q": [ 795 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8", + "module": "$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "1" ], + "B1": [ "1" ], + "B10": [ "1" ], + "B11": [ "1" ], + "B12": [ "1" ], + "B13": [ "1" ], + "B14": [ "1" ], + "B15": [ "1" ], + "B16": [ "1" ], + "B17": [ "1" ], + "B2": [ "1" ], + "B3": [ "1" ], + "B4": [ "1" ], + "B5": [ "1" ], + "B6": [ "1" ], + "B7": [ "1" ], + "B8": [ "1" ], + "B9": [ "1" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 746 ], + "P1": [ 747 ], + "P10": [ 767 ], + "P11": [ 768 ], + "P12": [ 724 ], + "P13": [ 725 ], + "P14": [ 757 ], + "P15": [ 758 ], + "P16": [ 811 ], + "P17": [ 812 ], + "P18": [ 813 ], + "P19": [ 814 ], + "P2": [ 753 ], + "P20": [ 815 ], + "P21": [ 816 ], + "P22": [ 817 ], + "P23": [ 818 ], + "P24": [ 819 ], + "P25": [ 820 ], + "P26": [ 821 ], + "P27": [ 822 ], + "P28": [ 823 ], + "P29": [ 824 ], + "P3": [ 754 ], + "P30": [ 825 ], + "P31": [ 826 ], + "P32": [ 827 ], + "P33": [ 828 ], + "P34": [ 829 ], + "P35": [ 830 ], + "P4": [ 734 ], + "P5": [ 735 ], + "P6": [ 776 ], + "P7": [ 777 ], + "P8": [ 785 ], + "P9": [ 786 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "1" ], + "B1": [ "1" ], + "B10": [ "1" ], + "B11": [ "1" ], + "B12": [ "1" ], + "B13": [ "1" ], + "B14": [ "1" ], + "B15": [ "1" ], + "B16": [ "1" ], + "B17": [ "1" ], + "B2": [ "1" ], + "B3": [ "1" ], + "B4": [ "1" ], + "B5": [ "1" ], + "B6": [ "1" ], + "B7": [ "1" ], + "B8": [ "1" ], + "B9": [ "1" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 744 ], + "P1": [ 745 ], + "P10": [ 765 ], + "P11": [ 766 ], + "P12": [ 722 ], + "P13": [ 723 ], + "P14": [ 755 ], + "P15": [ 756 ], + "P16": [ 831 ], + "P17": [ 832 ], + "P18": [ 833 ], + "P19": [ 834 ], + "P2": [ 751 ], + "P20": [ 835 ], + "P21": [ 836 ], + "P22": [ 837 ], + "P23": [ 838 ], + "P24": [ 839 ], + "P25": [ 840 ], + "P26": [ 841 ], + "P27": [ 842 ], + "P28": [ 843 ], + "P29": [ 844 ], + "P3": [ 752 ], + "P30": [ 845 ], + "P31": [ 846 ], + "P32": [ 847 ], + "P33": [ 848 ], + "P34": [ 849 ], + "P35": [ 850 ], + "P4": [ 732 ], + "P5": [ 733 ], + "P6": [ 774 ], + "P7": [ 775 ], + "P8": [ 783 ], + "P9": [ 784 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 810 ], + "CLK": [ 2 ], + "DI": [ 851 ], + "LSR": [ 3 ], + "Q": [ 27 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 810 ], + "CLK": [ 2 ], + "DI": [ 852 ], + "LSR": [ 3 ], + "Q": [ 21 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 810 ], + "CLK": [ 2 ], + "DI": [ 853 ], + "LSR": [ 3 ], + "Q": [ 22 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 810 ], + "CLK": [ 2 ], + "DI": [ "0" ], + "LSR": [ 3 ], + "Q": [ 28 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 810 ], + "CLK": [ 2 ], + "DI": [ 854 ], + "LSR": [ 3 ], + "Q": [ 23 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 810 ], + "CLK": [ 2 ], + "DI": [ 855 ], + "LSR": [ 3 ], + "Q": [ 24 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 810 ], + "CLK": [ 2 ], + "DI": [ 856 ], + "LSR": [ 3 ], + "Q": [ 25 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 810 ], + "CLK": [ 2 ], + "DI": [ 857 ], + "LSR": [ 3 ], + "Q": [ 26 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 696 ], + "C": [ 670 ], + "D": [ 858 ], + "Z": [ 854 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 694 ], + "C": [ 670 ], + "D": [ 858 ], + "Z": [ 852 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 698 ], + "C": [ 670 ], + "D": [ 858 ], + "Z": [ 856 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 692 ], + "C": [ 670 ], + "D": [ 858 ], + "Z": [ 853 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 650 ], + "C": [ 670 ], + "D": [ 858 ], + "Z": [ 851 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 690 ], + "C": [ 670 ], + "D": [ 858 ], + "Z": [ 855 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 648 ], + "C": [ 670 ], + "D": [ 858 ], + "Z": [ 857 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 668 ], + "D": [ 859 ], + "Z": [ 858 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 658 ], + "A1": [ 660 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 860 ], + "COUT": [ 859 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 861 ], + "S1": [ 862 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 654 ], + "A1": [ 656 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 863 ], + "COUT": [ 860 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 864 ], + "S1": [ 865 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 710 ], + "A1": [ 652 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 866 ], + "COUT": [ 863 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 867 ], + "S1": [ 868 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 666 ], + "A1": [ 704 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 869 ], + "COUT": [ 866 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 870 ], + "S1": [ 871 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 706 ], + "A1": [ 702 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 872 ], + "COUT": [ 869 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 873 ], + "S1": [ 874 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 686 ], + "A1": [ 700 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 875 ], + "COUT": [ 872 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 876 ], + "S1": [ 877 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 678 ], + "A1": [ 680 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 878 ], + "COUT": [ 875 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 879 ], + "S1": [ 880 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 662 ], + "A1": [ 708 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 881 ], + "COUT": [ 878 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 882 ], + "S1": [ 883 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 674 ], + "A1": [ 676 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 884 ], + "COUT": [ 881 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 885 ], + "S1": [ 886 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 688 ], + "A1": [ 682 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 887 ], + "COUT": [ 884 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 888 ], + "S1": [ 889 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 664 ], + "A1": [ 684 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 890 ], + "COUT": [ 887 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 891 ], + "S1": [ 892 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 650 ], + "A1": [ 672 ], + "B0": [ "1" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 893 ], + "COUT": [ 890 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 894 ], + "S1": [ 895 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 698 ], + "A1": [ 648 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 896 ], + "COUT": [ 893 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 897 ], + "S1": [ 898 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 696 ], + "A1": [ 690 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 899 ], + "COUT": [ 896 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 900 ], + "S1": [ 901 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 694 ], + "A1": [ 692 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ "1" ], + "COUT": [ 899 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 902 ], + "S1": [ 903 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron", + "module": "$paramod$d5562b26b0d20b9e83064f78f90a77e852659143\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 904 ], + "LSR": [ 905 ], + "Q": [ 906 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 907 ], + "LSR": [ 905 ], + "Q": [ 908 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 909 ], + "LSR": [ 905 ], + "Q": [ 910 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 911 ], + "LSR": [ 905 ], + "Q": [ 912 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 913 ], + "LSR": [ 905 ], + "Q": [ 914 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 915 ], + "LSR": [ 905 ], + "Q": [ 916 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 917 ], + "LSR": [ 905 ], + "Q": [ 918 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 919 ], + "LSR": [ 905 ], + "Q": [ 920 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 921 ], + "LSR": [ 905 ], + "Q": [ 922 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 923 ], + "LSR": [ 905 ], + "Q": [ 924 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 925 ], + "LSR": [ 905 ], + "Q": [ 926 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 927 ], + "LSR": [ 905 ], + "Q": [ 928 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 929 ], + "LSR": [ 905 ], + "Q": [ 930 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 931 ], + "LSR": [ 905 ], + "Q": [ 932 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 933 ], + "LSR": [ 905 ], + "Q": [ 934 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 935 ], + "LSR": [ 905 ], + "Q": [ 936 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 937 ], + "LSR": [ 905 ], + "Q": [ 938 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 939 ], + "LSR": [ 905 ], + "Q": [ 940 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 941 ], + "LSR": [ 905 ], + "Q": [ 942 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 943 ], + "LSR": [ 905 ], + "Q": [ 944 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 945 ], + "LSR": [ 905 ], + "Q": [ 946 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 947 ], + "LSR": [ 905 ], + "Q": [ 948 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_29": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 949 ], + "LSR": [ 905 ], + "Q": [ 950 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 951 ], + "LSR": [ 905 ], + "Q": [ 952 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_30": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 953 ], + "LSR": [ 905 ], + "Q": [ 954 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_31": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 955 ], + "LSR": [ 905 ], + "Q": [ 956 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 957 ], + "LSR": [ 905 ], + "Q": [ 958 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 959 ], + "LSR": [ 905 ], + "Q": [ 960 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 961 ], + "LSR": [ 905 ], + "Q": [ 962 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 963 ], + "LSR": [ 905 ], + "Q": [ 964 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 965 ], + "LSR": [ 905 ], + "Q": [ 966 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 967 ], + "LSR": [ 905 ], + "Q": [ 968 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 954 ], + "A1": [ 956 ], + "B0": [ 969 ], + "B1": [ 969 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 970 ], + "COUT": [ 971 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 953 ], + "S1": [ 955 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 964 ], + "A1": [ 942 ], + "B0": [ 972 ], + "B1": [ 973 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 974 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 963 ], + "S1": [ 941 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 926 ], + "A1": [ 928 ], + "B0": [ 969 ], + "B1": [ 969 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 975 ], + "COUT": [ 976 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 925 ], + "S1": [ 927 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 962 ], + "A1": [ 938 ], + "B0": [ 969 ], + "B1": [ 969 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 976 ], + "COUT": [ 977 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 961 ], + "S1": [ 937 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_12": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 916 ], + "A1": [ 920 ], + "B0": [ 969 ], + "B1": [ 969 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 977 ], + "COUT": [ 978 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 915 ], + "S1": [ 919 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 924 ], + "A1": [ 910 ], + "B0": [ 969 ], + "B1": [ 969 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 978 ], + "COUT": [ 979 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 923 ], + "S1": [ 909 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 958 ], + "A1": [ 914 ], + "B0": [ 969 ], + "B1": [ 969 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 979 ], + "COUT": [ 980 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 957 ], + "S1": [ 913 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 946 ], + "A1": [ 948 ], + "B0": [ 969 ], + "B1": [ 969 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 980 ], + "COUT": [ 970 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 945 ], + "S1": [ 947 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 981 ], + "A1": [ 982 ], + "B0": [ 983 ], + "B1": [ 984 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 985 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 972 ], + "S1": [ 973 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 950 ], + "A1": [ 906 ], + "B0": [ 986 ], + "B1": [ 987 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 974 ], + "COUT": [ 988 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 949 ], + "S1": [ 904 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 989 ], + "A1": [ 990 ], + "B0": [ 991 ], + "B1": [ 992 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 985 ], + "COUT": [ 993 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 986 ], + "S1": [ 987 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 952 ], + "A1": [ 960 ], + "B0": [ 994 ], + "B1": [ 995 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 988 ], + "COUT": [ 996 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 951 ], + "S1": [ 959 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 997 ], + "A1": [ 998 ], + "B0": [ 999 ], + "B1": [ 1000 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 993 ], + "COUT": [ 1001 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 994 ], + "S1": [ 995 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 966 ], + "A1": [ 968 ], + "B0": [ 1002 ], + "B1": [ 1003 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 996 ], + "COUT": [ 1004 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 965 ], + "S1": [ 967 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1005 ], + "A1": [ 1006 ], + "B0": [ 1007 ], + "B1": [ 1008 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1001 ], + "COUT": [ 1009 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1002 ], + "S1": [ 1003 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 912 ], + "A1": [ 932 ], + "B0": [ 1010 ], + "B1": [ 1011 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1004 ], + "COUT": [ 1012 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 911 ], + "S1": [ 931 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1013 ], + "A1": [ 1014 ], + "B0": [ 1015 ], + "B1": [ 1016 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1009 ], + "COUT": [ 1017 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1010 ], + "S1": [ 1011 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 940 ], + "A1": [ 930 ], + "B0": [ 1018 ], + "B1": [ 1019 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1012 ], + "COUT": [ 1020 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 939 ], + "S1": [ 929 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1021 ], + "A1": [ 1022 ], + "B0": [ 1023 ], + "B1": [ 1024 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1017 ], + "COUT": [ 1025 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1018 ], + "S1": [ 1019 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 908 ], + "A1": [ 918 ], + "B0": [ 1026 ], + "B1": [ 1027 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1020 ], + "COUT": [ 1028 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 907 ], + "S1": [ 917 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1029 ], + "A1": [ 1030 ], + "B0": [ 1031 ], + "B1": [ 1032 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1025 ], + "COUT": [ 1033 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1026 ], + "S1": [ 1027 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 934 ], + "A1": [ 936 ], + "B0": [ 1034 ], + "B1": [ 1035 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1028 ], + "COUT": [ 1036 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 933 ], + "S1": [ 935 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1037 ], + "A1": [ 1038 ], + "B0": [ 1039 ], + "B1": [ 1040 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1033 ], + "COUT": [ 1041 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1034 ], + "S1": [ 1035 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1038 ], + "A1": [ "0" ], + "B0": [ 1040 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1041 ], + "COUT": [ 1042 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 969 ], + "S1": [ 1043 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 944 ], + "A1": [ 922 ], + "B0": [ 969 ], + "B1": [ 969 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1036 ], + "COUT": [ 975 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 943 ], + "S1": [ 921 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1044 ], + "LSR": [ 3 ], + "Q": [ 41 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 41 ], + "D": [ 1045 ], + "Z": [ 1044 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1045 ], + "LSR": [ 1046 ], + "Q": [ 45 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 1047 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1048 ], + "COUT": [ 1049 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1050 ], + "S1": [ 1045 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 1051 ], + "B1": [ 1052 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 1053 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1054 ], + "S1": [ 1055 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 1056 ], + "B1": [ 1057 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1058 ], + "COUT": [ 1048 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1059 ], + "S1": [ 1060 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 1061 ], + "B1": [ 1062 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1053 ], + "COUT": [ 1058 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1063 ], + "S1": [ 1064 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1051 ], + "Z": [ 1065 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 41 ], + "D": [ 1045 ], + "Z": [ 1066 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 41 ], + "D": [ 1045 ], + "Z": [ 1067 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 41 ], + "Z": [ 905 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 41 ], + "Z": [ 1046 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1066 ], + "CLK": [ 2 ], + "DI": [ 1065 ], + "LSR": [ 905 ], + "Q": [ 1051 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1066 ], + "CLK": [ 2 ], + "DI": [ 1063 ], + "LSR": [ 905 ], + "Q": [ 1061 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1066 ], + "CLK": [ 2 ], + "DI": [ 1064 ], + "LSR": [ 905 ], + "Q": [ 1062 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1066 ], + "CLK": [ 2 ], + "DI": [ 1059 ], + "LSR": [ 905 ], + "Q": [ 1056 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1066 ], + "CLK": [ 2 ], + "DI": [ 1060 ], + "LSR": [ 905 ], + "Q": [ 1057 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1066 ], + "CLK": [ 2 ], + "DI": [ 1050 ], + "LSR": [ 905 ], + "Q": [ 1047 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1066 ], + "CLK": [ 2 ], + "DI": [ 1055 ], + "LSR": [ 905 ], + "Q": [ 1052 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8", + "module": "$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ 1068 ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 983 ], + "P1": [ 984 ], + "P10": [ 1023 ], + "P11": [ 1024 ], + "P12": [ 1031 ], + "P13": [ 1032 ], + "P14": [ 1039 ], + "P15": [ 1040 ], + "P16": [ 1069 ], + "P17": [ 1070 ], + "P18": [ 1071 ], + "P19": [ 1072 ], + "P2": [ 991 ], + "P20": [ 1073 ], + "P21": [ 1074 ], + "P22": [ 1075 ], + "P23": [ 1076 ], + "P24": [ 1077 ], + "P25": [ 1078 ], + "P26": [ 1079 ], + "P27": [ 1080 ], + "P28": [ 1081 ], + "P29": [ 1082 ], + "P3": [ 992 ], + "P30": [ 1083 ], + "P31": [ 1084 ], + "P32": [ 1085 ], + "P33": [ 1086 ], + "P34": [ 1087 ], + "P35": [ 1088 ], + "P4": [ 999 ], + "P5": [ 1000 ], + "P6": [ 1007 ], + "P7": [ 1008 ], + "P8": [ 1015 ], + "P9": [ 1016 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ 1068 ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 981 ], + "P1": [ 982 ], + "P10": [ 1021 ], + "P11": [ 1022 ], + "P12": [ 1029 ], + "P13": [ 1030 ], + "P14": [ 1037 ], + "P15": [ 1038 ], + "P16": [ 1089 ], + "P17": [ 1090 ], + "P18": [ 1091 ], + "P19": [ 1092 ], + "P2": [ 989 ], + "P20": [ 1093 ], + "P21": [ 1094 ], + "P22": [ 1095 ], + "P23": [ 1096 ], + "P24": [ 1097 ], + "P25": [ 1098 ], + "P26": [ 1099 ], + "P27": [ 1100 ], + "P28": [ 1101 ], + "P29": [ 1102 ], + "P3": [ 990 ], + "P30": [ 1103 ], + "P31": [ 1104 ], + "P32": [ 1105 ], + "P33": [ 1106 ], + "P34": [ 1107 ], + "P35": [ 1108 ], + "P4": [ 997 ], + "P5": [ 998 ], + "P6": [ 1005 ], + "P7": [ 1006 ], + "P8": [ 1013 ], + "P9": [ 1014 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1109 ], + "LSR": [ 1110 ], + "Q": [ 1068 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100111111011101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1056 ], + "B": [ 905 ], + "C": [ 1059 ], + "D": [ 1066 ], + "Z": [ 1109 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1047 ], + "B": [ 1057 ], + "C": [ 1066 ], + "D": [ 1111 ], + "Z": [ 1110 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0101010001010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 905 ], + "B": [ 1060 ], + "C": [ 1050 ], + "D": [ 1066 ], + "Z": [ 1111 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1067 ], + "CLK": [ 2 ], + "DI": [ 1112 ], + "LSR": [ 3 ], + "Q": [ 29 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1067 ], + "CLK": [ 2 ], + "DI": [ 1113 ], + "LSR": [ 3 ], + "Q": [ 30 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1067 ], + "CLK": [ 2 ], + "DI": [ 1114 ], + "LSR": [ 3 ], + "Q": [ 32 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1067 ], + "CLK": [ 2 ], + "DI": [ 1115 ], + "LSR": [ 3 ], + "Q": [ 31 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1067 ], + "CLK": [ 2 ], + "DI": [ 1116 ], + "LSR": [ 3 ], + "Q": [ 33 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1067 ], + "CLK": [ 2 ], + "DI": [ 1117 ], + "LSR": [ 3 ], + "Q": [ 34 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1067 ], + "CLK": [ 2 ], + "DI": [ 1118 ], + "LSR": [ 3 ], + "Q": [ 35 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1067 ], + "CLK": [ 2 ], + "DI": [ "0" ], + "LSR": [ 3 ], + "Q": [ 36 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 959 ], + "C": [ 955 ], + "D": [ 1119 ], + "Z": [ 1117 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 904 ], + "C": [ 955 ], + "D": [ 1119 ], + "Z": [ 1114 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 951 ], + "C": [ 955 ], + "D": [ 1119 ], + "Z": [ 1116 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 949 ], + "C": [ 955 ], + "D": [ 1119 ], + "Z": [ 1115 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 941 ], + "C": [ 955 ], + "D": [ 1119 ], + "Z": [ 1113 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 965 ], + "C": [ 955 ], + "D": [ 1119 ], + "Z": [ 1118 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 963 ], + "C": [ 955 ], + "D": [ 1119 ], + "Z": [ 1112 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 953 ], + "D": [ 1120 ], + "Z": [ 1119 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 945 ], + "A1": [ 947 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1121 ], + "COUT": [ 1120 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1122 ], + "S1": [ 1123 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 957 ], + "A1": [ 913 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1124 ], + "COUT": [ 1121 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1125 ], + "S1": [ 1126 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 923 ], + "A1": [ 909 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1127 ], + "COUT": [ 1124 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1128 ], + "S1": [ 1129 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 915 ], + "A1": [ 919 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1130 ], + "COUT": [ 1127 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1131 ], + "S1": [ 1132 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 961 ], + "A1": [ 937 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1133 ], + "COUT": [ 1130 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1134 ], + "S1": [ 1135 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 925 ], + "A1": [ 927 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1136 ], + "COUT": [ 1133 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1137 ], + "S1": [ 1138 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 943 ], + "A1": [ 921 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1139 ], + "COUT": [ 1136 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1140 ], + "S1": [ 1141 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 933 ], + "A1": [ 935 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1142 ], + "COUT": [ 1139 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1143 ], + "S1": [ 1144 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 907 ], + "A1": [ 917 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1145 ], + "COUT": [ 1142 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1146 ], + "S1": [ 1147 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 939 ], + "A1": [ 929 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1148 ], + "COUT": [ 1145 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1149 ], + "S1": [ 1150 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 911 ], + "A1": [ 931 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1151 ], + "COUT": [ 1148 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1152 ], + "S1": [ 1153 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 965 ], + "A1": [ 967 ], + "B0": [ "1" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1154 ], + "COUT": [ 1151 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1155 ], + "S1": [ 1156 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 951 ], + "A1": [ 959 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1157 ], + "COUT": [ 1154 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1158 ], + "S1": [ 1159 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 949 ], + "A1": [ 904 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1160 ], + "COUT": [ 1157 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1161 ], + "S1": [ 1162 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 963 ], + "A1": [ 941 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ "1" ], + "COUT": [ 1160 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1163 ], + "S1": [ 1164 ] + } + } + }, + "netnames": { + "bias_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:19.43-19.51" + } + }, + "busy": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:7.12-7.16" + } + }, + "clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:2.11-2.14" + } + }, + "done": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:8.12-8.16" + } + }, + "i": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:21.13-21.14" + } + }, + "rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:3.11-3.14" + } + }, + "start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:4.11-4.16" + } + }, + "start_LUT4_B_1_Z": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + } + }, + "start_LUT4_B_Z": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc": { + "hide_name": 0, + "bits": [ 51, 61, 63, 65, 67, 69, 71, 73, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 99, 101, 53, 75, 97, 103, 105, 107, 109, 111, 113, 55, 57, 59 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ 49, 60, 62, 64, 66, 68, 70, 72, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 98, 100, 52, 74, 96, 102, 104, 106, 108, 110, 112, 54, 56, 58 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_B1": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_COUT": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_COUT": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_B1": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_COUT": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_COUT": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_B1": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_COUT": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_B1": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_COUT": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_COUT": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_COUT": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_B1": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_COUT": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_6_COUT": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_B1": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_COUT": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_COUT": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_B1": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_COUT": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 42, 190 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 210, 205, 200, 201, 208, 209, 195 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:34.26-34.27" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_1_S0": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z": { + "hide_name": 0, + "bits": [ 206, 50, 208, 212 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ 49, 60, 62, 64, 66, 68, 70, 72, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 98, 100, 52, 74, 96, 102, 104, 106, 108, 110, 112, 54, 56, 58 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 202, 203, 196, 197, 206, 207, 192 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 153, 154, 187, 188, 125, 126, 136, 137, 145, 146, 172, 173, 164, 165, 178, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ 153, 154, 187, 188, 125, 126, 136, 137, 145, 146, 172, 173, 164, 165, 178, 179 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1165, 1166, 1167, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 153, 154, 187, 188, 125, 126, 136, 137, 145, 146, 172, 173, 164, 165, 178, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ 213, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 151, 152, 185, 186, 123, 124, 134, 135, 143, 144, 170, 171, 162, 163, 176, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ 151, 152, 185, 186, 123, 124, 134, 135, 143, 144, 170, 171, 162, 163, 176, 177 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1181, 1182, 1183, 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 151, 152, 185, 186, 123, 124, 134, 135, 143, 144, 170, 171, 162, 163, 176, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ 213, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ 51, 61, 63, 65, 67, 69, 71, 73, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 99, 101, 53, 75, 97, 103, 105, 107, 109, 111, 113, 55, 57, 59 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ 49, 60, 62, 64, 66, 68, 70, 72, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 98, 100, 52, 74, 96, 102, 104, 106, 108, 110, 112, 54, 56, 58 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ 153, 154, 187, 188, 125, 126, 136, 137, 145, 146, 172, 173, 164, 165, 178, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ 151, 152, 185, 186, 123, 124, 134, 135, 143, 144, 170, 171, 162, 163, 176, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ 153, 154, 187, 188, 125, 126, 136, 137, 145, 146, 172, 173, 164, 165, 178, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179, 179 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ 151, 152, 185, 186, 123, 124, 134, 135, 143, 144, 170, 171, 162, 163, 176, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177, 177 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ 1197, 1198, 1199, 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1213, 1213, 1213, 1213, 1213, 1213, 1213, 1213, 1213, 1213, 1213, 1213, 1213, 1213, 1213 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ 213, "0", "0", "0", "0", "0", "0", "0", 213, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 254 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 255 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 209, 195, 212, 256 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.w_group": { + "hide_name": 0, + "bits": [ 213, "0", "0", "0", "0", "0", "0", "0", 213, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y": { + "hide_name": 0, + "bits": [ 5, 6, 7, 8, 9, 10, 11, 12 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 257, 258, 259, 260, 261, 262, 263, "0" ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 70, 58, 264 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 265 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 266 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 269 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 272 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 275 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 278 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 281 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 284 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 287 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 290 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 293 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 296 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 299 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 302 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 305 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 308 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 309 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 306 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 307 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 303 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 304 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 300 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 301 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 297 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 298 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 294 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 295 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 291 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 292 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 288 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 289 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 285 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 286 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 282 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 283 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 279 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 280 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 276 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 277 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 273 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 274 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 270 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 271 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 267 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 268 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc": { + "hide_name": 0, + "bits": [ 339, 341, 343, 345, 311, 313, 347, 349, 351, 353, 355, 359, 361, 335, 357, 363, 365, 367, 369, 371, 373, 315, 317, 319, 321, 323, 325, 327, 329, 331, 333, 337 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ 338, 1214, 1215, 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41", + "unused_bits": "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_A1": { + "hide_name": 0, + "bits": [ 374 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT": { + "hide_name": 0, + "bits": [ 375 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 381 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 386 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 391 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 396 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 401 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 406 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 411 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 416 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 421 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 426 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 431 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 436 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 441 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 446 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 451 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 452 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 389, 450, 453 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 447 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 448 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 442 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 443 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 437 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 438 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 432 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 433 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 427 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 428 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 422 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 423 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 417 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 418 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 412 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 413 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 407 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 408 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 402 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 403 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 397 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 398 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 392 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 393 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 387 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 388 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 382 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 383 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_S0": { + "hide_name": 0, + "bits": [ 376 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_S1": { + "hide_name": 0, + "bits": [ 377 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 455 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 461 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 454 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 456 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1": { + "hide_name": 0, + "bits": [ 463 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 471 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 476 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 483 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 490 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 497 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 504 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 511 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 514 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 515 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 516 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 512 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 513 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 505 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 506 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 498 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 499 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 491 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 492 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 484 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 485 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 477 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 478 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 462 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 464 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 581, 465, 379 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S0_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 517 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S0_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 518 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 581, 466, 380 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 520 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 519, 384 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 521 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 522, 385 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 524 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 523, 389 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 525 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 526, 390 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 528 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 527, 394 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 529 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 530, 395 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 532 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 531, 399 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 533 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 534, 400 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 536 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 535, 404 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 537 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 538, 405 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 540 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 539, 409 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 541 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 542, 410 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 544 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 543, 414 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 545 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 546, 415 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 548 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 547, 419 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 549 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 550, 420 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 552 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 551, 424 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 553 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 554, 425 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 556 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 555, 429 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 557 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 558, 430 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 560 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 559, 434 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 561 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 562, 435 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 564 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 563, 439 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 565 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 566, 440 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 568 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 567, 444 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 569 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 570, 445 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 572 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 571, 449 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 573 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 581, 574, 450 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 575 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 576 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 579 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 596, 595, 586, 587, 590, 591, 580 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:34.26-34.27" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_S0_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 578 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_S0_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 584 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_S0_CCU2C_S1_2_S0": { + "hide_name": 0, + "bits": [ 594 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S1_S0_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 585 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 378 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "single_bit_vector": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_S0_S1_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 340, 342, 344, 310, 312, 346, 348, 350, 352, 354, 358, 360, 334, 356, 362, 364, 366, 368, 370, 372, 314, 316, 318, 320, 322, 324, 326, 328, 330, 332, 336 ], + "offset": 1, + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z": { + "hide_name": 0, + "bits": [ 597, 601, 600, 599, 602, 603, 598, "0" ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "1", "0", "1", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 604 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 605 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ 338, 1245, 1246, 1247, 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42", + "unused_bits": "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 592, 593, 582, 583, 588, 589, 577 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_CE": { + "hide_name": 0, + "bits": [ 606 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 459, 460, 469, 470, 474, 475, 481, 482, 488, 489, 495, 496, 502, 503, 509, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ 459, 460, 469, 470, 474, 475, 481, 482, 488, 489, 495, 496, 502, 503, 509, 510 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1276, 1277, 1278, 1279, 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 607, 608, 609, 610, 611, 612, 613, 614, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 459, 460, 469, 470, 474, 475, 481, 482, 488, 489, 495, 496, 502, 503, 509, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 457, 458, 467, 468, 472, 473, 479, 480, 486, 487, 493, 494, 500, 501, 507, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ 457, 458, 467, 468, 472, 473, 479, 480, 486, 487, 493, 494, 500, 501, 507, 508 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1292, 1293, 1294, 1295, 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 627, 628, 629, 630, 631, 632, 633, 634, 635, 636, 637, 638, 639, 640, 641, 642, 643, 644, 645, 646 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 457, 458, 467, 468, 472, 473, 479, 480, 486, 487, 493, 494, 500, 501, 507, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ 339, 341, 343, 345, 311, 313, 347, 349, 351, 353, 355, 359, 361, 335, 357, 363, 365, 367, 369, 371, 373, 315, 317, 319, 321, 323, 325, 327, 329, 331, 333, 337 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ 338, 1214, 1215, 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42", + "unused_bits": "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ 459, 460, 469, 470, 474, 475, 481, 482, 488, 489, 495, 496, 502, 503, 509, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ 457, 458, 467, 468, 472, 473, 479, 480, 486, 487, 493, 494, 500, 501, 507, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ 459, 460, 469, 470, 474, 475, 481, 482, 488, 489, 495, 496, 502, 503, 509, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510, 510 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ 457, 458, 467, 468, 472, 473, 479, 480, 486, 487, 493, 494, 500, 501, 507, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508, 508 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1324, 1324, 1324, 1324, 1324, 1324, 1324, 1324, 1324, 1324, 1324, 1324, 1324, 1324, 1324 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y": { + "hide_name": 0, + "bits": [ 13, 14, 15, 16, 17, 18, 19, 20 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_CE": { + "hide_name": 0, + "bits": [ 647 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc": { + "hide_name": 0, + "bits": [ 695, 693, 697, 691, 699, 649, 651, 673, 665, 685, 689, 683, 675, 677, 663, 709, 679, 681, 687, 701, 707, 703, 667, 705, 711, 653, 655, 657, 659, 661, 669, 671 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ 694, 692, 696, 690, 698, 648, 650, 672, 664, 684, 688, 682, 674, 676, 662, 708, 678, 680, 686, 700, 706, 702, 666, 704, 710, 652, 654, 656, 658, 660, 668, 670 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_B1": { + "hide_name": 0, + "bits": [ 720 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 727 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 719 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_COUT": { + "hide_name": 0, + "bits": [ 717 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_B1": { + "hide_name": 0, + "bits": [ 729 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 737 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 728 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_COUT": { + "hide_name": 0, + "bits": [ 731 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_COUT": { + "hide_name": 0, + "bits": [ 713 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_COUT": { + "hide_name": 0, + "bits": [ 740 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_B1": { + "hide_name": 0, + "bits": [ 742 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 748 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 741 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_COUT": { + "hide_name": 0, + "bits": [ 743 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_B1": { + "hide_name": 0, + "bits": [ 750 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 736 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 749 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_COUT": { + "hide_name": 0, + "bits": [ 730 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1": { + "hide_name": 0, + "bits": [ 716 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 759 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 760 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 712 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 761 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 715 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 718 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_B1": { + "hide_name": 0, + "bits": [ 763 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 726 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 762 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 721 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_COUT": { + "hide_name": 0, + "bits": [ 770 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_B1": { + "hide_name": 0, + "bits": [ 772 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 778 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 771 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_COUT": { + "hide_name": 0, + "bits": [ 773 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_COUT": { + "hide_name": 0, + "bits": [ 738 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_COUT": { + "hide_name": 0, + "bits": [ 779 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_COUT": { + "hide_name": 0, + "bits": [ 780 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_COUT": { + "hide_name": 0, + "bits": [ 739 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_B1": { + "hide_name": 0, + "bits": [ 782 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 769 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 781 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_COUT": { + "hide_name": 0, + "bits": [ 764 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 714 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 787 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 39, 788 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 792 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 808, 803, 806, 807, 797, 798, 793 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:34.26-34.27" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 801 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_1_S0": { + "hide_name": 0, + "bits": [ 802 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 796 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 791 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z": { + "hide_name": 0, + "bits": [ 810 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 809 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 789 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ 694, 692, 696, 690, 698, 648, 650, 672, 664, 684, 688, 682, 674, 676, 662, 708, 678, 680, 686, 700, 706, 702, 666, 704, 710, 652, 654, 656, 658, 660, 668, 670 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 799, 800, 804, 805, 794, 795, 790 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 746, 747, 753, 754, 734, 735, 776, 777, 785, 786, 767, 768, 724, 725, 757, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ 746, 747, 753, 754, 734, 735, 776, 777, 785, 786, 767, 768, 724, 725, 757, 758 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1325, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 811, 812, 813, 814, 815, 816, 817, 818, 819, 820, 821, 822, 823, 824, 825, 826, 827, 828, 829, 830 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 746, 747, 753, 754, 734, 735, 776, 777, 785, 786, 767, 768, 724, 725, 757, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 744, 745, 751, 752, 732, 733, 774, 775, 783, 784, 765, 766, 722, 723, 755, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ 744, 745, 751, 752, 732, 733, 774, 775, 783, 784, 765, 766, 722, 723, 755, 756 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1341, 1342, 1343, 1344, 1345, 1346, 1347, 1348, 1349, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 831, 832, 833, 834, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845, 846, 847, 848, 849, 850 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 744, 745, 751, 752, 732, 733, 774, 775, 783, 784, 765, 766, 722, 723, 755, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ 695, 693, 697, 691, 699, 649, 651, 673, 665, 685, 689, 683, 675, 677, 663, 709, 679, 681, 687, 701, 707, 703, 667, 705, 711, 653, 655, 657, 659, 661, 669, 671 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ 694, 692, 696, 690, 698, 648, 650, 672, 664, 684, 688, 682, 674, 676, 662, 708, 678, 680, 686, 700, 706, 702, 666, 704, 710, 652, 654, 656, 658, 660, 668, 670 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ 746, 747, 753, 754, 734, 735, 776, 777, 785, 786, 767, 768, 724, 725, 757, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ 744, 745, 751, 752, 732, 733, 774, 775, 783, 784, 765, 766, 722, 723, 755, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ 746, 747, 753, 754, 734, 735, 776, 777, 785, 786, 767, 768, 724, 725, 757, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758, 758 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ 744, 745, 751, 752, 732, 733, 774, 775, 783, 784, 765, 766, 722, 723, 755, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756, 756 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ 1357, 1358, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1367, 1368, 1369, 1370, 1371, 1372, 1373, 1373, 1373, 1373, 1373, 1373, 1373, 1373, 1373, 1373, 1373, 1373, 1373, 1373, 1373, 1373 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y": { + "hide_name": 0, + "bits": [ 21, 22, 23, 24, 25, 26, 27, 28 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 852, 853, 854, 855, 856, 857, 851, "0" ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 650, 670, 858 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 859 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 860 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 863 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 866 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 869 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 872 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 875 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 878 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 881 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 884 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 887 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 890 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 893 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 896 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 899 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 902 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 903 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 900 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 901 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 897 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 898 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 894 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 895 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 891 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 892 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 888 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 889 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 885 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 886 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 882 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 883 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 879 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 880 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 876 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 877 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 873 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 874 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 870 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 871 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 867 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 868 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 864 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 865 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 861 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 862 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc": { + "hide_name": 0, + "bits": [ 964, 942, 950, 906, 952, 960, 966, 968, 912, 932, 940, 930, 908, 918, 934, 936, 944, 922, 926, 928, 962, 938, 916, 920, 924, 910, 958, 914, 946, 948, 954, 956 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ 963, 941, 949, 904, 951, 959, 965, 967, 911, 931, 939, 929, 907, 917, 933, 935, 943, 921, 925, 927, 961, 937, 915, 919, 923, 909, 957, 913, 945, 947, 953, 955 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_COUT": { + "hide_name": 0, + "bits": [ 976 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_COUT": { + "hide_name": 0, + "bits": [ 977 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_12_COUT": { + "hide_name": 0, + "bits": [ 978 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_COUT": { + "hide_name": 0, + "bits": [ 979 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_COUT": { + "hide_name": 0, + "bits": [ 980 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_COUT": { + "hide_name": 0, + "bits": [ 970 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_B1": { + "hide_name": 0, + "bits": [ 973 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 985 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 972 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 974 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_B1": { + "hide_name": 0, + "bits": [ 987 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 993 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 986 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 988 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1": { + "hide_name": 0, + "bits": [ 995 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1001 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 994 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_COUT": { + "hide_name": 0, + "bits": [ 996 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1": { + "hide_name": 0, + "bits": [ 1003 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1009 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 1002 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_COUT": { + "hide_name": 0, + "bits": [ 1004 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1": { + "hide_name": 0, + "bits": [ 1011 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1017 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 1010 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_COUT": { + "hide_name": 0, + "bits": [ 1012 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1": { + "hide_name": 0, + "bits": [ 1019 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1025 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 1018 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_COUT": { + "hide_name": 0, + "bits": [ 1020 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1": { + "hide_name": 0, + "bits": [ 1027 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1033 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 1026 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_COUT": { + "hide_name": 0, + "bits": [ 1028 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1": { + "hide_name": 0, + "bits": [ 1035 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1041 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1042 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 969 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1043 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 1034 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_COUT": { + "hide_name": 0, + "bits": [ 1036 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_COUT": { + "hide_name": 0, + "bits": [ 975 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 971 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1044 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 41, 1045 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1049 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 1065, 1055, 1063, 1064, 1059, 1060, 1050 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:34.26-34.27" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 1048 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 1058 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1053 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_CCU2C_S1_S0_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 1054 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z": { + "hide_name": 0, + "bits": [ 1067 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 1056, 905, 1059, 1066 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 1046 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ 963, 941, 949, 904, 951, 959, 965, 967, 911, 931, 939, 929, 907, 917, 933, 935, 943, 921, 925, 927, 961, 937, 915, 919, 923, 909, 957, 913, 945, 947, 953, 955 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 1051, 1052, 1061, 1062, 1056, 1057, 1047 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 983, 984, 991, 992, 999, 1000, 1007, 1008, 1015, 1016, 1023, 1024, 1031, 1032, 1039, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ 983, 984, 991, 992, 999, 1000, 1007, 1008, 1015, 1016, 1023, 1024, 1031, 1032, 1039, 1040 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1383, 1384, 1385, 1386, 1387, 1388, 1389, 1069, 1070, 1071, 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, 1088 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 983, 984, 991, 992, 999, 1000, 1007, 1008, 1015, 1016, 1023, 1024, 1031, 1032, 1039, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", 1068, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 981, 982, 989, 990, 997, 998, 1005, 1006, 1013, 1014, 1021, 1022, 1029, 1030, 1037, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ 981, 982, 989, 990, 997, 998, 1005, 1006, 1013, 1014, 1021, 1022, 1029, 1030, 1037, 1038 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1390, 1391, 1392, 1393, 1394, 1395, 1396, 1397, 1398, 1399, 1400, 1401, 1402, 1403, 1404, 1405, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, 1104, 1105, 1106, 1107, 1108 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 981, 982, 989, 990, 997, 998, 1005, 1006, 1013, 1014, 1021, 1022, 1029, 1030, 1037, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", 1068, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ 964, 942, 950, 906, 952, 960, 966, 968, 912, 932, 940, 930, 908, 918, 934, 936, 944, 922, 926, 928, 962, 938, 916, 920, 924, 910, 958, 914, 946, 948, 954, 956 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ 963, 941, 949, 904, 951, 959, 965, 967, 911, 931, 939, 929, 907, 917, 933, 935, 943, 921, 925, 927, 961, 937, 915, 919, 923, 909, 957, 913, 945, 947, 953, 955 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ 983, 984, 991, 992, 999, 1000, 1007, 1008, 1015, 1016, 1023, 1024, 1031, 1032, 1039, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ 981, 982, 989, 990, 997, 998, 1005, 1006, 1013, 1014, 1021, 1022, 1029, 1030, 1037, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ 983, 984, 991, 992, 999, 1000, 1007, 1008, 1015, 1016, 1023, 1024, 1031, 1032, 1039, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ 981, 982, 989, 990, 997, 998, 1005, 1006, 1013, 1014, 1021, 1022, 1029, 1030, 1037, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038, 1038 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ 1406, 1407, 1408, 1409, 1410, 1411, 1412, 1413, 1414, 1415, 1416, 1417, 1418, 1419, 1420, 1421, 1422, 1422, 1422, 1422, 1422, 1422, 1422, 1422, 1422, 1422, 1422, 1422, 1422, 1422, 1422, 1422 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", 1068, "0", "0", "0", "0", "0", "0", "0", 1068, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1109 ], + "offset": 2, + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 1110 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1047, 1057, 1066, 1111 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "0", "0", 1068, "0", "0", "0", "0", "0", "0", "0", 1068, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y": { + "hide_name": 0, + "bits": [ 29, 30, 31, 32, 33, 34, 35, 36 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1112, 1113, 1115, 1114, 1116, 1117, 1118, "0" ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 965, 955, 1119 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1120 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1121 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1124 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1127 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1130 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1133 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1136 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1139 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1142 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1145 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1148 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1151 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1154 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1157 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1160 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1163 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1164 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1161 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1162 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1158 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1159 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1155 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1156 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1152 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1153 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1149 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1150 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1146 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1147 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1143 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1144 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1140 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1141 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1137 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1138 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1134 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1135 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1131 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1132 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1128 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1129 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1125 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1126 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1122 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1123 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.bias_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer bias_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:18.9-18.17" + } + }, + "u_layer.busy": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "hdlname": "u_layer busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:23.12-23.16" + } + }, + "u_layer.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:8.11-8.14" + } + }, + "u_layer.done": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "hdlname": "u_layer done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:24.12-24.16" + } + }, + "u_layer.neuron_busy": { + "hide_name": 0, + "bits": [ 42, 40, 39, 41 ], + "attributes": { + "hdlname": "u_layer neuron_busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:27.26-27.37" + } + }, + "u_layer.neuron_done": { + "hide_name": 0, + "bits": [ 46, 44, 43, 45 ], + "attributes": { + "hdlname": "u_layer neuron_done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:28.26-28.37" + } + }, + "u_layer.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:9.11-9.14" + } + }, + "u_layer.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:10.11-10.16" + } + }, + "u_layer.weights_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer weights_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:15.9-15.20" + } + }, + "u_layer.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:12.44-12.49" + } + }, + "u_layer.y_bus": { + "hide_name": 0, + "bits": [ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer y_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:21.9-21.14" + } + }, + "weights_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:18.52-18.63" + } + }, + "x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:17.42-17.47" + } + }, + "y_bus": { + "hide_name": 0, + "bits": [ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:6.26-6.31" + } + } + } + } + } +} diff --git a/synth/ecp5/p2/top.lpf b/synth/ecp5/p2/top.lpf new file mode 100644 index 0000000..e69de29 diff --git a/synth/ecp5/p2/top.v b/synth/ecp5/p2/top.v new file mode 100644 index 0000000..9d3fc52 --- /dev/null +++ b/synth/ecp5/p2/top.v @@ -0,0 +1,78 @@ +module top ( + input clk, + input rst, + input start, + + output signed [31:0] y_bus, + output busy, + output done +); + + localparam DATA_WIDTH = 8; + localparam N_INPUTS = 256; + localparam N_NEURONS = 4; + localparam PARALLEL = 2; + localparam ACC_WIDTH = 32; + + reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus; + reg signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0] weights_bus; + reg signed [DATA_WIDTH*N_NEURONS-1:0] bias_bus; + + integer i; + + initial begin + x_bus = 0; + weights_bus = 0; + bias_bus = 0; + + // X = 1 + for (i = 0; i < N_INPUTS; i = i + 1) + x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1; + + // Neuron 0: first 32 weights = +1 + for (i = 0; i < 32; i = i + 1) + weights_bus[ + 0*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = 8'sd1; + + // Neuron 1: all zero, bias = 10 + bias_bus[1*DATA_WIDTH +: DATA_WIDTH] = 8'sd10; + + // Neuron 2: all weights = -1 + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 2*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = -8'sd1; + + // Neuron 3: first 32 weights = +4 + for (i = 0; i < 32; i = i + 1) + weights_bus[ + 3*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = 8'sd4; + end + + layer #( + .DATA_WIDTH(DATA_WIDTH), + .N_INPUTS(N_INPUTS), + .N_NEURONS(N_NEURONS), + .PARALLEL(PARALLEL), + .ACC_WIDTH(ACC_WIDTH) + ) u_layer ( + .clk(clk), + .rst(rst), + .start(start), + .x_bus(x_bus), + .weights_bus(weights_bus), + .bias_bus(bias_bus), + .y_bus(y_bus), + .busy(busy), + .done(done) + ); + +endmodule diff --git a/synth/ecp5/p2/yosys.log b/synth/ecp5/p2/yosys.log new file mode 100644 index 0000000..e69de29 diff --git a/synth/ecp5/p4/report.txt b/synth/ecp5/p4/report.txt new file mode 100644 index 0000000..b2deb98 --- /dev/null +++ b/synth/ecp5/p4/report.txt @@ -0,0 +1,391 @@ +Warning: IO 'y_bus[31]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[30]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[29]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[28]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[27]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[26]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[25]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[24]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[23]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[22]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[21]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[20]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[19]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[18]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[17]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[16]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[15]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[14]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[13]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[12]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[11]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[10]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[9]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[8]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[7]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[6]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[5]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[4]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[3]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[2]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[1]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[0]' is unconstrained in LPF and will be automatically placed +Warning: IO 'start' is unconstrained in LPF and will be automatically placed +Warning: IO 'rst' is unconstrained in LPF and will be automatically placed +Warning: IO 'done' is unconstrained in LPF and will be automatically placed +Warning: IO 'clk' is unconstrained in LPF and will be automatically placed +Warning: IO 'busy' is unconstrained in LPF and will be automatically placed + +Info: Logic utilisation before packing: +Info: Total LUT4s: 804/43848 1% +Info: logic LUTs: 356/43848 0% +Info: carry LUTs: 448/43848 1% +Info: RAM LUTs: 0/ 5481 0% +Info: RAMW LUTs: 0/10962 0% + +Info: Total DFFs: 194/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 191 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0x93c68254 + +Info: Device utilisation: +Info: TRELLIS_IO: 37/ 245 15% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 108 0% +Info: MULT18X18D: 16/ 72 22% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 194/ 43848 0% +Info: TRELLIS_COMB: 890/ 43848 2% +Info: TRELLIS_RAMW: 0/ 5481 0% + +Info: Placed 0 cells based on constraints. +Info: Creating initial analytic placement for 398 cells, random placement wirelen = 65706. +Info: at initial placer iter 0, wirelen = 3255 +Info: at initial placer iter 1, wirelen = 2910 +Info: at initial placer iter 2, wirelen = 2817 +Info: at initial placer iter 3, wirelen = 2693 +Info: Running main analytical placer, max placement attempts per cell = 161880. +Info: at iteration #1, type ALL: wirelen solved = 2654, spread = 6917, legal = 7559; time = 0.01s +Info: at iteration #2, type ALL: wirelen solved = 2701, spread = 7543, legal = 8208; time = 0.01s +Info: at iteration #3, type ALL: wirelen solved = 2730, spread = 8315, legal = 8393; time = 0.01s +Info: at iteration #4, type ALL: wirelen solved = 2702, spread = 6982, legal = 7415; time = 0.01s +Info: at iteration #5, type ALL: wirelen solved = 2846, spread = 6733, legal = 7431; time = 0.01s +Info: at iteration #6, type ALL: wirelen solved = 2766, spread = 7088, legal = 7527; time = 0.01s +Info: at iteration #7, type ALL: wirelen solved = 2848, spread = 7040, legal = 7862; time = 0.01s +Info: at iteration #8, type ALL: wirelen solved = 2953, spread = 6901, legal = 8121; time = 0.01s +Info: at iteration #9, type ALL: wirelen solved = 2945, spread = 6701, legal = 8004; time = 0.01s +Info: HeAP Placer Time: 0.10s +Info: of which solving equations: 0.06s +Info: of which spreading cells: 0.01s +Info: of which strict legalisation: 0.00s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 277, wirelen = 7415 +Info: at iteration #5: temp = 0.000000, timing cost = 202, wirelen = 5008 +Info: at iteration #10: temp = 0.000000, timing cost = 301, wirelen = 4801 +Info: at iteration #15: temp = 0.000000, timing cost = 280, wirelen = 4741 +Info: at iteration #20: temp = 0.000000, timing cost = 272, wirelen = 4694 +Info: at iteration #20: temp = 0.000000, timing cost = 271, wirelen = 4699 +Info: SA placement time 0.33s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 76.41 MHz (FAIL at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.72 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 7.09 ns + +Info: Slack histogram: +Info: legend: * represents 2 endpoint(s) +Info: + represents [1,2) endpoint(s) +Info: [ -588, 38) |****+ +Info: [ 38, 664) |*+ +Info: [ 664, 1290) | +Info: [ 1290, 1916) | +Info: [ 1916, 2542) |**+ +Info: [ 2542, 3168) |**************+ +Info: [ 3168, 3794) |******+ +Info: [ 3794, 4420) |+ +Info: [ 4420, 5046) |*+ +Info: [ 5046, 5672) |*+ +Info: [ 5672, 6298) | +Info: [ 6298, 6924) |********+ +Info: [ 6924, 7550) |*****+ +Info: [ 7550, 8176) |*+ +Info: [ 8176, 8802) |**+ +Info: [ 8802, 9428) |************+ +Info: [ 9428, 10054) |************************************************************ +Info: [ 10054, 10680) |******************************************+ +Info: [ 10680, 11306) |*************************************+ +Info: [ 11306, 11932) |*******+ +Info: Checksum: 0x87182704 +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 2833 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 615 384 | 615 384 | 2543| 0.16 0.16| +Info: 2000 | 1342 657 | 727 273 | 2390| 0.18 0.34| +Info: 3000 | 2021 978 | 679 321 | 2204| 0.17 0.51| +Info: 4000 | 2356 1549 | 335 571 | 1570| 0.11 0.61| +Info: 5000 | 2415 2379 | 59 830 | 638| 0.06 0.67| +Info: 5643 | 2421 2956 | 6 577 | 0| 0.09 0.76| +Info: Routing complete. +Info: Router1 time 0.76s +Info: Checksum: 0xf9732732 + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.Q +Info: routing 1.14 1.53 Net u_layer.GEN_NEURON[0].u_neuron.w_group[0] (31,23) -> (23,22) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9.B0 +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50 +Info: logic 3.07 4.60 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9.P2 +Info: routing 1.52 6.12 Net u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[0][2] (23,22) -> (31,20) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.B +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13 +Info: logic 0.35 6.47 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 6.47 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (31,20) -> (31,20) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.00 6.47 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 6.47 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (31,20) -> (31,20) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 6.53 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 6.53 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (31,20) -> (31,20) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.00 6.53 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 6.53 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (31,20) -> (32,20) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.33 6.86 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.F +Info: routing 0.68 7.54 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[2] (32,20) -> (34,20) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 7.72 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0_LUT4_Z.F +Info: routing 1.09 8.81 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0 (34,20) -> (35,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.A +Info: logic 0.35 9.16 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.FCO +Info: routing 0.00 9.16 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_FCI_INT (35,19) -> (35,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCI +Info: logic 0.00 9.16 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCO +Info: routing 0.00 9.16 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_COUT (35,19) -> (35,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCI +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.22 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCO +Info: routing 0.00 9.22 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_FCI_INT (35,19) -> (35,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCI +Info: logic 0.00 9.22 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCO +Info: routing 0.00 9.22 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_COUT (35,19) -> (35,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCI +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.27 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCO +Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_FCI_INT (35,19) -> (35,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCI +Info: logic 0.00 9.27 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCO +Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_COUT (35,19) -> (35,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.33 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_FCI_INT (35,19) -> (35,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.00 9.33 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_COUT (35,19) -> (36,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCI +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.38 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCO +Info: routing 0.00 9.38 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_FCI_INT (36,19) -> (36,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCI +Info: logic 0.00 9.38 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCO +Info: routing 0.00 9.38 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_COUT (36,19) -> (36,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCI +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.44 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCO +Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_FCI_INT (36,19) -> (36,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.FCI +Info: logic 0.00 9.44 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.FCO +Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_COUT (36,19) -> (36,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB0.FCI +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 9.50 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB0.FCO +Info: routing 0.00 9.50 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_FCI_INT (36,19) -> (36,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB1.FCI +Info: logic 0.00 9.50 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB1.FCO +Info: routing 0.00 9.50 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_COUT (36,19) -> (36,19) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3$CCU2_COMB0.FCI +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.33 9.82 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3$CCU2_COMB0.F +Info: routing 0.85 10.67 Net u_layer.GEN_NEURON[0].u_neuron.acc_next[20] (36,19) -> (36,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42 +Info: logic 0.35 11.02 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 11.02 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,18) -> (36,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 11.02 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 11.02 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,18) -> (37,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 11.08 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 11.08 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 11.08 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 11.08 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (37,18) -> (37,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 11.14 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 11.14 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 11.14 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 11.14 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (37,18) -> (37,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 11.19 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 11.19 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 11.19 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 11.19 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN (37,18) -> (37,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 11.25 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 11.25 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 11.25 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 11.25 Net $nextpnr_CCU2C_19$CIN (37,18) -> (38,18) +Info: Sink $nextpnr_CCU2C_19$CCU2_COMB0.FCI +Info: logic 0.33 11.58 Source $nextpnr_CCU2C_19$CCU2_COMB0.F +Info: routing 0.63 12.21 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D (38,18) -> (38,23) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.D +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.18 12.39 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.F +Info: routing 0.64 13.03 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C[1] (38,23) -> (36,23) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 13.21 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4.F +Info: routing 0.12 13.33 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI[5] (36,23) -> (36,23) +Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_5.DI +Info: setup 0.00 13.33 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_5.DI +Info: 6.67 ns logic, 6.66 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': +Info: type curr total name +Info: source 0.00 0.00 Source rst$tr_io.O +Info: routing 3.60 3.60 Net rst$TRELLIS_IO_IN (0,23) -> (63,24) +Info: Sink start_LUT4_B_2.C +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:9.11-9.14 +Info: logic 0.18 3.78 Source start_LUT4_B_2.F +Info: routing 1.31 5.09 Net start_LUT4_B_2_Z (63,24) -> (67,27) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_31.LSR +Info: setup 0.29 5.38 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_31.LSR +Info: 0.47 ns logic, 4.91 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4.Q +Info: routing 4.40 4.79 Net y_bus[20]$TRELLIS_IO_OUT (64,25) -> (18,71) +Info: Sink y_bus[20]$tr_io.I +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:6.26-6.31 +Info: 0.40 ns logic, 4.40 ns routing + +ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 75.01 MHz (FAIL at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.38 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.79 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ -831, -207) |*******+ +Info: [ -207, 417) | +Info: [ 417, 1041) | +Info: [ 1041, 1665) | +Info: [ 1665, 2289) |*+ +Info: [ 2289, 2913) |*********************+ +Info: [ 2913, 3537) |*******+ +Info: [ 3537, 4161) |***+ +Info: [ 4161, 4785) |**+ +Info: [ 4785, 5409) | +Info: [ 5409, 6033) |***+ +Info: [ 6033, 6657) |**********+ +Info: [ 6657, 7281) |****+ +Info: [ 7281, 7905) |*+ +Info: [ 7905, 8529) |*+ +Info: [ 8529, 9153) |********************+ +Info: [ 9153, 9777) |************************+ +Info: [ 9777, 10401) |************************************************************ +Info: [ 10401, 11025) |*******************************************************+ +Info: [ 11025, 11649) |**********************************************+ +37 warnings, 1 error + +Info: Program finished normally. diff --git a/synth/ecp5/p4/synth.ys b/synth/ecp5/p4/synth.ys new file mode 100644 index 0000000..c4d8bd0 --- /dev/null +++ b/synth/ecp5/p4/synth.ys @@ -0,0 +1,8 @@ + +read_verilog -sv /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v + +hierarchy -top top + +synth_ecp5 -top top + +write_json /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.json diff --git a/synth/ecp5/p4/top.config b/synth/ecp5/p4/top.config new file mode 100644 index 0000000..436709f --- /dev/null +++ b/synth/ecp5/p4/top.config @@ -0,0 +1,15757 @@ +.device LFE5U-45F + +.comment Part: LFE5U-45F-8CABGA381 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R13C1:CIB_LR +arc: E3_H06E0303 JQ5 + +.tile CIB_R19C1:CIB_LR +arc: S1_V02S0501 E3_H06W0303 + +.tile CIB_R1C36:CIB +arc: JA0 E1_H02W0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C37:CIB +arc: E3_H06E0303 S3_V06N0303 +arc: JA0 H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C38:CIB +arc: JA0 S1_V02N0501 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C39:CIB +arc: JA0 V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C41:CIB +arc: E1_H02E0501 S1_V02N0501 + +.tile CIB_R1C42:CIB +arc: JA0 H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C43:CIB +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0000 S1_V02N0601 +arc: JA0 H00R0000 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C44:CIB +arc: E1_H02E0501 S3_V06N0303 +arc: JA0 S1_V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C45:CIB +arc: JA0 H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C47:CIB +arc: JA0 S1_V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C48:CIB +arc: JD7 E1_H01W0100 + +.tile CIB_R1C49:CIB +arc: H01W0100 W3_H06E0303 + +.tile CIB_R1C53:CIB +arc: E1_H02E0501 V06N0303 + +.tile CIB_R1C54:CIB +arc: JA0 H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C65:CIB +arc: E1_H02E0701 V06N0203 + +.tile CIB_R1C66:CIB +arc: JA0 H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C69:CIB +arc: E1_H02E0701 V06N0203 +arc: H00L0100 S1_V02N0101 +arc: JA0 H00L0100 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C70:CIB +arc: JA0 H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C72:CIB +arc: JA0 S1_V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R20C1:CIB_LR +arc: E1_H01E0001 E3_H06W0003 +arc: JA0 V02S0501 +arc: JA3 E1_H01E0001 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 H06W0203 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R20C89:CIB_LR +arc: JA0 W1_H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R22C1:CIB_LR_S +arc: JA0 N1_V02S0701 +arc: JA3 N1_V02S0501 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R22C22:CIB_DSP +arc: E3_H06E0003 JQ0 +arc: E3_H06E0103 JQ1 +arc: E3_H06E0203 JQ4 +arc: E3_H06E0303 JQ6 +arc: N1_V02N0201 JQ2 +arc: N1_V02N0301 JQ3 +arc: N1_V02N0501 JQ5 +arc: N1_V02N0701 JQ7 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R22C23:CIB_DSP +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0003 JQ0 +arc: E3_H06E0103 JQ1 +arc: E3_H06E0203 JQ4 +arc: E3_H06E0303 JQ5 +arc: N1_V01N0101 JQ2 +arc: N1_V02N0101 JQ3 +arc: N1_V02N0601 JQ6 +arc: N1_V02N0701 JQ7 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 + +.tile CIB_R22C24:CIB_DSP +arc: H00R0000 V02N0601 +arc: JD3 H00R0000 +arc: JLSR0 H02E0301 +arc: JLSR1 H02E0301 +arc: N1_V02N0301 H02E0301 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 1 + +.tile CIB_R22C25:CIB_DSP +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 + +.tile CIB_R22C26:CIB_DSP +arc: E1_H01E0001 JF7 +arc: E1_H01E0101 JF6 +arc: E3_H06E0203 JF4 +arc: E3_H06E0303 JQ5 +arc: H00R0100 E1_H02W0501 +arc: JCE0 H00R0100 +arc: JCE1 H00R0100 +arc: JCE2 H00R0100 +arc: JCE3 H00R0100 +arc: JD5 V02N0601 +arc: N1_V01N0001 JF5 +arc: N1_V01N0101 JQ4 +arc: N1_V02N0401 JQ6 +arc: N1_V02N0501 JQ7 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 1 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C27:CIB_DSP +arc: E1_H01E0001 JF2 +arc: E1_H01E0101 JF4 +arc: E1_H02E0001 JQ0 +arc: E1_H02E0301 JQ1 +arc: E3_H06E0003 JQ3 +arc: E3_H06E0103 JQ2 +arc: E3_H06E0203 JF7 +arc: E3_H06E0303 JQ6 +arc: N1_V01N0001 JQ4 +arc: N1_V01N0101 JQ5 +arc: N1_V02N0001 JF0 +arc: N1_V02N0101 JF3 +arc: N1_V02N0301 JF1 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 JQ7 +arc: N1_V02N0601 JF6 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0501 JF5 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R22C28:CIB_DSP +arc: E1_H01E0001 JF1 +arc: E1_H01E0101 JF2 +arc: E1_H02E0301 JQ3 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: JD7 V02N0601 +arc: JLSR0 H02W0301 +arc: JLSR1 H02W0301 +arc: N1_V01N0001 JQ1 +arc: N1_V01N0101 JQ0 +arc: N1_V02N0001 JQ2 +arc: N1_V02N0201 JF0 +arc: N1_V02N0301 JF3 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 1 + +.tile CIB_R22C29:CIB_DSP +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 H01E0101 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: JLSR1 H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 W1_H02E0301 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C30:CIB_DSP +arc: E1_H02E0501 W1_H02E0401 +arc: E3_H06E0003 W1_H02E0301 +arc: H00R0100 W1_H02E0501 +arc: JCE3 H00R0100 +arc: JLSR0 H02E0301 +arc: JLSR1 H02E0301 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 H06E0003 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C31:CIB_DSP +arc: E1_H01E0001 JF7 +arc: E1_H01E0101 JF6 +arc: E1_H02E0201 JQ2 +arc: E1_H02E0301 JQ3 +arc: E1_H02E0401 JQ6 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 JQ0 +arc: E3_H06E0103 JQ1 +arc: E3_H06E0203 JQ7 +arc: E3_H06E0303 JQ5 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: JCE0 H00R0100 +arc: JD1 H00R0000 +arc: JLSR0 W1_H02E0301 +arc: JLSR1 W1_H02E0301 +arc: N1_V01N0001 JQ4 +arc: N1_V01N0101 JF5 +arc: N1_V02N0001 JF0 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 JF2 +arc: N1_V02N0301 JF3 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 JF4 +arc: N1_V02N0701 H02W0701 +arc: W1_H02W0101 JF1 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 1 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R22C32:CIB_DSP +arc: E1_H01E0001 JF7 +arc: E1_H01E0101 JF6 +arc: E1_H02E0001 JQ0 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0601 JQ6 +arc: E1_H02E0701 JQ7 +arc: E3_H06E0003 JQ3 +arc: E3_H06E0103 JQ2 +arc: E3_H06E0203 JQ4 +arc: E3_H06E0303 JQ5 +arc: JLSR1 E1_H02W0501 +arc: N1_V01N0001 JQ1 +arc: N1_V01N0101 JF3 +arc: N1_V02N0001 JF0 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 JF2 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 JF4 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 JF1 +arc: N3_V06N0303 JF5 +arc: S1_V02S0501 W3_H06E0303 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 W3_H06E0203 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 + +.tile CIB_R22C33:CIB_DSP +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0401 +arc: JD5 E1_H02W0001 +arc: JLSR0 E1_H02W0301 +arc: JLSR1 E1_H02W0301 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 1 + +.tile CIB_R22C34:CIB_DSP +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0003 W1_H02E0001 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 W3_H06E0303 +arc: W1_H02W0501 S1_V02N0501 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 + +.tile CIB_R22C35:CIB_DSP +arc: E1_H01E0001 JF4 +arc: E1_H01E0101 JF6 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 JQ6 +arc: H00R0000 S1_V02N0601 +arc: H01W0100 JQ4 +arc: JCE0 H00R0000 +arc: JCE1 H00R0000 +arc: JCE2 S1_V02N0601 +arc: JCE3 S1_V02N0601 +arc: JD7 E1_H02W0001 +arc: N1_V01N0001 JQ7 +arc: N1_V01N0101 JQ5 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0501 JF7 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0701 JF5 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 E3_H06W0003 +arc: W3_H06W0003 E3_H06W0003 +enum: CIB.JB6MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 1 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C36:CIB_DSP +arc: E1_H01E0001 JF4 +arc: E1_H01E0101 JF2 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 JQ7 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0103 N1_V01S0100 +arc: E3_H06E0303 JQ6 +arc: H01W0000 JQ2 +arc: H01W0100 JQ3 +arc: N1_V01N0001 JQ5 +arc: N1_V01N0101 JQ4 +arc: N1_V02N0001 JF0 +arc: N1_V02N0101 JF1 +arc: N1_V02N0201 JQ0 +arc: N1_V02N0301 JF3 +arc: N1_V02N0501 JF7 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: N3_V06N0303 JF6 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 JF5 +arc: V01S0100 JQ1 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R22C37:CIB_DSP +arc: E1_H01E0001 JF3 +arc: E1_H01E0101 JF2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 JQ3 +arc: E1_H02E0301 JQ3 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: JLSR0 E1_H02W0301 +arc: JLSR1 E1_H02W0301 +arc: N1_V01N0101 JQ2 +arc: N1_V02N0001 JF0 +arc: N1_V02N0101 JF1 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 JQ1 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: V01S0100 JQ0 +arc: W1_H02W0001 V02S0001 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 1 + +.tile CIB_R22C38:CIB_DSP +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: JD1 H02E0001 +arc: JLSR1 H02W0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C39:CIB_DSP +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: H00R0100 S1_V02N0501 +arc: JCE3 H00R0100 +arc: JLSR0 E1_H02W0301 +arc: JLSR1 E1_H02W0301 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 W1_H02E0701 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 S1_V02N0501 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C40:CIB_DSP +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0501 H02W0501 + +.tile CIB_R22C41:CIB_DSP +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 W1_H02E0701 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 E3_H06W0303 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R22C42:CIB_DSP +arc: E1_H01E0001 JF2 +arc: E1_H01E0101 JF6 +arc: H00R0100 H02E0501 +arc: H01W0000 JF7 +arc: JCE0 H00R0100 +arc: JD3 H02W0001 +arc: JLSR0 H02E0301 +arc: JLSR1 H02E0301 +arc: N1_V01N0101 JF5 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 JF3 +arc: N1_V02N0201 JF0 +arc: N1_V02N0301 JF1 +arc: N1_V02N0401 JF4 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 W1_H02E0701 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 1 + +.tile CIB_R22C43:CIB_DSP +arc: E1_H01E0001 JF1 +arc: E1_H01E0101 JF7 +arc: H01W0000 JF6 +arc: JLSR1 V00T0100 +arc: N1_V01N0101 JF3 +arc: N1_V02N0001 JF2 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 JF0 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0701 JF5 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 JF4 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R22C44:CIB_DSP +arc: E1_H02E0101 N1_V01S0100 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C45:CIB_DSP +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 N1_V02S0001 + +.tile CIB_R22C47:CIB_DSP +arc: E3_H06E0003 W3_H06E0003 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile CIB_R22C50:CIB_DSP +arc: V01S0000 S3_V06N0103 + +.tile CIB_R22C51:CIB_DSP +arc: E1_H01E0101 JQ5 +arc: E1_H02E0501 JQ7 +arc: E3_H06E0003 JQ0 +arc: E3_H06E0103 JQ1 +arc: E3_H06E0203 JQ4 +arc: N1_V01N0101 JQ3 +arc: S1_V02S0001 JQ2 +arc: S1_V02S0401 JQ6 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R22C52:CIB_DSP +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 JQ7 +arc: E1_H02E0601 JQ6 +arc: E3_H06E0003 JQ3 +arc: E3_H06E0103 JQ2 +arc: E3_H06E0303 JQ5 +arc: S1_V02S0101 JQ1 +arc: S1_V02S0201 JQ0 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 JQ4 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 + +.tile CIB_R22C53:CIB_DSP +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: JLSR0 H02E0301 +arc: JLSR1 H02E0301 +arc: S1_V02S0301 W3_H06E0003 +arc: W3_H06W0303 E3_H06W0203 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 1 + +.tile CIB_R22C54:CIB_DSP +arc: E1_H02E0701 W1_H02E0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06E0203 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 + +.tile CIB_R22C55:CIB_DSP +arc: E1_H01E0001 JQ6 +arc: E1_H01E0101 JQ4 +arc: E1_H02E0501 JQ7 +arc: E3_H06E0303 JQ5 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 JF7 +arc: H01W0100 JF6 +arc: JCE0 H00R0100 +arc: JCE1 H00R0100 +arc: JCE2 H00R0100 +arc: JCE3 H00R0100 +arc: N1_V01N0101 JF5 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V01S0100 JF4 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 1 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C56:CIB_DSP +arc: E1_H01E0001 JQ5 +arc: E1_H01E0101 JF6 +arc: E1_H02E0101 JQ3 +arc: E1_H02E0201 JQ2 +arc: E1_H02E0301 JQ1 +arc: E1_H02E0401 JQ4 +arc: E1_H02E0701 JQ7 +arc: E3_H06E0003 JQ0 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0203 H01E0001 +arc: E3_H06E0303 JQ6 +arc: H01W0000 JF4 +arc: H01W0100 JF2 +arc: N1_V02N0701 JF7 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 JF3 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 JF5 +arc: S1_V02S0701 W1_H02E0701 +arc: V01S0100 JF0 +arc: W1_H02W0301 JF1 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R22C57:CIB_DSP +arc: E1_H01E0001 JQ2 +arc: E1_H02E0101 JQ3 +arc: E1_H02E0301 JQ1 +arc: E3_H06E0003 JQ0 +arc: E3_H06E0203 H01E0001 +arc: H01W0000 JF2 +arc: H01W0100 JF3 +arc: JLSR0 E1_H02W0301 +arc: JLSR1 E1_H02W0301 +arc: S1_V02S0101 JF1 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: V01S0100 JF0 +arc: W1_H02W0701 H01E0101 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 1 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C58:CIB_DSP +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0203 H01E0001 +arc: JLSR1 V00T0000 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 S1_V02N0401 +arc: W3_H06W0003 E1_H01W0000 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R22C59:CIB_DSP +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0000 H02E0401 +arc: H01W0000 W3_H06E0103 +arc: JCE3 H00R0000 +arc: JLSR0 V00B0000 +arc: JLSR1 V00B0000 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 H02E0601 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0203 E3_H06W0103 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C60:CIB_DSP +arc: E1_H01E0001 JF0 +arc: E1_H01E0101 JF1 +arc: H00R0000 W1_H02E0401 +arc: H01W0000 JF4 +arc: H01W0100 JF2 +arc: JCE0 H00R0000 +arc: JLSR0 H02E0301 +arc: JLSR1 H02E0301 +arc: N1_V01N0101 JF7 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 JF6 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06E0203 +arc: V01S0100 JF5 +arc: W1_H02W0101 JF3 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 1 + +.tile CIB_R22C61:CIB_DSP +arc: E1_H01E0101 JF4 +arc: H01W0000 JF0 +arc: H01W0100 JF2 +arc: JLSR1 V00T0100 +arc: N1_V01N0101 JF3 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 JF1 +arc: S1_V02S0401 JF6 +arc: S1_V02S0501 JF7 +arc: S1_V02S0701 H06E0203 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 JF5 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 H01E0101 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R22C62:CIB_DSP +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 H01E0101 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C63:CIB_DSP +arc: E1_H02E0101 E1_H01W0100 +arc: S1_V02S0101 E1_H02W0101 + +.tile CIB_R22C64:CIB_DSP +arc: E1_H01E0101 JQ6 +arc: E1_H02E0501 JQ7 +arc: H01W0100 JQ4 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 JQ5 + +.tile CIB_R22C65:CIB_DSP +arc: E1_H01E0001 JQ2 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 JQ4 +arc: E1_H02E0501 JQ5 +arc: E1_H02E0701 JQ7 +arc: E3_H06E0103 W3_H06E0003 +arc: H01W0100 JQ3 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 JQ1 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H01E0101 +arc: V01S0000 JQ0 +arc: V01S0100 JQ6 +arc: W1_H02W0101 W3_H06E0103 +arc: W3_H06W0103 E3_H06W0003 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 + +.tile CIB_R22C66:CIB_DSP +arc: E1_H01E0101 JQ2 +arc: E1_H02E0101 JQ3 +arc: N1_V01N0101 JQ1 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H02E0701 +arc: V01S0000 JQ0 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 1 + +.tile CIB_R22C67:CIB_DSP +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0701 S1_V02N0701 +arc: JLSR1 V00T0100 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 E1_H02W0701 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C68:CIB_DSP +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0100 H02E0701 +arc: JCE3 H00R0100 +arc: JLSR0 H02E0301 +arc: JLSR1 H02E0301 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 E1_H02W0701 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C69:CIB_DSP +arc: E1_H01E0001 JF0 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0501 JQ7 +arc: H00R0100 W1_H02E0701 +arc: H01W0000 JF4 +arc: H01W0100 JF3 +arc: JCE0 H00R0100 +arc: JLSR0 V00B0100 +arc: JLSR1 V00B0100 +arc: N1_V01N0001 JF7 +arc: N1_V01N0101 JQ2 +arc: N1_V02N0001 JF2 +arc: N1_V02N0301 JF1 +arc: S1_V02S0001 JQ0 +arc: S1_V02S0101 JQ3 +arc: S1_V02S0301 JQ1 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0303 JQ6 +arc: V00B0100 V02N0101 +arc: V01S0000 JQ4 +arc: V01S0100 JQ5 +arc: W1_H02W0701 JF5 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 JF6 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA2MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JA0MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 1 + +.tile CIB_R22C70:CIB_DSP +arc: E1_H01E0001 JQ7 +arc: E1_H01E0101 JQ6 +arc: H01W0000 JF0 +arc: H01W0100 JF4 +arc: JLSR1 V00T0000 +arc: N1_V01N0001 JQ1 +arc: N1_V01N0101 JQ2 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0001 JQ0 +arc: S1_V02S0101 JQ3 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 JQ4 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 S1_V02N0401 +arc: V01S0000 JQ5 +arc: V01S0100 JF3 +arc: W1_H02W0301 JF1 +arc: W1_H02W0701 JF5 +arc: W3_H06W0103 JF2 +arc: W3_H06W0203 JF7 +arc: W3_H06W0303 JF6 +enum: CIB.JC1MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R22C71:CIB_DSP +arc: E1_H02E0201 W3_H06E0103 +arc: JLSR0 W1_H02E0301 +arc: JLSR1 W1_H02E0301 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H01E0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W3_H06W0003 E3_H06W0003 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 1 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C72:CIB_DSP +arc: S1_V02S0301 E1_H02W0301 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 + +.tile CIB_R22C73:CIB_DSP +arc: E1_H02E0301 W1_H02E0201 +arc: H00R0000 S1_V02N0601 +arc: H01W0000 JF7 +arc: H01W0100 JF6 +arc: JCE0 H00R0000 +arc: JCE1 H00R0000 +arc: JCE2 S1_V02N0601 +arc: JCE3 S1_V02N0601 +arc: S1_V02S0701 JF5 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 JF4 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C74:CIB_DSP +arc: H01W0000 JF7 +arc: H01W0100 JF1 +arc: N1_V02N0001 JF0 +arc: S1_V02S0001 JF2 +arc: S1_V02S0401 JF4 +arc: S1_V02S0701 JF5 +arc: W1_H02W0301 JF3 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 JF6 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB6MUX 1 +enum: CIB.JD7MUX 1 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R22C75:CIB_DSP +arc: H01W0000 JF0 +arc: H01W0100 JF3 +arc: JLSR0 W1_H02E0301 +arc: JLSR1 W1_H02E0301 +arc: N1_V02N0101 JF1 +arc: W1_H02W0201 JF2 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JA1MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JB4MUX 1 +enum: CIB.JD5MUX 1 +enum: CIB.JB2MUX 1 +enum: CIB.JD3MUX 1 +enum: CIB.JB0MUX 1 +enum: CIB.JD1MUX 1 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R22C76:CIB_DSP +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R22C77:CIB_DSP +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R22C83:CIB_DSP +arc: W3_H06W0003 E3_H06W0303 + +.tile CIB_R22C89:CIB_LR_S +arc: W3_H06W0303 JQ5 + +.tile CIB_R23C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: JA0 E1_H02W0701 +arc: S1_V02S0501 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R23C89:CIB_LR +arc: JA3 W1_H02E0701 +enum: CIB.JB3MUX 0 + +.tile CIB_R25C1:CIB_LR +arc: JA0 N1_V02S0501 +arc: JA3 N1_V02S0701 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R25C89:CIB_LR +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0701 W3_H06E0203 + +.tile CIB_R26C89:CIB_LR +arc: H00L0100 V02S0101 +arc: JA0 V02S0701 +arc: JA3 H00L0100 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0701 W3_H06E0203 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R28C89:CIB_LR +arc: H00L0100 N1_V02S0301 +arc: JA0 H00L0100 +arc: JA3 N1_V02S0701 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R29C1:CIB_LR +arc: JA0 E1_H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R29C89:CIB_LR +arc: JA0 W1_H02E0501 +arc: JA3 H01E0001 +arc: S1_V02S0501 H06E0303 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R31C1:CIB_LR +arc: JA0 E1_H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R31C89:CIB_LR +arc: JA0 N1_V02S0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R5C1:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C89:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C15:CIB +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C18:CIB +arc: JA0 H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C19:CIB +arc: W1_H02W0701 V06S0203 + +.tile CIB_R70C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C69:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C70:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C71:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C72:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C73:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C74:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C75:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C76:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C77:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C78:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C79:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R70C80:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C87:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile MIB_R0C36:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C37:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C38:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C39:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C3:BANKREF0 +enum: BANK.VCCIO 3V3 + +.tile MIB_R0C40:TMID_0 +arc: G_TDCC0CLKI G_JTRQPCLKCIB1 + +.tile MIB_R0C42:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C43:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C44:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C45:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C47:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C54:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C66:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C69:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C70:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C72:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C87:BANKREF1 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C30:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C40:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R10C41:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R10C50:EBR_SPINE_UR0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C77:EBR_SPINE_UR1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C90:BANKREF2 +enum: BANK.VCCIO 3V3 + +.tile MIB_R12C0:PICL1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON + +.tile MIB_R13C0:PICL2 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C36:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C37:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C38:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C39:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C42:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C43:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C44:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C45:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C47:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C54:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C66:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C69:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C70:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C72:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R20C0:PICL0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R20C90:PICR0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R21C0:PICL1 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R21C90:PICR1 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON + +.tile MIB_R22C0:MIB_CIB_LR +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R22C90:MIB_CIB_LR_A +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R23C0:PICL0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R23C90:PICR0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R24C0:PICL1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R24C90:PICR1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R25C0:PICL2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R26C90:PICR0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R27C90:PICR1_DQS0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R28C90:PICR2_DQS1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R29C0:PICL0_DQS2 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R29C90:PICR0_DQS2 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R30C0:PICL1_DQS3 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R30C90:PICR1_DQS3 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R31C0:PICL2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R31C90:PICR2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R58C40:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R58C41:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R71C15:PICB0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C18:SPICB0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C3:BANKREF8 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile R11C38:PLC2 +arc: N1_V02N0401 S3_V06N0203 + +.tile R11C41:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R11C43:PLC2 +arc: N3_V06N0003 S3_V06N0003 + +.tile R11C47:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R12C39:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R12C53:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R12C65:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R12C69:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R13C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R13C19:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R13C25:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R13C31:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R13C37:PLC2 +arc: N3_V06N0303 W3_H06E0303 + +.tile R13C38:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R13C44:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R13C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R15C41:PLC2 +arc: N3_V06N0203 S3_V06N0203 + +.tile R15C69:PLC2 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile R16C32:PLC2 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 S3_V06N0303 + +.tile R17C34:PLC2 +arc: S1_V02S0301 S3_V06N0003 + +.tile R17C37:PLC2 +arc: E3_H06E0003 S3_V06N0003 + +.tile R17C38:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R17C41:PLC2 +arc: N3_V06N0103 S3_V06N0103 + +.tile R17C43:PLC2 +arc: N3_V06N0003 W3_H06E0003 + +.tile R17C47:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R18C31:PLC2 +arc: E3_H06E0003 V01N0001 + +.tile R18C32:PLC2 +arc: E1_H02E0701 V01N0101 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0501 N1_V02S0501 + +.tile R18C34:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00R0000 V02N0601 +arc: S1_V02S0301 H06E0003 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: A2 W1_H02E0701 +arc: B0 V02N0301 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICED.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C35:PLC2 +arc: H00R0000 V02N0601 +arc: S1_V02S0101 H02E0101 +arc: V00T0000 V02N0401 +arc: A0 V01N0101 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B5 V02N0501 +arc: B6 V00T0000 +arc: B7 V02N0701 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 1001100110011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C36:PLC2 +arc: H00R0000 V02N0401 +arc: V00T0000 V02N0601 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: A6 H00R0000 +arc: B0 V01N0001 +arc: B1 V02N0101 +arc: B3 V02N0301 +arc: B5 V02N0701 +arc: B7 V02N0501 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0011001100111100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C37:PLC2 +arc: H00R0000 V02N0401 +arc: V00T0000 V02N0601 +arc: A0 V01N0101 +arc: B1 V02N0101 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0101010101011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C38:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: F0 F0_SLICE +arc: S3_V06S0003 F0 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C39:PLC2 +arc: H00R0000 V02N0401 +arc: N3_V06N0203 S3_V06N0103 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 V02N0601 +arc: A0 H02W0501 +arc: A2 V00B0000 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICED.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C40:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: H00R0000 V02N0401 +arc: S1_V02S0201 W1_H02E0201 +arc: V00T0000 V02N0601 +arc: W1_H02W0501 S3_V06N0303 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: A6 H00R0000 +arc: B0 V01N0001 +arc: B1 V02N0301 +arc: B3 V02N0101 +arc: B5 V02N0501 +arc: B7 V02N0701 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 1001100110011100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C41:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02N0601 +arc: S1_V02S0201 H02E0201 +arc: V00T0000 V02N0401 +arc: A2 V01N0101 +arc: A4 V00T0000 +arc: A6 H00R0000 +arc: B0 V01N0001 +arc: B1 V02N0101 +arc: B3 V02N0301 +arc: B5 V02N0501 +arc: B7 V02N0701 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0011001100111100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C42:PLC2 +arc: H00R0000 V02N0401 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 H02E0601 +arc: V00T0000 V02N0601 +arc: A0 V01N0101 +arc: B1 V02N0301 +arc: B2 V01N0001 +arc: B3 V02N0101 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: B7 V02N0501 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0101010101011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C43:PLC2 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R18C44:PLC2 +arc: S1_V02S0201 H01E0001 + +.tile R18C53:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R18C65:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R18C69:PLC2 +arc: N3_V06N0103 S3_V06N0003 + +.tile R19C13:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R19C19:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R19C25:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R19C31:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V01N0101 +arc: H00R0000 S1_V02N0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0401 +arc: W3_H06W0203 E3_H06W0103 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A7 S1_V02N0101 +arc: B0 E1_H02W0101 +arc: B3 V02N0301 +arc: B6 E1_H02W0301 +arc: C0 V02N0401 +arc: C3 E1_H02W0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0201 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: D0 H00R0000 +arc: D3 V00B0100 +arc: D4 S1_V02N0601 +arc: D5 S1_V02N0601 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: V01S0000 F7 +arc: V01S0100 F0 +word: SLICED.K0.INIT 1111110011000000 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICEA.K0.INIT 1100001100111100 +word: SLICED.K1.INIT 1010010101011010 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEC.K1.INIT 1010010101011010 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R19C32:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: H00R0000 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 S1_V02N0501 +arc: A2 V01N0101 +arc: B0 V00T0000 +arc: B2 E1_H02W0101 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: C5 V00T0000 +arc: C6 V02N0201 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 V02N0201 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: E1_H01E0001 F0 +arc: E1_H02E0201 F2 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1001100101100110 +word: SLICEB.K0.INIT 1110111010001000 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICED.K0.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C33:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0203 V01N0001 +arc: H00L0100 E1_H02W0101 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 E1_H01W0000 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: A6 H02W0501 +arc: A7 H02W0701 +arc: B0 S1_V02N0301 +arc: B1 H02E0101 +arc: B3 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B6 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C2 V02N0401 +arc: C4 V00T0100 +arc: D0 V02N0001 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 S1_V02N0201 +arc: D4 V02N0601 +arc: D5 S1_V02N0401 +arc: D6 H02E0001 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F1 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +word: SLICEB.K1.INIT 1001100101100110 +word: SLICEB.K0.INIT 1010010101011010 +word: SLICEC.K1.INIT 1110111010001000 +word: SLICED.K0.INIT 1110111010001000 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICEA.K0.INIT 1111110011000000 +word: SLICED.K1.INIT 1110111010001000 +word: SLICEA.K1.INIT 1001100101100110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R19C34:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 H02E0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0301 N1_V01S0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S1_V02N0301 +arc: A3 W1_H02E0501 +arc: A4 V00B0000 +arc: A5 V02S0301 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 H02W0301 +arc: B2 H00L0000 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B5 W1_H02E0301 +arc: B6 H01E0101 +arc: B7 H02E0101 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: LSR0 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F5 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +arc: W1_H02W0501 Q7 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C35:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: H00R0000 W1_H02E0401 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0301 S3_V06N0003 +arc: A0 H00R0000 +arc: A1 V02N0501 +arc: A2 V00T0000 +arc: A3 S1_V02N0501 +arc: A4 S1_V02N0301 +arc: A5 H02E0501 +arc: A6 V02N0301 +arc: A7 V02N0101 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B2 H00L0000 +arc: B3 S1_V02N0101 +arc: B4 V02N0701 +arc: B5 S1_V02N0701 +arc: B6 H02E0301 +arc: B7 W1_H02E0301 +arc: CE0 E1_H02W0101 +arc: CE1 E1_H02W0101 +arc: CE2 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q5 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F7 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 Q4 +arc: S3_V06S0003 F0 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 Q7 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C36:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V06N0303 +arc: H00L0000 H02E0001 +arc: H00R0000 S1_V02N0401 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0201 +arc: A0 H02E0501 +arc: A1 H00L0000 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 W1_H02E0701 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 S1_V02N0301 +arc: B0 V02N0301 +arc: B1 W1_H02E0101 +arc: B2 V02N0101 +arc: B3 V01N0001 +arc: B4 V02N0701 +arc: B5 S1_V02N0701 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: CE0 H02W0101 +arc: CE1 H02W0101 +arc: CE2 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F5 +arc: S1_V02S0101 Q3 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 Q6 +arc: V01S0000 Q1 +arc: V01S0100 Q7 +arc: W1_H02W0301 Q1 +arc: W3_H06W0203 Q4 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C37:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0000 V02N0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0401 +arc: S1_V02S0501 H02E0501 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 E1_H02W0701 +arc: A1 V02N0501 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 H00L0000 +arc: A7 H02W0501 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 H02E0301 +arc: B3 W1_H02E0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 Q6 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q7 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C38:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V02N0501 +arc: A0 F7 +arc: A1 F5 +arc: A4 H02E0501 +arc: A5 V00T0100 +arc: B0 V00B0000 +arc: B1 H01W0100 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0001 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S3_V06S0103 F1 +arc: V00B0000 F4 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICED.K0.INIT 1111110011000000 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEC.K1.INIT 1010010101011010 +word: SLICED.K1.INIT 1100001100111100 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C39:PLC2 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 H02E0201 +arc: H00R0000 V02N0401 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: A2 V00B0000 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: A5 V00T0000 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0301 +arc: B0 H02W0101 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B5 V00B0100 +arc: B6 S1_V02N0701 +arc: B7 S1_V02N0501 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0501 F5 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F5 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 Q4 +arc: S1_V02S0701 Q7 +arc: V01S0000 F7 +arc: V01S0100 Q6 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C40:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: H00L0000 V02N0001 +arc: H00R0000 S1_V02N0401 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V06N0103 +arc: A0 W1_H02E0501 +arc: A1 V01N0101 +arc: A2 H02E0701 +arc: A3 V02N0701 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A6 H00R0000 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B1 V02N0101 +arc: B2 H00L0000 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0501 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 E1_H02W0301 +arc: CE0 V02S0201 +arc: CE1 V02S0201 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q2 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0401 Q4 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q3 +arc: V01S0100 Q7 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C41:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 V02N0201 +arc: H00R0000 E1_H02W0401 +arc: V00B0000 V02N0001 +arc: V00T0000 E1_H02W0201 +arc: A0 H02W0501 +arc: A1 S1_V02N0501 +arc: A2 V01N0101 +arc: A3 H02W0701 +arc: A4 E1_H02W0701 +arc: A5 V02N0301 +arc: A6 S1_V02N0101 +arc: A7 S1_V02N0301 +arc: B0 V01N0001 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B3 V02N0101 +arc: B4 H00L0000 +arc: B5 V02N0501 +arc: B6 V00B0000 +arc: B7 V02N0701 +arc: CE0 V02S0201 +arc: CE1 V02S0201 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F5 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 Q6 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C42:PLC2 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: V00B0000 V02N0201 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V01N0101 +arc: A0 V02N0501 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 E1_H02W0701 +arc: A5 V02N0101 +arc: A6 V00T0100 +arc: A7 E1_H01W0000 +arc: B0 H00R0100 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0301 +arc: B3 V01N0001 +arc: B4 H00L0000 +arc: B5 H02W0101 +arc: B6 V02N0701 +arc: B7 V00B0100 +arc: CE0 V02S0201 +arc: CE1 V02S0201 +arc: CE2 V02S0601 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q4 +arc: E1_H02E0401 Q6 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F5 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q5 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C43:PLC2 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H02E0601 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 H02W0501 +arc: A1 F7 +arc: A4 H02E0701 +arc: B0 V00B0000 +arc: B1 E1_H01W0100 +arc: B5 H02W0101 +arc: B6 H02W0101 +arc: B7 V01S0000 +arc: C4 S1_V02N0001 +arc: C5 H01E0001 +arc: C6 H02E0401 +arc: C7 S1_V02N0001 +arc: CE0 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D4 H02W0201 +arc: D5 S1_V02N0601 +arc: D6 S1_V02N0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00B0000 F4 +arc: V01S0000 Q1 +arc: W1_H02W0501 F5 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICED.K0.INIT 1111110011000000 +word: SLICEC.K1.INIT 1100001100111100 +word: SLICED.K1.INIT 1100001100111100 +word: SLICEC.K0.INIT 1111101010100000 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R19C44:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 H02E0001 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 V02N0701 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: B0 E1_H02W0301 +arc: B2 F3 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: CE0 V02N0201 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 H01E0101 +arc: D3 V02S0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F4 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N3_V06N0003 Q0 +arc: V00T0100 F3 +arc: V01S0000 F3 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 Q1 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEC.K1.INIT 1010010101011010 +word: SLICEA.K1.INIT 0101000001010101 +word: SLICEA.K0.INIT 0100010001010101 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEB.K0.INIT 0000000011110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R19C45:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: H00R0000 V02N0401 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 W3_H06E0303 +arc: A1 E1_H01E0001 +arc: B0 V02N0301 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0000110000001111 +word: SLICEA.K1.INIT 0000101000001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R19C46:PLC2 +arc: W1_H02W0301 W3_H06E0003 + +.tile R19C51:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R19C57:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R19C63:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R19C69:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R19C75:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R19C7:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R19C81:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R19C87:PLC2 +arc: S1_V02S0501 W3_H06E0303 + +.tile R20C11:PLC2 +arc: W3_H06W0103 E1_H01W0100 + +.tile R20C12:PLC2 +arc: H01W0100 E3_H06W0303 + +.tile R20C13:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R20C14:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R20C18:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R20C19:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R20C20:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R20C22:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 + +.tile R20C23:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 + +.tile R20C24:PLC2 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0103 W1_H02E0201 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0501 +arc: V00B0100 S1_V02N0301 +arc: CE2 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: LSR1 H02W0501 +arc: M4 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: W3_H06W0203 Q4 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C25:PLC2 +arc: E3_H06E0103 W1_H02E0101 +arc: E3_H06E0203 W1_H02E0701 +arc: E3_H06E0303 W1_H02E0601 +arc: W1_H02W0501 V06N0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R20C26:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 + +.tile R20C27:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H01W0100 E3_H06W0303 + +.tile R20C28:PLC2 +arc: E3_H06E0203 W1_H02E0401 +arc: E3_H06E0303 W1_H02E0501 + +.tile R20C29:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E3_H06E0303 W1_H02E0501 + +.tile R20C30:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 + +.tile R20C31:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 S1_V02N0601 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02E0101 +arc: W3_H06W0003 E3_H06W0303 +arc: A2 V00B0000 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: A5 S1_V02N0301 +arc: A6 H00R0000 +arc: A7 H02E0501 +arc: B0 E1_H02W0101 +arc: B2 S1_V02N0101 +arc: B3 W1_H02E0101 +arc: B4 H00L0000 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: B7 V02N0701 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F5 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: V01S0000 F6 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R20C32:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0401 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A2 V00B0000 +arc: A3 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 S1_V02N0301 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B2 S1_V02N0101 +arc: B3 N1_V02S0101 +arc: B4 H00L0000 +arc: B5 H02E0101 +arc: B6 S1_V02N0501 +arc: B7 N1_V02S0501 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: V01S0000 F3 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R20C33:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 E1_H02W0001 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: B0 S1_V02N0101 +arc: B1 V00B0000 +arc: B2 H00L0000 +arc: B6 H02W0301 +arc: B7 V02S0701 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D6 F2 +arc: D7 F2 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F0 +arc: E1_H02E0201 F2 +arc: E1_H02E0301 F1 +arc: E1_H02E0701 F7 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: S1_V02S0201 F2 +arc: V01S0000 F2 +arc: V01S0100 F2 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICED.K0.INIT 1111110011000000 +word: SLICED.K1.INIT 1100001100111100 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R20C34:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 S1_V02N0501 +arc: A3 H02W0501 +arc: A4 W1_H02E0701 +arc: A7 H02W0501 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B5 W1_H02E0101 +arc: B6 H02E0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 E1_H02W0601 +arc: C7 V02N0001 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D3 V02N0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 V02N0401 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F2 +arc: S1_V02S0501 F5 +word: SLICEA.K0.INIT 1111110011000000 +word: SLICEA.K1.INIT 1100001100111100 +word: SLICEB.K0.INIT 1111110011000000 +word: SLICED.K0.INIT 1100001100111100 +word: SLICED.K1.INIT 1111101010100000 +word: SLICEB.K1.INIT 1010010101011010 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICEC.K0.INIT 1010010101011010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R20C35:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: H00L0000 V02S0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H02E0501 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 V02S0501 +arc: A2 V00T0000 +arc: A3 W1_H02E0501 +arc: A4 V00B0000 +arc: B1 E1_H02W0101 +arc: B5 H00L0000 +arc: B6 V02S0501 +arc: B7 N1_V01S0000 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 V02N0401 +arc: C3 V02S0601 +arc: C4 W1_H02E0401 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 H02E0401 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 H00R0000 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0201 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 F3 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0701 F7 +arc: V01S0100 F2 +word: SLICEA.K1.INIT 1100001100111100 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEA.K0.INIT 1111101010100000 +word: SLICED.K0.INIT 1100001100111100 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICEB.K1.INIT 1010010101011010 +word: SLICEB.K0.INIT 1111101010100000 +word: SLICED.K1.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R20C36:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V01N0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H02E0301 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 V02S0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A7 H00R0000 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: B2 V02S0101 +arc: B6 V00B0000 +arc: C0 V02S0401 +arc: C3 V02S0601 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 W1_H02E0201 +arc: D5 H02E0201 +arc: D6 W1_H02E0201 +arc: D7 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F0 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F5 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100001100111100 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEA.K1.INIT 1001100101100110 +word: SLICED.K0.INIT 1100001100111100 +word: SLICEB.K1.INIT 1111101010100000 +word: SLICED.K1.INIT 1010010101011010 +word: SLICEC.K1.INIT 1111101010100000 +word: SLICEB.K0.INIT 1001100101100110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R20C37:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V01S0100 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 H00R0000 +arc: A7 H00R0000 +arc: B1 V00T0000 +arc: B2 E1_H02W0101 +arc: B3 V02S0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0101 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02S0601 +arc: C3 V02N0601 +arc: C4 V00T0100 +arc: C5 V02N0201 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 H02E0201 +arc: D3 E1_H02W0201 +arc: D4 H02E0201 +arc: D5 E1_H02W0201 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0001 F0 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F7 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1111101010100000 +word: SLICED.K0.INIT 1111110011000000 +word: SLICEC.K1.INIT 1100001100111100 +word: SLICEA.K0.INIT 1010010101011010 +word: SLICEA.K1.INIT 1111110011000000 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICEB.K0.INIT 1100001100111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R20C38:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: B4 V02S0701 +arc: C4 W1_H02E0401 +arc: D4 V02N0401 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +word: SLICEC.K0.INIT 1100001100111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R20C39:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E3_H06E0203 N1_V01S0000 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0501 H06E0303 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00L0000 +arc: A2 H02W0701 +arc: A4 V02S0301 +arc: A6 V02S0301 +arc: A7 V02S0101 +arc: B1 V00T0000 +arc: B2 W1_H02E0101 +arc: B3 V02S0101 +arc: B5 H00L0000 +arc: C0 H02W0401 +arc: C1 E1_H02W0401 +arc: C3 W1_H02E0401 +arc: C4 S1_V02N0001 +arc: C5 V02N0201 +arc: C6 S1_V02N0201 +arc: C7 W1_H02E0401 +arc: CE0 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 H02E0001 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F7 +word: SLICEB.K0.INIT 1110111010001000 +word: SLICEA.K1.INIT 1111110011000000 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICED.K0.INIT 1010010101011010 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICED.K1.INIT 1010010101011010 +word: SLICEA.K0.INIT 1010010101011010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C40:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H01E0101 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: A1 V02S0701 +arc: A3 V00B0000 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: B0 V02S0101 +arc: B2 V02S0301 +arc: B3 H02E0101 +arc: B4 W1_H02E0101 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 E1_H02W0401 +arc: C1 H02E0401 +arc: C2 W1_H02E0601 +arc: C4 E1_H02W0401 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: C7 V00T0000 +arc: D0 V00T0100 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 V02N0201 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0001 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: V01S0100 F2 +word: SLICEB.K1.INIT 1110111010001000 +word: SLICEC.K0.INIT 1001011010010110 +word: SLICEC.K1.INIT 1010010101011010 +word: SLICED.K1.INIT 1111110011000000 +word: SLICEA.K0.INIT 1111110011000000 +word: SLICEB.K0.INIT 1100001100111100 +word: SLICED.K0.INIT 1100001100111100 +word: SLICEA.K1.INIT 1010010101011010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R20C41:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H06W0303 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0401 V02N0401 +arc: A2 V02N0701 +arc: A7 H00R0000 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 V02S0101 +arc: B4 N1_V01S0000 +arc: B5 H02E0101 +arc: B6 E1_H02W0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C6 V01N0101 +arc: C7 V02N0201 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F0 +arc: N1_V02N0301 F1 +arc: N1_V02N0701 F7 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 1001100101100110 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICED.K1.INIT 1111101010100000 +word: SLICEA.K1.INIT 1111110011000000 +word: SLICED.K0.INIT 1111110011000000 +word: SLICEA.K0.INIT 1100001100111100 +word: SLICEB.K1.INIT 1100001100111100 +word: SLICEC.K0.INIT 1100001100111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R20C42:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 V02S0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0301 +arc: A2 H02E0501 +arc: A4 V00B0000 +arc: A5 V02S0101 +arc: A7 H02E0501 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B3 H02E0101 +arc: B6 H02E0301 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 V02N0201 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F6 +arc: N1_V02N0001 F0 +arc: N1_V02N0601 F4 +arc: V01S0100 F1 +arc: W1_H02W0501 F7 +word: SLICEA.K0.INIT 1111110011000000 +word: SLICEB.K0.INIT 1111101010100000 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEC.K1.INIT 1010010101011010 +word: SLICEA.K1.INIT 1100001100111100 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICED.K1.INIT 1010010101011010 +word: SLICED.K0.INIT 1111110011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R20C43:PLC2 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0701 H01E0101 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: B2 V02S0101 +arc: B3 V02N0101 +arc: B6 H02E0101 +arc: B7 V00T0000 +arc: C0 H02E0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: D0 V02N0001 +arc: D1 W1_H02E0201 +arc: D2 H02W0201 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02W0201 +arc: D7 W1_H02E0201 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F0 +arc: N1_V02N0101 F3 +arc: W1_H02W0101 F1 +arc: W1_H02W0701 F7 +word: SLICEC.K1.INIT 1111101010100000 +word: SLICEA.K0.INIT 1111101010100000 +word: SLICED.K1.INIT 1100001100111100 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICEA.K1.INIT 1010010101011010 +word: SLICEB.K0.INIT 1100001100111100 +word: SLICED.K0.INIT 1111110011000000 +word: SLICEC.K0.INIT 1010010101011010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R20C44:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 V02S0501 +arc: A1 H02W0701 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K1.INIT 0000101000001111 +word: SLICEA.K0.INIT 0000101000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C45:PLC2 +arc: N1_V02N0301 W3_H06E0003 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 S1_V02N0601 +arc: C1 V02N0601 +arc: C6 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D6 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0401 F6 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F1 +arc: V00T0000 Q0 +arc: V01S0000 F1 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 F6 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 0000110000001100 +word: SLICED.K0.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111111100110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R20C4:PLC2 +arc: W3_H06W0203 E1_H01W0000 + +.tile R20C5:PLC2 +arc: H01W0000 E3_H06W0103 + +.tile R20C7:PLC2 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E1_H01W0100 + +.tile R20C87:PLC2 +arc: E1_H02E0501 V02S0501 + +.tile R20C8:PLC2 +arc: H01W0100 E3_H06W0303 + +.tile R21C23:PLC2 +arc: E3_H06E0303 V01N0101 + +.tile R21C26:PLC2 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 V01N0101 + +.tile R21C27:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0103 V01N0101 + +.tile R21C28:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0203 V01N0001 +arc: E3_H06E0303 V01N0101 + +.tile R21C29:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0003 W3_H06E0303 + +.tile R21C30:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0701 + +.tile R21C31:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V01N0001 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0701 V01N0101 +arc: A2 V02N0701 +arc: A3 S1_V02N0501 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0501 +arc: A6 H00L0000 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B2 H02W0101 +arc: B3 H02W0301 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0301 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F6 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C32:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V01N0001 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H01E0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 W1_H02E0501 +arc: A1 H02E0501 +arc: A2 W1_H02E0701 +arc: A3 S1_V02N0501 +arc: A4 H02E0701 +arc: A5 H02W0701 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0701 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0301 +arc: B2 H02W0301 +arc: B3 H02W0101 +arc: B4 H00R0000 +arc: B5 V02S0501 +arc: B6 V00T0000 +arc: B7 H02E0301 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F0 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F6 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F2 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C33:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0501 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B6 V02S0501 +arc: B7 N1_V02S0701 +arc: C6 V02S0201 +arc: C7 V02S0201 +arc: D6 F2 +arc: D7 F2 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F0 +arc: N1_V02N0001 F2 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICED.K0.INIT 1100001100111100 +word: SLICED.K1.INIT 1111110011000000 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R21C34:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V02S0501 +arc: E3_H06E0303 H01E0101 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H01E0101 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: B0 W1_H02E0301 +arc: B3 H02W0301 +arc: C0 H00L0100 +arc: C3 W1_H02E0401 +arc: D0 W1_H02E0201 +arc: D3 V00T0100 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 1100001100111100 +word: SLICEA.K0.INIT 1111110011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R21C35:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02N0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 E1_H02W0001 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0301 N1_V02S0301 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0301 +arc: B6 V00T0000 +arc: C6 W1_H02E0401 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: E1_H02E0401 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +word: SLICED.K0.INIT 1111110011000000 +word: SLICEB.K1.INIT 1110111010001000 +word: SLICEB.K0.INIT 1001100101100110 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 + +.tile R21C36:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0601 +arc: W1_H02W0501 N1_V02S0501 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0501 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 S1_V02N0101 +arc: B2 W1_H02E0301 +arc: B3 H02E0301 +arc: B4 V02N0701 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: B7 S1_V02N0501 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F5 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: V01S0000 F3 +arc: V01S0100 F3 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C37:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 H01E0101 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 N1_V02S0201 +arc: A0 V02N0501 +arc: A1 W1_H02E0701 +arc: A2 V00B0000 +arc: A3 S1_V02N0501 +arc: A4 E1_H02W0501 +arc: A5 H02E0501 +arc: A6 H00L0000 +arc: A7 V02N0101 +arc: B0 V00T0000 +arc: B1 H02E0301 +arc: B2 H02E0101 +arc: B3 H00R0000 +arc: B4 N1_V02S0501 +arc: B5 V02N0701 +arc: B6 S1_V02N0701 +arc: B7 V00B0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F7 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F0 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C38:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0000 V02N0001 +arc: W1_H02W0501 V02N0501 +arc: A0 V02N0701 +arc: A1 H00R0000 +arc: A2 V00B0000 +arc: B0 H02E0101 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F1 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C39:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 W1_H02E0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 E1_H01W0000 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02W0501 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 V02N0501 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A3 W1_H02E0701 +arc: A4 H02W0701 +arc: A5 H02W0701 +arc: A6 H00L0000 +arc: A7 W1_H02E0701 +arc: B2 H00L0000 +arc: B4 N1_V02S0501 +arc: B5 N1_V02S0501 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 E1_H02W0401 +arc: C3 H02W0601 +arc: C6 E1_H02W0401 +arc: C7 V00T0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F4 +arc: N1_V02N0701 F5 +word: SLICEB.K0.INIT 1111110011000000 +word: SLICED.K0.INIT 1010010101011010 +word: SLICEA.K0.INIT 1111101010100000 +word: SLICED.K1.INIT 1111101010100000 +word: SLICEC.K1.INIT 1110111010001000 +word: SLICEA.K1.INIT 1010010101011010 +word: SLICEB.K1.INIT 1010010101011010 +word: SLICEC.K0.INIT 1001100101100110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R21C40:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: V00B0000 V02N0001 +arc: V00T0000 E1_H02W0201 +arc: A2 V00T0000 +arc: A3 V02N0701 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: A6 H00R0000 +arc: A7 E1_H02W0701 +arc: B0 V01N0001 +arc: B2 V02N0101 +arc: B3 E1_H02W0301 +arc: B4 H02E0101 +arc: B5 E1_H02W0101 +arc: B6 H02E0301 +arc: B7 V02N0501 +arc: E1_H01E0001 F4 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F6 +arc: N1_V01N0001 F2 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F7 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C41:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 V02N0701 +arc: A1 W1_H02E0701 +arc: A2 V00T0000 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: A6 H00R0000 +arc: A7 H02E0701 +arc: B0 E1_H02W0101 +arc: B1 V00B0000 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B6 V02N0501 +arc: B7 S1_V02N0701 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: N1_V02N0701 F7 +arc: V01S0000 F7 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 F0 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 F4 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R21C42:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V01N0101 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: B2 E1_H02W0301 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C6 H02E0601 +arc: C7 H02E0401 +arc: D6 F0 +arc: D7 F0 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F6 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F2 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 F2 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 1100001100111100 +word: SLICED.K0.INIT 1111110011000000 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R21C43:PLC2 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H02W0701 +arc: A3 N1_V02S0501 +arc: A4 N1_V02S0301 +arc: A7 E1_H01W0000 +arc: B0 E1_H01W0100 +arc: B2 N1_V02S0301 +arc: B4 H01E0101 +arc: B5 H02W0101 +arc: B7 H02E0301 +arc: C0 E1_H02W0401 +arc: C2 H02E0601 +arc: C3 E1_H01W0000 +arc: C5 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 H01E0101 +arc: D3 H02E0201 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D7 H02E0001 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 F2 +arc: N1_V02N0401 F4 +arc: V01S0000 Q0 +arc: W1_H02W0301 F3 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1011101010111111 +word: SLICEB.K0.INIT 1100001100111100 +word: SLICEB.K1.INIT 1010010101011010 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICED.K1.INIT 1001100101100110 +word: SLICEC.K0.INIT 1110111010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R21C44:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00R0000 H02W0401 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0301 S1_V02N0201 +arc: V00B0100 H02W0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W3_H06W0003 E1_H01W0000 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B2 E1_H01W0100 +arc: B3 Q3 +arc: B6 V01S0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q4 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q5 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: LSR1 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: V00B0000 Q4 +arc: V01S0000 Q6 +arc: V01S0100 Q7 +arc: W1_H02W0701 Q5 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C45:PLC2 +arc: E1_H02E0201 V02S0201 +arc: H00L0100 V02S0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 H02E0401 +arc: V00T0000 V02N0601 +arc: W1_H02W0401 N1_V01S0000 +arc: A2 F5 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: B2 V02N0101 +arc: B3 H00R0100 +arc: B4 N1_V01S0000 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C4 H01E0001 +arc: C5 V02S0201 +arc: C6 Q6 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D2 V02S0001 +arc: D3 H01E0101 +arc: D4 F2 +arc: D5 H02E0201 +arc: E1_H01E0101 F3 +arc: E1_H02E0601 Q6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00B0100 F5 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F5 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEB.K0.INIT 0101010101010100 +word: SLICEC.K0.INIT 1111101100000000 +word: SLICED.K0.INIT 0000111100001111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111111100001010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R21C46:PLC2 +arc: B0 W1_H02E0301 +arc: C0 H02E0601 +arc: C4 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D4 H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00B0000 F4 +word: SLICEC.K0.INIT 1111000011111111 +word: SLICEA.K0.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R21C51:PLC2 +arc: E3_H06E0303 V01N0101 + +.tile R21C52:PLC2 +arc: S3_V06S0003 W3_H06E0003 + +.tile R21C54:PLC2 +arc: S1_V02S0501 H06E0303 + +.tile R21C55:PLC2 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 H02W0701 + +.tile R21C56:PLC2 +arc: W1_H02W0701 V02N0701 + +.tile R21C60:PLC2 +arc: S1_V02S0701 V01N0101 + +.tile R21C61:PLC2 +arc: S1_V02S0101 V01N0101 + +.tile R21C65:PLC2 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 H06W0203 + +.tile R21C66:PLC2 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 H06W0203 + +.tile R21C67:PLC2 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0301 + +.tile R21C68:PLC2 +arc: W3_H06W0203 E1_H02W0401 + +.tile R21C69:PLC2 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 V01N0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W3_H06W0203 V01N0001 + +.tile R21C70:PLC2 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 V01N0101 +arc: W1_H02W0401 V02N0401 + +.tile R21C72:PLC2 +arc: W3_H06W0003 E1_H02W0001 + +.tile R21C73:PLC2 +arc: W3_H06W0103 E1_H02W0101 + +.tile R21C74:PLC2 +arc: W1_H02W0001 V02N0001 + +.tile R21C75:PLC2 +arc: W1_H02W0101 V02N0101 + +.tile R23C11:PLC2 +arc: W3_H06W0303 E1_H01W0100 + +.tile R23C12:PLC2 +arc: H01W0100 E3_H06W0303 + +.tile R23C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0203 + +.tile R23C14:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R23C15:PLC2 +arc: S3_V06S0203 H06W0203 + +.tile R23C18:PLC2 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R23C19:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0103 + +.tile R23C20:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R23C24:PLC2 +arc: N1_V02N0601 H02W0601 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0203 + +.tile R23C25:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0303 W3_H06E0303 +arc: N3_V06N0303 W3_H06E0303 +arc: W1_H02W0601 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0103 + +.tile R23C26:PLC2 +arc: N1_V02N0601 H02E0601 +arc: W3_H06W0103 E3_H06W0103 + +.tile R23C27:PLC2 +arc: E1_H02E0501 V02S0501 + +.tile R23C28:PLC2 +arc: N1_V02N0601 H06W0303 + +.tile R23C29:PLC2 +arc: E3_H06E0303 W1_H02E0501 + +.tile R23C30:PLC2 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile R23C31:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: N1_V02N0501 H02W0501 +arc: V00B0100 H02W0701 +arc: W3_H06W0103 E3_H06W0103 +arc: A6 V02N0101 +arc: B6 E1_H02W0301 +arc: C6 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D6 V02N0601 +arc: F6 F6_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0401 Q6 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 1111000111111101 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C32:PLC2 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06E0303 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0103 E3_H06W0003 + +.tile R23C33:PLC2 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0401 E1_H01W0000 + +.tile R23C34:PLC2 +arc: E1_H02E0401 V06S0203 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N3_V06N0003 E3_H06W0003 +arc: W1_H02W0301 E3_H06W0003 + +.tile R23C35:PLC2 +arc: E1_H02E0701 V02S0701 + +.tile R23C36:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0701 H02E0701 +arc: B0 E1_H02W0301 +arc: B2 E1_H02W0101 +arc: C0 V02S0401 +arc: C2 W1_H02E0401 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V02S0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 0000000011110011 +word: SLICEB.K0.INIT 0000000011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C37:PLC2 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: H00R0000 E1_H02W0601 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0101 E1_H02W0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 E1_H02W0601 +arc: A1 S1_V02N0501 +arc: B0 V02S0301 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02S0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: W3_H06W0103 Q1 +word: SLICEA.K0.INIT 0000000011001111 +word: SLICEA.K1.INIT 0000000010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R23C38:PLC2 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 E1_H02W0201 +arc: V00B0000 H02E0601 +arc: V00T0000 E1_H02W0201 +arc: A2 S1_V02N0501 +arc: A4 F7 +arc: A7 H00R0000 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0301 +arc: B3 N1_V02S0101 +arc: B4 H02W0101 +arc: B7 E1_H02W0301 +arc: C0 V02S0601 +arc: C1 N1_V02S0401 +arc: C2 N1_V02S0401 +arc: C4 V01N0101 +arc: C7 V00T0000 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D7 V01N0001 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N3_V06N0103 Q1 +arc: V00T0100 F3 +arc: V01S0100 F3 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 F4 +word: SLICEA.K1.INIT 0000110000001111 +word: SLICEA.K0.INIT 0011000000110011 +word: SLICEB.K0.INIT 0000101000001111 +word: SLICEB.K1.INIT 0000000000110011 +word: SLICED.K1.INIT 0011001100110010 +word: SLICEC.K0.INIT 1010101010100010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R23C39:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 W1_H02E0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02N0201 +arc: D2 H00R0000 +arc: D3 V02N0201 +arc: D4 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F3 +arc: E3_H06E0203 F4 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: S1_V02S0001 F2 +arc: V01S0100 F3 +arc: W1_H02W0101 F3 +arc: W1_H02W0601 F4 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 1111111100001111 +word: SLICEB.K1.INIT 0000000011110000 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R23C3:PLC2 +arc: W1_H02W0701 E1_H02W0601 + +.tile R23C40:PLC2 +arc: H00R0000 H02E0601 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 H02E0601 +arc: W1_H02W0001 H01E0001 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H00R0000 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 F1 +arc: V01S0100 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K1.INIT 1111111100001010 +word: SLICEA.K0.INIT 1111111100001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C41:PLC2 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06E0103 +arc: B3 N1_V02S0101 +arc: C3 S1_V02N0601 +arc: D3 H02W0001 +arc: F3 F3_SLICE +arc: N1_V02N0101 F3 +word: SLICEB.K1.INIT 1100001100111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C42:PLC2 +arc: W1_H02W0001 N1_V02S0001 + +.tile R23C43:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: W1_H02W0701 V02S0701 + +.tile R23C44:PLC2 +arc: N1_V02N0201 H01E0001 + +.tile R23C45:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 W3_H06E0203 + +.tile R23C46:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: N1_V02N0001 H06E0003 + +.tile R23C47:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: A5 V02N0101 +arc: B5 W1_H02E0101 +arc: C5 V02N0001 +arc: D5 H02E0001 +arc: F5 F5_SLICE +arc: N3_V06N0303 F5 +word: SLICEC.K1.INIT 1111111111111110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C48:PLC2 +arc: H00R0000 H02E0401 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0000 +arc: E3_H06E0203 Q4 +arc: LSR1 H02W0301 +arc: M4 E1_H02W0401 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R23C49:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 + +.tile R23C50:PLC2 +arc: W1_H02W0401 N1_V01S0000 + +.tile R23C51:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0401 V02S0401 + +.tile R23C52:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V02S0601 + +.tile R23C53:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W1_H02E0401 + +.tile R23C54:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0001 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: A2 H02W0701 +arc: A3 V00B0000 +arc: A4 V02S0101 +arc: A5 V00T0000 +arc: A6 E1_H02W0701 +arc: A7 V02S0301 +arc: B0 H02E0301 +arc: B2 H00L0000 +arc: B3 H02W0301 +arc: B4 H02E0101 +arc: B5 N1_V02S0501 +arc: B6 V02S0701 +arc: B7 W1_H02E0301 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C55:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: H00R0000 V02S0601 +arc: S1_V02S0001 W3_H06E0003 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 W1_H02E0501 +arc: A1 V02S0501 +arc: A2 V00T0000 +arc: A3 H02W0501 +arc: A4 V02S0101 +arc: A5 V00B0000 +arc: A6 H02E0701 +arc: A7 H00R0000 +arc: B0 V02S0301 +arc: B1 H02W0301 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 V02S0701 +arc: B5 N1_V02S0701 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 F0 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C56:PLC2 +arc: E3_H06E0303 H01E0101 +arc: V00B0000 V02S0201 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0701 +arc: A1 W1_H02E0501 +arc: A2 W1_H02E0501 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: S3_V06S0103 F1 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C57:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02S0501 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0301 N1_V01S0100 + +.tile R23C58:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: S3_V06S0103 H06E0103 + +.tile R23C59:PLC2 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0501 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: A2 V00T0000 +arc: A3 V02S0501 +arc: A4 V02S0301 +arc: A5 W1_H02E0501 +arc: A6 H00R0000 +arc: A7 H02W0501 +arc: B0 V02S0101 +arc: B2 H00L0000 +arc: B3 H00R0100 +arc: B4 V02S0701 +arc: B5 H02E0101 +arc: B6 V00B0000 +arc: B7 W1_H02E0301 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F6 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F5 +arc: V01S0000 F4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C5:PLC2 +arc: W1_H02W0601 E3_H06W0303 + +.tile R23C60:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: H01W0100 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: V00B0000 V02S0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 H00L0000 +arc: A1 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 V02S0701 +arc: A4 V02S0301 +arc: A5 W1_H02E0701 +arc: A6 E1_H02W0701 +arc: A7 H02W0701 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 H00R0000 +arc: B3 H02W0301 +arc: B4 V00B0100 +arc: B5 H02W0101 +arc: B6 V00B0000 +arc: B7 W1_H02E0301 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F0 +arc: E1_H02E0501 F7 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V01S0000 F6 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C61:PLC2 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0701 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: E1_H01E0101 F1 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: S1_V02S0201 F0 +arc: S3_V06S0103 F2 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C62:PLC2 +arc: E3_H06E0303 H01E0101 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 V02S0701 + +.tile R23C63:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W1_H02E0201 + +.tile R23C64:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 V02S0701 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06W0203 + +.tile R23C65:PLC2 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 V02S0401 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0601 +arc: A2 N1_V02S0701 +arc: A3 H02E0701 +arc: A4 N1_V02S0101 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: A7 V02S0301 +arc: B0 W1_H02E0101 +arc: B2 V02S0101 +arc: B3 N1_V02S0301 +arc: B4 V02S0701 +arc: B5 V02S0501 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0103 F2 +arc: V01S0000 F4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C66:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0203 W3_H06E0203 +arc: H00R0000 V02S0601 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: A0 H00R0000 +arc: A1 N1_V02S0701 +arc: A2 V00T0000 +arc: A3 V02S0501 +arc: A4 H02E0701 +arc: A5 E1_H02W0701 +arc: A6 V02S0101 +arc: A7 N1_V02S0301 +arc: B0 V00B0000 +arc: B1 W1_H02E0301 +arc: B2 V02S0301 +arc: B3 E1_H02W0301 +arc: B4 W1_H02E0101 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 V02N0701 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F4 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F6 +arc: S1_V02S0001 F2 +arc: S1_V02S0501 F5 +arc: V01S0000 F0 +arc: V01S0100 F1 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C67:PLC2 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02W0501 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W3_H06W0203 E1_H02W0701 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: B0 V02S0301 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: B6 V00T0000 +arc: B7 V00T0000 +arc: C6 S1_V02N0001 +arc: C7 S1_V02N0201 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0201 F2 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V00T0000 F0 +arc: V01S0000 F2 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 1111110011000000 +word: SLICED.K0.INIT 1100001100111100 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R23C68:PLC2 +arc: E1_H02E0101 V02S0101 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0501 +arc: S1_V02S0201 V01N0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A3 H01E0001 +arc: B5 H01E0101 +arc: B6 H01E0101 +arc: B7 H01E0101 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C3 S1_V02N0601 +arc: C5 S1_V02N0001 +arc: C6 V00T0000 +arc: C7 S1_V02N0001 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 H00R0000 +arc: D5 V02N0401 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +word: SLICEC.K1.INIT 1100001100111100 +word: SLICED.K1.INIT 1111110011000000 +word: SLICEB.K1.INIT 1010010101011010 +word: SLICEA.K1.INIT 1111101010100000 +word: SLICEA.K0.INIT 1010010101011010 +word: SLICED.K0.INIT 1111110011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R23C69:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 H02E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 E1_H02W0201 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V00B0000 +arc: A3 E1_H02W0701 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A6 N1_V02S0301 +arc: A7 N1_V01S0100 +arc: B0 H02E0101 +arc: B2 H00R0000 +arc: B3 V02S0301 +arc: B4 N1_V02S0501 +arc: B5 V02S0701 +arc: B6 N1_V01S0000 +arc: B7 V02S0501 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: V01S0000 F7 +arc: V01S0100 F2 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C70:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 N1_V02S0401 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 S1_V02N0501 +arc: A1 V02S0501 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A4 H02W0501 +arc: A5 V02S0101 +arc: A6 V00T0100 +arc: A7 N1_V02S0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B4 N1_V02S0701 +arc: B5 V00B0100 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: S1_V02S0501 F5 +arc: V01S0000 F0 +arc: V01S0100 F6 +arc: W1_H02W0501 F7 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F4 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C71:PLC2 +arc: H00R0000 V02S0401 +arc: V00T0000 V02S0401 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02S0701 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: B0 V02S0301 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: V01S0000 F2 +arc: V01S0100 F2 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 F0 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R23C72:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E1_H02W0701 + +.tile R23C73:PLC2 +arc: W1_H02W0701 V02S0701 + +.tile R23C74:PLC2 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0701 V02S0701 + +.tile R23C78:PLC2 +arc: E1_H01E0101 W3_H06E0203 + +.tile R23C79:PLC2 +arc: E3_H06E0303 H01E0101 + +.tile R23C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0203 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 + +.tile R23C85:PLC2 +arc: E1_H02E0601 W3_H06E0303 + +.tile R23C87:PLC2 +arc: E1_H02E0701 W1_H02E0601 + +.tile R23C8:PLC2 +arc: H01W0100 E3_H06W0303 + +.tile R24C28:PLC2 +arc: N1_V02N0501 E3_H06W0303 + +.tile R24C31:PLC2 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0601 H02W0601 + +.tile R24C32:PLC2 +arc: W1_H02W0601 E3_H06W0303 + +.tile R24C34:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0501 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 + +.tile R24C35:PLC2 +arc: N1_V02N0601 H02E0601 + +.tile R24C37:PLC2 +arc: E1_H02E0101 V02S0101 +arc: W3_H06W0103 E1_H01W0100 + +.tile R24C38:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: V00T0000 E1_H02W0201 +arc: A2 V00T0000 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 N1_V02S0301 +arc: B3 Q3 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q6 +arc: E1_H02E0101 Q3 +arc: E1_H02E0501 Q5 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q5 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F7 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 F6 +arc: V00B0000 Q4 +arc: W3_H06W0303 F5 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C39:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: H00R0100 H02E0701 +arc: N1_V02N0501 E1_H01W0100 +arc: N3_V06N0103 H06W0103 +arc: V00B0000 V02S0001 +arc: A2 F7 +arc: A7 H02E0501 +arc: B2 H02E0101 +arc: B7 H01E0101 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D2 H02W0201 +arc: D7 H00R0100 +arc: E3_H06E0103 Q2 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0201 F2 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1000100000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C40:PLC2 +arc: H01W0100 E3_H06W0303 +arc: N3_V06N0303 E3_H06W0303 +arc: V00B0100 V02S0301 +arc: W1_H02W0301 N1_V01S0100 +arc: W3_H06W0303 E3_H06W0303 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C42:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R24C43:PLC2 +arc: N1_V02N0501 H06W0303 + +.tile R24C45:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R24C46:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R24C47:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 + +.tile R24C48:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R24C49:PLC2 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 E3_H06W0103 + +.tile R24C51:PLC2 +arc: E1_H02E0101 W3_H06E0103 + +.tile R24C52:PLC2 +arc: E1_H02E0001 V06S0003 +arc: W3_H06W0303 E3_H06W0203 + +.tile R24C53:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 E1_H02W0101 +arc: A7 V00T0100 +arc: B7 W1_H02E0101 +arc: C7 V00T0000 +arc: D7 H02E0001 +arc: F7 F7_SLICE +arc: N3_V06N0203 F7 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R24C54:PLC2 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 H02E0401 +arc: V00T0000 H02W0001 +arc: CE2 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: LSR0 V00T0000 +arc: M5 H00R0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: W3_H06W0303 Q5 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C55:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0401 W1_H02E0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 E3_H06W0003 +arc: A0 V01N0101 +arc: A3 V02N0501 +arc: B0 F3 +arc: B3 V01N0001 +arc: C2 E1_H01W0000 +arc: C3 V02N0601 +arc: C6 V02S0001 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 F0 +arc: D3 S1_V02N0001 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0501 F7 +arc: V00B0000 F6 +arc: V00T0000 F0 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 1111000011111111 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 1000100000000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C56:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0401 N1_V02S0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 H01E0101 +arc: B0 H01W0100 +arc: C0 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C57:PLC2 +arc: H00R0000 H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 H06W0303 +arc: A2 H02W0501 +arc: B0 H02W0301 +arc: B2 E1_H01W0100 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C2 E1_H01W0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 W1_H02E0001 +arc: D2 H00R0000 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 F2 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 F0 +arc: V00T0100 F1 +arc: V01S0000 F0 +arc: W1_H02W0001 Q0 +word: SLICEA.K1.INIT 1111111100001111 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 1100000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R24C58:PLC2 +arc: N1_V02N0401 E3_H06W0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 S1_V02N0301 +arc: B2 V01N0001 +arc: B3 Q3 +arc: CE1 S1_V02N0201 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q4 +arc: H01W0100 Q7 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: V00B0000 Q4 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 Q5 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C59:PLC2 +arc: A2 H02W0701 +arc: A7 H02W0701 +arc: B7 N1_V01S0000 +arc: C2 V02N0601 +arc: D2 N1_V01S0000 +arc: D7 V02N0601 +arc: F2 F2_SLICE +arc: F7 F7_SLICE +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1110111010001000 +word: SLICEB.K0.INIT 1010010101011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R24C60:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 E1_H01W0100 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E1_H01W0100 + +.tile R24C61:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0201 +arc: N1_V02N0701 H06W0203 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02S0101 +arc: B0 H01W0100 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R24C62:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E3_H06E0103 W3_H06E0003 +arc: H00L0000 H02E0001 +arc: H00R0000 W1_H02E0601 +arc: V00B0000 H02E0601 +arc: W1_H02W0201 N1_V02S0201 +arc: A2 H02E0701 +arc: A4 V00B0000 +arc: A7 H02E0701 +arc: B0 H02W0301 +arc: B5 H00R0000 +arc: C0 V02N0601 +arc: C2 S1_V02N0401 +arc: C4 W1_H02E0601 +arc: C5 H02E0601 +arc: C7 V02S0201 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D2 V02S0201 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: D7 S1_V02N0601 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICEC.K0.INIT 1010010101011010 +word: SLICEB.K0.INIT 1111101010100000 +word: SLICED.K1.INIT 1010010101011010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C63:PLC2 +arc: H00L0000 H02E0201 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: B2 E1_H02W0301 +arc: C2 H00L0000 +arc: D2 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: S1_V02S0001 F2 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1100110011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R24C64:PLC2 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H01E0001 +arc: W1_H02W0301 H01E0101 +arc: E3_H06E0203 F7 +arc: F7 F7_SLICE +arc: S1_V02S0501 F7 +arc: W3_H06W0203 F7 +word: SLICED.K1.INIT 1111111111111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R24C65:PLC2 +arc: H00R0000 E1_H02W0401 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0301 V02S0301 +arc: A0 V02N0501 +arc: B3 V01N0001 +arc: B4 N1_V01S0000 +arc: B5 V02S0501 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C3 E1_H02W0601 +arc: C4 V00T0000 +arc: C5 E1_H02W0601 +arc: C7 V00T0000 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V01N0001 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0701 F5 +arc: V01S0000 F4 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0000101000001111 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICED.K1.INIT 1111110011000000 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICEB.K1.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R24C66:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 E1_H02W0001 +arc: A0 H00L0000 +arc: A1 V01N0101 +arc: A3 V02S0501 +arc: A4 N1_V01S0100 +arc: B2 E1_H02W0301 +arc: B5 H00L0000 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 V02S0601 +arc: C1 N1_V01S0100 +arc: C2 V02N0601 +arc: C3 H00R0100 +arc: C4 V01N0101 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: C7 E1_H02W0601 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D2 N1_V02S0001 +arc: D3 E1_H02W0001 +arc: D4 V02S0401 +arc: D5 V02S0601 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F1 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +arc: V01S0100 F2 +word: SLICED.K0.INIT 1100001100111100 +word: SLICEA.K0.INIT 1111101010100000 +word: SLICEC.K1.INIT 1100001100111100 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEA.K1.INIT 1010010101011010 +word: SLICEB.K0.INIT 1111110011000000 +word: SLICEB.K1.INIT 1111101010100000 +word: SLICED.K1.INIT 1100001100111100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C67:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 W3_H06E0003 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 H01E0101 +arc: A4 V02S0301 +arc: A5 V02N0101 +arc: A6 V02N0301 +arc: B0 V02S0301 +arc: B1 E1_H02W0101 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B6 N1_V01S0000 +arc: B7 N1_V01S0000 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V02S0001 +arc: C5 V02S0201 +arc: C7 E1_H02W0401 +arc: D0 V02S0001 +arc: D1 V02S0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0101 F4 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: V01S0100 F0 +word: SLICEA.K0.INIT 1111110011000000 +word: SLICEB.K0.INIT 1100001100111100 +word: SLICEC.K0.INIT 1010010101011010 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICEA.K1.INIT 1111110011000000 +word: SLICED.K1.INIT 1100001100111100 +word: SLICEC.K1.INIT 1010010101011010 +word: SLICED.K0.INIT 1110111010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 + +.tile R24C68:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0000 H02W0401 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A6 H00R0000 +arc: B0 V00B0000 +arc: B1 H02W0101 +arc: B5 H02W0101 +arc: B7 V00T0000 +arc: C0 W1_H02E0601 +arc: C1 H02E0601 +arc: C2 V02N0401 +arc: C3 H02W0401 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C6 H02E0601 +arc: C7 H02W0401 +arc: D0 V02N0201 +arc: D1 V00T0100 +arc: D2 H00R0000 +arc: D3 V00T0100 +arc: D4 W1_H02E0001 +arc: D5 H02E0001 +arc: D6 V02N0401 +arc: D7 H02E0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F7 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: V01S0000 F1 +arc: V01S0100 F0 +word: SLICEC.K0.INIT 1010010101011010 +word: SLICEB.K0.INIT 1010010101011010 +word: SLICED.K0.INIT 1111101010100000 +word: SLICEA.K0.INIT 1111110011000000 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICEA.K1.INIT 1100001100111100 +word: SLICED.K1.INIT 1100001100111100 +word: SLICEB.K1.INIT 1111101010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R24C69:PLC2 +arc: H00R0000 W1_H02E0401 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02E0401 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 N1_V01S0000 +arc: B0 V01N0001 +arc: B4 E1_H02W0101 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C4 W1_H02E0601 +arc: C7 E1_H02W0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D4 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N3_V06N0003 Q0 +arc: V01S0100 F4 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0011000000110011 +word: SLICEC.K0.INIT 1100001100111100 +word: SLICED.K1.INIT 1111110011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R24C70:PLC2 +arc: E3_H06E0303 W3_H06E0203 +arc: N1_V02N0401 W3_H06E0203 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V01S0000 + +.tile R24C71:PLC2 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W3_H06W0303 N1_V01S0100 + +.tile R24C73:PLC2 +arc: N1_V02N0601 H06E0303 + +.tile R25C19:PLC2 +arc: S3_V06S0003 H06W0003 + +.tile R25C22:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R25C28:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R25C34:PLC2 +arc: E3_H06E0303 N3_V06S0303 +arc: W3_H06W0203 E3_H06W0103 + +.tile R25C35:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E3_H06E0003 N3_V06S0003 +arc: N3_V06N0003 E3_H06W0003 + +.tile R25C36:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E1_H02W0201 + +.tile R25C37:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0501 H06E0303 + +.tile R25C38:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 E1_H02W0501 +arc: W1_H02W0201 N3_V06S0103 + +.tile R25C40:PLC2 +arc: W1_H02W0501 N3_V06S0303 +arc: W3_H06W0103 E3_H06W0003 + +.tile R25C41:PLC2 +arc: N1_V02N0601 N3_V06S0303 +arc: W3_H06W0003 V06N0003 + +.tile R25C46:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R25C52:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R25C55:PLC2 +arc: H00R0100 V02S0501 +arc: V00T0000 V02S0401 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B2 V01N0001 +arc: B3 Q3 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: LSR1 E1_H02W0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q3 +arc: N1_V02N0501 Q7 +arc: N1_V02N0601 Q6 +arc: V00B0000 Q4 +arc: V01S0000 Q5 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C56:PLC2 +arc: B6 N1_V01S0000 +arc: C6 V02S0001 +arc: D6 V02S0401 +arc: E1_H01E0101 F6 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: V01S0100 F6 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 1111001111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R25C57:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: W1_H02W0301 H01E0101 + +.tile R25C58:PLC2 +arc: W3_H06W0203 E3_H06W0103 +arc: C1 H02E0601 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H02E0001 +arc: D2 Q2 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q2 +arc: LSR1 H02E0501 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q2 +arc: V01S0000 F1 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R25C59:PLC2 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0601 + +.tile R25C60:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: N1_V02N0501 H06W0303 +arc: S1_V02S0501 H06W0303 + +.tile R25C61:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0701 N1_V02S0701 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 N1_V01S0100 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: C4 H02W0601 +arc: C5 H02W0601 +arc: D4 E1_H01W0100 +arc: D5 E1_H01W0100 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: S1_V02S0501 F5 +word: SLICEC.K0.INIT 1111110011000000 +word: SLICEC.K1.INIT 1100001100111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R25C62:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 H01E0101 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 V02N0701 +arc: A4 N1_V02S0101 +arc: A5 N1_V02S0101 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: B4 H02E0301 +arc: B5 H02E0301 +arc: C1 H02W0601 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0001 +arc: D4 H01W0000 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0401 F6 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICED.K1.INIT 1111101010100000 +word: SLICED.K0.INIT 1010010101011010 +word: SLICEC.K0.INIT 1110111010001000 +word: SLICEC.K1.INIT 1001100101100110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C63:PLC2 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 H02E0101 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0501 V01N0101 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0303 N1_V01S0100 +arc: A4 V02N0101 +arc: A7 V02N0101 +arc: B0 V02S0301 +arc: B3 V02N0101 +arc: B4 H02E0101 +arc: B7 H02E0101 +arc: C0 S1_V02N0401 +arc: C3 H00L0100 +arc: C4 V02N0001 +arc: CE0 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0201 +arc: D3 V01S0100 +arc: D7 H01W0000 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F7 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICEC.K0.INIT 1001011010010110 +word: SLICED.K1.INIT 1001100101100110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C64:PLC2 +arc: H00R0100 V02S0701 +arc: S1_V02S0301 V01N0101 +arc: V00B0000 H02W0401 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: A3 H02W0701 +arc: A4 N1_V02S0101 +arc: A5 E1_H01W0000 +arc: A6 H02W0701 +arc: B0 N1_V02S0101 +arc: B1 V00B0000 +arc: B2 H02W0101 +arc: B3 E1_H01W0100 +arc: B5 H02W0101 +arc: C0 H02W0601 +arc: C1 W1_H02E0401 +arc: C2 E1_H01W0000 +arc: C4 H02W0601 +arc: C6 V00T0100 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 V02N0201 +arc: D2 H02W0201 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: D6 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F0 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0103 Q1 +word: SLICEA.K1.INIT 0000110000001111 +word: SLICEB.K0.INIT 1100001100111100 +word: SLICEC.K1.INIT 1110111010001000 +word: SLICED.K0.INIT 1010010101011010 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEB.K1.INIT 1110111010001000 +word: SLICEA.K0.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R25C65:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0401 H06W0203 +arc: V00B0000 H02E0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02N0501 +arc: A3 H01E0001 +arc: A4 H02E0701 +arc: A5 N1_V01S0100 +arc: A6 H00L0000 +arc: A7 V02S0301 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: B4 N1_V01S0000 +arc: B5 H01E0101 +arc: B6 H02E0101 +arc: B7 V00B0000 +arc: CE1 V02S0201 +arc: CE2 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F3 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR1 E1_H02W0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 Q4 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 Q6 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C66:PLC2 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0601 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 E1_H02W0001 +arc: A0 H02E0701 +arc: A1 N1_V02S0701 +arc: A2 V02S0501 +arc: A3 V02S0701 +arc: A4 V02S0101 +arc: A5 H02E0501 +arc: A6 V02S0301 +arc: A7 N1_V01S0100 +arc: B0 V00B0000 +arc: B1 E1_H02W0101 +arc: B2 H00L0000 +arc: B3 N1_V02S0301 +arc: B4 H02W0101 +arc: B5 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 V00T0000 +arc: CE0 H02E0101 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q5 +arc: N1_V02N0601 Q6 +arc: N1_V02N0701 Q7 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: V01S0000 F7 +arc: V01S0100 F6 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C67:PLC2 +arc: E1_H02E0501 E1_H01W0100 +arc: H00L0000 H02W0201 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 E1_H01W0100 +arc: A0 H00R0000 +arc: A1 N1_V02S0701 +arc: A2 S1_V02N0501 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 V02N0101 +arc: A6 S1_V02N0101 +arc: A7 V02S0301 +arc: B0 H02W0301 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 S1_V02N0301 +arc: B4 N1_V01S0000 +arc: B5 E1_H02W0101 +arc: B6 V02S0501 +arc: B7 N1_V02S0501 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q4 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0601 Q6 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 Q5 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C68:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 W3_H06E0003 +arc: H00L0000 S1_V02N0201 +arc: H00L0100 V02S0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02S0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0001 W3_H06E0003 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0501 +arc: A2 V02N0701 +arc: A3 H02W0501 +arc: A4 N1_V02S0101 +arc: A5 V00T0000 +arc: A6 H00R0000 +arc: A7 H02W0701 +arc: B0 H00R0100 +arc: B1 E1_H02W0301 +arc: B2 V02N0301 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B5 N1_V01S0000 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: CE0 V02S0201 +arc: CE1 V02S0201 +arc: CE2 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q1 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 Q0 +arc: N1_V02N0601 Q4 +arc: N1_V02N0701 Q5 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 Q6 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C69:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H01E0001 +arc: S3_V06S0303 W3_H06E0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 E1_H02W0501 +arc: A1 V01N0101 +arc: A4 N1_V02S0101 +arc: A6 N1_V02S0101 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 V00T0000 +arc: B5 H01E0101 +arc: B6 W1_H02E0301 +arc: B7 H01E0101 +arc: C4 V00B0100 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D4 H00L0100 +arc: D5 V02S0401 +arc: D7 V02S0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F4 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F1 +arc: S1_V02S0701 F5 +arc: V01S0000 Q1 +arc: V01S0100 F0 +arc: W1_H02W0601 F6 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 1001100101100110 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICED.K0.INIT 1001011010010110 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 + +.tile R25C70:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H00R0000 V02S0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 H02E0401 +arc: V00B0100 V02S0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 H01E0101 +arc: A0 H01E0001 +arc: A5 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B6 V00B0000 +arc: C0 E1_H02W0601 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W1_H02W0201 F2 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0101000001010101 +word: SLICEC.K1.INIT 1010010101011010 +word: SLICEB.K0.INIT 1111110011000000 +word: SLICED.K0.INIT 1111110011000000 +word: SLICEB.K1.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R25C71:PLC2 +arc: H00R0000 H02E0401 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0601 W3_H06E0303 +arc: V00T0100 V02N0501 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 H01E0101 +arc: B0 W1_H02E0101 +arc: C0 W1_H02E0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 0011000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C72:PLC2 +arc: W1_H02W0601 W3_H06E0303 + +.tile R25C76:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R25C77:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R25C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 + +.tile R25C83:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 H01E0001 + +.tile R26C53:PLC2 +arc: N1_V02N0401 S1_V02N0101 + +.tile R26C54:PLC2 +arc: E3_H06E0303 V06S0303 + +.tile R26C55:PLC2 +arc: E3_H06E0103 V06S0103 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 N1_V01S0000 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C56:PLC2 +arc: E3_H06E0103 V06S0103 +arc: W1_H02W0301 N1_V01S0100 + +.tile R26C57:PLC2 +arc: E1_H02E0601 N1_V02S0601 + +.tile R26C58:PLC2 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 N1_V01S0000 + +.tile R26C59:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0100 V02S0301 +arc: H00R0000 W1_H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0001 +arc: V00T0100 V02S0501 +arc: B0 H02W0101 +arc: B1 V00T0000 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: C0 H00L0100 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C3 E1_H01W0000 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 H02W0201 +arc: D3 H02W0001 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 F1 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 F2 +word: SLICEB.K0.INIT 1111110011000000 +word: SLICEA.K1.INIT 1111110011000000 +word: SLICEA.K0.INIT 1100001100111100 +word: SLICEB.K1.INIT 1100001100111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C60:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 H01E0101 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: A2 V02N0701 +arc: A3 V01N0101 +arc: B3 H01W0100 +arc: B5 H00R0000 +arc: B6 V00B0000 +arc: C0 V02N0601 +arc: C2 H02E0401 +arc: C3 H02E0601 +arc: C5 V01N0101 +arc: C6 V02N0201 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D2 S1_V02N0001 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0501 F5 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 1001011010010110 +word: SLICEB.K0.INIT 1111101010100000 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICED.K0.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R26C61:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: H00R0100 V02S0701 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 H02E0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 V02N0701 +arc: B0 E1_H02W0301 +arc: B1 V00B0000 +arc: B2 E1_H02W0301 +arc: B5 H02W0301 +arc: B6 V02N0701 +arc: B7 H02W0301 +arc: C0 H02W0401 +arc: C1 E1_H01W0000 +arc: C2 E1_H02W0401 +arc: C5 V02S0201 +arc: C6 H02E0401 +arc: C7 V02S0201 +arc: CE0 V02N0201 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D2 S1_V02N0201 +arc: D5 H01W0000 +arc: D6 E1_H01W0100 +arc: D7 H01W0000 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: V01S0100 F1 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 1111110011000000 +word: SLICEC.K1.INIT 1100001100111100 +word: SLICEA.K1.INIT 1111110011000000 +word: SLICED.K0.INIT 1100001100111100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R26C62:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H00L0000 H02W0201 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0301 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V01N0001 +arc: A1 V02N0501 +arc: A4 S1_V02N0101 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B1 H02W0301 +arc: B2 H00R0000 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 H02E0101 +arc: B6 S1_V02N0501 +arc: C0 S1_V02N0401 +arc: C2 W1_H02E0601 +arc: C3 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 V00T0100 +arc: C7 W1_H02E0601 +arc: CE0 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 H02E0201 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 H02E0001 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 Q6 +arc: S1_V02S0501 F5 +arc: V01S0000 F2 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEC.K0.INIT 1011101110001000 +word: SLICED.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICEC.K1.INIT 1100001100111100 +word: SLICEB.K0.INIT 1111110011000000 +word: SLICED.K1.INIT 1010010101011010 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C63:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0100 W1_H02E0101 +arc: N1_V02N0101 H02E0101 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 H02W0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V01N0001 +arc: A0 V01N0101 +arc: A2 V02N0501 +arc: A6 V00T0100 +arc: A7 H00L0000 +arc: B1 H02E0101 +arc: B3 W1_H02E0101 +arc: B4 H02E0101 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: B7 W1_H02E0101 +arc: C0 S1_V02N0601 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 S1_V02N0001 +arc: C7 V00T0100 +arc: CE0 N1_V02S0201 +arc: CE1 N1_V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 V00B0100 +arc: D3 V00T0100 +arc: D4 H00L0100 +arc: D5 H02E0201 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0101 F1 +arc: N1_V02N0001 Q2 +arc: S1_V02S0101 F3 +arc: S1_V02S0601 F4 +arc: V01S0000 F5 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICED.K1.INIT 1110100011101000 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICEB.K1.INIT 1100001100111100 +word: SLICEC.K0.INIT 1111110011000000 +word: SLICEA.K1.INIT 1100001100111100 +word: SLICED.K0.INIT 1001011010010110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C64:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0201 H02E0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 V01N0101 +arc: B0 H02E0301 +arc: B1 V02N0101 +arc: B2 W1_H02E0101 +arc: B3 W1_H02E0101 +arc: B4 W1_H02E0101 +arc: B5 W1_H02E0101 +arc: B6 W1_H02E0101 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02E0401 +arc: C5 H02E0401 +arc: C6 H02E0401 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 H02E0001 +arc: D6 H01W0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F6 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0701 F5 +arc: V00T0100 Q1 +arc: V01S0000 F2 +word: SLICEA.K0.INIT 1110111000100010 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1111110011000000 +word: SLICEB.K1.INIT 1100001100111100 +word: SLICEC.K0.INIT 1111110011000000 +word: SLICEC.K1.INIT 1111110011000000 +word: SLICED.K0.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C65:PLC2 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 S1_V02N0401 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 H06E0203 +arc: V00T0000 V02S0401 +arc: A0 H02E0501 +arc: A4 V00T0000 +arc: A6 N1_V01S0100 +arc: B2 V02N0101 +arc: B3 V02S0101 +arc: B5 V02S0701 +arc: B7 N1_V01S0000 +word: SLICED.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R26C66:PLC2 +arc: E1_H02E0001 V02S0001 +arc: H00L0000 V02S0201 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: A4 V00T0000 +arc: A6 N1_V01S0100 +arc: B0 V00B0000 +arc: B1 V02S0301 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B5 V02S0501 +arc: B7 N1_V01S0000 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 1001100110011100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R26C67:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E3_H06E0203 V06S0203 +arc: N1_V02N0101 V01N0101 +arc: S1_V02S0201 N1_V02S0201 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 W3_H06E0103 +arc: A4 N1_V01S0100 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B2 N1_V02S0101 +arc: B3 V02S0301 +arc: B5 V02S0501 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0011001100111100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R26C68:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0201 N1_V02S0201 +arc: V00T0000 N1_V02S0601 +arc: A4 N1_V01S0100 +arc: A6 H00R0000 +arc: B0 V00T0000 +arc: B1 V02S0101 +arc: B2 N1_V02S0301 +arc: B3 V02S0301 +arc: B5 V02S0501 +arc: B7 N1_V01S0000 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0011001100111100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R26C69:PLC2 +arc: E1_H02E0501 W1_H02E0401 +arc: S1_V02S0401 N1_V02S0401 +arc: W1_H02W0701 V02S0701 +arc: B6 N1_V01S0000 +arc: C2 N1_V01S0100 +arc: C6 N1_V02S0201 +arc: D2 F0 +arc: D6 N1_V02S0401 +arc: E1_H01E0101 F2 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F6 F6_SLICE +arc: N1_V01N0101 F6 +arc: N1_V02N0201 F2 +arc: W3_H06W0103 F2 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICED.K0.INIT 1100001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R26C70:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0701 H06E0203 +arc: B0 W1_H02E0101 +arc: C0 V02S0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0000110000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C71:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: B0 V02S0101 +arc: C0 V02S0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0011000000110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C76:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R26C77:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R26C82:PLC2 +arc: E1_H01E0001 W3_H06E0003 + +.tile R26C83:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 H01E0001 + +.tile R27C41:PLC2 +arc: N3_V06N0203 E3_H06W0203 + +.tile R27C47:PLC2 +arc: W3_H06W0203 E3_H06W0203 + +.tile R27C53:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R27C58:PLC2 +arc: E1_H02E0101 V02N0101 + +.tile R27C59:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V06S0203 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 E1_H02W0401 +arc: A3 N1_V02S0701 +arc: B2 V02N0101 +arc: B3 S1_V02N0101 +arc: B4 N1_V02S0701 +arc: C2 S1_V02N0601 +arc: C4 S1_V02N0201 +arc: CE1 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D2 V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0601 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F4 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 0000000011001111 +word: SLICEC.K0.INIT 1111110011000000 +word: SLICEB.K1.INIT 1001100101100110 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R27C60:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02S0501 +arc: H00L0000 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: V00B0100 V02N0301 +arc: V00T0100 N1_V02S0501 +arc: A1 H02W0701 +arc: A7 V02N0101 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: C0 H02W0601 +arc: C7 E1_H02W0601 +arc: CE0 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V00B0100 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q1 +arc: V01S0000 Q7 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C61:PLC2 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: A2 V02S0701 +arc: A3 W1_H02E0501 +arc: A4 V02S0101 +arc: A5 W1_H02E0701 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B3 V02S0301 +arc: B4 W1_H02E0101 +arc: B5 V02S0501 +arc: B6 W1_H02E0301 +arc: B7 V00B0000 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F4 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R27C62:PLC2 +arc: E1_H02E0501 V02S0501 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 V01N0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0601 H01E0001 +arc: A0 V02S0701 +arc: A1 H02E0501 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0701 +arc: A4 V00T0000 +arc: A5 N1_V01S0100 +arc: A6 N1_V02S0301 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B1 V02S0301 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 V00B0100 +arc: B5 H02E0301 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0000 F6 +arc: V01S0100 F0 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R27C63:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00L0000 V02S0001 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0601 H01E0001 +arc: V00T0000 N1_V02S0401 +arc: A0 V02S0501 +arc: A1 V02S0701 +arc: A2 H02W0501 +arc: A3 N1_V02S0501 +arc: A4 H02E0501 +arc: A5 V02S0101 +arc: A6 N1_V01S0100 +arc: A7 N1_V02S0301 +arc: B0 N1_V02S0101 +arc: B1 E1_H02W0301 +arc: B2 V02S0301 +arc: B3 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 H00L0000 +arc: B6 N1_V02S0701 +arc: B7 V00T0000 +arc: E1_H02E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F5 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 F7 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0203 F4 +arc: V01S0000 F6 +arc: V01S0100 F0 +word: SLICED.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R27C64:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 W1_H02E0201 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 V01N0101 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H02W0401 +arc: A0 V02S0701 +arc: A1 H00R0000 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A4 V02S0301 +arc: A5 E1_H02W0701 +arc: A6 V02N0101 +arc: A7 H02W0501 +arc: B0 N1_V02S0301 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 S1_V02N0301 +arc: B4 S1_V02N0501 +arc: B5 N1_V01S0000 +arc: B6 E1_H02W0101 +arc: B7 V00T0000 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0101 F0 +arc: N1_V02N0601 F4 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 F2 +arc: V01S0000 F6 +arc: V01S0100 F0 +word: SLICED.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R27C65:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V02S0401 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H06W0003 +arc: V00B0000 V02S0201 +arc: V00T0000 H02E0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 V01N0101 +arc: A0 E1_H01E0001 +arc: A1 H00L0000 +arc: A4 S1_V02N0101 +arc: A7 S1_V02N0301 +arc: B0 V02N0101 +arc: B1 E1_H02W0301 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: C4 S1_V02N0201 +arc: C5 V02N0201 +arc: C6 S1_V02N0001 +arc: C7 V02S0201 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D4 V02N0601 +arc: D5 W1_H02E0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0100 F7 +arc: LSR1 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0301 F1 +arc: V01S0100 F0 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICED.K1.INIT 1111101010100000 +word: SLICED.K0.INIT 1100001100111100 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R27C66:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 S1_V02N0101 +arc: V00B0000 H02W0601 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0301 H01E0101 +arc: A1 W1_H02E0701 +arc: A2 S1_V02N0501 +arc: A5 S1_V02N0101 +arc: A6 S1_V02N0101 +arc: B0 H02E0101 +arc: B3 S1_V02N0101 +arc: B4 S1_V02N0501 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H02E0401 +arc: C3 H02W0601 +arc: C4 H02E0401 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 W1_H02E0201 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: D4 H01W0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0100 Q1 +arc: V01S0100 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K1.INIT 1111101000001010 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICED.K1.INIT 1100001100111100 +word: SLICEC.K1.INIT 1111101010100000 +word: SLICED.K0.INIT 1010010101011010 +word: SLICEC.K0.INIT 1111110011000000 +word: SLICEB.K0.INIT 1010010101011010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R27C67:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 N1_V02S0701 +arc: S1_V02S0001 W3_H06E0003 +arc: V00B0000 V02S0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: A3 N1_V02S0701 +arc: A7 H00R0000 +arc: B0 W1_H02E0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0101 +arc: B5 H00R0000 +arc: C0 H02E0401 +arc: C1 E1_H02W0401 +arc: C2 S1_V02N0601 +arc: C3 H02W0601 +arc: C5 V02S0201 +arc: C7 N1_V02S0201 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 N1_V02S0201 +arc: D2 V01S0100 +arc: D3 V02S0201 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N1_V02N0501 F7 +arc: V01S0100 Q0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 1111000011001100 +word: SLICEB.K0.INIT 1100001100111100 +word: SLICEC.K1.INIT 1100001100111100 +word: SLICEB.K1.INIT 1111101010100000 +word: SLICEA.K1.INIT 1111110011000000 +word: SLICED.K1.INIT 1010010101011010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R27C68:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 H02E0201 +arc: H00R0000 H02W0401 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0601 V06S0303 +arc: A6 H00R0000 +arc: B0 S1_V02N0101 +arc: B2 H00R0000 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 H00R0000 +arc: C0 H02W0601 +arc: C2 H00L0000 +arc: C3 H02W0601 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C6 V00T0000 +arc: CE0 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 N1_V02S0201 +arc: D3 V01S0100 +arc: D4 N1_V02S0601 +arc: D5 H02E0201 +arc: D6 N1_V02S0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 F5 +arc: N1_V02N0201 F2 +arc: N1_V02N0601 F6 +arc: V01S0100 Q0 +arc: W3_H06W0003 F3 +word: SLICEC.K0.INIT 1111110011000000 +word: SLICEB.K1.INIT 1111110011000000 +word: SLICED.K0.INIT 1010010101011010 +word: SLICEA.K0.INIT 1100001100111100 +word: SLICEB.K0.INIT 1111110011000000 +word: SLICEC.K1.INIT 1100001100111100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R27C69:PLC2 +arc: H00L0100 V02N0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 V06S0303 +arc: A0 V02N0501 +arc: B2 V02N0301 +arc: C0 H02E0601 +arc: C2 H02E0601 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D2 V02N0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +word: SLICEA.K0.INIT 0000000010101111 +word: SLICEB.K0.INIT 0011001100000011 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R28C10:PLC2 +arc: H01W0000 E3_H06W0103 + +.tile R28C16:PLC2 +arc: W3_H06W0103 E1_H01W0100 + +.tile R28C17:PLC2 +arc: H01W0100 E3_H06W0303 + +.tile R28C23:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R28C29:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R28C35:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R28C3:PLC2 +arc: S3_V06S0203 E3_H06W0203 + +.tile R28C40:PLC2 +arc: E1_H02E0301 V02N0301 +arc: N3_V06N0003 E1_H01W0000 + +.tile R28C41:PLC2 +arc: CE0 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: H01W0000 F0 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 F0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R28C43:PLC2 +arc: W1_H02W0101 E1_H02W0101 + +.tile R28C44:PLC2 +arc: N3_V06N0003 H06E0003 + +.tile R28C45:PLC2 +arc: W1_H02W0101 E3_H06W0103 + +.tile R28C47:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R28C50:PLC2 +arc: N3_V06N0103 H06E0103 + +.tile R28C51:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R28C53:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 + +.tile R28C57:PLC2 +arc: C3 S1_V02N0601 +arc: D3 S1_V02N0001 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: W3_H06W0003 F3 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R28C58:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0101 H01E0101 + +.tile R28C59:PLC2 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 E3_H06W0003 + +.tile R28C60:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 E1_H01W0000 +arc: A0 H02W0701 +arc: C0 H02W0401 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C61:PLC2 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0701 N1_V02S0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0401 N1_V01S0000 +arc: A3 V00T0000 +arc: A7 V02S0101 +arc: B0 W1_H02E0101 +arc: B2 V02S0301 +arc: B4 V02S0701 +arc: B5 N1_V01S0000 +arc: B6 V02S0501 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +arc: V01S0100 F4 +arc: W1_H02W0101 F3 +arc: W1_H02W0701 F5 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R28C62:PLC2 +arc: E3_H06E0003 H01E0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 E1_H02W0301 +arc: A3 V00T0000 +arc: B0 V02S0101 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B4 V02S0501 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 H02W0101 +arc: E1_H01E0101 F7 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F6 +arc: N1_V02N0101 F3 +arc: N1_V02N0701 F5 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F5 +arc: V01S0000 F2 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R28C63:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 N1_V01S0100 +arc: A3 V00T0000 +arc: A7 H02W0501 +arc: B0 V02S0301 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B4 V02S0501 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: E1_H01E0101 F7 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: N1_V01N0001 F5 +arc: N1_V02N0401 F6 +arc: N1_V02N0601 F4 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: V01S0000 F4 +arc: V01S0100 F6 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R28C64:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 H01E0101 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V01S0100 +arc: A3 V00T0000 +arc: B0 V02S0301 +arc: B1 V00B0000 +arc: B2 V02S0101 +arc: B4 V02S0501 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 H02W0101 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 F0 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F3 +arc: S1_V02S0001 F0 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 F3 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R28C65:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 E1_H02W0601 +arc: W1_H02W0101 N1_V01S0100 +arc: A4 V02N0101 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: B0 V02S0301 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C6 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: E1_H01E0001 F0 +arc: E1_H02E0201 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: N1_V01N0101 F4 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010010101011010 +word: SLICEC.K1.INIT 1111101010100000 +word: SLICED.K0.INIT 1010010101011010 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R28C66:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E3_H06E0003 H01E0001 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 H01E0001 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: A2 W1_H02E0501 +arc: A3 V00B0000 +arc: A4 V02N0101 +arc: A6 V02N0101 +arc: B0 S1_V02N0301 +arc: B1 V02N0101 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C2 W1_H02E0601 +arc: C3 E1_H01W0000 +arc: C4 H02W0601 +arc: C6 H02W0601 +arc: CE0 V02N0201 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 E1_H01W0100 +arc: D6 H01W0000 +arc: E1_H01E0101 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F3 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V02N0201 Q0 +arc: V01S0100 Q2 +arc: W1_H02W0101 F1 +arc: W1_H02W0401 F6 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111101010100000 +word: SLICEB.K1.INIT 1010010101011010 +word: SLICED.K0.INIT 1111101010100000 +word: SLICEA.K1.INIT 1100001100111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C67:PLC2 +arc: E1_H02E0501 W3_H06E0303 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0601 V02N0601 +arc: A0 W1_H02E0701 +arc: C0 W1_H02E0401 +arc: CE0 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C68:PLC2 +arc: E1_H01E0001 W3_H06E0003 + +.tile R28C69:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 W1_H02E0501 +arc: W1_H02W0501 V06S0303 + +.tile R28C9:PLC2 +arc: W3_H06W0203 E1_H01W0000 + +.tile R29C11:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R29C15:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R29C17:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R29C23:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R29C29:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R29C35:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R29C3:PLC2 +arc: W1_H02W0701 E1_H02W0601 + +.tile R29C40:PLC2 +arc: N1_V02N0301 N3_V06S0003 + +.tile R29C41:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R29C47:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R29C53:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R29C54:PLC2 +arc: E3_H06E0203 N3_V06S0203 + +.tile R29C55:PLC2 +arc: E3_H06E0203 N3_V06S0203 + +.tile R29C58:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 N3_V06S0103 + +.tile R29C59:PLC2 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 E3_H06W0303 +arc: V00T0000 H02E0201 +arc: B0 H01W0100 +arc: C0 H02W0601 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: F0 F0_SLICE +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0000000011110011 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R29C5:PLC2 +arc: W1_H02W0601 E3_H06W0303 + +.tile R29C60:PLC2 +arc: N1_V02N0701 W3_H06E0203 +arc: W1_H02W0601 V06S0303 +arc: B3 H02W0301 +arc: E1_H01E0001 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0011001100110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R29C61:PLC2 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0701 W3_H06E0203 +arc: W1_H02W0301 N1_V02S0301 +arc: A0 V02N0701 +arc: A2 V02S0701 +arc: A3 H01E0001 +arc: A4 V02S0301 +arc: A5 N1_V01S0100 +arc: B6 V02S0501 +arc: B7 N1_V01S0000 +word: SLICED.K1.INIT 1001100110011100 +word: SLICED.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R29C62:PLC2 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 V02S0001 +arc: N1_V02N0201 N1_V01S0000 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: A0 V02S0701 +arc: A4 V02S0101 +arc: A5 N1_V01S0100 +arc: B1 V00B0000 +arc: B2 V02S0301 +arc: B3 H00L0000 +arc: B6 V02S0501 +arc: B7 V00T0000 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 1001100110011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R29C63:PLC2 +arc: E1_H02E0501 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: S1_V02S0001 N1_V02S0001 +arc: V00B0000 V02S0201 +arc: A0 V02S0701 +arc: A1 H00L0000 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A7 N1_V01S0100 +arc: B2 V02S0101 +arc: B5 N1_V01S0000 +arc: B6 V02S0501 +word: SLICED.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEA.K0.INIT 0101010101011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R29C64:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00L0000 V02S0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0000 V02S0201 +arc: A0 V02S0501 +arc: A1 H00L0000 +arc: A3 V00B0000 +arc: A4 V02S0301 +arc: A5 N1_V01S0100 +arc: B2 V02S0101 +arc: B6 V02S0701 +arc: B7 N1_V01S0000 +word: SLICED.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEA.K0.INIT 0101010101011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R29C65:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 E1_H02W0601 +arc: B4 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C4 E1_H02W0401 +arc: C6 V02S0001 +arc: C7 E1_H02W0401 +arc: D4 V02N0601 +arc: D6 F0 +arc: D7 V02N0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F4 +arc: E1_H02E0601 F6 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: W3_H06W0303 F6 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEC.K0.INIT 1111110011000000 +word: SLICED.K1.INIT 1100001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R29C66:PLC2 +arc: E1_H02E0101 V02S0101 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 E1_H02W0501 +arc: V00B0100 H02W0701 +arc: W1_H02W0501 H01E0101 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: CE0 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02W0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K1.INIT 0000010100001111 +word: SLICEA.K0.INIT 0000111100000101 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R29C67:PLC2 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 V02S0701 +arc: C0 W1_H02E0601 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0000000010101111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R29C68:PLC2 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0601 H06E0303 +arc: W1_H02W0501 N3_V06S0303 + +.tile R29C72:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 + +.tile R29C73:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 H01E0001 + +.tile R29C78:PLC2 +arc: E1_H02E0201 W3_H06E0103 + +.tile R29C79:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 + +.tile R29C80:PLC2 +arc: E1_H02E0301 W1_H02E0201 + +.tile R29C82:PLC2 +arc: E3_H06E0003 W1_H02E0301 + +.tile R29C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 + +.tile R29C86:PLC2 +arc: E3_H06E0303 H01E0101 + +.tile R29C87:PLC2 +arc: E1_H02E0501 W1_H02E0501 + +.tile R29C88:PLC2 +arc: E1_H01E0001 W3_H06E0003 + +.tile R2C39:PLC2 +arc: N1_V02N0501 S1_V02N0501 + +.tile R30C57:PLC2 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0601 N3_V06S0303 + +.tile R30C60:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 N3_V06S0103 + +.tile R30C61:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: N1_V02N0701 N3_V06S0203 + +.tile R30C62:PLC2 +arc: H00L0100 H02E0301 +arc: B0 H02W0301 +arc: C0 H02W0401 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 1100110011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R30C63:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0100 W1_H02E0301 +arc: N1_V01N0001 N3_V06S0003 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: B0 N1_V02S0101 +arc: C0 N1_V01N0001 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: F0 F0_SLICE +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 1100111111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C64:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 N3_V06S0003 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: C0 N1_V02S0601 +arc: C1 V02S0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 N1_V02S0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0201 Q0 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C65:PLC2 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 N1_V02S0701 +arc: C0 H00L0000 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: F0 F0_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C66:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H06E0003 + +.tile R30C67:PLC2 +arc: N1_V01N0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 + +.tile R31C19:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R31C3:PLC2 +arc: W1_H02W0701 V06S0203 + +.tile R35C15:PLC2 +arc: S3_V06S0003 N3_V06S0303 + +.tile R37C19:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R3C38:PLC2 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S3_V06N0203 + +.tile R3C41:PLC2 +arc: N1_V02N0501 S1_V02N0401 +arc: W3_H06W0303 S3_V06N0303 + +.tile R3C43:PLC2 +arc: N1_V02N0601 S1_V02N0301 + +.tile R3C44:PLC2 +arc: N1_V02N0701 S1_V02N0601 + +.tile R3C47:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R3C69:PLC2 +arc: E3_H06E0203 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 + +.tile R3C72:PLC2 +arc: N1_V02N0701 H06E0203 + +.tile R41C15:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R43C19:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R47C15:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R49C19:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R4C39:PLC2 +arc: N1_V02N0501 S1_V02N0501 + +.tile R4C53:PLC2 +arc: N3_V06N0303 S1_V02N0601 + +.tile R4C65:PLC2 +arc: N3_V06N0203 S1_V02N0701 + +.tile R4C69:PLC2 +arc: N3_V06N0203 S1_V02N0701 + +.tile R53C15:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R55C19:PLC2 +arc: S3_V06S0103 N3_V06S0103 + +.tile R59C15:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R5C41:PLC2 +arc: N1_V02N0401 S3_V06N0203 + +.tile R5C43:PLC2 +arc: N1_V02N0301 S3_V06N0003 + +.tile R5C44:PLC2 +arc: N1_V02N0601 S1_V02N0301 + +.tile R61C19:PLC2 +arc: S3_V06S0203 N3_V06S0103 + +.tile R65C15:PLC2 +arc: V01S0100 N3_V06S0303 + +.tile R66C15:PLC2 +arc: S1_V02S0701 N1_V01S0100 + +.tile R67C19:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R68C15:PLC2 +arc: S1_V02S0701 N1_V02S0701 + +.tile R6C39:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R6C53:PLC2 +arc: N1_V02N0601 S3_V06N0303 + +.tile R6C65:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R6C69:PLC2 +arc: N1_V02N0701 S3_V06N0203 + +.tile R7C37:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R7C38:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R7C44:PLC2 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 + +.tile R9C38:PLC2 +arc: N3_V06N0203 S1_V02N0401 + +.tile R9C41:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R9C47:PLC2 +arc: N3_V06N0303 S1_V02N0501 + +.tile R9C69:PLC2 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 + +.tile TAP_R19C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C51:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R20C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C51:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R21C51:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R23C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R23C51:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R24C31:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R25C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R26C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R27C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R27C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R28C51:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R28C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R29C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R29C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R30C51:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C78:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile_group MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 MIB_R22C74:MIB_DSP5 MIB_R22C74:MIB2_DSP5 MIB_R22C75:MIB_DSP6 MIB_R22C75:MIB2_DSP6 MIB_R22C76:MIB_DSP7 MIB_R22C76:MIB2_DSP7 MIB_R22C77:MIB_DSP8 MIB_R22C77:MIB2_DSP8 +enum: MULT18_4.REG_INPUTA_CLK NONE +enum: MULT18_4.REG_INPUTA_CE CE0 +enum: MULT18_4.REG_INPUTA_RST RST0 +enum: MULT18_4.REG_INPUTB_CLK NONE +enum: MULT18_4.REG_INPUTB_CE CE0 +enum: MULT18_4.REG_INPUTB_RST RST0 +enum: MULT18_4.REG_INPUTC_CLK NONE +enum: MULT18_4.REG_PIPELINE_CLK NONE +enum: MULT18_4.REG_PIPELINE_CE CE0 +enum: MULT18_4.REG_PIPELINE_RST RST0 +enum: MULT18_4.REG_OUTPUT_CLK NONE +enum: MULT18_4.REG_OUTPUT_RST RST0 +enum: MULT18_4.CLK0_DIV ENABLED +enum: MULT18_4.CLK1_DIV ENABLED +enum: MULT18_4.CLK2_DIV ENABLED +enum: MULT18_4.CLK3_DIV ENABLED +enum: MULT18_4.GSR ENABLED +enum: MULT18_4.SOURCEB_MODE B_SHIFT +enum: MULT18_4.RESETMODE SYNC +enum: MULT18_4.MODE MULT18X18D +enum: MULT18_4.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_4.CLK0MUX CLK0 +enum: MULT18_4.CLK1MUX CLK1 +enum: MULT18_4.CLK2MUX CLK2 +enum: MULT18_4.CLK3MUX CLK3 +enum: MULT18_4.CE0MUX CE0 +enum: MULT18_4.CE1MUX CE1 +enum: MULT18_4.CE2MUX CE2 +enum: MULT18_4.CE3MUX CE3 +enum: MULT18_4.RST0MUX RST0 +enum: MULT18_4.RST1MUX RST1 +enum: MULT18_4.RST2MUX RST2 +enum: MULT18_4.RST3MUX RST3 + +.tile_group MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 MIB_R22C27:MIB_DSP5 MIB_R22C27:MIB2_DSP5 MIB_R22C28:MIB_DSP6 MIB_R22C28:MIB2_DSP6 MIB_R22C29:MIB_DSP7 MIB_R22C29:MIB2_DSP7 MIB_R22C30:MIB_DSP8 MIB_R22C30:MIB2_DSP8 +enum: MULT18_4.REG_INPUTA_CLK NONE +enum: MULT18_4.REG_INPUTA_CE CE0 +enum: MULT18_4.REG_INPUTA_RST RST0 +enum: MULT18_4.REG_INPUTB_CLK NONE +enum: MULT18_4.REG_INPUTB_CE CE0 +enum: MULT18_4.REG_INPUTB_RST RST0 +enum: MULT18_4.REG_INPUTC_CLK NONE +enum: MULT18_4.REG_PIPELINE_CLK NONE +enum: MULT18_4.REG_PIPELINE_CE CE0 +enum: MULT18_4.REG_PIPELINE_RST RST0 +enum: MULT18_4.REG_OUTPUT_CLK NONE +enum: MULT18_4.REG_OUTPUT_RST RST0 +enum: MULT18_4.CLK0_DIV ENABLED +enum: MULT18_4.CLK1_DIV ENABLED +enum: MULT18_4.CLK2_DIV ENABLED +enum: MULT18_4.CLK3_DIV ENABLED +enum: MULT18_4.GSR ENABLED +enum: MULT18_4.SOURCEB_MODE B_SHIFT +enum: MULT18_4.RESETMODE SYNC +enum: MULT18_4.MODE MULT18X18D +enum: MULT18_4.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_4.CLK0MUX CLK0 +enum: MULT18_4.CLK1MUX CLK1 +enum: MULT18_4.CLK2MUX CLK2 +enum: MULT18_4.CLK3MUX CLK3 +enum: MULT18_4.CE0MUX CE0 +enum: MULT18_4.CE1MUX CE1 +enum: MULT18_4.CE2MUX CE2 +enum: MULT18_4.CE3MUX CE3 +enum: MULT18_4.RST0MUX RST0 +enum: MULT18_4.RST1MUX RST1 +enum: MULT18_4.RST2MUX RST2 +enum: MULT18_4.RST3MUX RST3 + +.tile_group MIB_R22C69:MIB_DSP0 MIB_R22C69:MIB2_DSP0 MIB_R22C70:MIB_DSP1 MIB_R22C70:MIB2_DSP1 MIB_R22C71:MIB_DSP2 MIB_R22C71:MIB2_DSP2 MIB_R22C72:MIB_DSP3 MIB_R22C72:MIB2_DSP3 MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 +enum: MULT18_1.REG_INPUTA_CLK NONE +enum: MULT18_1.REG_INPUTA_CE CE0 +enum: MULT18_1.REG_INPUTA_RST RST0 +enum: MULT18_1.REG_INPUTB_CLK NONE +enum: MULT18_1.REG_INPUTB_CE CE0 +enum: MULT18_1.REG_INPUTB_RST RST0 +enum: MULT18_1.REG_INPUTC_CLK NONE +enum: MULT18_1.REG_PIPELINE_CLK NONE +enum: MULT18_1.REG_PIPELINE_CE CE0 +enum: MULT18_1.REG_PIPELINE_RST RST0 +enum: MULT18_1.REG_OUTPUT_CLK NONE +enum: MULT18_1.CLK0_DIV ENABLED +enum: MULT18_1.CLK1_DIV ENABLED +enum: MULT18_1.CLK2_DIV ENABLED +enum: MULT18_1.CLK3_DIV ENABLED +enum: MULT18_1.GSR ENABLED +enum: MULT18_1.SOURCEB_MODE B_SHIFT +enum: MULT18_1.RESETMODE SYNC +enum: MULT18_1.MODE MULT18X18D +enum: MULT18_1.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_1.CLK0MUX CLK0 +enum: MULT18_1.CLK1MUX CLK1 +enum: MULT18_1.CLK2MUX CLK2 +enum: MULT18_1.CLK3MUX CLK3 +enum: MULT18_1.CE0MUX CE0 +enum: MULT18_1.CE1MUX CE1 +enum: MULT18_1.CE2MUX CE2 +enum: MULT18_1.CE3MUX CE3 +enum: MULT18_1.RST0MUX RST0 +enum: MULT18_1.RST1MUX RST1 +enum: MULT18_1.RST2MUX RST2 +enum: MULT18_1.RST3MUX RST3 + +.tile_group MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 MIB_R22C27:MIB_DSP5 MIB_R22C27:MIB2_DSP5 MIB_R22C28:MIB_DSP6 MIB_R22C28:MIB2_DSP6 MIB_R22C29:MIB_DSP7 MIB_R22C29:MIB2_DSP7 MIB_R22C30:MIB_DSP8 MIB_R22C30:MIB2_DSP8 +enum: MULT18_5.REG_INPUTA_CLK NONE +enum: MULT18_5.REG_INPUTA_CE CE0 +enum: MULT18_5.REG_INPUTA_RST RST0 +enum: MULT18_5.REG_INPUTB_CLK NONE +enum: MULT18_5.REG_INPUTB_CE CE0 +enum: MULT18_5.REG_INPUTB_RST RST0 +enum: MULT18_5.REG_INPUTC_CLK NONE +enum: MULT18_5.REG_PIPELINE_CLK NONE +enum: MULT18_5.REG_PIPELINE_CE CE0 +enum: MULT18_5.REG_PIPELINE_RST RST0 +enum: MULT18_5.REG_OUTPUT_CLK NONE +enum: MULT18_5.CLK0_DIV ENABLED +enum: MULT18_5.CLK1_DIV ENABLED +enum: MULT18_5.CLK2_DIV ENABLED +enum: MULT18_5.CLK3_DIV ENABLED +enum: MULT18_5.GSR ENABLED +enum: MULT18_5.SOURCEB_MODE B_SHIFT +enum: MULT18_5.RESETMODE SYNC +enum: MULT18_5.MODE MULT18X18D +enum: MULT18_5.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_5.CLK0MUX CLK0 +enum: MULT18_5.CLK1MUX CLK1 +enum: MULT18_5.CLK2MUX CLK2 +enum: MULT18_5.CLK3MUX CLK3 +enum: MULT18_5.CE0MUX CE0 +enum: MULT18_5.CE1MUX CE1 +enum: MULT18_5.CE2MUX CE2 +enum: MULT18_5.CE3MUX CE3 +enum: MULT18_5.RST0MUX RST0 +enum: MULT18_5.RST1MUX RST1 +enum: MULT18_5.RST2MUX RST2 +enum: MULT18_5.RST3MUX RST3 + +.tile_group MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 MIB_R22C36:MIB_DSP5 MIB_R22C36:MIB2_DSP5 MIB_R22C37:MIB_DSP6 MIB_R22C37:MIB2_DSP6 MIB_R22C38:MIB_DSP7 MIB_R22C38:MIB2_DSP7 MIB_R22C39:MIB_DSP8 MIB_R22C39:MIB2_DSP8 +enum: MULT18_4.REG_INPUTA_CLK NONE +enum: MULT18_4.REG_INPUTA_CE CE0 +enum: MULT18_4.REG_INPUTA_RST RST0 +enum: MULT18_4.REG_INPUTB_CLK NONE +enum: MULT18_4.REG_INPUTB_CE CE0 +enum: MULT18_4.REG_INPUTB_RST RST0 +enum: MULT18_4.REG_INPUTC_CLK NONE +enum: MULT18_4.REG_PIPELINE_CLK NONE +enum: MULT18_4.REG_PIPELINE_CE CE0 +enum: MULT18_4.REG_PIPELINE_RST RST0 +enum: MULT18_4.REG_OUTPUT_CLK NONE +enum: MULT18_4.REG_OUTPUT_RST RST0 +enum: MULT18_4.CLK0_DIV ENABLED +enum: MULT18_4.CLK1_DIV ENABLED +enum: MULT18_4.CLK2_DIV ENABLED +enum: MULT18_4.CLK3_DIV ENABLED +enum: MULT18_4.GSR ENABLED +enum: MULT18_4.SOURCEB_MODE B_SHIFT +enum: MULT18_4.RESETMODE SYNC +enum: MULT18_4.MODE MULT18X18D +enum: MULT18_4.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_4.CLK0MUX CLK0 +enum: MULT18_4.CLK1MUX CLK1 +enum: MULT18_4.CLK2MUX CLK2 +enum: MULT18_4.CLK3MUX CLK3 +enum: MULT18_4.CE0MUX CE0 +enum: MULT18_4.CE1MUX CE1 +enum: MULT18_4.CE2MUX CE2 +enum: MULT18_4.CE3MUX CE3 +enum: MULT18_4.RST0MUX RST0 +enum: MULT18_4.RST1MUX RST1 +enum: MULT18_4.RST2MUX RST2 +enum: MULT18_4.RST3MUX RST3 + +.tile_group MIB_R22C31:MIB_DSP0 MIB_R22C31:MIB2_DSP0 MIB_R22C32:MIB_DSP1 MIB_R22C32:MIB2_DSP1 MIB_R22C33:MIB_DSP2 MIB_R22C33:MIB2_DSP2 MIB_R22C34:MIB_DSP3 MIB_R22C34:MIB2_DSP3 MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 +enum: MULT18_0.REG_INPUTA_CLK NONE +enum: MULT18_0.REG_INPUTA_CE CE0 +enum: MULT18_0.REG_INPUTA_RST RST0 +enum: MULT18_0.REG_INPUTB_CLK NONE +enum: MULT18_0.REG_INPUTB_CE CE0 +enum: MULT18_0.REG_INPUTB_RST RST0 +enum: MULT18_0.REG_INPUTC_CLK NONE +enum: MULT18_0.REG_PIPELINE_CLK NONE +enum: MULT18_0.REG_PIPELINE_CE CE0 +enum: MULT18_0.REG_PIPELINE_RST RST0 +enum: MULT18_0.REG_OUTPUT_CLK NONE +enum: MULT18_0.REG_OUTPUT_RST RST0 +enum: MULT18_0.CLK0_DIV ENABLED +enum: MULT18_0.CLK1_DIV ENABLED +enum: MULT18_0.CLK2_DIV ENABLED +enum: MULT18_0.CLK3_DIV ENABLED +enum: MULT18_0.GSR ENABLED +enum: MULT18_0.SOURCEB_MODE B_SHIFT +enum: MULT18_0.RESETMODE SYNC +enum: MULT18_0.MODE MULT18X18D +enum: MULT18_0.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_0.CLK0MUX CLK0 +enum: MULT18_0.CLK1MUX CLK1 +enum: MULT18_0.CLK2MUX CLK2 +enum: MULT18_0.CLK3MUX CLK3 +enum: MULT18_0.CE0MUX CE0 +enum: MULT18_0.CE1MUX CE1 +enum: MULT18_0.CE2MUX CE2 +enum: MULT18_0.CE3MUX CE3 +enum: MULT18_0.RST0MUX RST0 +enum: MULT18_0.RST1MUX RST1 +enum: MULT18_0.RST2MUX RST2 +enum: MULT18_0.RST3MUX RST3 + +.tile_group MIB_R22C60:MIB_DSP0 MIB_R22C60:MIB2_DSP0 MIB_R22C61:MIB_DSP1 MIB_R22C61:MIB2_DSP1 MIB_R22C62:MIB_DSP2 MIB_R22C62:MIB2_DSP2 MIB_R22C63:MIB_DSP3 MIB_R22C63:MIB2_DSP3 MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 +enum: MULT18_0.REG_INPUTA_CLK NONE +enum: MULT18_0.REG_INPUTA_CE CE0 +enum: MULT18_0.REG_INPUTA_RST RST0 +enum: MULT18_0.REG_INPUTB_CLK NONE +enum: MULT18_0.REG_INPUTB_CE CE0 +enum: MULT18_0.REG_INPUTB_RST RST0 +enum: MULT18_0.REG_INPUTC_CLK NONE +enum: MULT18_0.REG_PIPELINE_CLK NONE +enum: MULT18_0.REG_PIPELINE_CE CE0 +enum: MULT18_0.REG_PIPELINE_RST RST0 +enum: MULT18_0.REG_OUTPUT_CLK NONE +enum: MULT18_0.REG_OUTPUT_RST RST0 +enum: MULT18_0.CLK0_DIV ENABLED +enum: MULT18_0.CLK1_DIV ENABLED +enum: MULT18_0.CLK2_DIV ENABLED +enum: MULT18_0.CLK3_DIV ENABLED +enum: MULT18_0.GSR ENABLED +enum: MULT18_0.SOURCEB_MODE B_SHIFT +enum: MULT18_0.RESETMODE SYNC +enum: MULT18_0.MODE MULT18X18D +enum: MULT18_0.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_0.CLK0MUX CLK0 +enum: MULT18_0.CLK1MUX CLK1 +enum: MULT18_0.CLK2MUX CLK2 +enum: MULT18_0.CLK3MUX CLK3 +enum: MULT18_0.CE0MUX CE0 +enum: MULT18_0.CE1MUX CE1 +enum: MULT18_0.CE2MUX CE2 +enum: MULT18_0.CE3MUX CE3 +enum: MULT18_0.RST0MUX RST0 +enum: MULT18_0.RST1MUX RST1 +enum: MULT18_0.RST2MUX RST2 +enum: MULT18_0.RST3MUX RST3 + +.tile_group MIB_R22C42:MIB_DSP0 MIB_R22C42:MIB2_DSP0 MIB_R22C43:MIB_DSP1 MIB_R22C43:MIB2_DSP1 MIB_R22C44:MIB_DSP2 MIB_R22C44:MIB2_DSP2 MIB_R22C45:MIB_DSP3 MIB_R22C45:MIB2_DSP3 MIB_R22C46:MIB_DSP4 MIB_R22C46:MIB2_DSP4 +enum: MULT18_0.REG_INPUTA_CLK NONE +enum: MULT18_0.REG_INPUTA_CE CE0 +enum: MULT18_0.REG_INPUTA_RST RST0 +enum: MULT18_0.REG_INPUTB_CLK NONE +enum: MULT18_0.REG_INPUTB_CE CE0 +enum: MULT18_0.REG_INPUTB_RST RST0 +enum: MULT18_0.REG_INPUTC_CLK NONE +enum: MULT18_0.REG_PIPELINE_CLK NONE +enum: MULT18_0.REG_PIPELINE_CE CE0 +enum: MULT18_0.REG_PIPELINE_RST RST0 +enum: MULT18_0.REG_OUTPUT_CLK NONE +enum: MULT18_0.REG_OUTPUT_RST RST0 +enum: MULT18_0.CLK0_DIV ENABLED +enum: MULT18_0.CLK1_DIV ENABLED +enum: MULT18_0.CLK2_DIV ENABLED +enum: MULT18_0.CLK3_DIV ENABLED +enum: MULT18_0.GSR ENABLED +enum: MULT18_0.SOURCEB_MODE B_SHIFT +enum: MULT18_0.RESETMODE SYNC +enum: MULT18_0.MODE MULT18X18D +enum: MULT18_0.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_0.CLK0MUX CLK0 +enum: MULT18_0.CLK1MUX CLK1 +enum: MULT18_0.CLK2MUX CLK2 +enum: MULT18_0.CLK3MUX CLK3 +enum: MULT18_0.CE0MUX CE0 +enum: MULT18_0.CE1MUX CE1 +enum: MULT18_0.CE2MUX CE2 +enum: MULT18_0.CE3MUX CE3 +enum: MULT18_0.RST0MUX RST0 +enum: MULT18_0.RST1MUX RST1 +enum: MULT18_0.RST2MUX RST2 +enum: MULT18_0.RST3MUX RST3 + +.tile_group MIB_R22C31:MIB_DSP0 MIB_R22C31:MIB2_DSP0 MIB_R22C32:MIB_DSP1 MIB_R22C32:MIB2_DSP1 MIB_R22C33:MIB_DSP2 MIB_R22C33:MIB2_DSP2 MIB_R22C34:MIB_DSP3 MIB_R22C34:MIB2_DSP3 MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 +enum: MULT18_1.REG_INPUTA_CLK NONE +enum: MULT18_1.REG_INPUTA_CE CE0 +enum: MULT18_1.REG_INPUTA_RST RST0 +enum: MULT18_1.REG_INPUTB_CLK NONE +enum: MULT18_1.REG_INPUTB_CE CE0 +enum: MULT18_1.REG_INPUTB_RST RST0 +enum: MULT18_1.REG_INPUTC_CLK NONE +enum: MULT18_1.REG_PIPELINE_CLK NONE +enum: MULT18_1.REG_PIPELINE_CE CE0 +enum: MULT18_1.REG_PIPELINE_RST RST0 +enum: MULT18_1.REG_OUTPUT_CLK NONE +enum: MULT18_1.CLK0_DIV ENABLED +enum: MULT18_1.CLK1_DIV ENABLED +enum: MULT18_1.CLK2_DIV ENABLED +enum: MULT18_1.CLK3_DIV ENABLED +enum: MULT18_1.GSR ENABLED +enum: MULT18_1.SOURCEB_MODE B_SHIFT +enum: MULT18_1.RESETMODE SYNC +enum: MULT18_1.MODE MULT18X18D +enum: MULT18_1.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_1.CLK0MUX CLK0 +enum: MULT18_1.CLK1MUX CLK1 +enum: MULT18_1.CLK2MUX CLK2 +enum: MULT18_1.CLK3MUX CLK3 +enum: MULT18_1.CE0MUX CE0 +enum: MULT18_1.CE1MUX CE1 +enum: MULT18_1.CE2MUX CE2 +enum: MULT18_1.CE3MUX CE3 +enum: MULT18_1.RST0MUX RST0 +enum: MULT18_1.RST1MUX RST1 +enum: MULT18_1.RST2MUX RST2 +enum: MULT18_1.RST3MUX RST3 + +.tile_group MIB_R22C22:MIB_DSP0 MIB_R22C22:MIB2_DSP0 MIB_R22C23:MIB_DSP1 MIB_R22C23:MIB2_DSP1 MIB_R22C24:MIB_DSP2 MIB_R22C24:MIB2_DSP2 MIB_R22C25:MIB_DSP3 MIB_R22C25:MIB2_DSP3 MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 +enum: MULT18_1.REG_INPUTA_CLK NONE +enum: MULT18_1.REG_INPUTA_CE CE0 +enum: MULT18_1.REG_INPUTA_RST RST0 +enum: MULT18_1.REG_INPUTB_CLK NONE +enum: MULT18_1.REG_INPUTB_CE CE0 +enum: MULT18_1.REG_INPUTB_RST RST0 +enum: MULT18_1.REG_INPUTC_CLK NONE +enum: MULT18_1.REG_PIPELINE_CLK NONE +enum: MULT18_1.REG_PIPELINE_CE CE0 +enum: MULT18_1.REG_PIPELINE_RST RST0 +enum: MULT18_1.REG_OUTPUT_CLK NONE +enum: MULT18_1.CLK0_DIV ENABLED +enum: MULT18_1.CLK1_DIV ENABLED +enum: MULT18_1.CLK2_DIV ENABLED +enum: MULT18_1.CLK3_DIV ENABLED +enum: MULT18_1.GSR ENABLED +enum: MULT18_1.SOURCEB_MODE B_SHIFT +enum: MULT18_1.RESETMODE SYNC +enum: MULT18_1.MODE MULT18X18D +enum: MULT18_1.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_1.CLK0MUX CLK0 +enum: MULT18_1.CLK1MUX CLK1 +enum: MULT18_1.CLK2MUX CLK2 +enum: MULT18_1.CLK3MUX CLK3 +enum: MULT18_1.CE0MUX CE0 +enum: MULT18_1.CE1MUX CE1 +enum: MULT18_1.CE2MUX CE2 +enum: MULT18_1.CE3MUX CE3 +enum: MULT18_1.RST0MUX RST0 +enum: MULT18_1.RST1MUX RST1 +enum: MULT18_1.RST2MUX RST2 +enum: MULT18_1.RST3MUX RST3 + +.tile_group MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 MIB_R22C36:MIB_DSP5 MIB_R22C36:MIB2_DSP5 MIB_R22C37:MIB_DSP6 MIB_R22C37:MIB2_DSP6 MIB_R22C38:MIB_DSP7 MIB_R22C38:MIB2_DSP7 MIB_R22C39:MIB_DSP8 MIB_R22C39:MIB2_DSP8 +enum: MULT18_5.REG_INPUTA_CLK NONE +enum: MULT18_5.REG_INPUTA_CE CE0 +enum: MULT18_5.REG_INPUTA_RST RST0 +enum: MULT18_5.REG_INPUTB_CLK NONE +enum: MULT18_5.REG_INPUTB_CE CE0 +enum: MULT18_5.REG_INPUTB_RST RST0 +enum: MULT18_5.REG_INPUTC_CLK NONE +enum: MULT18_5.REG_PIPELINE_CLK NONE +enum: MULT18_5.REG_PIPELINE_CE CE0 +enum: MULT18_5.REG_PIPELINE_RST RST0 +enum: MULT18_5.REG_OUTPUT_CLK NONE +enum: MULT18_5.CLK0_DIV ENABLED +enum: MULT18_5.CLK1_DIV ENABLED +enum: MULT18_5.CLK2_DIV ENABLED +enum: MULT18_5.CLK3_DIV ENABLED +enum: MULT18_5.GSR ENABLED +enum: MULT18_5.SOURCEB_MODE B_SHIFT +enum: MULT18_5.RESETMODE SYNC +enum: MULT18_5.MODE MULT18X18D +enum: MULT18_5.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_5.CLK0MUX CLK0 +enum: MULT18_5.CLK1MUX CLK1 +enum: MULT18_5.CLK2MUX CLK2 +enum: MULT18_5.CLK3MUX CLK3 +enum: MULT18_5.CE0MUX CE0 +enum: MULT18_5.CE1MUX CE1 +enum: MULT18_5.CE2MUX CE2 +enum: MULT18_5.CE3MUX CE3 +enum: MULT18_5.RST0MUX RST0 +enum: MULT18_5.RST1MUX RST1 +enum: MULT18_5.RST2MUX RST2 +enum: MULT18_5.RST3MUX RST3 + +.tile_group MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4 MIB_R22C56:MIB_DSP5 MIB_R22C56:MIB2_DSP5 MIB_R22C57:MIB_DSP6 MIB_R22C57:MIB2_DSP6 MIB_R22C58:MIB_DSP7 MIB_R22C58:MIB2_DSP7 MIB_R22C59:MIB_DSP8 MIB_R22C59:MIB2_DSP8 +enum: MULT18_5.REG_INPUTA_CLK NONE +enum: MULT18_5.REG_INPUTA_CE CE0 +enum: MULT18_5.REG_INPUTA_RST RST0 +enum: MULT18_5.REG_INPUTB_CLK NONE +enum: MULT18_5.REG_INPUTB_CE CE0 +enum: MULT18_5.REG_INPUTB_RST RST0 +enum: MULT18_5.REG_INPUTC_CLK NONE +enum: MULT18_5.REG_PIPELINE_CLK NONE +enum: MULT18_5.REG_PIPELINE_CE CE0 +enum: MULT18_5.REG_PIPELINE_RST RST0 +enum: MULT18_5.REG_OUTPUT_CLK NONE +enum: MULT18_5.CLK0_DIV ENABLED +enum: MULT18_5.CLK1_DIV ENABLED +enum: MULT18_5.CLK2_DIV ENABLED +enum: MULT18_5.CLK3_DIV ENABLED +enum: MULT18_5.GSR ENABLED +enum: MULT18_5.SOURCEB_MODE B_SHIFT +enum: MULT18_5.RESETMODE SYNC +enum: MULT18_5.MODE MULT18X18D +enum: MULT18_5.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_5.CLK0MUX CLK0 +enum: MULT18_5.CLK1MUX CLK1 +enum: MULT18_5.CLK2MUX CLK2 +enum: MULT18_5.CLK3MUX CLK3 +enum: MULT18_5.CE0MUX CE0 +enum: MULT18_5.CE1MUX CE1 +enum: MULT18_5.CE2MUX CE2 +enum: MULT18_5.CE3MUX CE3 +enum: MULT18_5.RST0MUX RST0 +enum: MULT18_5.RST1MUX RST1 +enum: MULT18_5.RST2MUX RST2 +enum: MULT18_5.RST3MUX RST3 + +.tile_group MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 MIB_R22C65:MIB_DSP5 MIB_R22C65:MIB2_DSP5 MIB_R22C66:MIB_DSP6 MIB_R22C66:MIB2_DSP6 MIB_R22C67:MIB_DSP7 MIB_R22C67:MIB2_DSP7 MIB_R22C68:MIB_DSP8 MIB_R22C68:MIB2_DSP8 +enum: MULT18_5.REG_INPUTA_CLK NONE +enum: MULT18_5.REG_INPUTA_CE CE0 +enum: MULT18_5.REG_INPUTA_RST RST0 +enum: MULT18_5.REG_INPUTB_CLK NONE +enum: MULT18_5.REG_INPUTB_CE CE0 +enum: MULT18_5.REG_INPUTB_RST RST0 +enum: MULT18_5.REG_INPUTC_CLK NONE +enum: MULT18_5.REG_PIPELINE_CLK NONE +enum: MULT18_5.REG_PIPELINE_CE CE0 +enum: MULT18_5.REG_PIPELINE_RST RST0 +enum: MULT18_5.REG_OUTPUT_CLK NONE +enum: MULT18_5.CLK0_DIV ENABLED +enum: MULT18_5.CLK1_DIV ENABLED +enum: MULT18_5.CLK2_DIV ENABLED +enum: MULT18_5.CLK3_DIV ENABLED +enum: MULT18_5.GSR ENABLED +enum: MULT18_5.SOURCEB_MODE B_SHIFT +enum: MULT18_5.RESETMODE SYNC +enum: MULT18_5.MODE MULT18X18D +enum: MULT18_5.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_5.CLK0MUX CLK0 +enum: MULT18_5.CLK1MUX CLK1 +enum: MULT18_5.CLK2MUX CLK2 +enum: MULT18_5.CLK3MUX CLK3 +enum: MULT18_5.CE0MUX CE0 +enum: MULT18_5.CE1MUX CE1 +enum: MULT18_5.CE2MUX CE2 +enum: MULT18_5.CE3MUX CE3 +enum: MULT18_5.RST0MUX RST0 +enum: MULT18_5.RST1MUX RST1 +enum: MULT18_5.RST2MUX RST2 +enum: MULT18_5.RST3MUX RST3 + +.tile_group MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4 MIB_R22C56:MIB_DSP5 MIB_R22C56:MIB2_DSP5 MIB_R22C57:MIB_DSP6 MIB_R22C57:MIB2_DSP6 MIB_R22C58:MIB_DSP7 MIB_R22C58:MIB2_DSP7 MIB_R22C59:MIB_DSP8 MIB_R22C59:MIB2_DSP8 +enum: MULT18_4.REG_INPUTA_CLK NONE +enum: MULT18_4.REG_INPUTA_CE CE0 +enum: MULT18_4.REG_INPUTA_RST RST0 +enum: MULT18_4.REG_INPUTB_CLK NONE +enum: MULT18_4.REG_INPUTB_CE CE0 +enum: MULT18_4.REG_INPUTB_RST RST0 +enum: MULT18_4.REG_INPUTC_CLK NONE +enum: MULT18_4.REG_PIPELINE_CLK NONE +enum: MULT18_4.REG_PIPELINE_CE CE0 +enum: MULT18_4.REG_PIPELINE_RST RST0 +enum: MULT18_4.REG_OUTPUT_CLK NONE +enum: MULT18_4.REG_OUTPUT_RST RST0 +enum: MULT18_4.CLK0_DIV ENABLED +enum: MULT18_4.CLK1_DIV ENABLED +enum: MULT18_4.CLK2_DIV ENABLED +enum: MULT18_4.CLK3_DIV ENABLED +enum: MULT18_4.GSR ENABLED +enum: MULT18_4.SOURCEB_MODE B_SHIFT +enum: MULT18_4.RESETMODE SYNC +enum: MULT18_4.MODE MULT18X18D +enum: MULT18_4.CIBOUT_BYP ON +enum: DSP_RIGHT.CIBOUT ON +enum: MULT18_4.CLK0MUX CLK0 +enum: MULT18_4.CLK1MUX CLK1 +enum: MULT18_4.CLK2MUX CLK2 +enum: MULT18_4.CLK3MUX CLK3 +enum: MULT18_4.CE0MUX CE0 +enum: MULT18_4.CE1MUX CE1 +enum: MULT18_4.CE2MUX CE2 +enum: MULT18_4.CE3MUX CE3 +enum: MULT18_4.RST0MUX RST0 +enum: MULT18_4.RST1MUX RST1 +enum: MULT18_4.RST2MUX RST2 +enum: MULT18_4.RST3MUX RST3 + +.tile_group MIB_R22C69:MIB_DSP0 MIB_R22C69:MIB2_DSP0 MIB_R22C70:MIB_DSP1 MIB_R22C70:MIB2_DSP1 MIB_R22C71:MIB_DSP2 MIB_R22C71:MIB2_DSP2 MIB_R22C72:MIB_DSP3 MIB_R22C72:MIB2_DSP3 MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 +enum: MULT18_0.REG_INPUTA_CLK NONE +enum: MULT18_0.REG_INPUTA_CE CE0 +enum: MULT18_0.REG_INPUTA_RST RST0 +enum: MULT18_0.REG_INPUTB_CLK NONE +enum: MULT18_0.REG_INPUTB_CE CE0 +enum: MULT18_0.REG_INPUTB_RST RST0 +enum: MULT18_0.REG_INPUTC_CLK NONE +enum: MULT18_0.REG_PIPELINE_CLK NONE +enum: MULT18_0.REG_PIPELINE_CE CE0 +enum: MULT18_0.REG_PIPELINE_RST RST0 +enum: MULT18_0.REG_OUTPUT_CLK NONE +enum: MULT18_0.REG_OUTPUT_RST RST0 +enum: MULT18_0.CLK0_DIV ENABLED +enum: MULT18_0.CLK1_DIV ENABLED +enum: MULT18_0.CLK2_DIV ENABLED +enum: MULT18_0.CLK3_DIV ENABLED +enum: MULT18_0.GSR ENABLED +enum: MULT18_0.SOURCEB_MODE B_SHIFT +enum: MULT18_0.RESETMODE SYNC +enum: MULT18_0.MODE MULT18X18D +enum: MULT18_0.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_0.CLK0MUX CLK0 +enum: MULT18_0.CLK1MUX CLK1 +enum: MULT18_0.CLK2MUX CLK2 +enum: MULT18_0.CLK3MUX CLK3 +enum: MULT18_0.CE0MUX CE0 +enum: MULT18_0.CE1MUX CE1 +enum: MULT18_0.CE2MUX CE2 +enum: MULT18_0.CE3MUX CE3 +enum: MULT18_0.RST0MUX RST0 +enum: MULT18_0.RST1MUX RST1 +enum: MULT18_0.RST2MUX RST2 +enum: MULT18_0.RST3MUX RST3 + +.tile_group MIB_R22C51:MIB_DSP0 MIB_R22C51:MIB2_DSP0 MIB_R22C52:MIB_DSP1 MIB_R22C52:MIB2_DSP1 MIB_R22C53:MIB_DSP2 MIB_R22C53:MIB2_DSP2 MIB_R22C54:MIB_DSP3 MIB_R22C54:MIB2_DSP3 MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4 +enum: MULT18_1.REG_INPUTA_CLK NONE +enum: MULT18_1.REG_INPUTA_CE CE0 +enum: MULT18_1.REG_INPUTA_RST RST0 +enum: MULT18_1.REG_INPUTB_CLK NONE +enum: MULT18_1.REG_INPUTB_CE CE0 +enum: MULT18_1.REG_INPUTB_RST RST0 +enum: MULT18_1.REG_INPUTC_CLK NONE +enum: MULT18_1.REG_PIPELINE_CLK NONE +enum: MULT18_1.REG_PIPELINE_CE CE0 +enum: MULT18_1.REG_PIPELINE_RST RST0 +enum: MULT18_1.REG_OUTPUT_CLK NONE +enum: MULT18_1.CLK0_DIV ENABLED +enum: MULT18_1.CLK1_DIV ENABLED +enum: MULT18_1.CLK2_DIV ENABLED +enum: MULT18_1.CLK3_DIV ENABLED +enum: MULT18_1.GSR ENABLED +enum: MULT18_1.SOURCEB_MODE B_SHIFT +enum: MULT18_1.RESETMODE SYNC +enum: MULT18_1.MODE MULT18X18D +enum: MULT18_1.CIBOUT_BYP ON +enum: DSP_LEFT.CIBOUT ON +enum: MULT18_1.CLK0MUX CLK0 +enum: MULT18_1.CLK1MUX CLK1 +enum: MULT18_1.CLK2MUX CLK2 +enum: MULT18_1.CLK3MUX CLK3 +enum: MULT18_1.CE0MUX CE0 +enum: MULT18_1.CE1MUX CE1 +enum: MULT18_1.CE2MUX CE2 +enum: MULT18_1.CE3MUX CE3 +enum: MULT18_1.RST0MUX RST0 +enum: MULT18_1.RST1MUX RST1 +enum: MULT18_1.RST2MUX RST2 +enum: MULT18_1.RST3MUX RST3 + diff --git a/synth/ecp5/p4/top.json b/synth/ecp5/p4/top.json new file mode 100644 index 0000000..f4f108f --- /dev/null +++ b/synth/ecp5/p4/top.json @@ -0,0 +1,57007 @@ +{ + "creator": "Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)", + "modules": { + "$__ABC9_DELAY": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000011", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.1-7.10" + }, + "parameter_default_values": { + "DELAY": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + "$specify$7435": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000000000000", + "T_FALL_MIN": "00000000000000000000000000000000", + "T_FALL_TYP": "00000000000000000000000000000000", + "T_RISE_MAX": "00000000000000000000000000000000", + "T_RISE_MIN": "00000000000000000000000000000000", + "T_RISE_TYP": "00000000000000000000000000000000" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:5.5-5.22" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 3 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + } + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.29-2.30" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.39-2.40" + } + } + } + }, + "$__ABC9_SCC_BREAKER": { + "attributes": { + "dynports": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.1-11.10" + }, + "parameter_default_values": { + "WIDTH": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "offset": -1, + "upto": 1, + "bits": [ 2, 3 ] + }, + "O": { + "direction": "output", + "offset": -1, + "upto": 1, + "bits": [ 4, 5 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2, 3 ], + "offset": -1, + "upto": 1, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.47-9.48" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4, 5 ], + "offset": -1, + "upto": 1, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.69-9.70" + } + } + } + }, + "$__DFF_N__$abc9_flop": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000010", + "blackbox": "00000000000000000000000000000001", + "abc9_flop": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.1-20.10" + }, + "ports": { + "C": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "input", + "bits": [ 4 ] + }, + "n1": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "C": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.36-14.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.39-14.40" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.42-14.43" + } + }, + "n1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.52-14.54" + } + } + } + }, + "$__DFF_P__$abc9_flop": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "abc9_flop": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.1-29.10" + }, + "ports": { + "C": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "input", + "bits": [ 4 ] + }, + "n1": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "C": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.36-23.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.39-23.40" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.42-23.43" + } + }, + "n1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.52-23.54" + } + } + } + }, + "$paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\\CCU2C": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000100", + "blackbox": "00000000000000000000000000000001", + "hdlname": "CCU2C", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:3.1-61.10" + }, + "parameter_default_values": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "ports": { + "CIN": { + "direction": "input", + "bits": [ 2 ] + }, + "A0": { + "direction": "input", + "bits": [ 3 ] + }, + "B0": { + "direction": "input", + "bits": [ 4 ] + }, + "C0": { + "direction": "input", + "bits": [ 5 ] + }, + "D0": { + "direction": "input", + "bits": [ 6 ] + }, + "A1": { + "direction": "input", + "bits": [ 7 ] + }, + "B1": { + "direction": "input", + "bits": [ 8 ] + }, + "C1": { + "direction": "input", + "bits": [ 9 ] + }, + "D1": { + "direction": "input", + "bits": [ 10 ] + }, + "S0": { + "direction": "output", + "bits": [ 11 ] + }, + "S1": { + "direction": "output", + "bits": [ 12 ] + }, + "COUT": { + "direction": "output", + "bits": [ 13 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.9-6.11" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.25-6.27" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.13-6.15" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.29-6.31" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.17-6.19" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.33-6.35" + } + }, + "CIN": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:5.9-5.12" + } + }, + "COUT": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "D0": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.21-6.23" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.37-6.39" + } + }, + "S0": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.9-7.11" + } + }, + "S1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.13-7.15" + } + } + } + }, + "\\$__ABC9_LUT5": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000000010", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.1-30.10" + }, + "ports": { + "M0": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "C": { + "direction": "input", + "bits": [ 4 ] + }, + "B": { + "direction": "input", + "bits": [ 5 ] + }, + "A": { + "direction": "input", + "bits": [ 6 ] + }, + "Z": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + "$specify$335": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000010010111", + "T_FALL_MIN": "00000000000000000000000010010111", + "T_FALL_TYP": "00000000000000000000000010010111", + "T_RISE_MAX": "00000000000000000000000010010111", + "T_RISE_MIN": "00000000000000000000000010010111", + "T_RISE_TYP": "00000000000000000000000010010111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:24.9-24.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + }, + "$specify$336": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000011101111", + "T_FALL_MIN": "00000000000000000000000011101111", + "T_FALL_TYP": "00000000000000000000000011101111", + "T_RISE_MAX": "00000000000000000000000011101111", + "T_RISE_MIN": "00000000000000000000000011101111", + "T_RISE_TYP": "00000000000000000000000011101111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:25.9-25.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 3 ] + } + }, + "$specify$337": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000101110101", + "T_FALL_MIN": "00000000000000000000000101110101", + "T_FALL_TYP": "00000000000000000000000101110101", + "T_RISE_MAX": "00000000000000000000000101110101", + "T_RISE_MIN": "00000000000000000000000101110101", + "T_RISE_TYP": "00000000000000000000000101110101" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:26.9-26.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 4 ] + } + }, + "$specify$338": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000111011101", + "T_FALL_MIN": "00000000000000000000000111011101", + "T_FALL_TYP": "00000000000000000000000111011101", + "T_RISE_MAX": "00000000000000000000000111011101", + "T_RISE_MIN": "00000000000000000000000111011101", + "T_RISE_TYP": "00000000000000000000000111011101" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:27.9-27.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 5 ] + } + }, + "$specify$339": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000111011101", + "T_FALL_MIN": "00000000000000000000000111011101", + "T_FALL_TYP": "00000000000000000000000111011101", + "T_RISE_MAX": "00000000000000000000000111011101", + "T_RISE_MIN": "00000000000000000000000111011101", + "T_RISE_TYP": "00000000000000000000000111011101" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:28.9-28.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 6 ] + } + } + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.42-22.43" + } + }, + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.39-22.40" + } + }, + "C": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.36-22.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.33-22.34" + } + }, + "M0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.29-22.31" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.52-22.53" + } + } + } + }, + "\\$__ABC9_LUT6": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000000100", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.1-45.10" + }, + "ports": { + "M1": { + "direction": "input", + "bits": [ 2 ] + }, + "M0": { + "direction": "input", + "bits": [ 3 ] + }, + "D": { + "direction": "input", + "bits": [ 4 ] + }, + "C": { + "direction": "input", + "bits": [ 5 ] + }, + "B": { + "direction": "input", + "bits": [ 6 ] + }, + "A": { + "direction": "input", + "bits": [ 7 ] + }, + "Z": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + "$specify$340": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000010010100", + "T_FALL_MIN": "00000000000000000000000010010100", + "T_FALL_TYP": "00000000000000000000000010010100", + "T_RISE_MAX": "00000000000000000000000010010100", + "T_RISE_MIN": "00000000000000000000000010010100", + "T_RISE_TYP": "00000000000000000000000010010100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:38.9-38.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + }, + "$specify$341": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000100100100", + "T_FALL_MIN": "00000000000000000000000100100100", + "T_FALL_TYP": "00000000000000000000000100100100", + "T_RISE_MAX": "00000000000000000000000100100100", + "T_RISE_MIN": "00000000000000000000000100100100", + "T_RISE_TYP": "00000000000000000000000100100100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:39.9-39.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 3 ] + } + }, + "$specify$342": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000101111100", + "T_FALL_MIN": "00000000000000000000000101111100", + "T_FALL_TYP": "00000000000000000000000101111100", + "T_RISE_MAX": "00000000000000000000000101111100", + "T_RISE_MIN": "00000000000000000000000101111100", + "T_RISE_TYP": "00000000000000000000000101111100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:40.9-40.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 4 ] + } + }, + "$specify$343": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001000000010", + "T_FALL_MIN": "00000000000000000000001000000010", + "T_FALL_TYP": "00000000000000000000001000000010", + "T_RISE_MAX": "00000000000000000000001000000010", + "T_RISE_MIN": "00000000000000000000001000000010", + "T_RISE_TYP": "00000000000000000000001000000010" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:41.9-41.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 5 ] + } + }, + "$specify$344": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001001101010", + "T_FALL_MIN": "00000000000000000000001001101010", + "T_FALL_TYP": "00000000000000000000001001101010", + "T_RISE_MAX": "00000000000000000000001001101010", + "T_RISE_MIN": "00000000000000000000001001101010", + "T_RISE_TYP": "00000000000000000000001001101010" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:42.9-42.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 6 ] + } + }, + "$specify$345": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001001101010", + "T_FALL_MIN": "00000000000000000000001001101010", + "T_FALL_TYP": "00000000000000000000001001101010", + "T_RISE_MAX": "00000000000000000000001001101010", + "T_RISE_MIN": "00000000000000000000001001101010", + "T_RISE_TYP": "00000000000000000000001001101010" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:43.9-43.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 7 ] + } + } + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.46-36.47" + } + }, + "B": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.43-36.44" + } + }, + "C": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.40-36.41" + } + }, + "D": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.37-36.38" + } + }, + "M0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.33-36.35" + } + }, + "M1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.29-36.31" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.56-36.57" + } + } + } + }, + "\\$__ABC9_LUT7": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000001000", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.1-61.10" + }, + "ports": { + "M2": { + "direction": "input", + "bits": [ 2 ] + }, + "M1": { + "direction": "input", + "bits": [ 3 ] + }, + "M0": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "C": { + "direction": "input", + "bits": [ 6 ] + }, + "B": { + "direction": "input", + "bits": [ 7 ] + }, + "A": { + "direction": "input", + "bits": [ 8 ] + }, + "Z": { + "direction": "output", + "bits": [ 9 ] + } + }, + "cells": { + "$specify$346": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000010010100", + "T_FALL_MIN": "00000000000000000000000010010100", + "T_FALL_TYP": "00000000000000000000000010010100", + "T_RISE_MAX": "00000000000000000000000010010100", + "T_RISE_MIN": "00000000000000000000000010010100", + "T_RISE_TYP": "00000000000000000000000010010100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:53.9-53.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + }, + "$specify$347": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000100100001", + "T_FALL_MIN": "00000000000000000000000100100001", + "T_FALL_TYP": "00000000000000000000000100100001", + "T_RISE_MAX": "00000000000000000000000100100001", + "T_RISE_MIN": "00000000000000000000000100100001", + "T_RISE_TYP": "00000000000000000000000100100001" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:54.9-54.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 3 ] + } + }, + "$specify$348": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000110110001", + "T_FALL_MIN": "00000000000000000000000110110001", + "T_FALL_TYP": "00000000000000000000000110110001", + "T_RISE_MAX": "00000000000000000000000110110001", + "T_RISE_MIN": "00000000000000000000000110110001", + "T_RISE_TYP": "00000000000000000000000110110001" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:55.9-55.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 4 ] + } + }, + "$specify$349": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001000001001", + "T_FALL_MIN": "00000000000000000000001000001001", + "T_FALL_TYP": "00000000000000000000001000001001", + "T_RISE_MAX": "00000000000000000000001000001001", + "T_RISE_MIN": "00000000000000000000001000001001", + "T_RISE_TYP": "00000000000000000000001000001001" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:56.9-56.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 5 ] + } + }, + "$specify$350": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001010001111", + "T_FALL_MIN": "00000000000000000000001010001111", + "T_FALL_TYP": "00000000000000000000001010001111", + "T_RISE_MAX": "00000000000000000000001010001111", + "T_RISE_MIN": "00000000000000000000001010001111", + "T_RISE_TYP": "00000000000000000000001010001111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:57.9-57.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 6 ] + } + }, + "$specify$351": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001011110111", + "T_FALL_MIN": "00000000000000000000001011110111", + "T_FALL_TYP": "00000000000000000000001011110111", + "T_RISE_MAX": "00000000000000000000001011110111", + "T_RISE_MIN": "00000000000000000000001011110111", + "T_RISE_TYP": "00000000000000000000001011110111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:58.9-58.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 7 ] + } + }, + "$specify$352": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001011110111", + "T_FALL_MIN": "00000000000000000000001011110111", + "T_FALL_TYP": "00000000000000000000001011110111", + "T_RISE_MAX": "00000000000000000000001011110111", + "T_RISE_MIN": "00000000000000000000001011110111", + "T_RISE_TYP": "00000000000000000000001011110111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:59.9-59.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 8 ] + } + } + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.50-51.51" + } + }, + "B": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.47-51.48" + } + }, + "C": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.44-51.45" + } + }, + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.41-51.42" + } + }, + "M0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.37-51.39" + } + }, + "M1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.33-51.35" + } + }, + "M2": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.29-51.31" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.60-51.61" + } + } + } + }, + "ALU54B": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:489.1-1007.10" + }, + "parameter_default_values": { + "CLK0_DIV": "ENABLED", + "CLK1_DIV": "ENABLED", + "CLK2_DIV": "ENABLED", + "CLK3_DIV": "ENABLED", + "FORCE_ZERO_BARREL_SHIFT": "DISABLED", + "GSR": "ENABLED", + "LEGACY": "DISABLED", + "MASK01": "0x00000000000000 ", + "MASKPAT": "0x00000000000000 ", + "MASKPAT_SOURCE": "STATIC", + "MCPAT": "0x00000000000000 ", + "MCPAT_SOURCE": "STATIC", + "MULT9_MODE": "DISABLED", + "REG_FLAG_CE": "CE0", + "REG_FLAG_CLK": "NONE", + "REG_FLAG_RST": "RST0", + "REG_INPUTC0_CE": "CE0", + "REG_INPUTC0_CLK": "NONE", + "REG_INPUTC0_RST": "RST0", + "REG_INPUTC1_CE": "CE0", + "REG_INPUTC1_CLK": "NONE", + "REG_INPUTC1_RST": "RST0", + "REG_INPUTCFB_CE": "CE0", + "REG_INPUTCFB_CLK": "NONE", + "REG_INPUTCFB_RST": "RST0", + "REG_OPCODEIN_0_CE": "CE0", + "REG_OPCODEIN_0_CLK": "NONE", + "REG_OPCODEIN_0_RST": "RST0", + "REG_OPCODEIN_1_CE": "CE0", + "REG_OPCODEIN_1_CLK": "NONE", + "REG_OPCODEIN_1_RST": "RST0", + "REG_OPCODEOP0_0_CE": "CE0", + "REG_OPCODEOP0_0_CLK": "NONE", + "REG_OPCODEOP0_0_RST": "RST0", + "REG_OPCODEOP0_1_CE": "CE0", + "REG_OPCODEOP0_1_CLK": "NONE", + "REG_OPCODEOP0_1_RST": "RST0", + "REG_OPCODEOP1_0_CLK": "NONE", + "REG_OPCODEOP1_1_CLK": "NONE", + "REG_OUTPUT0_CE": "CE0", + "REG_OUTPUT0_CLK": "NONE", + "REG_OUTPUT0_RST": "RST0", + "REG_OUTPUT1_CE": "CE0", + "REG_OUTPUT1_CLK": "NONE", + "REG_OUTPUT1_RST": "RST0", + "RESETMODE": "SYNC", + "RNDPAT": "0x00000000000000 " + }, + "ports": { + "CE3": { + "direction": "input", + "bits": [ 2 ] + }, + "CE2": { + "direction": "input", + "bits": [ 3 ] + }, + "CE1": { + "direction": "input", + "bits": [ 4 ] + }, + "CE0": { + "direction": "input", + "bits": [ 5 ] + }, + "CLK3": { + "direction": "input", + "bits": [ 6 ] + }, + "CLK2": { + "direction": "input", + "bits": [ 7 ] + }, + "CLK1": { + "direction": "input", + "bits": [ 8 ] + }, + "CLK0": { + "direction": "input", + "bits": [ 9 ] + }, + "RST3": { + "direction": "input", + "bits": [ 10 ] + }, + "RST2": { + "direction": "input", + "bits": [ 11 ] + }, + "RST1": { + "direction": "input", + "bits": [ 12 ] + }, + "RST0": { + "direction": "input", + "bits": [ 13 ] + }, + "SIGNEDIA": { + "direction": "input", + "bits": [ 14 ] + }, + "SIGNEDIB": { + "direction": "input", + "bits": [ 15 ] + }, + "SIGNEDCIN": { + "direction": "input", + "bits": [ 16 ] + }, + "A35": { + "direction": "input", + "bits": [ 17 ] + }, + "A34": { + "direction": "input", + "bits": [ 18 ] + }, + "A33": { + "direction": "input", + "bits": [ 19 ] + }, + "A32": { + "direction": "input", + "bits": [ 20 ] + }, + "A31": { + "direction": "input", + "bits": [ 21 ] + }, + "A30": { + "direction": "input", + "bits": [ 22 ] + }, + "A29": { + "direction": "input", + "bits": [ 23 ] + }, + "A28": { + "direction": "input", + "bits": [ 24 ] + }, + "A27": { + "direction": "input", + "bits": [ 25 ] + }, + "A26": { + "direction": "input", + "bits": [ 26 ] + }, + "A25": { + "direction": "input", + "bits": [ 27 ] + }, + "A24": { + "direction": "input", + "bits": [ 28 ] + }, + "A23": { + "direction": "input", + "bits": [ 29 ] + }, + "A22": { + "direction": "input", + "bits": [ 30 ] + }, + "A21": { + "direction": "input", + "bits": [ 31 ] + }, + "A20": { + "direction": "input", + "bits": [ 32 ] + }, + "A19": { + "direction": "input", + "bits": [ 33 ] + }, + "A18": { + "direction": "input", + "bits": [ 34 ] + }, + "A17": { + "direction": "input", + "bits": [ 35 ] + }, + "A16": { + "direction": "input", + "bits": [ 36 ] + }, + "A15": { + "direction": "input", + "bits": [ 37 ] + }, + "A14": { + "direction": "input", + "bits": [ 38 ] + }, + "A13": { + "direction": "input", + "bits": [ 39 ] + }, + "A12": { + "direction": "input", + "bits": [ 40 ] + }, + "A11": { + "direction": "input", + "bits": [ 41 ] + }, + "A10": { + "direction": "input", + "bits": [ 42 ] + }, + "A9": { + "direction": "input", + "bits": [ 43 ] + }, + "A8": { + "direction": "input", + "bits": [ 44 ] + }, + "A7": { + "direction": "input", + "bits": [ 45 ] + }, + "A6": { + "direction": "input", + "bits": [ 46 ] + }, + "A5": { + "direction": "input", + "bits": [ 47 ] + }, + "A4": { + "direction": "input", + "bits": [ 48 ] + }, + "A3": { + "direction": "input", + "bits": [ 49 ] + }, + "A2": { + "direction": "input", + "bits": [ 50 ] + }, + "A1": { + "direction": "input", + "bits": [ 51 ] + }, + "A0": { + "direction": "input", + "bits": [ 52 ] + }, + "B35": { + "direction": "input", + "bits": [ 53 ] + }, + "B34": { + "direction": "input", + "bits": [ 54 ] + }, + "B33": { + "direction": "input", + "bits": [ 55 ] + }, + "B32": { + "direction": "input", + "bits": [ 56 ] + }, + "B31": { + "direction": "input", + "bits": [ 57 ] + }, + "B30": { + "direction": "input", + "bits": [ 58 ] + }, + "B29": { + "direction": "input", + "bits": [ 59 ] + }, + "B28": { + "direction": "input", + "bits": [ 60 ] + }, + "B27": { + "direction": "input", + "bits": [ 61 ] + }, + "B26": { + "direction": "input", + "bits": [ 62 ] + }, + "B25": { + "direction": "input", + "bits": [ 63 ] + }, + "B24": { + "direction": "input", + "bits": [ 64 ] + }, + "B23": { + "direction": "input", + "bits": [ 65 ] + }, + "B22": { + "direction": "input", + "bits": [ 66 ] + }, + "B21": { + "direction": "input", + "bits": [ 67 ] + }, + "B20": { + "direction": "input", + "bits": [ 68 ] + }, + "B19": { + "direction": "input", + "bits": [ 69 ] + }, + "B18": { + "direction": "input", + "bits": [ 70 ] + }, + "B17": { + "direction": "input", + "bits": [ 71 ] + }, + "B16": { + "direction": "input", + "bits": [ 72 ] + }, + "B15": { + "direction": "input", + "bits": [ 73 ] + }, + "B14": { + "direction": "input", + "bits": [ 74 ] + }, + "B13": { + "direction": "input", + "bits": [ 75 ] + }, + "B12": { + "direction": "input", + "bits": [ 76 ] + }, + "B11": { + "direction": "input", + "bits": [ 77 ] + }, + "B10": { + "direction": "input", + "bits": [ 78 ] + }, + "B9": { + "direction": "input", + "bits": [ 79 ] + }, + "B8": { + "direction": "input", + "bits": [ 80 ] + }, + "B7": { + "direction": "input", + "bits": [ 81 ] + }, + "B6": { + "direction": "input", + "bits": [ 82 ] + }, + "B5": { + "direction": "input", + "bits": [ 83 ] + }, + "B4": { + "direction": "input", + "bits": [ 84 ] + }, + "B3": { + "direction": "input", + "bits": [ 85 ] + }, + "B2": { + "direction": "input", + "bits": [ 86 ] + }, + "B1": { + "direction": "input", + "bits": [ 87 ] + }, + "B0": { + "direction": "input", + "bits": [ 88 ] + }, + "C53": { + "direction": "input", + "bits": [ 89 ] + }, + "C52": { + "direction": "input", + "bits": [ 90 ] + }, + "C51": { + "direction": "input", + "bits": [ 91 ] + }, + "C50": { + "direction": "input", + "bits": [ 92 ] + }, + "C49": { + "direction": "input", + "bits": [ 93 ] + }, + "C48": { + "direction": "input", + "bits": [ 94 ] + }, + "C47": { + "direction": "input", + "bits": [ 95 ] + }, + "C46": { + "direction": "input", + "bits": [ 96 ] + }, + "C45": { + "direction": "input", + "bits": [ 97 ] + }, + "C44": { + "direction": "input", + "bits": [ 98 ] + }, + "C43": { + "direction": "input", + "bits": [ 99 ] + }, + "C42": { + "direction": "input", + "bits": [ 100 ] + }, + "C41": { + "direction": "input", + "bits": [ 101 ] + }, + "C40": { + "direction": "input", + "bits": [ 102 ] + }, + "C39": { + "direction": "input", + "bits": [ 103 ] + }, + "C38": { + "direction": "input", + "bits": [ 104 ] + }, + "C37": { + "direction": "input", + "bits": [ 105 ] + }, + "C36": { + "direction": "input", + "bits": [ 106 ] + }, + "C35": { + "direction": "input", + "bits": [ 107 ] + }, + "C34": { + "direction": "input", + "bits": [ 108 ] + }, + "C33": { + "direction": "input", + "bits": [ 109 ] + }, + "C32": { + "direction": "input", + "bits": [ 110 ] + }, + "C31": { + "direction": "input", + "bits": [ 111 ] + }, + "C30": { + "direction": "input", + "bits": [ 112 ] + }, + "C29": { + "direction": "input", + "bits": [ 113 ] + }, + "C28": { + "direction": "input", + "bits": [ 114 ] + }, + "C27": { + "direction": "input", + "bits": [ 115 ] + }, + "C26": { + "direction": "input", + "bits": [ 116 ] + }, + "C25": { + "direction": "input", + "bits": [ 117 ] + }, + "C24": { + "direction": "input", + "bits": [ 118 ] + }, + "C23": { + "direction": "input", + "bits": [ 119 ] + }, + "C22": { + "direction": "input", + "bits": [ 120 ] + }, + "C21": { + "direction": "input", + "bits": [ 121 ] + }, + "C20": { + "direction": "input", + "bits": [ 122 ] + }, + "C19": { + "direction": "input", + "bits": [ 123 ] + }, + "C18": { + "direction": "input", + "bits": [ 124 ] + }, + "C17": { + "direction": "input", + "bits": [ 125 ] + }, + "C16": { + "direction": "input", + "bits": [ 126 ] + }, + "C15": { + "direction": "input", + "bits": [ 127 ] + }, + "C14": { + "direction": "input", + "bits": [ 128 ] + }, + "C13": { + "direction": "input", + "bits": [ 129 ] + }, + "C12": { + "direction": "input", + "bits": [ 130 ] + }, + "C11": { + "direction": "input", + "bits": [ 131 ] + }, + "C10": { + "direction": "input", + "bits": [ 132 ] + }, + "C9": { + "direction": "input", + "bits": [ 133 ] + }, + "C8": { + "direction": "input", + "bits": [ 134 ] + }, + "C7": { + "direction": "input", + "bits": [ 135 ] + }, + "C6": { + "direction": "input", + "bits": [ 136 ] + }, + "C5": { + "direction": "input", + "bits": [ 137 ] + }, + "C4": { + "direction": "input", + "bits": [ 138 ] + }, + "C3": { + "direction": "input", + "bits": [ 139 ] + }, + "C2": { + "direction": "input", + "bits": [ 140 ] + }, + "C1": { + "direction": "input", + "bits": [ 141 ] + }, + "C0": { + "direction": "input", + "bits": [ 142 ] + }, + "CFB53": { + "direction": "input", + "bits": [ 143 ] + }, + "CFB52": { + "direction": "input", + "bits": [ 144 ] + }, + "CFB51": { + "direction": "input", + "bits": [ 145 ] + }, + "CFB50": { + "direction": "input", + "bits": [ 146 ] + }, + "CFB49": { + "direction": "input", + "bits": [ 147 ] + }, + "CFB48": { + "direction": "input", + "bits": [ 148 ] + }, + "CFB47": { + "direction": "input", + "bits": [ 149 ] + }, + "CFB46": { + "direction": "input", + "bits": [ 150 ] + }, + "CFB45": { + "direction": "input", + "bits": [ 151 ] + }, + "CFB44": { + "direction": "input", + "bits": [ 152 ] + }, + "CFB43": { + "direction": "input", + "bits": [ 153 ] + }, + "CFB42": { + "direction": "input", + "bits": [ 154 ] + }, + "CFB41": { + "direction": "input", + "bits": [ 155 ] + }, + "CFB40": { + "direction": "input", + "bits": [ 156 ] + }, + "CFB39": { + "direction": "input", + "bits": [ 157 ] + }, + "CFB38": { + "direction": "input", + "bits": [ 158 ] + }, + "CFB37": { + "direction": "input", + "bits": [ 159 ] + }, + "CFB36": { + "direction": "input", + "bits": [ 160 ] + }, + "CFB35": { + "direction": "input", + "bits": [ 161 ] + }, + "CFB34": { + "direction": "input", + "bits": [ 162 ] + }, + "CFB33": { + "direction": "input", + "bits": [ 163 ] + }, + "CFB32": { + "direction": "input", + "bits": [ 164 ] + }, + "CFB31": { + "direction": "input", + "bits": [ 165 ] + }, + "CFB30": { + "direction": "input", + "bits": [ 166 ] + }, + "CFB29": { + "direction": "input", + "bits": [ 167 ] + }, + "CFB28": { + "direction": "input", + "bits": [ 168 ] + }, + "CFB27": { + "direction": "input", + "bits": [ 169 ] + }, + "CFB26": { + "direction": "input", + "bits": [ 170 ] + }, + "CFB25": { + "direction": "input", + "bits": [ 171 ] + }, + "CFB24": { + "direction": "input", + "bits": [ 172 ] + }, + "CFB23": { + "direction": "input", + "bits": [ 173 ] + }, + "CFB22": { + "direction": "input", + "bits": [ 174 ] + }, + "CFB21": { + "direction": "input", + "bits": [ 175 ] + }, + "CFB20": { + "direction": "input", + "bits": [ 176 ] + }, + "CFB19": { + "direction": "input", + "bits": [ 177 ] + }, + "CFB18": { + "direction": "input", + "bits": [ 178 ] + }, + "CFB17": { + "direction": "input", + "bits": [ 179 ] + }, + "CFB16": { + "direction": "input", + "bits": [ 180 ] + }, + "CFB15": { + "direction": "input", + "bits": [ 181 ] + }, + "CFB14": { + "direction": "input", + "bits": [ 182 ] + }, + "CFB13": { + "direction": "input", + "bits": [ 183 ] + }, + "CFB12": { + "direction": "input", + "bits": [ 184 ] + }, + "CFB11": { + "direction": "input", + "bits": [ 185 ] + }, + "CFB10": { + "direction": "input", + "bits": [ 186 ] + }, + "CFB9": { + "direction": "input", + "bits": [ 187 ] + }, + "CFB8": { + "direction": "input", + "bits": [ 188 ] + }, + "CFB7": { + "direction": "input", + "bits": [ 189 ] + }, + "CFB6": { + "direction": "input", + "bits": [ 190 ] + }, + "CFB5": { + "direction": "input", + "bits": [ 191 ] + }, + "CFB4": { + "direction": "input", + "bits": [ 192 ] + }, + "CFB3": { + "direction": "input", + "bits": [ 193 ] + }, + "CFB2": { + "direction": "input", + "bits": [ 194 ] + }, + "CFB1": { + "direction": "input", + "bits": [ 195 ] + }, + "CFB0": { + "direction": "input", + "bits": [ 196 ] + }, + "MA35": { + "direction": "input", + "bits": [ 197 ] + }, + "MA34": { + "direction": "input", + "bits": [ 198 ] + }, + "MA33": { + "direction": "input", + "bits": [ 199 ] + }, + "MA32": { + "direction": "input", + "bits": [ 200 ] + }, + "MA31": { + "direction": "input", + "bits": [ 201 ] + }, + "MA30": { + "direction": "input", + "bits": [ 202 ] + }, + "MA29": { + "direction": "input", + "bits": [ 203 ] + }, + "MA28": { + "direction": "input", + "bits": [ 204 ] + }, + "MA27": { + "direction": "input", + "bits": [ 205 ] + }, + "MA26": { + "direction": "input", + "bits": [ 206 ] + }, + "MA25": { + "direction": "input", + "bits": [ 207 ] + }, + "MA24": { + "direction": "input", + "bits": [ 208 ] + }, + "MA23": { + "direction": "input", + "bits": [ 209 ] + }, + "MA22": { + "direction": "input", + "bits": [ 210 ] + }, + "MA21": { + "direction": "input", + "bits": [ 211 ] + }, + "MA20": { + "direction": "input", + "bits": [ 212 ] + }, + "MA19": { + "direction": "input", + "bits": [ 213 ] + }, + "MA18": { + "direction": "input", + "bits": [ 214 ] + }, + "MA17": { + "direction": "input", + "bits": [ 215 ] + }, + "MA16": { + "direction": "input", + "bits": [ 216 ] + }, + "MA15": { + "direction": "input", + "bits": [ 217 ] + }, + "MA14": { + "direction": "input", + "bits": [ 218 ] + }, + "MA13": { + "direction": "input", + "bits": [ 219 ] + }, + "MA12": { + "direction": "input", + "bits": [ 220 ] + }, + "MA11": { + "direction": "input", + "bits": [ 221 ] + }, + "MA10": { + "direction": "input", + "bits": [ 222 ] + }, + "MA9": { + "direction": "input", + "bits": [ 223 ] + }, + "MA8": { + "direction": "input", + "bits": [ 224 ] + }, + "MA7": { + "direction": "input", + "bits": [ 225 ] + }, + "MA6": { + "direction": "input", + "bits": [ 226 ] + }, + "MA5": { + "direction": "input", + "bits": [ 227 ] + }, + "MA4": { + "direction": "input", + "bits": [ 228 ] + }, + "MA3": { + "direction": "input", + "bits": [ 229 ] + }, + "MA2": { + "direction": "input", + "bits": [ 230 ] + }, + "MA1": { + "direction": "input", + "bits": [ 231 ] + }, + "MA0": { + "direction": "input", + "bits": [ 232 ] + }, + "MB35": { + "direction": "input", + "bits": [ 233 ] + }, + "MB34": { + "direction": "input", + "bits": [ 234 ] + }, + "MB33": { + "direction": "input", + "bits": [ 235 ] + }, + "MB32": { + "direction": "input", + "bits": [ 236 ] + }, + "MB31": { + "direction": "input", + "bits": [ 237 ] + }, + "MB30": { + "direction": "input", + "bits": [ 238 ] + }, + "MB29": { + "direction": "input", + "bits": [ 239 ] + }, + "MB28": { + "direction": "input", + "bits": [ 240 ] + }, + "MB27": { + "direction": "input", + "bits": [ 241 ] + }, + "MB26": { + "direction": "input", + "bits": [ 242 ] + }, + "MB25": { + "direction": "input", + "bits": [ 243 ] + }, + "MB24": { + "direction": "input", + "bits": [ 244 ] + }, + "MB23": { + "direction": "input", + "bits": [ 245 ] + }, + "MB22": { + "direction": "input", + "bits": [ 246 ] + }, + "MB21": { + "direction": "input", + "bits": [ 247 ] + }, + "MB20": { + "direction": "input", + "bits": [ 248 ] + }, + "MB19": { + "direction": "input", + "bits": [ 249 ] + }, + "MB18": { + "direction": "input", + "bits": [ 250 ] + }, + "MB17": { + "direction": "input", + "bits": [ 251 ] + }, + "MB16": { + "direction": "input", + "bits": [ 252 ] + }, + "MB15": { + "direction": "input", + "bits": [ 253 ] + }, + "MB14": { + "direction": "input", + "bits": [ 254 ] + }, + "MB13": { + "direction": "input", + "bits": [ 255 ] + }, + "MB12": { + "direction": "input", + "bits": [ 256 ] + }, + "MB11": { + "direction": "input", + "bits": [ 257 ] + }, + "MB10": { + "direction": "input", + "bits": [ 258 ] + }, + "MB9": { + "direction": "input", + "bits": [ 259 ] + }, + "MB8": { + "direction": "input", + "bits": [ 260 ] + }, + "MB7": { + "direction": "input", + "bits": [ 261 ] + }, + "MB6": { + "direction": "input", + "bits": [ 262 ] + }, + "MB5": { + "direction": "input", + "bits": [ 263 ] + }, + "MB4": { + "direction": "input", + "bits": [ 264 ] + }, + "MB3": { + "direction": "input", + "bits": [ 265 ] + }, + "MB2": { + "direction": "input", + "bits": [ 266 ] + }, + "MB1": { + "direction": "input", + "bits": [ 267 ] + }, + "MB0": { + "direction": "input", + "bits": [ 268 ] + }, + "CIN53": { + "direction": "input", + "bits": [ 269 ] + }, + "CIN52": { + "direction": "input", + "bits": [ 270 ] + }, + "CIN51": { + "direction": "input", + "bits": [ 271 ] + }, + "CIN50": { + "direction": "input", + "bits": [ 272 ] + }, + "CIN49": { + "direction": "input", + "bits": [ 273 ] + }, + "CIN48": { + "direction": "input", + "bits": [ 274 ] + }, + "CIN47": { + "direction": "input", + "bits": [ 275 ] + }, + "CIN46": { + "direction": "input", + "bits": [ 276 ] + }, + "CIN45": { + "direction": "input", + "bits": [ 277 ] + }, + "CIN44": { + "direction": "input", + "bits": [ 278 ] + }, + "CIN43": { + "direction": "input", + "bits": [ 279 ] + }, + "CIN42": { + "direction": "input", + "bits": [ 280 ] + }, + "CIN41": { + "direction": "input", + "bits": [ 281 ] + }, + "CIN40": { + "direction": "input", + "bits": [ 282 ] + }, + "CIN39": { + "direction": "input", + "bits": [ 283 ] + }, + "CIN38": { + "direction": "input", + "bits": [ 284 ] + }, + "CIN37": { + "direction": "input", + "bits": [ 285 ] + }, + "CIN36": { + "direction": "input", + "bits": [ 286 ] + }, + "CIN35": { + "direction": "input", + "bits": [ 287 ] + }, + "CIN34": { + "direction": "input", + "bits": [ 288 ] + }, + "CIN33": { + "direction": "input", + "bits": [ 289 ] + }, + "CIN32": { + "direction": "input", + "bits": [ 290 ] + }, + "CIN31": { + "direction": "input", + "bits": [ 291 ] + }, + "CIN30": { + "direction": "input", + "bits": [ 292 ] + }, + "CIN29": { + "direction": "input", + "bits": [ 293 ] + }, + "CIN28": { + "direction": "input", + "bits": [ 294 ] + }, + "CIN27": { + "direction": "input", + "bits": [ 295 ] + }, + "CIN26": { + "direction": "input", + "bits": [ 296 ] + }, + "CIN25": { + "direction": "input", + "bits": [ 297 ] + }, + "CIN24": { + "direction": "input", + "bits": [ 298 ] + }, + "CIN23": { + "direction": "input", + "bits": [ 299 ] + }, + "CIN22": { + "direction": "input", + "bits": [ 300 ] + }, + "CIN21": { + "direction": "input", + "bits": [ 301 ] + }, + "CIN20": { + "direction": "input", + "bits": [ 302 ] + }, + "CIN19": { + "direction": "input", + "bits": [ 303 ] + }, + "CIN18": { + "direction": "input", + "bits": [ 304 ] + }, + "CIN17": { + "direction": "input", + "bits": [ 305 ] + }, + "CIN16": { + "direction": "input", + "bits": [ 306 ] + }, + "CIN15": { + "direction": "input", + "bits": [ 307 ] + }, + "CIN14": { + "direction": "input", + "bits": [ 308 ] + }, + "CIN13": { + "direction": "input", + "bits": [ 309 ] + }, + "CIN12": { + "direction": "input", + "bits": [ 310 ] + }, + "CIN11": { + "direction": "input", + "bits": [ 311 ] + }, + "CIN10": { + "direction": "input", + "bits": [ 312 ] + }, + "CIN9": { + "direction": "input", + "bits": [ 313 ] + }, + "CIN8": { + "direction": "input", + "bits": [ 314 ] + }, + "CIN7": { + "direction": "input", + "bits": [ 315 ] + }, + "CIN6": { + "direction": "input", + "bits": [ 316 ] + }, + "CIN5": { + "direction": "input", + "bits": [ 317 ] + }, + "CIN4": { + "direction": "input", + "bits": [ 318 ] + }, + "CIN3": { + "direction": "input", + "bits": [ 319 ] + }, + "CIN2": { + "direction": "input", + "bits": [ 320 ] + }, + "CIN1": { + "direction": "input", + "bits": [ 321 ] + }, + "CIN0": { + "direction": "input", + "bits": [ 322 ] + }, + "OP10": { + "direction": "input", + "bits": [ 323 ] + }, + "OP9": { + "direction": "input", + "bits": [ 324 ] + }, + "OP8": { + "direction": "input", + "bits": [ 325 ] + }, + "OP7": { + "direction": "input", + "bits": [ 326 ] + }, + "OP6": { + "direction": "input", + "bits": [ 327 ] + }, + "OP5": { + "direction": "input", + "bits": [ 328 ] + }, + "OP4": { + "direction": "input", + "bits": [ 329 ] + }, + "OP3": { + "direction": "input", + "bits": [ 330 ] + }, + "OP2": { + "direction": "input", + "bits": [ 331 ] + }, + "OP1": { + "direction": "input", + "bits": [ 332 ] + }, + "OP0": { + "direction": "input", + "bits": [ 333 ] + }, + "R53": { + "direction": "output", + "bits": [ 334 ] + }, + "R52": { + "direction": "output", + "bits": [ 335 ] + }, + "R51": { + "direction": "output", + "bits": [ 336 ] + }, + "R50": { + "direction": "output", + "bits": [ 337 ] + }, + "R49": { + "direction": "output", + "bits": [ 338 ] + }, + "R48": { + "direction": "output", + "bits": [ 339 ] + }, + "R47": { + "direction": "output", + "bits": [ 340 ] + }, + "R46": { + "direction": "output", + "bits": [ 341 ] + }, + "R45": { + "direction": "output", + "bits": [ 342 ] + }, + "R44": { + "direction": "output", + "bits": [ 343 ] + }, + "R43": { + "direction": "output", + "bits": [ 344 ] + }, + "R42": { + "direction": "output", + "bits": [ 345 ] + }, + "R41": { + "direction": "output", + "bits": [ 346 ] + }, + "R40": { + "direction": "output", + "bits": [ 347 ] + }, + "R39": { + "direction": "output", + "bits": [ 348 ] + }, + "R38": { + "direction": "output", + "bits": [ 349 ] + }, + "R37": { + "direction": "output", + "bits": [ 350 ] + }, + "R36": { + "direction": "output", + "bits": [ 351 ] + }, + "R35": { + "direction": "output", + "bits": [ 352 ] + }, + "R34": { + "direction": "output", + "bits": [ 353 ] + }, + "R33": { + "direction": "output", + "bits": [ 354 ] + }, + "R32": { + "direction": "output", + "bits": [ 355 ] + }, + "R31": { + "direction": "output", + "bits": [ 356 ] + }, + "R30": { + "direction": "output", + "bits": [ 357 ] + }, + "R29": { + "direction": "output", + "bits": [ 358 ] + }, + "R28": { + "direction": "output", + "bits": [ 359 ] + }, + "R27": { + "direction": "output", + "bits": [ 360 ] + }, + "R26": { + "direction": "output", + "bits": [ 361 ] + }, + "R25": { + "direction": "output", + "bits": [ 362 ] + }, + "R24": { + "direction": "output", + "bits": [ 363 ] + }, + "R23": { + "direction": "output", + "bits": [ 364 ] + }, + "R22": { + "direction": "output", + "bits": [ 365 ] + }, + "R21": { + "direction": "output", + "bits": [ 366 ] + }, + "R20": { + "direction": "output", + "bits": [ 367 ] + }, + "R19": { + "direction": "output", + "bits": [ 368 ] + }, + "R18": { + "direction": "output", + "bits": [ 369 ] + }, + "R17": { + "direction": "output", + "bits": [ 370 ] + }, + "R16": { + "direction": "output", + "bits": [ 371 ] + }, + "R15": { + "direction": "output", + "bits": [ 372 ] + }, + "R14": { + "direction": "output", + "bits": [ 373 ] + }, + "R13": { + "direction": "output", + "bits": [ 374 ] + }, + "R12": { + "direction": "output", + "bits": [ 375 ] + }, + "R11": { + "direction": "output", + "bits": [ 376 ] + }, + "R10": { + "direction": "output", + "bits": [ 377 ] + }, + "R9": { + "direction": "output", + "bits": [ 378 ] + }, + "R8": { + "direction": "output", + "bits": [ 379 ] + }, + "R7": { + "direction": "output", + "bits": [ 380 ] + }, + "R6": { + "direction": "output", + "bits": [ 381 ] + }, + "R5": { + "direction": "output", + "bits": [ 382 ] + }, + "R4": { + "direction": "output", + "bits": [ 383 ] + }, + "R3": { + "direction": "output", + "bits": [ 384 ] + }, + "R2": { + "direction": "output", + "bits": [ 385 ] + }, + "R1": { + "direction": "output", + "bits": [ 386 ] + }, + "R0": { + "direction": "output", + "bits": [ 387 ] + }, + "CO53": { + "direction": "output", + "bits": [ 388 ] + }, + "CO52": { + "direction": "output", + "bits": [ 389 ] + }, + "CO51": { + "direction": "output", + "bits": [ 390 ] + }, + "CO50": { + "direction": "output", + "bits": [ 391 ] + }, + "CO49": { + "direction": "output", + "bits": [ 392 ] + }, + "CO48": { + "direction": "output", + "bits": [ 393 ] + }, + "CO47": { + "direction": "output", + "bits": [ 394 ] + }, + "CO46": { + "direction": "output", + "bits": [ 395 ] + }, + "CO45": { + "direction": "output", + "bits": [ 396 ] + }, + "CO44": { + "direction": "output", + "bits": [ 397 ] + }, + "CO43": { + "direction": "output", + "bits": [ 398 ] + }, + "CO42": { + "direction": "output", + "bits": [ 399 ] + }, + "CO41": { + "direction": "output", + "bits": [ 400 ] + }, + "CO40": { + "direction": "output", + "bits": [ 401 ] + }, + "CO39": { + "direction": "output", + "bits": [ 402 ] + }, + "CO38": { + "direction": "output", + "bits": [ 403 ] + }, + "CO37": { + "direction": "output", + "bits": [ 404 ] + }, + "CO36": { + "direction": "output", + "bits": [ 405 ] + }, + "CO35": { + "direction": "output", + "bits": [ 406 ] + }, + "CO34": { + "direction": "output", + "bits": [ 407 ] + }, + "CO33": { + "direction": "output", + "bits": [ 408 ] + }, + "CO32": { + "direction": "output", + "bits": [ 409 ] + }, + "CO31": { + "direction": "output", + "bits": [ 410 ] + }, + "CO30": { + "direction": "output", + "bits": [ 411 ] + }, + "CO29": { + "direction": "output", + "bits": [ 412 ] + }, + "CO28": { + "direction": "output", + "bits": [ 413 ] + }, + "CO27": { + "direction": "output", + "bits": [ 414 ] + }, + "CO26": { + "direction": "output", + "bits": [ 415 ] + }, + "CO25": { + "direction": "output", + "bits": [ 416 ] + }, + "CO24": { + "direction": "output", + "bits": [ 417 ] + }, + "CO23": { + "direction": "output", + "bits": [ 418 ] + }, + "CO22": { + "direction": "output", + "bits": [ 419 ] + }, + "CO21": { + "direction": "output", + "bits": [ 420 ] + }, + "CO20": { + "direction": "output", + "bits": [ 421 ] + }, + "CO19": { + "direction": "output", + "bits": [ 422 ] + }, + "CO18": { + "direction": "output", + "bits": [ 423 ] + }, + "CO17": { + "direction": "output", + "bits": [ 424 ] + }, + "CO16": { + "direction": "output", + "bits": [ 425 ] + }, + "CO15": { + "direction": "output", + "bits": [ 426 ] + }, + "CO14": { + "direction": "output", + "bits": [ 427 ] + }, + "CO13": { + "direction": "output", + "bits": [ 428 ] + }, + "CO12": { + "direction": "output", + "bits": [ 429 ] + }, + "CO11": { + "direction": "output", + "bits": [ 430 ] + }, + "CO10": { + "direction": "output", + "bits": [ 431 ] + }, + "CO9": { + "direction": "output", + "bits": [ 432 ] + }, + "CO8": { + "direction": "output", + "bits": [ 433 ] + }, + "CO7": { + "direction": "output", + "bits": [ 434 ] + }, + "CO6": { + "direction": "output", + "bits": [ 435 ] + }, + "CO5": { + "direction": "output", + "bits": [ 436 ] + }, + "CO4": { + "direction": "output", + "bits": [ 437 ] + }, + "CO3": { + "direction": "output", + "bits": [ 438 ] + }, + "CO2": { + "direction": "output", + "bits": [ 439 ] + }, + "CO1": { + "direction": "output", + "bits": [ 440 ] + }, + "CO0": { + "direction": "output", + "bits": [ 441 ] + }, + "EQZ": { + "direction": "output", + "bits": [ 442 ] + }, + "EQZM": { + "direction": "output", + "bits": [ 443 ] + }, + "EQOM": { + "direction": "output", + "bits": [ 444 ] + }, + "EQPAT": { + "direction": "output", + "bits": [ 445 ] + }, + "EQPATB": { + "direction": "output", + "bits": [ 446 ] + }, + "OVER": { + "direction": "output", + "bits": [ 447 ] + }, + "UNDER": { + "direction": "output", + "bits": [ 448 ] + }, + "OVERUNDER": { + "direction": "output", + "bits": [ 449 ] + }, + "SIGNEDR": { + "direction": "output", + "bits": [ 450 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:608.11-608.13" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:607.11-607.13" + } + }, + "A10": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:598.11-598.14" + } + }, + "A11": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:597.11-597.14" + } + }, + "A12": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:596.11-596.14" + } + }, + "A13": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:595.11-595.14" + } + }, + "A14": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:594.11-594.14" + } + }, + "A15": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:593.11-593.14" + } + }, + "A16": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:592.11-592.14" + } + }, + "A17": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:591.11-591.14" + } + }, + "A18": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:590.11-590.14" + } + }, + "A19": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:589.11-589.14" + } + }, + "A2": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:606.11-606.13" + } + }, + "A20": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:588.11-588.14" + } + }, + "A21": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:587.11-587.14" + } + }, + "A22": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:586.11-586.14" + } + }, + "A23": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:585.11-585.14" + } + }, + "A24": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:584.11-584.14" + } + }, + "A25": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:583.11-583.14" + } + }, + "A26": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:582.11-582.14" + } + }, + "A27": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:581.11-581.14" + } + }, + "A28": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:580.11-580.14" + } + }, + "A29": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:579.11-579.14" + } + }, + "A3": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:605.11-605.13" + } + }, + "A30": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:578.11-578.14" + } + }, + "A31": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:577.11-577.14" + } + }, + "A32": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:576.11-576.14" + } + }, + "A33": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:575.11-575.14" + } + }, + "A34": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:574.11-574.14" + } + }, + "A35": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:573.11-573.14" + } + }, + "A4": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:604.11-604.13" + } + }, + "A5": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:603.11-603.13" + } + }, + "A6": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:602.11-602.13" + } + }, + "A7": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:601.11-601.13" + } + }, + "A8": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:600.11-600.13" + } + }, + "A9": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:599.11-599.13" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:644.11-644.13" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:643.11-643.13" + } + }, + "B10": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:634.11-634.14" + } + }, + "B11": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:633.11-633.14" + } + }, + "B12": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:632.11-632.14" + } + }, + "B13": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:631.11-631.14" + } + }, + "B14": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:630.11-630.14" + } + }, + "B15": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:629.11-629.14" + } + }, + "B16": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:628.11-628.14" + } + }, + "B17": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:627.11-627.14" + } + }, + "B18": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:626.11-626.14" + } + }, + "B19": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:625.11-625.14" + } + }, + "B2": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:642.11-642.13" + } + }, + "B20": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:624.11-624.14" + } + }, + "B21": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:623.11-623.14" + } + }, + "B22": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:622.11-622.14" + } + }, + "B23": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:621.11-621.14" + } + }, + "B24": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:620.11-620.14" + } + }, + "B25": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:619.11-619.14" + } + }, + "B26": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:618.11-618.14" + } + }, + "B27": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:617.11-617.14" + } + }, + "B28": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:616.11-616.14" + } + }, + "B29": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:615.11-615.14" + } + }, + "B3": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:641.11-641.13" + } + }, + "B30": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:614.11-614.14" + } + }, + "B31": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:613.11-613.14" + } + }, + "B32": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:612.11-612.14" + } + }, + "B33": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:611.11-611.14" + } + }, + "B34": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:610.11-610.14" + } + }, + "B35": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:609.11-609.14" + } + }, + "B4": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:640.11-640.13" + } + }, + "B5": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:639.11-639.13" + } + }, + "B6": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:638.11-638.13" + } + }, + "B7": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:637.11-637.13" + } + }, + "B8": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:636.11-636.13" + } + }, + "B9": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:635.11-635.13" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:698.11-698.13" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:697.11-697.13" + } + }, + "C10": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:688.11-688.14" + } + }, + "C11": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:687.11-687.14" + } + }, + "C12": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:686.11-686.14" + } + }, + "C13": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:685.11-685.14" + } + }, + "C14": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:684.11-684.14" + } + }, + "C15": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:683.11-683.14" + } + }, + "C16": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:682.11-682.14" + } + }, + "C17": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:681.11-681.14" + } + }, + "C18": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:680.11-680.14" + } + }, + "C19": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:679.11-679.14" + } + }, + "C2": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:696.11-696.13" + } + }, + "C20": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:678.11-678.14" + } + }, + "C21": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:677.11-677.14" + } + }, + "C22": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:676.11-676.14" + } + }, + "C23": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:675.11-675.14" + } + }, + "C24": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:674.11-674.14" + } + }, + "C25": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:673.11-673.14" + } + }, + "C26": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:672.11-672.14" + } + }, + "C27": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:671.11-671.14" + } + }, + "C28": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:670.11-670.14" + } + }, + "C29": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:669.11-669.14" + } + }, + "C3": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:695.11-695.13" + } + }, + "C30": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:668.11-668.14" + } + }, + "C31": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:667.11-667.14" + } + }, + "C32": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:666.11-666.14" + } + }, + "C33": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:665.11-665.14" + } + }, + "C34": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:664.11-664.14" + } + }, + "C35": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:663.11-663.14" + } + }, + "C36": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:662.11-662.14" + } + }, + "C37": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:661.11-661.14" + } + }, + "C38": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:660.11-660.14" + } + }, + "C39": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:659.11-659.14" + } + }, + "C4": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:694.11-694.13" + } + }, + "C40": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:658.11-658.14" + } + }, + "C41": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:657.11-657.14" + } + }, + "C42": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:656.11-656.14" + } + }, + "C43": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:655.11-655.14" + } + }, + "C44": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:654.11-654.14" + } + }, + "C45": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:653.11-653.14" + } + }, + "C46": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:652.11-652.14" + } + }, + "C47": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:651.11-651.14" + } + }, + "C48": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:650.11-650.14" + } + }, + "C49": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:649.11-649.14" + } + }, + "C5": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:693.11-693.13" + } + }, + "C50": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:648.11-648.14" + } + }, + "C51": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:647.11-647.14" + } + }, + "C52": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:646.11-646.14" + } + }, + "C53": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:645.11-645.14" + } + }, + "C6": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:692.11-692.13" + } + }, + "C7": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:691.11-691.13" + } + }, + "C8": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:690.11-690.13" + } + }, + "C9": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:689.11-689.13" + } + }, + "CE0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:561.11-561.14" + } + }, + "CE1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:560.11-560.14" + } + }, + "CE2": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:559.11-559.14" + } + }, + "CE3": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:558.11-558.14" + } + }, + "CFB0": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:752.11-752.15" + } + }, + "CFB1": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:751.11-751.15" + } + }, + "CFB10": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:742.11-742.16" + } + }, + "CFB11": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:741.11-741.16" + } + }, + "CFB12": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:740.11-740.16" + } + }, + "CFB13": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:739.11-739.16" + } + }, + "CFB14": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:738.11-738.16" + } + }, + "CFB15": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:737.11-737.16" + } + }, + "CFB16": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:736.11-736.16" + } + }, + "CFB17": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:735.11-735.16" + } + }, + "CFB18": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:734.11-734.16" + } + }, + "CFB19": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:733.11-733.16" + } + }, + "CFB2": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:750.11-750.15" + } + }, + "CFB20": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:732.11-732.16" + } + }, + "CFB21": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:731.11-731.16" + } + }, + "CFB22": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:730.11-730.16" + } + }, + "CFB23": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:729.11-729.16" + } + }, + "CFB24": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:728.11-728.16" + } + }, + "CFB25": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:727.11-727.16" + } + }, + "CFB26": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:726.11-726.16" + } + }, + "CFB27": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:725.11-725.16" + } + }, + "CFB28": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:724.11-724.16" + } + }, + "CFB29": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:723.11-723.16" + } + }, + "CFB3": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:749.11-749.15" + } + }, + "CFB30": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:722.11-722.16" + } + }, + "CFB31": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:721.11-721.16" + } + }, + "CFB32": { + "hide_name": 0, + "bits": [ 164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:720.11-720.16" + } + }, + "CFB33": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:719.11-719.16" + } + }, + "CFB34": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:718.11-718.16" + } + }, + "CFB35": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:717.11-717.16" + } + }, + "CFB36": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:716.11-716.16" + } + }, + "CFB37": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:715.11-715.16" + } + }, + "CFB38": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:714.11-714.16" + } + }, + "CFB39": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:713.11-713.16" + } + }, + "CFB4": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:748.11-748.15" + } + }, + "CFB40": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:712.11-712.16" + } + }, + "CFB41": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:711.11-711.16" + } + }, + "CFB42": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:710.11-710.16" + } + }, + "CFB43": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:709.11-709.16" + } + }, + "CFB44": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:708.11-708.16" + } + }, + "CFB45": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:707.11-707.16" + } + }, + "CFB46": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:706.11-706.16" + } + }, + "CFB47": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:705.11-705.16" + } + }, + "CFB48": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:704.11-704.16" + } + }, + "CFB49": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:703.11-703.16" + } + }, + "CFB5": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:747.11-747.15" + } + }, + "CFB50": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:702.11-702.16" + } + }, + "CFB51": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:701.11-701.16" + } + }, + "CFB52": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:700.11-700.16" + } + }, + "CFB53": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:699.11-699.16" + } + }, + "CFB6": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:746.11-746.15" + } + }, + "CFB7": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:745.11-745.15" + } + }, + "CFB8": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:744.11-744.15" + } + }, + "CFB9": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:743.11-743.15" + } + }, + "CIN0": { + "hide_name": 0, + "bits": [ 322 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:878.11-878.15" + } + }, + "CIN1": { + "hide_name": 0, + "bits": [ 321 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:877.11-877.15" + } + }, + "CIN10": { + "hide_name": 0, + "bits": [ 312 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:868.11-868.16" + } + }, + "CIN11": { + "hide_name": 0, + "bits": [ 311 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:867.11-867.16" + } + }, + "CIN12": { + "hide_name": 0, + "bits": [ 310 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:866.11-866.16" + } + }, + "CIN13": { + "hide_name": 0, + "bits": [ 309 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:865.11-865.16" + } + }, + "CIN14": { + "hide_name": 0, + "bits": [ 308 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:864.11-864.16" + } + }, + "CIN15": { + "hide_name": 0, + "bits": [ 307 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:863.11-863.16" + } + }, + "CIN16": { + "hide_name": 0, + "bits": [ 306 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:862.11-862.16" + } + }, + "CIN17": { + "hide_name": 0, + "bits": [ 305 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:861.11-861.16" + } + }, + "CIN18": { + "hide_name": 0, + "bits": [ 304 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:860.11-860.16" + } + }, + "CIN19": { + "hide_name": 0, + "bits": [ 303 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:859.11-859.16" + } + }, + "CIN2": { + "hide_name": 0, + "bits": [ 320 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:876.11-876.15" + } + }, + "CIN20": { + "hide_name": 0, + "bits": [ 302 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:858.11-858.16" + } + }, + "CIN21": { + "hide_name": 0, + "bits": [ 301 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:857.11-857.16" + } + }, + "CIN22": { + "hide_name": 0, + "bits": [ 300 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:856.11-856.16" + } + }, + "CIN23": { + "hide_name": 0, + "bits": [ 299 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:855.11-855.16" + } + }, + "CIN24": { + "hide_name": 0, + "bits": [ 298 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:854.11-854.16" + } + }, + "CIN25": { + "hide_name": 0, + "bits": [ 297 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:853.11-853.16" + } + }, + "CIN26": { + "hide_name": 0, + "bits": [ 296 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:852.11-852.16" + } + }, + "CIN27": { + "hide_name": 0, + "bits": [ 295 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:851.11-851.16" + } + }, + "CIN28": { + "hide_name": 0, + "bits": [ 294 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:850.11-850.16" + } + }, + "CIN29": { + "hide_name": 0, + "bits": [ 293 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:849.11-849.16" + } + }, + "CIN3": { + "hide_name": 0, + "bits": [ 319 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:875.11-875.15" + } + }, + "CIN30": { + "hide_name": 0, + "bits": [ 292 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:848.11-848.16" + } + }, + "CIN31": { + "hide_name": 0, + "bits": [ 291 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:847.11-847.16" + } + }, + "CIN32": { + "hide_name": 0, + "bits": [ 290 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:846.11-846.16" + } + }, + "CIN33": { + "hide_name": 0, + "bits": [ 289 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:845.11-845.16" + } + }, + "CIN34": { + "hide_name": 0, + "bits": [ 288 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:844.11-844.16" + } + }, + "CIN35": { + "hide_name": 0, + "bits": [ 287 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:843.11-843.16" + } + }, + "CIN36": { + "hide_name": 0, + "bits": [ 286 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:842.11-842.16" + } + }, + "CIN37": { + "hide_name": 0, + "bits": [ 285 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:841.11-841.16" + } + }, + "CIN38": { + "hide_name": 0, + "bits": [ 284 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:840.11-840.16" + } + }, + "CIN39": { + "hide_name": 0, + "bits": [ 283 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:839.11-839.16" + } + }, + "CIN4": { + "hide_name": 0, + "bits": [ 318 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:874.11-874.15" + } + }, + "CIN40": { + "hide_name": 0, + "bits": [ 282 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:838.11-838.16" + } + }, + "CIN41": { + "hide_name": 0, + "bits": [ 281 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:837.11-837.16" + } + }, + "CIN42": { + "hide_name": 0, + "bits": [ 280 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:836.11-836.16" + } + }, + "CIN43": { + "hide_name": 0, + "bits": [ 279 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:835.11-835.16" + } + }, + "CIN44": { + "hide_name": 0, + "bits": [ 278 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:834.11-834.16" + } + }, + "CIN45": { + "hide_name": 0, + "bits": [ 277 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:833.11-833.16" + } + }, + "CIN46": { + "hide_name": 0, + "bits": [ 276 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:832.11-832.16" + } + }, + "CIN47": { + "hide_name": 0, + "bits": [ 275 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:831.11-831.16" + } + }, + "CIN48": { + "hide_name": 0, + "bits": [ 274 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:830.11-830.16" + } + }, + "CIN49": { + "hide_name": 0, + "bits": [ 273 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:829.11-829.16" + } + }, + "CIN5": { + "hide_name": 0, + "bits": [ 317 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:873.11-873.15" + } + }, + "CIN50": { + "hide_name": 0, + "bits": [ 272 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:828.11-828.16" + } + }, + "CIN51": { + "hide_name": 0, + "bits": [ 271 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:827.11-827.16" + } + }, + "CIN52": { + "hide_name": 0, + "bits": [ 270 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:826.11-826.16" + } + }, + "CIN53": { + "hide_name": 0, + "bits": [ 269 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:825.11-825.16" + } + }, + "CIN6": { + "hide_name": 0, + "bits": [ 316 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:872.11-872.15" + } + }, + "CIN7": { + "hide_name": 0, + "bits": [ 315 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:871.11-871.15" + } + }, + "CIN8": { + "hide_name": 0, + "bits": [ 314 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:870.11-870.15" + } + }, + "CIN9": { + "hide_name": 0, + "bits": [ 313 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:869.11-869.15" + } + }, + "CLK0": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:565.11-565.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:564.11-564.15" + } + }, + "CLK2": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:563.11-563.15" + } + }, + "CLK3": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:562.11-562.15" + } + }, + "CO0": { + "hide_name": 0, + "bits": [ 441 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:997.12-997.15" + } + }, + "CO1": { + "hide_name": 0, + "bits": [ 440 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:996.12-996.15" + } + }, + "CO10": { + "hide_name": 0, + "bits": [ 431 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:987.12-987.16" + } + }, + "CO11": { + "hide_name": 0, + "bits": [ 430 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:986.12-986.16" + } + }, + "CO12": { + "hide_name": 0, + "bits": [ 429 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:985.12-985.16" + } + }, + "CO13": { + "hide_name": 0, + "bits": [ 428 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:984.12-984.16" + } + }, + "CO14": { + "hide_name": 0, + "bits": [ 427 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:983.12-983.16" + } + }, + "CO15": { + "hide_name": 0, + "bits": [ 426 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:982.12-982.16" + } + }, + "CO16": { + "hide_name": 0, + "bits": [ 425 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:981.12-981.16" + } + }, + "CO17": { + "hide_name": 0, + "bits": [ 424 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:980.12-980.16" + } + }, + "CO18": { + "hide_name": 0, + "bits": [ 423 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:979.12-979.16" + } + }, + "CO19": { + "hide_name": 0, + "bits": [ 422 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:978.12-978.16" + } + }, + "CO2": { + "hide_name": 0, + "bits": [ 439 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:995.12-995.15" + } + }, + "CO20": { + "hide_name": 0, + "bits": [ 421 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:977.12-977.16" + } + }, + "CO21": { + "hide_name": 0, + "bits": [ 420 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:976.12-976.16" + } + }, + "CO22": { + "hide_name": 0, + "bits": [ 419 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:975.12-975.16" + } + }, + "CO23": { + "hide_name": 0, + "bits": [ 418 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:974.12-974.16" + } + }, + "CO24": { + "hide_name": 0, + "bits": [ 417 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:973.12-973.16" + } + }, + "CO25": { + "hide_name": 0, + "bits": [ 416 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:972.12-972.16" + } + }, + "CO26": { + "hide_name": 0, + "bits": [ 415 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:971.12-971.16" + } + }, + "CO27": { + "hide_name": 0, + "bits": [ 414 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:970.12-970.16" + } + }, + "CO28": { + "hide_name": 0, + "bits": [ 413 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:969.12-969.16" + } + }, + "CO29": { + "hide_name": 0, + "bits": [ 412 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:968.12-968.16" + } + }, + "CO3": { + "hide_name": 0, + "bits": [ 438 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:994.12-994.15" + } + }, + "CO30": { + "hide_name": 0, + "bits": [ 411 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:967.12-967.16" + } + }, + "CO31": { + "hide_name": 0, + "bits": [ 410 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:966.12-966.16" + } + }, + "CO32": { + "hide_name": 0, + "bits": [ 409 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:965.12-965.16" + } + }, + "CO33": { + "hide_name": 0, + "bits": [ 408 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:964.12-964.16" + } + }, + "CO34": { + "hide_name": 0, + "bits": [ 407 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:963.12-963.16" + } + }, + "CO35": { + "hide_name": 0, + "bits": [ 406 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:962.12-962.16" + } + }, + "CO36": { + "hide_name": 0, + "bits": [ 405 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:961.12-961.16" + } + }, + "CO37": { + "hide_name": 0, + "bits": [ 404 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:960.12-960.16" + } + }, + "CO38": { + "hide_name": 0, + "bits": [ 403 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:959.12-959.16" + } + }, + "CO39": { + "hide_name": 0, + "bits": [ 402 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:958.12-958.16" + } + }, + "CO4": { + "hide_name": 0, + "bits": [ 437 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:993.12-993.15" + } + }, + "CO40": { + "hide_name": 0, + "bits": [ 401 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:957.12-957.16" + } + }, + "CO41": { + "hide_name": 0, + "bits": [ 400 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:956.12-956.16" + } + }, + "CO42": { + "hide_name": 0, + "bits": [ 399 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:955.12-955.16" + } + }, + "CO43": { + "hide_name": 0, + "bits": [ 398 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:954.12-954.16" + } + }, + "CO44": { + "hide_name": 0, + "bits": [ 397 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:953.12-953.16" + } + }, + "CO45": { + "hide_name": 0, + "bits": [ 396 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:952.12-952.16" + } + }, + "CO46": { + "hide_name": 0, + "bits": [ 395 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:951.12-951.16" + } + }, + "CO47": { + "hide_name": 0, + "bits": [ 394 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:950.12-950.16" + } + }, + "CO48": { + "hide_name": 0, + "bits": [ 393 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:949.12-949.16" + } + }, + "CO49": { + "hide_name": 0, + "bits": [ 392 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:948.12-948.16" + } + }, + "CO5": { + "hide_name": 0, + "bits": [ 436 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:992.12-992.15" + } + }, + "CO50": { + "hide_name": 0, + "bits": [ 391 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:947.12-947.16" + } + }, + "CO51": { + "hide_name": 0, + "bits": [ 390 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:946.12-946.16" + } + }, + "CO52": { + "hide_name": 0, + "bits": [ 389 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:945.12-945.16" + } + }, + "CO53": { + "hide_name": 0, + "bits": [ 388 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:944.12-944.16" + } + }, + "CO6": { + "hide_name": 0, + "bits": [ 435 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:991.12-991.15" + } + }, + "CO7": { + "hide_name": 0, + "bits": [ 434 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:990.12-990.15" + } + }, + "CO8": { + "hide_name": 0, + "bits": [ 433 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:989.12-989.15" + } + }, + "CO9": { + "hide_name": 0, + "bits": [ 432 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:988.12-988.15" + } + }, + "EQOM": { + "hide_name": 0, + "bits": [ 444 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1000.12-1000.16" + } + }, + "EQPAT": { + "hide_name": 0, + "bits": [ 445 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1001.12-1001.17" + } + }, + "EQPATB": { + "hide_name": 0, + "bits": [ 446 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1002.12-1002.18" + } + }, + "EQZ": { + "hide_name": 0, + "bits": [ 442 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:998.12-998.15" + } + }, + "EQZM": { + "hide_name": 0, + "bits": [ 443 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:999.12-999.16" + } + }, + "MA0": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:788.11-788.14" + } + }, + "MA1": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:787.11-787.14" + } + }, + "MA10": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:778.11-778.15" + } + }, + "MA11": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:777.11-777.15" + } + }, + "MA12": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:776.11-776.15" + } + }, + "MA13": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:775.11-775.15" + } + }, + "MA14": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:774.11-774.15" + } + }, + "MA15": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:773.11-773.15" + } + }, + "MA16": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:772.11-772.15" + } + }, + "MA17": { + "hide_name": 0, + "bits": [ 215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:771.11-771.15" + } + }, + "MA18": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:770.11-770.15" + } + }, + "MA19": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:769.11-769.15" + } + }, + "MA2": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:786.11-786.14" + } + }, + "MA20": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:768.11-768.15" + } + }, + "MA21": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:767.11-767.15" + } + }, + "MA22": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:766.11-766.15" + } + }, + "MA23": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:765.11-765.15" + } + }, + "MA24": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:764.11-764.15" + } + }, + "MA25": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:763.11-763.15" + } + }, + "MA26": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:762.11-762.15" + } + }, + "MA27": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:761.11-761.15" + } + }, + "MA28": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:760.11-760.15" + } + }, + "MA29": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:759.11-759.15" + } + }, + "MA3": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:785.11-785.14" + } + }, + "MA30": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:758.11-758.15" + } + }, + "MA31": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:757.11-757.15" + } + }, + "MA32": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:756.11-756.15" + } + }, + "MA33": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:755.11-755.15" + } + }, + "MA34": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:754.11-754.15" + } + }, + "MA35": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:753.11-753.15" + } + }, + "MA4": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:784.11-784.14" + } + }, + "MA5": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:783.11-783.14" + } + }, + "MA6": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:782.11-782.14" + } + }, + "MA7": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:781.11-781.14" + } + }, + "MA8": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:780.11-780.14" + } + }, + "MA9": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:779.11-779.14" + } + }, + "MB0": { + "hide_name": 0, + "bits": [ 268 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:824.11-824.14" + } + }, + "MB1": { + "hide_name": 0, + "bits": [ 267 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:823.11-823.14" + } + }, + "MB10": { + "hide_name": 0, + "bits": [ 258 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:814.11-814.15" + } + }, + "MB11": { + "hide_name": 0, + "bits": [ 257 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:813.11-813.15" + } + }, + "MB12": { + "hide_name": 0, + "bits": [ 256 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:812.11-812.15" + } + }, + "MB13": { + "hide_name": 0, + "bits": [ 255 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:811.11-811.15" + } + }, + "MB14": { + "hide_name": 0, + "bits": [ 254 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:810.11-810.15" + } + }, + "MB15": { + "hide_name": 0, + "bits": [ 253 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:809.11-809.15" + } + }, + "MB16": { + "hide_name": 0, + "bits": [ 252 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:808.11-808.15" + } + }, + "MB17": { + "hide_name": 0, + "bits": [ 251 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:807.11-807.15" + } + }, + "MB18": { + "hide_name": 0, + "bits": [ 250 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:806.11-806.15" + } + }, + "MB19": { + "hide_name": 0, + "bits": [ 249 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:805.11-805.15" + } + }, + "MB2": { + "hide_name": 0, + "bits": [ 266 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:822.11-822.14" + } + }, + "MB20": { + "hide_name": 0, + "bits": [ 248 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:804.11-804.15" + } + }, + "MB21": { + "hide_name": 0, + "bits": [ 247 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:803.11-803.15" + } + }, + "MB22": { + "hide_name": 0, + "bits": [ 246 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:802.11-802.15" + } + }, + "MB23": { + "hide_name": 0, + "bits": [ 245 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:801.11-801.15" + } + }, + "MB24": { + "hide_name": 0, + "bits": [ 244 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:800.11-800.15" + } + }, + "MB25": { + "hide_name": 0, + "bits": [ 243 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:799.11-799.15" + } + }, + "MB26": { + "hide_name": 0, + "bits": [ 242 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:798.11-798.15" + } + }, + "MB27": { + "hide_name": 0, + "bits": [ 241 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:797.11-797.15" + } + }, + "MB28": { + "hide_name": 0, + "bits": [ 240 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:796.11-796.15" + } + }, + "MB29": { + "hide_name": 0, + "bits": [ 239 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:795.11-795.15" + } + }, + "MB3": { + "hide_name": 0, + "bits": [ 265 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:821.11-821.14" + } + }, + "MB30": { + "hide_name": 0, + "bits": [ 238 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:794.11-794.15" + } + }, + "MB31": { + "hide_name": 0, + "bits": [ 237 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:793.11-793.15" + } + }, + "MB32": { + "hide_name": 0, + "bits": [ 236 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:792.11-792.15" + } + }, + "MB33": { + "hide_name": 0, + "bits": [ 235 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:791.11-791.15" + } + }, + "MB34": { + "hide_name": 0, + "bits": [ 234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:790.11-790.15" + } + }, + "MB35": { + "hide_name": 0, + "bits": [ 233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:789.11-789.15" + } + }, + "MB4": { + "hide_name": 0, + "bits": [ 264 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:820.11-820.14" + } + }, + "MB5": { + "hide_name": 0, + "bits": [ 263 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:819.11-819.14" + } + }, + "MB6": { + "hide_name": 0, + "bits": [ 262 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:818.11-818.14" + } + }, + "MB7": { + "hide_name": 0, + "bits": [ 261 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:817.11-817.14" + } + }, + "MB8": { + "hide_name": 0, + "bits": [ 260 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:816.11-816.14" + } + }, + "MB9": { + "hide_name": 0, + "bits": [ 259 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:815.11-815.14" + } + }, + "OP0": { + "hide_name": 0, + "bits": [ 333 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:889.11-889.14" + } + }, + "OP1": { + "hide_name": 0, + "bits": [ 332 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:888.11-888.14" + } + }, + "OP10": { + "hide_name": 0, + "bits": [ 323 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:879.11-879.15" + } + }, + "OP2": { + "hide_name": 0, + "bits": [ 331 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:887.11-887.14" + } + }, + "OP3": { + "hide_name": 0, + "bits": [ 330 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:886.11-886.14" + } + }, + "OP4": { + "hide_name": 0, + "bits": [ 329 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:885.11-885.14" + } + }, + "OP5": { + "hide_name": 0, + "bits": [ 328 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:884.11-884.14" + } + }, + "OP6": { + "hide_name": 0, + "bits": [ 327 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:883.11-883.14" + } + }, + "OP7": { + "hide_name": 0, + "bits": [ 326 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:882.11-882.14" + } + }, + "OP8": { + "hide_name": 0, + "bits": [ 325 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:881.11-881.14" + } + }, + "OP9": { + "hide_name": 0, + "bits": [ 324 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:880.11-880.14" + } + }, + "OVER": { + "hide_name": 0, + "bits": [ 447 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1003.12-1003.16" + } + }, + "OVERUNDER": { + "hide_name": 0, + "bits": [ 449 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1005.12-1005.21" + } + }, + "R0": { + "hide_name": 0, + "bits": [ 387 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:943.12-943.14" + } + }, + "R1": { + "hide_name": 0, + "bits": [ 386 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:942.12-942.14" + } + }, + "R10": { + "hide_name": 0, + "bits": [ 377 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:933.12-933.15" + } + }, + "R11": { + "hide_name": 0, + "bits": [ 376 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:932.12-932.15" + } + }, + "R12": { + "hide_name": 0, + "bits": [ 375 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:931.12-931.15" + } + }, + "R13": { + "hide_name": 0, + "bits": [ 374 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:930.12-930.15" + } + }, + "R14": { + "hide_name": 0, + "bits": [ 373 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:929.12-929.15" + } + }, + "R15": { + "hide_name": 0, + "bits": [ 372 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:928.12-928.15" + } + }, + "R16": { + "hide_name": 0, + "bits": [ 371 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:927.12-927.15" + } + }, + "R17": { + "hide_name": 0, + "bits": [ 370 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:926.12-926.15" + } + }, + "R18": { + "hide_name": 0, + "bits": [ 369 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:925.12-925.15" + } + }, + "R19": { + "hide_name": 0, + "bits": [ 368 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:924.12-924.15" + } + }, + "R2": { + "hide_name": 0, + "bits": [ 385 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:941.12-941.14" + } + }, + "R20": { + "hide_name": 0, + "bits": [ 367 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:923.12-923.15" + } + }, + "R21": { + "hide_name": 0, + "bits": [ 366 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:922.12-922.15" + } + }, + "R22": { + "hide_name": 0, + "bits": [ 365 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:921.12-921.15" + } + }, + "R23": { + "hide_name": 0, + "bits": [ 364 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:920.12-920.15" + } + }, + "R24": { + "hide_name": 0, + "bits": [ 363 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:919.12-919.15" + } + }, + "R25": { + "hide_name": 0, + "bits": [ 362 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:918.12-918.15" + } + }, + "R26": { + "hide_name": 0, + "bits": [ 361 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:917.12-917.15" + } + }, + "R27": { + "hide_name": 0, + "bits": [ 360 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:916.12-916.15" + } + }, + "R28": { + "hide_name": 0, + "bits": [ 359 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:915.12-915.15" + } + }, + "R29": { + "hide_name": 0, + "bits": [ 358 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:914.12-914.15" + } + }, + "R3": { + "hide_name": 0, + "bits": [ 384 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:940.12-940.14" + } + }, + "R30": { + "hide_name": 0, + "bits": [ 357 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:913.12-913.15" + } + }, + "R31": { + "hide_name": 0, + "bits": [ 356 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:912.12-912.15" + } + }, + "R32": { + "hide_name": 0, + "bits": [ 355 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:911.12-911.15" + } + }, + "R33": { + "hide_name": 0, + "bits": [ 354 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:910.12-910.15" + } + }, + "R34": { + "hide_name": 0, + "bits": [ 353 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:909.12-909.15" + } + }, + "R35": { + "hide_name": 0, + "bits": [ 352 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:908.12-908.15" + } + }, + "R36": { + "hide_name": 0, + "bits": [ 351 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:907.12-907.15" + } + }, + "R37": { + "hide_name": 0, + "bits": [ 350 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:906.12-906.15" + } + }, + "R38": { + "hide_name": 0, + "bits": [ 349 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:905.12-905.15" + } + }, + "R39": { + "hide_name": 0, + "bits": [ 348 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:904.12-904.15" + } + }, + "R4": { + "hide_name": 0, + "bits": [ 383 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:939.12-939.14" + } + }, + "R40": { + "hide_name": 0, + "bits": [ 347 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:903.12-903.15" + } + }, + "R41": { + "hide_name": 0, + "bits": [ 346 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:902.12-902.15" + } + }, + "R42": { + "hide_name": 0, + "bits": [ 345 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:901.12-901.15" + } + }, + "R43": { + "hide_name": 0, + "bits": [ 344 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:900.12-900.15" + } + }, + "R44": { + "hide_name": 0, + "bits": [ 343 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:899.12-899.15" + } + }, + "R45": { + "hide_name": 0, + "bits": [ 342 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:898.12-898.15" + } + }, + "R46": { + "hide_name": 0, + "bits": [ 341 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:897.12-897.15" + } + }, + "R47": { + "hide_name": 0, + "bits": [ 340 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:896.12-896.15" + } + }, + "R48": { + "hide_name": 0, + "bits": [ 339 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:895.12-895.15" + } + }, + "R49": { + "hide_name": 0, + "bits": [ 338 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:894.12-894.15" + } + }, + "R5": { + "hide_name": 0, + "bits": [ 382 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:938.12-938.14" + } + }, + "R50": { + "hide_name": 0, + "bits": [ 337 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:893.12-893.15" + } + }, + "R51": { + "hide_name": 0, + "bits": [ 336 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:892.12-892.15" + } + }, + "R52": { + "hide_name": 0, + "bits": [ 335 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:891.12-891.15" + } + }, + "R53": { + "hide_name": 0, + "bits": [ 334 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:890.12-890.15" + } + }, + "R6": { + "hide_name": 0, + "bits": [ 381 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:937.12-937.14" + } + }, + "R7": { + "hide_name": 0, + "bits": [ 380 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:936.12-936.14" + } + }, + "R8": { + "hide_name": 0, + "bits": [ 379 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:935.12-935.14" + } + }, + "R9": { + "hide_name": 0, + "bits": [ 378 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:934.12-934.14" + } + }, + "RST0": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:569.11-569.15" + } + }, + "RST1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:568.11-568.15" + } + }, + "RST2": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:567.11-567.15" + } + }, + "RST3": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:566.11-566.15" + } + }, + "SIGNEDCIN": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:572.11-572.20" + } + }, + "SIGNEDIA": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:570.11-570.19" + } + }, + "SIGNEDIB": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:571.11-571.19" + } + }, + "SIGNEDR": { + "hide_name": 0, + "bits": [ 450 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1006.12-1006.19" + } + }, + "UNDER": { + "hide_name": 0, + "bits": [ 448 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1004.12-1004.17" + } + } + } + }, + "BB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + }, + "B": { + "direction": "inout", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.68-10.69" + } + }, + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.20-10.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.34-10.35" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.23-10.24" + } + } + } + }, + "BBPD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + }, + "B": { + "direction": "inout", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.68-12.69" + } + }, + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.20-12.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.34-12.35" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.23-12.24" + } + } + } + }, + "BBPU": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + }, + "B": { + "direction": "inout", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.68-11.69" + } + }, + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.20-11.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.34-11.35" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.23-11.24" + } + } + } + }, + "CCU2C": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "abc9_box_id": "00000000000000000000000000000101", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:3.1-61.10" + }, + "parameter_default_values": { + "INIT0": "0000000000000000", + "INIT1": "0000000000000000", + "INJECT1_0": "YES", + "INJECT1_1": "YES" + }, + "ports": { + "CIN": { + "direction": "input", + "bits": [ 2 ] + }, + "A0": { + "direction": "input", + "bits": [ 3 ] + }, + "B0": { + "direction": "input", + "bits": [ 4 ] + }, + "C0": { + "direction": "input", + "bits": [ 5 ] + }, + "D0": { + "direction": "input", + "bits": [ 6 ] + }, + "A1": { + "direction": "input", + "bits": [ 7 ] + }, + "B1": { + "direction": "input", + "bits": [ 8 ] + }, + "C1": { + "direction": "input", + "bits": [ 9 ] + }, + "D1": { + "direction": "input", + "bits": [ 10 ] + }, + "S0": { + "direction": "output", + "bits": [ 11 ] + }, + "S1": { + "direction": "output", + "bits": [ 12 ] + }, + "COUT": { + "direction": "output", + "bits": [ 13 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.9-6.11" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.25-6.27" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.13-6.15" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.29-6.31" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.17-6.19" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.33-6.35" + } + }, + "CIN": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:5.9-5.12" + } + }, + "COUT": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "D0": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.21-6.23" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.37-6.39" + } + }, + "S0": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.9-7.11" + } + }, + "S1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.13-7.15" + } + } + } + }, + "CLKDIVF": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1010.1-1017.10" + }, + "parameter_default_values": { + "DIV": "2.0", + "GSR": "DISABLED" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "ALIGNWD": { + "direction": "input", + "bits": [ 4 ] + }, + "CDIVX": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "ALIGNWD": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1015.11-1015.18" + } + }, + "CDIVX": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1016.12-1016.17" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1013.11-1013.15" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1014.11-1014.14" + } + } + } + }, + "DCCA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1043.1-1047.10" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "CE": { + "direction": "input", + "bits": [ 3 ] + }, + "CLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "CE": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1045.11-1045.13" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1044.11-1044.15" + } + }, + "CLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1046.12-1046.16" + } + } + } + }, + "DCSC": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1032.1-1040.10" + }, + "parameter_default_values": { + "DCSMODE": "POS" + }, + "ports": { + "CLK1": { + "direction": "input", + "bits": [ 2 ] + }, + "CLK0": { + "direction": "input", + "bits": [ 3 ] + }, + "SEL1": { + "direction": "input", + "bits": [ 4 ] + }, + "SEL0": { + "direction": "input", + "bits": [ 5 ] + }, + "MODESEL": { + "direction": "input", + "bits": [ 6 ] + }, + "DCSOUT": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "CLK0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1035.11-1035.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1034.11-1034.15" + } + }, + "DCSOUT": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1039.12-1039.18" + } + }, + "MODESEL": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1038.11-1038.18" + } + }, + "SEL0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1037.11-1037.15" + } + }, + "SEL1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1036.11-1036.15" + } + } + } + }, + "DCUA": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1456.1-2032.10" + }, + "parameter_default_values": { + "CH0_AUTO_CALIB_EN": "DONTCARE", + "CH0_AUTO_FACQ_EN": "DONTCARE", + "CH0_BAND_THRESHOLD": "DONTCARE", + "CH0_CALIB_CK_MODE": "DONTCARE", + "CH0_CC_MATCH_1": "DONTCARE", + "CH0_CC_MATCH_2": "DONTCARE", + "CH0_CC_MATCH_3": "DONTCARE", + "CH0_CC_MATCH_4": "DONTCARE", + "CH0_CDR_CNT4SEL": "DONTCARE", + "CH0_CDR_CNT8SEL": "DONTCARE", + "CH0_CDR_MAX_RATE": "DONTCARE", + "CH0_CTC_BYPASS": "DONTCARE", + "CH0_DCOATDCFG": "DONTCARE", + "CH0_DCOATDDLY": "DONTCARE", + "CH0_DCOBYPSATD": "DONTCARE", + "CH0_DCOCALDIV": "DONTCARE", + "CH0_DCOCTLGI": "DONTCARE", + "CH0_DCODISBDAVOID": "DONTCARE", + "CH0_DCOFLTDAC": "DONTCARE", + "CH0_DCOFTNRG": "DONTCARE", + "CH0_DCOIOSTUNE": "DONTCARE", + "CH0_DCOITUNE": "DONTCARE", + "CH0_DCOITUNE4LSB": "DONTCARE", + "CH0_DCOIUPDNX2": "DONTCARE", + "CH0_DCONUOFLSB": "DONTCARE", + "CH0_DCOSCALEI": "DONTCARE", + "CH0_DCOSTARTVAL": "DONTCARE", + "CH0_DCOSTEP": "DONTCARE", + "CH0_DEC_BYPASS": "DONTCARE", + "CH0_ENABLE_CG_ALIGN": "DONTCARE", + "CH0_ENC_BYPASS": "DONTCARE", + "CH0_FF_RX_F_CLK_DIS": "DONTCARE", + "CH0_FF_RX_H_CLK_EN": "DONTCARE", + "CH0_FF_TX_F_CLK_DIS": "DONTCARE", + "CH0_FF_TX_H_CLK_EN": "DONTCARE", + "CH0_GE_AN_ENABLE": "DONTCARE", + "CH0_INVERT_RX": "DONTCARE", + "CH0_INVERT_TX": "DONTCARE", + "CH0_LDR_CORE2TX_SEL": "DONTCARE", + "CH0_LDR_RX2CORE_SEL": "DONTCARE", + "CH0_LEQ_OFFSET_SEL": "DONTCARE", + "CH0_LEQ_OFFSET_TRIM": "DONTCARE", + "CH0_LSM_DISABLE": "DONTCARE", + "CH0_MATCH_2_ENABLE": "DONTCARE", + "CH0_MATCH_4_ENABLE": "DONTCARE", + "CH0_MIN_IPG_CNT": "DONTCARE", + "CH0_PCIE_EI_EN": "DONTCARE", + "CH0_PCIE_MODE": "DONTCARE", + "CH0_PCS_DET_TIME_SEL": "DONTCARE", + "CH0_PDEN_SEL": "DONTCARE", + "CH0_PRBS_ENABLE": "DONTCARE", + "CH0_PRBS_LOCK": "DONTCARE", + "CH0_PRBS_SELECTION": "DONTCARE", + "CH0_PROTOCOL": "DONTCARE", + "CH0_RATE_MODE_RX": "DONTCARE", + "CH0_RATE_MODE_TX": "DONTCARE", + "CH0_RCV_DCC_EN": "DONTCARE", + "CH0_REG_BAND_OFFSET": "DONTCARE", + "CH0_REG_BAND_SEL": "DONTCARE", + "CH0_REG_IDAC_EN": "DONTCARE", + "CH0_REG_IDAC_SEL": "DONTCARE", + "CH0_REQ_EN": "DONTCARE", + "CH0_REQ_LVL_SET": "DONTCARE", + "CH0_RIO_MODE": "DONTCARE", + "CH0_RLOS_SEL": "DONTCARE", + "CH0_RPWDNB": "DONTCARE", + "CH0_RTERM_RX": "DONTCARE", + "CH0_RTERM_TX": "DONTCARE", + "CH0_RXIN_CM": "DONTCARE", + "CH0_RXTERM_CM": "DONTCARE", + "CH0_RX_DCO_CK_DIV": "DONTCARE", + "CH0_RX_DIV11_SEL": "DONTCARE", + "CH0_RX_GEAR_BYPASS": "DONTCARE", + "CH0_RX_GEAR_MODE": "DONTCARE", + "CH0_RX_LOS_CEQ": "DONTCARE", + "CH0_RX_LOS_EN": "DONTCARE", + "CH0_RX_LOS_HYST_EN": "DONTCARE", + "CH0_RX_LOS_LVL": "DONTCARE", + "CH0_RX_RATE_SEL": "DONTCARE", + "CH0_RX_SB_BYPASS": "DONTCARE", + "CH0_SB_BYPASS": "DONTCARE", + "CH0_SEL_SD_RX_CLK": "DONTCARE", + "CH0_TDRV_DAT_SEL": "DONTCARE", + "CH0_TDRV_POST_EN": "DONTCARE", + "CH0_TDRV_PRE_EN": "DONTCARE", + "CH0_TDRV_SLICE0_CUR": "DONTCARE", + "CH0_TDRV_SLICE0_SEL": "DONTCARE", + "CH0_TDRV_SLICE1_CUR": "DONTCARE", + "CH0_TDRV_SLICE1_SEL": "DONTCARE", + "CH0_TDRV_SLICE2_CUR": "DONTCARE", + "CH0_TDRV_SLICE2_SEL": "DONTCARE", + "CH0_TDRV_SLICE3_CUR": "DONTCARE", + "CH0_TDRV_SLICE3_SEL": "DONTCARE", + "CH0_TDRV_SLICE4_CUR": "DONTCARE", + "CH0_TDRV_SLICE4_SEL": "DONTCARE", + "CH0_TDRV_SLICE5_CUR": "DONTCARE", + "CH0_TDRV_SLICE5_SEL": "DONTCARE", + "CH0_TPWDNB": "DONTCARE", + "CH0_TXAMPLITUDE": "DONTCARE", + "CH0_TXDEPOST": "DONTCARE", + "CH0_TXDEPRE": "DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 138 ] + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 139 ] + }, + "D_SCAN_ENABLE": { + "direction": "input", + "bits": [ 140 ] + }, + "D_SCAN_IN_0": { + "direction": "input", + "bits": [ 141 ] + }, + "D_SCAN_IN_1": { + "direction": "input", + "bits": [ 142 ] + }, + "D_SCAN_IN_2": { + "direction": "input", + "bits": [ 143 ] + }, + "D_SCAN_IN_3": { + "direction": "input", + "bits": [ 144 ] + }, + "D_SCAN_IN_4": { + "direction": "input", + "bits": [ 145 ] + }, + "D_SCAN_IN_5": { + "direction": "input", + "bits": [ 146 ] + }, + "D_SCAN_IN_6": { + "direction": "input", + "bits": [ 147 ] + }, + "D_SCAN_IN_7": { + "direction": "input", + "bits": [ 148 ] + }, + "D_SCAN_MODE": { + "direction": "input", + "bits": [ 149 ] + }, + "D_SCAN_RESET": { + "direction": "input", + "bits": [ 150 ] + }, + "D_CIN0": { + "direction": "input", + "bits": [ 151 ] + }, + "D_CIN1": { + "direction": "input", + "bits": [ 152 ] + }, + "D_CIN2": { + "direction": "input", + "bits": [ 153 ] + }, + "D_CIN3": { + "direction": "input", + "bits": [ 154 ] + }, + "D_CIN4": { + "direction": "input", + "bits": [ 155 ] + }, + "D_CIN5": { + "direction": "input", + "bits": [ 156 ] + }, + "D_CIN6": { + "direction": "input", + "bits": [ 157 ] + }, + "D_CIN7": { + "direction": "input", + "bits": [ 158 ] + }, + "D_CIN8": { + "direction": "input", + "bits": [ 159 ] + }, + "D_CIN9": { + "direction": "input", + "bits": [ 160 ] + }, + "D_CIN10": { + "direction": "input", + "bits": [ 161 ] + }, + "D_CIN11": { + "direction": "input", + "bits": [ 162 ] + }, + "CH0_HDOUTP": { + "direction": "output", + "bits": [ 163 ] + }, + "CH1_HDOUTP": { + "direction": "output", + "bits": [ 164 ] + }, + "CH0_HDOUTN": { + "direction": "output", + "bits": [ 165 ] + }, + "CH1_HDOUTN": { + "direction": "output", + "bits": [ 166 ] + }, + "D_TXBIT_CLKP_TO_ND": { + "direction": "output", + "bits": [ 167 ] + }, + "D_TXBIT_CLKN_TO_ND": { + "direction": "output", + "bits": [ 168 ] + }, + "D_SYNC_PULSE2ND": { + "direction": "output", + "bits": [ 169 ] + }, + "D_TXPLL_LOL_TO_ND": { + "direction": "output", + "bits": [ 170 ] + }, + "CH0_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 171 ] + }, + "CH1_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 172 ] + }, + "CH0_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 173 ] + }, + "CH1_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 174 ] + }, + "CH0_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 175 ] + }, + "CH1_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 176 ] + }, + "CH0_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 177 ] + }, + "CH1_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 178 ] + }, + "CH0_FF_RX_PCLK": { + "direction": "output", + "bits": [ 179 ] + }, + "CH1_FF_RX_PCLK": { + "direction": "output", + "bits": [ 180 ] + }, + "CH0_FF_TX_PCLK": { + "direction": "output", + "bits": [ 181 ] + }, + "CH1_FF_TX_PCLK": { + "direction": "output", + "bits": [ 182 ] + }, + "CH0_FF_RX_D_0": { + "direction": "output", + "bits": [ 183 ] + }, + "CH1_FF_RX_D_0": { + "direction": "output", + "bits": [ 184 ] + }, + "CH0_FF_RX_D_1": { + "direction": "output", + "bits": [ 185 ] + }, + "CH1_FF_RX_D_1": { + "direction": "output", + "bits": [ 186 ] + }, + "CH0_FF_RX_D_2": { + "direction": "output", + "bits": [ 187 ] + }, + "CH1_FF_RX_D_2": { + "direction": "output", + "bits": [ 188 ] + }, + "CH0_FF_RX_D_3": { + "direction": "output", + "bits": [ 189 ] + }, + "CH1_FF_RX_D_3": { + "direction": "output", + "bits": [ 190 ] + }, + "CH0_FF_RX_D_4": { + "direction": "output", + "bits": [ 191 ] + }, + "CH1_FF_RX_D_4": { + "direction": "output", + "bits": [ 192 ] + }, + "CH0_FF_RX_D_5": { + "direction": "output", + "bits": [ 193 ] + }, + "CH1_FF_RX_D_5": { + "direction": "output", + "bits": [ 194 ] + }, + "CH0_FF_RX_D_6": { + "direction": "output", + "bits": [ 195 ] + }, + "CH1_FF_RX_D_6": { + "direction": "output", + "bits": [ 196 ] + }, + "CH0_FF_RX_D_7": { + "direction": "output", + "bits": [ 197 ] + }, + "CH1_FF_RX_D_7": { + "direction": "output", + "bits": [ 198 ] + }, + "CH0_FF_RX_D_8": { + "direction": "output", + "bits": [ 199 ] + }, + "CH1_FF_RX_D_8": { + "direction": "output", + "bits": [ 200 ] + }, + "CH0_FF_RX_D_9": { + "direction": "output", + "bits": [ 201 ] + }, + "CH1_FF_RX_D_9": { + "direction": "output", + "bits": [ 202 ] + }, + "CH0_FF_RX_D_10": { + "direction": "output", + "bits": [ 203 ] + }, + "CH1_FF_RX_D_10": { + "direction": "output", + "bits": [ 204 ] + }, + "CH0_FF_RX_D_11": { + "direction": "output", + "bits": [ 205 ] + }, + "CH1_FF_RX_D_11": { + "direction": "output", + "bits": [ 206 ] + }, + "CH0_FF_RX_D_12": { + "direction": "output", + "bits": [ 207 ] + }, + "CH1_FF_RX_D_12": { + "direction": "output", + "bits": [ 208 ] + }, + "CH0_FF_RX_D_13": { + "direction": "output", + "bits": [ 209 ] + }, + "CH1_FF_RX_D_13": { + "direction": "output", + "bits": [ 210 ] + }, + "CH0_FF_RX_D_14": { + "direction": "output", + "bits": [ 211 ] + }, + "CH1_FF_RX_D_14": { + "direction": "output", + "bits": [ 212 ] + }, + "CH0_FF_RX_D_15": { + "direction": "output", + "bits": [ 213 ] + }, + "CH1_FF_RX_D_15": { + "direction": "output", + "bits": [ 214 ] + }, + "CH0_FF_RX_D_16": { + "direction": "output", + "bits": [ 215 ] + }, + "CH1_FF_RX_D_16": { + "direction": "output", + "bits": [ 216 ] + }, + "CH0_FF_RX_D_17": { + "direction": "output", + "bits": [ 217 ] + }, + "CH1_FF_RX_D_17": { + "direction": "output", + "bits": [ 218 ] + }, + "CH0_FF_RX_D_18": { + "direction": "output", + "bits": [ 219 ] + }, + "CH1_FF_RX_D_18": { + "direction": "output", + "bits": [ 220 ] + }, + "CH0_FF_RX_D_19": { + "direction": "output", + "bits": [ 221 ] + }, + "CH1_FF_RX_D_19": { + "direction": "output", + "bits": [ 222 ] + }, + "CH0_FF_RX_D_20": { + "direction": "output", + "bits": [ 223 ] + }, + "CH1_FF_RX_D_20": { + "direction": "output", + "bits": [ 224 ] + }, + "CH0_FF_RX_D_21": { + "direction": "output", + "bits": [ 225 ] + }, + "CH1_FF_RX_D_21": { + "direction": "output", + "bits": [ 226 ] + }, + "CH0_FF_RX_D_22": { + "direction": "output", + "bits": [ 227 ] + }, + "CH1_FF_RX_D_22": { + "direction": "output", + "bits": [ 228 ] + }, + "CH0_FF_RX_D_23": { + "direction": "output", + "bits": [ 229 ] + }, + "CH1_FF_RX_D_23": { + "direction": "output", + "bits": [ 230 ] + }, + "CH0_FFS_PCIE_DONE": { + "direction": "output", + "bits": [ 231 ] + }, + "CH1_FFS_PCIE_DONE": { + "direction": "output", + "bits": [ 232 ] + }, + "CH0_FFS_PCIE_CON": { + "direction": "output", + "bits": [ 233 ] + }, + "CH1_FFS_PCIE_CON": { + "direction": "output", + "bits": [ 234 ] + }, + "CH0_FFS_RLOS": { + "direction": "output", + "bits": [ 235 ] + }, + "CH1_FFS_RLOS": { + "direction": "output", + "bits": [ 236 ] + }, + "CH0_FFS_LS_SYNC_STATUS": { + "direction": "output", + "bits": [ 237 ] + }, + "CH1_FFS_LS_SYNC_STATUS": { + "direction": "output", + "bits": [ 238 ] + }, + "CH0_FFS_CC_UNDERRUN": { + "direction": "output", + "bits": [ 239 ] + }, + "CH1_FFS_CC_UNDERRUN": { + "direction": "output", + "bits": [ 240 ] + }, + "CH0_FFS_CC_OVERRUN": { + "direction": "output", + "bits": [ 241 ] + }, + "CH1_FFS_CC_OVERRUN": { + "direction": "output", + "bits": [ 242 ] + }, + "CH0_FFS_RXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 243 ] + }, + "CH1_FFS_RXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 244 ] + }, + "CH0_FFS_TXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 245 ] + }, + "CH1_FFS_TXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 246 ] + }, + "CH0_FFS_RLOL": { + "direction": "output", + "bits": [ 247 ] + }, + "CH1_FFS_RLOL": { + "direction": "output", + "bits": [ 248 ] + }, + "CH0_FFS_SKP_ADDED": { + "direction": "output", + "bits": [ 249 ] + }, + "CH1_FFS_SKP_ADDED": { + "direction": "output", + "bits": [ 250 ] + }, + "CH0_FFS_SKP_DELETED": { + "direction": "output", + "bits": [ 251 ] + }, + "CH1_FFS_SKP_DELETED": { + "direction": "output", + "bits": [ 252 ] + }, + "CH0_LDR_RX2CORE": { + "direction": "output", + "bits": [ 253 ] + }, + "CH1_LDR_RX2CORE": { + "direction": "output", + "bits": [ 254 ] + }, + "D_SCIRDATA0": { + "direction": "output", + "bits": [ 255 ] + }, + "D_SCIRDATA1": { + "direction": "output", + "bits": [ 256 ] + }, + "D_SCIRDATA2": { + "direction": "output", + "bits": [ 257 ] + }, + "D_SCIRDATA3": { + "direction": "output", + "bits": [ 258 ] + }, + "D_SCIRDATA4": { + "direction": "output", + "bits": [ 259 ] + }, + "D_SCIRDATA5": { + "direction": "output", + "bits": [ 260 ] + }, + "D_SCIRDATA6": { + "direction": "output", + "bits": [ 261 ] + }, + "D_SCIRDATA7": { + "direction": "output", + "bits": [ 262 ] + }, + "D_SCIINT": { + "direction": "output", + "bits": [ 263 ] + }, + "D_SCAN_OUT_0": { + "direction": "output", + "bits": [ 264 ] + }, + "D_SCAN_OUT_1": { + "direction": "output", + "bits": [ 265 ] + }, + "D_SCAN_OUT_2": { + "direction": "output", + "bits": [ 266 ] + }, + "D_SCAN_OUT_3": { + "direction": "output", + "bits": [ 267 ] + }, + "D_SCAN_OUT_4": { + "direction": "output", + "bits": [ 268 ] + }, + "D_SCAN_OUT_5": { + "direction": "output", + "bits": [ 269 ] + }, + "D_SCAN_OUT_6": { + "direction": "output", + "bits": [ 270 ] + }, + "D_SCAN_OUT_7": { + "direction": "output", + "bits": [ 271 ] + }, + "D_COUT0": { + "direction": "output", + "bits": [ 272 ] + }, + "D_COUT1": { + "direction": "output", + "bits": [ 273 ] + }, + "D_COUT2": { + "direction": "output", + "bits": [ 274 ] + }, + "D_COUT3": { + "direction": "output", + "bits": [ 275 ] + }, + "D_COUT4": { + "direction": "output", + "bits": [ 276 ] + }, + "D_COUT5": { + "direction": "output", + "bits": [ 277 ] + }, + "D_COUT6": { + "direction": "output", + "bits": [ 278 ] + }, + "D_COUT7": { + "direction": "output", + "bits": [ 279 ] + }, + "D_COUT8": { + "direction": "output", + "bits": [ 280 ] + }, + "D_COUT9": { + "direction": "output", + "bits": [ 281 ] + }, + "D_COUT10": { + "direction": "output", + "bits": [ 282 ] + }, + "D_COUT11": { + "direction": "output", + "bits": [ 283 ] + }, + "D_COUT12": { + "direction": "output", + "bits": [ 284 ] + }, + "D_COUT13": { + "direction": "output", + "bits": [ 285 ] + }, + "D_COUT14": { + "direction": "output", + "bits": [ 286 ] + }, + "D_COUT15": { + "direction": "output", + "bits": [ 287 ] + }, + "D_COUT16": { + "direction": "output", + "bits": [ 288 ] + }, + "D_COUT17": { + "direction": "output", + "bits": [ 289 ] + }, + "D_COUT18": { + "direction": "output", + "bits": [ 290 ] + }, + "D_COUT19": { + "direction": "output", + "bits": [ 291 ] + }, + "D_REFCLKI": { + "direction": "input", + "bits": [ 292 ] + }, + "D_FFS_PLOL": { + "direction": "output", + "bits": [ 293 ] + } + }, + "cells": { + }, + "netnames": { + "CH0_FFC_CDR_EN_BITSLIP": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1876.11-1876.33" + } + }, + "CH0_FFC_DIV11_MODE_RX": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1826.11-1826.32" + } + }, + "CH0_FFC_DIV11_MODE_TX": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1832.11-1832.32" + } + }, + "CH0_FFC_EI_EN": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1804.11-1804.24" + } + }, + "CH0_FFC_ENABLE_CGALIGN": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1812.11-1812.33" + } + }, + "CH0_FFC_FB_LOOPBACK": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1816.11-1816.30" + } + }, + "CH0_FFC_LANE_RX_RST": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1838.11-1838.30" + } + }, + "CH0_FFC_LANE_TX_RST": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1836.11-1836.30" + } + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1834.11-1834.33" + } + }, + "CH0_FFC_PCIE_CT": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1808.11-1808.26" + } + }, + "CH0_FFC_PCIE_DET_EN": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1806.11-1806.30" + } + }, + "CH0_FFC_PFIFO_CLR": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1820.11-1820.28" + } + }, + "CH0_FFC_RATE_MODE_RX": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1822.11-1822.31" + } + }, + "CH0_FFC_RATE_MODE_TX": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1824.11-1824.31" + } + }, + "CH0_FFC_RRST": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1840.11-1840.23" + } + }, + "CH0_FFC_RXPWDNB": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1844.11-1844.26" + } + }, + "CH0_FFC_RX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1828.11-1828.31" + } + }, + "CH0_FFC_SB_INV_RX": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1810.11-1810.28" + } + }, + "CH0_FFC_SB_PFIFO_LP": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1818.11-1818.30" + } + }, + "CH0_FFC_SIGNAL_DETECT": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1814.11-1814.32" + } + }, + "CH0_FFC_TXPWDNB": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1842.11-1842.26" + } + }, + "CH0_FFC_TX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1830.11-1830.31" + } + }, + "CH0_FFS_CC_OVERRUN": { + "hide_name": 0, + "bits": [ 241 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1979.12-1979.30" + } + }, + "CH0_FFS_CC_UNDERRUN": { + "hide_name": 0, + "bits": [ 239 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1977.12-1977.31" + } + }, + "CH0_FFS_LS_SYNC_STATUS": { + "hide_name": 0, + "bits": [ 237 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1975.12-1975.34" + } + }, + "CH0_FFS_PCIE_CON": { + "hide_name": 0, + "bits": [ 233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1971.12-1971.28" + } + }, + "CH0_FFS_PCIE_DONE": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1969.12-1969.29" + } + }, + "CH0_FFS_RLOL": { + "hide_name": 0, + "bits": [ 247 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1985.12-1985.24" + } + }, + "CH0_FFS_RLOS": { + "hide_name": 0, + "bits": [ 235 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1973.12-1973.24" + } + }, + "CH0_FFS_RXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 243 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1981.12-1981.34" + } + }, + "CH0_FFS_SKP_ADDED": { + "hide_name": 0, + "bits": [ 249 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1987.12-1987.29" + } + }, + "CH0_FFS_SKP_DELETED": { + "hide_name": 0, + "bits": [ 251 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1989.12-1989.31" + } + }, + "CH0_FFS_TXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 245 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1983.12-1983.34" + } + }, + "CH0_FF_EBRD_CLK": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1754.11-1754.26" + } + }, + "CH0_FF_RXI_CLK": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1750.11-1750.25" + } + }, + "CH0_FF_RX_D_0": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1921.12-1921.25" + } + }, + "CH0_FF_RX_D_1": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1923.12-1923.25" + } + }, + "CH0_FF_RX_D_10": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1941.12-1941.26" + } + }, + "CH0_FF_RX_D_11": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1943.12-1943.26" + } + }, + "CH0_FF_RX_D_12": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1945.12-1945.26" + } + }, + "CH0_FF_RX_D_13": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1947.12-1947.26" + } + }, + "CH0_FF_RX_D_14": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1949.12-1949.26" + } + }, + "CH0_FF_RX_D_15": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1951.12-1951.26" + } + }, + "CH0_FF_RX_D_16": { + "hide_name": 0, + "bits": [ 215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1953.12-1953.26" + } + }, + "CH0_FF_RX_D_17": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1955.12-1955.26" + } + }, + "CH0_FF_RX_D_18": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1957.12-1957.26" + } + }, + "CH0_FF_RX_D_19": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1959.12-1959.26" + } + }, + "CH0_FF_RX_D_2": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1925.12-1925.25" + } + }, + "CH0_FF_RX_D_20": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1961.12-1961.26" + } + }, + "CH0_FF_RX_D_21": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1963.12-1963.26" + } + }, + "CH0_FF_RX_D_22": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1965.12-1965.26" + } + }, + "CH0_FF_RX_D_23": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1967.12-1967.26" + } + }, + "CH0_FF_RX_D_3": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1927.12-1927.25" + } + }, + "CH0_FF_RX_D_4": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1929.12-1929.25" + } + }, + "CH0_FF_RX_D_5": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1931.12-1931.25" + } + }, + "CH0_FF_RX_D_6": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1933.12-1933.25" + } + }, + "CH0_FF_RX_D_7": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1935.12-1935.25" + } + }, + "CH0_FF_RX_D_8": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1937.12-1937.25" + } + }, + "CH0_FF_RX_D_9": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1939.12-1939.25" + } + }, + "CH0_FF_RX_F_CLK": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1909.12-1909.27" + } + }, + "CH0_FF_RX_H_CLK": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1911.12-1911.27" + } + }, + "CH0_FF_RX_PCLK": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1917.12-1917.26" + } + }, + "CH0_FF_TXI_CLK": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1752.11-1752.25" + } + }, + "CH0_FF_TX_D_0": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1756.11-1756.24" + } + }, + "CH0_FF_TX_D_1": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1758.11-1758.24" + } + }, + "CH0_FF_TX_D_10": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1776.11-1776.25" + } + }, + "CH0_FF_TX_D_11": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1778.11-1778.25" + } + }, + "CH0_FF_TX_D_12": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1780.11-1780.25" + } + }, + "CH0_FF_TX_D_13": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1782.11-1782.25" + } + }, + "CH0_FF_TX_D_14": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1784.11-1784.25" + } + }, + "CH0_FF_TX_D_15": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1786.11-1786.25" + } + }, + "CH0_FF_TX_D_16": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1788.11-1788.25" + } + }, + "CH0_FF_TX_D_17": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1790.11-1790.25" + } + }, + "CH0_FF_TX_D_18": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1792.11-1792.25" + } + }, + "CH0_FF_TX_D_19": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1794.11-1794.25" + } + }, + "CH0_FF_TX_D_2": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1760.11-1760.24" + } + }, + "CH0_FF_TX_D_20": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1796.11-1796.25" + } + }, + "CH0_FF_TX_D_21": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1798.11-1798.25" + } + }, + "CH0_FF_TX_D_22": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1800.11-1800.25" + } + }, + "CH0_FF_TX_D_23": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1802.11-1802.25" + } + }, + "CH0_FF_TX_D_3": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1762.11-1762.24" + } + }, + "CH0_FF_TX_D_4": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1764.11-1764.24" + } + }, + "CH0_FF_TX_D_5": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1766.11-1766.24" + } + }, + "CH0_FF_TX_D_6": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1768.11-1768.24" + } + }, + "CH0_FF_TX_D_7": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1770.11-1770.24" + } + }, + "CH0_FF_TX_D_8": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1772.11-1772.24" + } + }, + "CH0_FF_TX_D_9": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1774.11-1774.24" + } + }, + "CH0_FF_TX_F_CLK": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1913.12-1913.27" + } + }, + "CH0_FF_TX_H_CLK": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1915.12-1915.27" + } + }, + "CH0_FF_TX_PCLK": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1919.12-1919.26" + } + }, + "CH0_HDINN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1741.11-1741.20" + } + }, + "CH0_HDINP": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1737.11-1737.20" + } + }, + "CH0_HDOUTN": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1903.12-1903.22" + } + }, + "CH0_HDOUTP": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1901.12-1901.22" + } + }, + "CH0_LDR_CORE2TX": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1846.11-1846.26" + } + }, + "CH0_LDR_RX2CORE": { + "hide_name": 0, + "bits": [ 253 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1991.12-1991.27" + } + }, + "CH0_RX_REFCLK": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1748.11-1748.24" + } + }, + "CH0_SCIEN": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1864.11-1864.20" + } + }, + "CH0_SCISEL": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1866.11-1866.21" + } + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1877.11-1877.33" + } + }, + "CH1_FFC_DIV11_MODE_RX": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1827.11-1827.32" + } + }, + "CH1_FFC_DIV11_MODE_TX": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1833.11-1833.32" + } + }, + "CH1_FFC_EI_EN": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1805.11-1805.24" + } + }, + "CH1_FFC_ENABLE_CGALIGN": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1813.11-1813.33" + } + }, + "CH1_FFC_FB_LOOPBACK": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1817.11-1817.30" + } + }, + "CH1_FFC_LANE_RX_RST": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1839.11-1839.30" + } + }, + "CH1_FFC_LANE_TX_RST": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1837.11-1837.30" + } + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1835.11-1835.33" + } + }, + "CH1_FFC_PCIE_CT": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1809.11-1809.26" + } + }, + "CH1_FFC_PCIE_DET_EN": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1807.11-1807.30" + } + }, + "CH1_FFC_PFIFO_CLR": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1821.11-1821.28" + } + }, + "CH1_FFC_RATE_MODE_RX": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1823.11-1823.31" + } + }, + "CH1_FFC_RATE_MODE_TX": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1825.11-1825.31" + } + }, + "CH1_FFC_RRST": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1841.11-1841.23" + } + }, + "CH1_FFC_RXPWDNB": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1845.11-1845.26" + } + }, + "CH1_FFC_RX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1829.11-1829.31" + } + }, + "CH1_FFC_SB_INV_RX": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1811.11-1811.28" + } + }, + "CH1_FFC_SB_PFIFO_LP": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1819.11-1819.30" + } + }, + "CH1_FFC_SIGNAL_DETECT": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1815.11-1815.32" + } + }, + "CH1_FFC_TXPWDNB": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1843.11-1843.26" + } + }, + "CH1_FFC_TX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1831.11-1831.31" + } + }, + "CH1_FFS_CC_OVERRUN": { + "hide_name": 0, + "bits": [ 242 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1980.12-1980.30" + } + }, + "CH1_FFS_CC_UNDERRUN": { + "hide_name": 0, + "bits": [ 240 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1978.12-1978.31" + } + }, + "CH1_FFS_LS_SYNC_STATUS": { + "hide_name": 0, + "bits": [ 238 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1976.12-1976.34" + } + }, + "CH1_FFS_PCIE_CON": { + "hide_name": 0, + "bits": [ 234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1972.12-1972.28" + } + }, + "CH1_FFS_PCIE_DONE": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1970.12-1970.29" + } + }, + "CH1_FFS_RLOL": { + "hide_name": 0, + "bits": [ 248 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1986.12-1986.24" + } + }, + "CH1_FFS_RLOS": { + "hide_name": 0, + "bits": [ 236 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1974.12-1974.24" + } + }, + "CH1_FFS_RXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 244 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1982.12-1982.34" + } + }, + "CH1_FFS_SKP_ADDED": { + "hide_name": 0, + "bits": [ 250 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1988.12-1988.29" + } + }, + "CH1_FFS_SKP_DELETED": { + "hide_name": 0, + "bits": [ 252 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1990.12-1990.31" + } + }, + "CH1_FFS_TXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 246 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1984.12-1984.34" + } + }, + "CH1_FF_EBRD_CLK": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1755.11-1755.26" + } + }, + "CH1_FF_RXI_CLK": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1751.11-1751.25" + } + }, + "CH1_FF_RX_D_0": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1922.12-1922.25" + } + }, + "CH1_FF_RX_D_1": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1924.12-1924.25" + } + }, + "CH1_FF_RX_D_10": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1942.12-1942.26" + } + }, + "CH1_FF_RX_D_11": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1944.12-1944.26" + } + }, + "CH1_FF_RX_D_12": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1946.12-1946.26" + } + }, + "CH1_FF_RX_D_13": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1948.12-1948.26" + } + }, + "CH1_FF_RX_D_14": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1950.12-1950.26" + } + }, + "CH1_FF_RX_D_15": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1952.12-1952.26" + } + }, + "CH1_FF_RX_D_16": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1954.12-1954.26" + } + }, + "CH1_FF_RX_D_17": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1956.12-1956.26" + } + }, + "CH1_FF_RX_D_18": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1958.12-1958.26" + } + }, + "CH1_FF_RX_D_19": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1960.12-1960.26" + } + }, + "CH1_FF_RX_D_2": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1926.12-1926.25" + } + }, + "CH1_FF_RX_D_20": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1962.12-1962.26" + } + }, + "CH1_FF_RX_D_21": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1964.12-1964.26" + } + }, + "CH1_FF_RX_D_22": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1966.12-1966.26" + } + }, + "CH1_FF_RX_D_23": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1968.12-1968.26" + } + }, + "CH1_FF_RX_D_3": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1928.12-1928.25" + } + }, + "CH1_FF_RX_D_4": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1930.12-1930.25" + } + }, + "CH1_FF_RX_D_5": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1932.12-1932.25" + } + }, + "CH1_FF_RX_D_6": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1934.12-1934.25" + } + }, + "CH1_FF_RX_D_7": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1936.12-1936.25" + } + }, + "CH1_FF_RX_D_8": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1938.12-1938.25" + } + }, + "CH1_FF_RX_D_9": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1940.12-1940.25" + } + }, + "CH1_FF_RX_F_CLK": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1910.12-1910.27" + } + }, + "CH1_FF_RX_H_CLK": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1912.12-1912.27" + } + }, + "CH1_FF_RX_PCLK": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1918.12-1918.26" + } + }, + "CH1_FF_TXI_CLK": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1753.11-1753.25" + } + }, + "CH1_FF_TX_D_0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1757.11-1757.24" + } + }, + "CH1_FF_TX_D_1": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1759.11-1759.24" + } + }, + "CH1_FF_TX_D_10": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1777.11-1777.25" + } + }, + "CH1_FF_TX_D_11": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1779.11-1779.25" + } + }, + "CH1_FF_TX_D_12": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1781.11-1781.25" + } + }, + "CH1_FF_TX_D_13": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1783.11-1783.25" + } + }, + "CH1_FF_TX_D_14": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1785.11-1785.25" + } + }, + "CH1_FF_TX_D_15": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1787.11-1787.25" + } + }, + "CH1_FF_TX_D_16": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1789.11-1789.25" + } + }, + "CH1_FF_TX_D_17": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1791.11-1791.25" + } + }, + "CH1_FF_TX_D_18": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1793.11-1793.25" + } + }, + "CH1_FF_TX_D_19": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1795.11-1795.25" + } + }, + "CH1_FF_TX_D_2": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1761.11-1761.24" + } + }, + "CH1_FF_TX_D_20": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1797.11-1797.25" + } + }, + "CH1_FF_TX_D_21": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1799.11-1799.25" + } + }, + "CH1_FF_TX_D_22": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1801.11-1801.25" + } + }, + "CH1_FF_TX_D_23": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1803.11-1803.25" + } + }, + "CH1_FF_TX_D_3": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1763.11-1763.24" + } + }, + "CH1_FF_TX_D_4": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1765.11-1765.24" + } + }, + "CH1_FF_TX_D_5": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1767.11-1767.24" + } + }, + "CH1_FF_TX_D_6": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1769.11-1769.24" + } + }, + "CH1_FF_TX_D_7": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1771.11-1771.24" + } + }, + "CH1_FF_TX_D_8": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1773.11-1773.24" + } + }, + "CH1_FF_TX_D_9": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1775.11-1775.24" + } + }, + "CH1_FF_TX_F_CLK": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1914.12-1914.27" + } + }, + "CH1_FF_TX_H_CLK": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1916.12-1916.27" + } + }, + "CH1_FF_TX_PCLK": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1920.12-1920.26" + } + }, + "CH1_HDINN": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1743.11-1743.20" + } + }, + "CH1_HDINP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1739.11-1739.20" + } + }, + "CH1_HDOUTN": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1904.12-1904.22" + } + }, + "CH1_HDOUTP": { + "hide_name": 0, + "bits": [ 164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1902.12-1902.22" + } + }, + "CH1_LDR_CORE2TX": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1847.11-1847.26" + } + }, + "CH1_LDR_RX2CORE": { + "hide_name": 0, + "bits": [ 254 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1992.12-1992.27" + } + }, + "CH1_RX_REFCLK": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1749.11-1749.24" + } + }, + "CH1_SCIEN": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1865.11-1865.20" + } + }, + "CH1_SCISEL": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1867.11-1867.21" + } + }, + "D_CIN0": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1889.11-1889.17" + } + }, + "D_CIN1": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1890.11-1890.17" + } + }, + "D_CIN10": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1899.11-1899.18" + } + }, + "D_CIN11": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1900.11-1900.18" + } + }, + "D_CIN2": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1891.11-1891.17" + } + }, + "D_CIN3": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1892.11-1892.17" + } + }, + "D_CIN4": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1893.11-1893.17" + } + }, + "D_CIN5": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1894.11-1894.17" + } + }, + "D_CIN6": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1895.11-1895.17" + } + }, + "D_CIN7": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1896.11-1896.17" + } + }, + "D_CIN8": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1897.11-1897.17" + } + }, + "D_CIN9": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1898.11-1898.17" + } + }, + "D_COUT0": { + "hide_name": 0, + "bits": [ 272 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2010.12-2010.19" + } + }, + "D_COUT1": { + "hide_name": 0, + "bits": [ 273 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2011.12-2011.19" + } + }, + "D_COUT10": { + "hide_name": 0, + "bits": [ 282 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2020.12-2020.20" + } + }, + "D_COUT11": { + "hide_name": 0, + "bits": [ 283 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2021.12-2021.20" + } + }, + "D_COUT12": { + "hide_name": 0, + "bits": [ 284 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2022.12-2022.20" + } + }, + "D_COUT13": { + "hide_name": 0, + "bits": [ 285 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2023.12-2023.20" + } + }, + "D_COUT14": { + "hide_name": 0, + "bits": [ 286 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2024.12-2024.20" + } + }, + "D_COUT15": { + "hide_name": 0, + "bits": [ 287 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2025.12-2025.20" + } + }, + "D_COUT16": { + "hide_name": 0, + "bits": [ 288 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2026.12-2026.20" + } + }, + "D_COUT17": { + "hide_name": 0, + "bits": [ 289 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2027.12-2027.20" + } + }, + "D_COUT18": { + "hide_name": 0, + "bits": [ 290 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2028.12-2028.20" + } + }, + "D_COUT19": { + "hide_name": 0, + "bits": [ 291 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2029.12-2029.20" + } + }, + "D_COUT2": { + "hide_name": 0, + "bits": [ 274 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2012.12-2012.19" + } + }, + "D_COUT3": { + "hide_name": 0, + "bits": [ 275 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2013.12-2013.19" + } + }, + "D_COUT4": { + "hide_name": 0, + "bits": [ 276 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2014.12-2014.19" + } + }, + "D_COUT5": { + "hide_name": 0, + "bits": [ 277 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2015.12-2015.19" + } + }, + "D_COUT6": { + "hide_name": 0, + "bits": [ 278 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2016.12-2016.19" + } + }, + "D_COUT7": { + "hide_name": 0, + "bits": [ 279 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2017.12-2017.19" + } + }, + "D_COUT8": { + "hide_name": 0, + "bits": [ 280 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2018.12-2018.19" + } + }, + "D_COUT9": { + "hide_name": 0, + "bits": [ 281 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2019.12-2019.19" + } + }, + "D_CYAWSTN": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1870.11-1870.20" + } + }, + "D_FFC_DUAL_RST": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1872.11-1872.25" + } + }, + "D_FFC_MACROPDB": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1874.11-1874.25" + } + }, + "D_FFC_MACRO_RST": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1873.11-1873.26" + } + }, + "D_FFC_SYNC_TOGGLE": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1871.11-1871.28" + } + }, + "D_FFC_TRST": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1875.11-1875.21" + } + }, + "D_FFS_PLOL": { + "hide_name": 0, + "bits": [ 293 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2031.12-2031.22" + } + }, + "D_REFCLKI": { + "hide_name": 0, + "bits": [ 292 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2030.11-2030.20" + } + }, + "D_SCAN_ENABLE": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1878.11-1878.24" + } + }, + "D_SCAN_IN_0": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1879.11-1879.22" + } + }, + "D_SCAN_IN_1": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1880.11-1880.22" + } + }, + "D_SCAN_IN_2": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1881.11-1881.22" + } + }, + "D_SCAN_IN_3": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1882.11-1882.22" + } + }, + "D_SCAN_IN_4": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1883.11-1883.22" + } + }, + "D_SCAN_IN_5": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1884.11-1884.22" + } + }, + "D_SCAN_IN_6": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1885.11-1885.22" + } + }, + "D_SCAN_IN_7": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1886.11-1886.22" + } + }, + "D_SCAN_MODE": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1887.11-1887.22" + } + }, + "D_SCAN_OUT_0": { + "hide_name": 0, + "bits": [ 264 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2002.12-2002.24" + } + }, + "D_SCAN_OUT_1": { + "hide_name": 0, + "bits": [ 265 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2003.12-2003.24" + } + }, + "D_SCAN_OUT_2": { + "hide_name": 0, + "bits": [ 266 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2004.12-2004.24" + } + }, + "D_SCAN_OUT_3": { + "hide_name": 0, + "bits": [ 267 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2005.12-2005.24" + } + }, + "D_SCAN_OUT_4": { + "hide_name": 0, + "bits": [ 268 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2006.12-2006.24" + } + }, + "D_SCAN_OUT_5": { + "hide_name": 0, + "bits": [ 269 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2007.12-2007.24" + } + }, + "D_SCAN_OUT_6": { + "hide_name": 0, + "bits": [ 270 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2008.12-2008.24" + } + }, + "D_SCAN_OUT_7": { + "hide_name": 0, + "bits": [ 271 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2009.12-2009.24" + } + }, + "D_SCAN_RESET": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1888.11-1888.23" + } + }, + "D_SCIADDR0": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1856.11-1856.21" + } + }, + "D_SCIADDR1": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1857.11-1857.21" + } + }, + "D_SCIADDR2": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1858.11-1858.21" + } + }, + "D_SCIADDR3": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1859.11-1859.21" + } + }, + "D_SCIADDR4": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1860.11-1860.21" + } + }, + "D_SCIADDR5": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1861.11-1861.21" + } + }, + "D_SCIENAUX": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1862.11-1862.21" + } + }, + "D_SCIINT": { + "hide_name": 0, + "bits": [ 263 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2001.12-2001.20" + } + }, + "D_SCIRD": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1868.11-1868.18" + } + }, + "D_SCIRDATA0": { + "hide_name": 0, + "bits": [ 255 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1993.12-1993.23" + } + }, + "D_SCIRDATA1": { + "hide_name": 0, + "bits": [ 256 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1994.12-1994.23" + } + }, + "D_SCIRDATA2": { + "hide_name": 0, + "bits": [ 257 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1995.12-1995.23" + } + }, + "D_SCIRDATA3": { + "hide_name": 0, + "bits": [ 258 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1996.12-1996.23" + } + }, + "D_SCIRDATA4": { + "hide_name": 0, + "bits": [ 259 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1997.12-1997.23" + } + }, + "D_SCIRDATA5": { + "hide_name": 0, + "bits": [ 260 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1998.12-1998.23" + } + }, + "D_SCIRDATA6": { + "hide_name": 0, + "bits": [ 261 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1999.12-1999.23" + } + }, + "D_SCIRDATA7": { + "hide_name": 0, + "bits": [ 262 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2000.12-2000.23" + } + }, + "D_SCISELAUX": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1863.11-1863.22" + } + }, + "D_SCIWDATA0": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1848.11-1848.22" + } + }, + "D_SCIWDATA1": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1849.11-1849.22" + } + }, + "D_SCIWDATA2": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1850.11-1850.22" + } + }, + "D_SCIWDATA3": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1851.11-1851.22" + } + }, + "D_SCIWDATA4": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1852.11-1852.22" + } + }, + "D_SCIWDATA5": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1853.11-1853.22" + } + }, + "D_SCIWDATA6": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1854.11-1854.22" + } + }, + "D_SCIWDATA7": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1855.11-1855.22" + } + }, + "D_SCIWSTN": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1869.11-1869.20" + } + }, + "D_SYNC_ND": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1746.11-1746.20" + } + }, + "D_SYNC_PULSE2ND": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1907.12-1907.27" + } + }, + "D_TXBIT_CLKN_FROM_ND": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1745.11-1745.31" + } + }, + "D_TXBIT_CLKN_TO_ND": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1906.12-1906.30" + } + }, + "D_TXBIT_CLKP_FROM_ND": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1744.11-1744.31" + } + }, + "D_TXBIT_CLKP_TO_ND": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1905.12-1905.30" + } + }, + "D_TXPLL_LOL_FROM_ND": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1747.11-1747.30" + } + }, + "D_TXPLL_LOL_TO_ND": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1908.12-1908.29" + } + } + } + }, + "DDRDLLA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1139.1-1156.10" + }, + "parameter_default_values": { + "FORCE_MAX_DELAY": "NO", + "GSR": "ENABLED" + }, + "ports": { + "CLK": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "UDDCNTLN": { + "direction": "input", + "bits": [ 4 ] + }, + "FREEZE": { + "direction": "input", + "bits": [ 5 ] + }, + "DDRDEL": { + "direction": "output", + "bits": [ 6 ] + }, + "LOCK": { + "direction": "output", + "bits": [ 7 ] + }, + "DCNTL7": { + "direction": "output", + "bits": [ 8 ] + }, + "DCNTL6": { + "direction": "output", + "bits": [ 9 ] + }, + "DCNTL5": { + "direction": "output", + "bits": [ 10 ] + }, + "DCNTL4": { + "direction": "output", + "bits": [ 11 ] + }, + "DCNTL3": { + "direction": "output", + "bits": [ 12 ] + }, + "DCNTL2": { + "direction": "output", + "bits": [ 13 ] + }, + "DCNTL1": { + "direction": "output", + "bits": [ 14 ] + }, + "DCNTL0": { + "direction": "output", + "bits": [ 15 ] + } + }, + "cells": { + }, + "netnames": { + "CLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1142.11-1142.14" + } + }, + "DCNTL0": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1155.12-1155.18" + } + }, + "DCNTL1": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1154.12-1154.18" + } + }, + "DCNTL2": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1153.12-1153.18" + } + }, + "DCNTL3": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1152.12-1152.18" + } + }, + "DCNTL4": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1151.12-1151.18" + } + }, + "DCNTL5": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1150.12-1150.18" + } + }, + "DCNTL6": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1149.12-1149.18" + } + }, + "DCNTL7": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1148.12-1148.18" + } + }, + "DDRDEL": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1146.12-1146.18" + } + }, + "FREEZE": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1145.11-1145.17" + } + }, + "LOCK": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1147.12-1147.16" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1143.11-1143.14" + } + }, + "UDDCNTLN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1144.11-1144.19" + } + } + } + }, + "DELAYF": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1065.1-1074.10" + }, + "parameter_default_values": { + "DEL_MODE": "USER_DEFINED", + "DEL_VALUE": "00000000000000000000000000000000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "LOADN": { + "direction": "input", + "bits": [ 3 ] + }, + "MOVE": { + "direction": "input", + "bits": [ 4 ] + }, + "DIRECTION": { + "direction": "input", + "bits": [ 5 ] + }, + "Z": { + "direction": "output", + "bits": [ 6 ] + }, + "CFLAG": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1068.11-1068.12" + } + }, + "CFLAG": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1073.12-1073.17" + } + }, + "DIRECTION": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1071.11-1071.20" + } + }, + "LOADN": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1069.11-1069.16" + } + }, + "MOVE": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1070.11-1070.15" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1072.12-1072.13" + } + } + } + }, + "DELAYG": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1077.1-1082.10" + }, + "parameter_default_values": { + "DEL_MODE": "USER_DEFINED", + "DEL_VALUE": "00000000000000000000000000000000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "Z": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1080.11-1080.12" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1081.12-1081.13" + } + } + } + }, + "DLLDELD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1159.1-1167.10" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "DDRDEL": { + "direction": "input", + "bits": [ 3 ] + }, + "LOADN": { + "direction": "input", + "bits": [ 4 ] + }, + "MOVE": { + "direction": "input", + "bits": [ 5 ] + }, + "DIRECTION": { + "direction": "input", + "bits": [ 6 ] + }, + "Z": { + "direction": "output", + "bits": [ 7 ] + }, + "CFLAG": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1160.11-1160.12" + } + }, + "CFLAG": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1166.12-1166.17" + } + }, + "DDRDEL": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1161.11-1161.17" + } + }, + "DIRECTION": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1164.11-1164.20" + } + }, + "LOADN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1162.11-1162.16" + } + }, + "MOVE": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1163.11-1163.15" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1165.12-1165.13" + } + } + } + }, + "DP16KD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:5.1-219.10" + }, + "parameter_default_values": { + "ADA0MUX": "ADA0", + "ADA10MUX": "ADA10", + "ADA11MUX": "ADA11", + "ADA12MUX": "ADA12", + "ADA13MUX": "ADA13", + "ADA1MUX": "ADA1", + "ADA2MUX": "ADA2", + "ADA3MUX": "ADA3", + "ADA4MUX": "ADA4", + "ADA5MUX": "ADA5", + "ADA6MUX": "ADA6", + "ADA7MUX": "ADA7", + "ADA8MUX": "ADA8", + "ADA9MUX": "ADA9", + "ADB0MUX": "ADB0", + "ADB10MUX": "ADB10", + "ADB11MUX": "ADB11", + "ADB12MUX": "ADB12", + "ADB13MUX": "ADB13", + "ADB1MUX": "ADB1", + "ADB2MUX": "ADB2", + "ADB3MUX": "ADB3", + "ADB4MUX": "ADB4", + "ADB5MUX": "ADB5", + "ADB6MUX": "ADB6", + "ADB7MUX": "ADB7", + "ADB8MUX": "ADB8", + "ADB9MUX": "ADB9", + "ASYNC_RESET_RELEASE": "SYNC", + "CEAMUX": "CEA", + "CEBMUX": "CEB", + "CLKAMUX": "CLKA", + "CLKBMUX": "CLKB", + "CSA0MUX": "CSA0", + "CSA1MUX": "CSA1", + "CSA2MUX": "CSA2", + "CSB0MUX": "CSB0", + "CSB1MUX": "CSB1", + "CSB2MUX": "CSB2", + "CSDECODE_A": "0b000", + "CSDECODE_B": "0b000", + "DATA_WIDTH_A": "00000000000000000000000000010010", + "DATA_WIDTH_B": "00000000000000000000000000010010", + "DIA0MUX": "DIA0", + "DIA10MUX": "DIA10", + "DIA11MUX": "DIA11", + "DIA12MUX": "DIA12", + "DIA13MUX": "DIA13", + "DIA14MUX": "DIA14", + "DIA15MUX": "DIA15", + "DIA16MUX": "DIA16", + "DIA17MUX": "DIA17", + "DIA1MUX": "DIA1", + "DIA2MUX": "DIA2", + "DIA3MUX": "DIA3", + "DIA4MUX": "DIA4", + "DIA5MUX": "DIA5", + "DIA6MUX": "DIA6", + "DIA7MUX": "DIA7", + "DIA8MUX": "DIA8", + "DIA9MUX": "DIA9", + "DIB0MUX": "DIB0", + "DIB10MUX": "DIB10", + "DIB11MUX": "DIB11", + "DIB12MUX": "DIB12", + "DIB13MUX": "DIB13", + "DIB14MUX": "DIB14", + "DIB15MUX": "DIB15", + "DIB16MUX": "DIB16", + "DIB17MUX": "DIB17", + "DIB1MUX": "DIB1", + "DIB2MUX": "DIB2", + "DIB3MUX": "DIB3", + "DIB4MUX": "DIB4", + "DIB5MUX": "DIB5", + "DIB6MUX": "DIB6", + "DIB7MUX": "DIB7", + "DIB8MUX": "DIB8", + "DIB9MUX": "DIB9", + "DOA0MUX": "DOA0", + "DOA10MUX": "DOA10", + "DOA11MUX": "DOA11", + "DOA12MUX": "DOA12", + "DOA13MUX": "DOA13", + "DOA14MUX": "DOA14", + "DOA15MUX": "DOA15", + "DOA16MUX": "DOA16", + "DOA17MUX": "DOA17", + "DOA1MUX": "DOA1", + "DOA2MUX": "DOA2", + "DOA3MUX": "DOA3", + "DOA4MUX": "DOA4", + "DOA5MUX": "DOA5", + "DOA6MUX": "DOA6", + "DOA7MUX": "DOA7", + "DOA8MUX": "DOA8", + "DOA9MUX": "DOA9", + "DOB0MUX": "DOB0", + "DOB10MUX": "DOB10", + "DOB11MUX": "DOB11", + "DOB12MUX": "DOB12", + "DOB13MUX": "DOB13", + "DOB14MUX": "DOB14", + "DOB15MUX": "DOB15", + "DOB16MUX": "DOB16", + "DOB17MUX": "DOB17", + "DOB1MUX": "DOB1", + "DOB2MUX": "DOB2", + "DOB3MUX": "DOB3", + "DOB4MUX": "DOB4", + "DOB5MUX": "DOB5", + "DOB6MUX": "DOB6", + "DOB7MUX": "DOB7", + "DOB8MUX": "DOB8", + "DOB9MUX": "DOB9", + "GSR": "ENABLED", + "INITVAL_00": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_01": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_02": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_03": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_04": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_05": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_06": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_07": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_08": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_09": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_10": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_11": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_12": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_13": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_14": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_15": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_16": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_17": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_18": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_19": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_20": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_21": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_22": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_23": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_24": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_25": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_26": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_27": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_28": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_29": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_30": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_31": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_32": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_33": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_34": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_35": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_36": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_37": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_38": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_39": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INIT_DATA": "STATIC", + "OCEAMUX": "OCEA", + "OCEBMUX": "OCEB", + "REGMODE_A": "NOREG", + "REGMODE_B": "NOREG", + "RESETMODE": "SYNC", + "RSTAMUX": "RSTA", + "RSTBMUX": "RSTB", + "WEAMUX": "WEA", + "WEBMUX": "WEB", + "WID": "00000000000000000000000000000000", + "WRITEMODE_A": "NORMAL", + "WRITEMODE_B": "NORMAL" + }, + "ports": { + "DIA17": { + "direction": "input", + "bits": [ 2 ] + }, + "DIA16": { + "direction": "input", + "bits": [ 3 ] + }, + "DIA15": { + "direction": "input", + "bits": [ 4 ] + }, + "DIA14": { + "direction": "input", + "bits": [ 5 ] + }, + "DIA13": { + "direction": "input", + "bits": [ 6 ] + }, + "DIA12": { + "direction": "input", + "bits": [ 7 ] + }, + "DIA11": { + "direction": "input", + "bits": [ 8 ] + }, + "DIA10": { + "direction": "input", + "bits": [ 9 ] + }, + "DIA9": { + "direction": "input", + "bits": [ 10 ] + }, + "DIA8": { + "direction": "input", + "bits": [ 11 ] + }, + "DIA7": { + "direction": "input", + "bits": [ 12 ] + }, + "DIA6": { + "direction": "input", + "bits": [ 13 ] + }, + "DIA5": { + "direction": "input", + "bits": [ 14 ] + }, + "DIA4": { + "direction": "input", + "bits": [ 15 ] + }, + "DIA3": { + "direction": "input", + "bits": [ 16 ] + }, + "DIA2": { + "direction": "input", + "bits": [ 17 ] + }, + "DIA1": { + "direction": "input", + "bits": [ 18 ] + }, + "DIA0": { + "direction": "input", + "bits": [ 19 ] + }, + "ADA13": { + "direction": "input", + "bits": [ 20 ] + }, + "ADA12": { + "direction": "input", + "bits": [ 21 ] + }, + "ADA11": { + "direction": "input", + "bits": [ 22 ] + }, + "ADA10": { + "direction": "input", + "bits": [ 23 ] + }, + "ADA9": { + "direction": "input", + "bits": [ 24 ] + }, + "ADA8": { + "direction": "input", + "bits": [ 25 ] + }, + "ADA7": { + "direction": "input", + "bits": [ 26 ] + }, + "ADA6": { + "direction": "input", + "bits": [ 27 ] + }, + "ADA5": { + "direction": "input", + "bits": [ 28 ] + }, + "ADA4": { + "direction": "input", + "bits": [ 29 ] + }, + "ADA3": { + "direction": "input", + "bits": [ 30 ] + }, + "ADA2": { + "direction": "input", + "bits": [ 31 ] + }, + "ADA1": { + "direction": "input", + "bits": [ 32 ] + }, + "ADA0": { + "direction": "input", + "bits": [ 33 ] + }, + "CEA": { + "direction": "input", + "bits": [ 34 ] + }, + "OCEA": { + "direction": "input", + "bits": [ 35 ] + }, + "CLKA": { + "direction": "input", + "bits": [ 36 ] + }, + "WEA": { + "direction": "input", + "bits": [ 37 ] + }, + "RSTA": { + "direction": "input", + "bits": [ 38 ] + }, + "CSA2": { + "direction": "input", + "bits": [ 39 ] + }, + "CSA1": { + "direction": "input", + "bits": [ 40 ] + }, + "CSA0": { + "direction": "input", + "bits": [ 41 ] + }, + "DOA17": { + "direction": "output", + "bits": [ 42 ] + }, + "DOA16": { + "direction": "output", + "bits": [ 43 ] + }, + "DOA15": { + "direction": "output", + "bits": [ 44 ] + }, + "DOA14": { + "direction": "output", + "bits": [ 45 ] + }, + "DOA13": { + "direction": "output", + "bits": [ 46 ] + }, + "DOA12": { + "direction": "output", + "bits": [ 47 ] + }, + "DOA11": { + "direction": "output", + "bits": [ 48 ] + }, + "DOA10": { + "direction": "output", + "bits": [ 49 ] + }, + "DOA9": { + "direction": "output", + "bits": [ 50 ] + }, + "DOA8": { + "direction": "output", + "bits": [ 51 ] + }, + "DOA7": { + "direction": "output", + "bits": [ 52 ] + }, + "DOA6": { + "direction": "output", + "bits": [ 53 ] + }, + "DOA5": { + "direction": "output", + "bits": [ 54 ] + }, + "DOA4": { + "direction": "output", + "bits": [ 55 ] + }, + "DOA3": { + "direction": "output", + "bits": [ 56 ] + }, + "DOA2": { + "direction": "output", + "bits": [ 57 ] + }, + "DOA1": { + "direction": "output", + "bits": [ 58 ] + }, + "DOA0": { + "direction": "output", + "bits": [ 59 ] + }, + "DIB17": { + "direction": "input", + "bits": [ 60 ] + }, + "DIB16": { + "direction": "input", + "bits": [ 61 ] + }, + "DIB15": { + "direction": "input", + "bits": [ 62 ] + }, + "DIB14": { + "direction": "input", + "bits": [ 63 ] + }, + "DIB13": { + "direction": "input", + "bits": [ 64 ] + }, + "DIB12": { + "direction": "input", + "bits": [ 65 ] + }, + "DIB11": { + "direction": "input", + "bits": [ 66 ] + }, + "DIB10": { + "direction": "input", + "bits": [ 67 ] + }, + "DIB9": { + "direction": "input", + "bits": [ 68 ] + }, + "DIB8": { + "direction": "input", + "bits": [ 69 ] + }, + "DIB7": { + "direction": "input", + "bits": [ 70 ] + }, + "DIB6": { + "direction": "input", + "bits": [ 71 ] + }, + "DIB5": { + "direction": "input", + "bits": [ 72 ] + }, + "DIB4": { + "direction": "input", + "bits": [ 73 ] + }, + "DIB3": { + "direction": "input", + "bits": [ 74 ] + }, + "DIB2": { + "direction": "input", + "bits": [ 75 ] + }, + "DIB1": { + "direction": "input", + "bits": [ 76 ] + }, + "DIB0": { + "direction": "input", + "bits": [ 77 ] + }, + "ADB13": { + "direction": "input", + "bits": [ 78 ] + }, + "ADB12": { + "direction": "input", + "bits": [ 79 ] + }, + "ADB11": { + "direction": "input", + "bits": [ 80 ] + }, + "ADB10": { + "direction": "input", + "bits": [ 81 ] + }, + "ADB9": { + "direction": "input", + "bits": [ 82 ] + }, + "ADB8": { + "direction": "input", + "bits": [ 83 ] + }, + "ADB7": { + "direction": "input", + "bits": [ 84 ] + }, + "ADB6": { + "direction": "input", + "bits": [ 85 ] + }, + "ADB5": { + "direction": "input", + "bits": [ 86 ] + }, + "ADB4": { + "direction": "input", + "bits": [ 87 ] + }, + "ADB3": { + "direction": "input", + "bits": [ 88 ] + }, + "ADB2": { + "direction": "input", + "bits": [ 89 ] + }, + "ADB1": { + "direction": "input", + "bits": [ 90 ] + }, + "ADB0": { + "direction": "input", + "bits": [ 91 ] + }, + "CEB": { + "direction": "input", + "bits": [ 92 ] + }, + "OCEB": { + "direction": "input", + "bits": [ 93 ] + }, + "CLKB": { + "direction": "input", + "bits": [ 94 ] + }, + "WEB": { + "direction": "input", + "bits": [ 95 ] + }, + "RSTB": { + "direction": "input", + "bits": [ 96 ] + }, + "CSB2": { + "direction": "input", + "bits": [ 97 ] + }, + "CSB1": { + "direction": "input", + "bits": [ 98 ] + }, + "CSB0": { + "direction": "input", + "bits": [ 99 ] + }, + "DOB17": { + "direction": "output", + "bits": [ 100 ] + }, + "DOB16": { + "direction": "output", + "bits": [ 101 ] + }, + "DOB15": { + "direction": "output", + "bits": [ 102 ] + }, + "DOB14": { + "direction": "output", + "bits": [ 103 ] + }, + "DOB13": { + "direction": "output", + "bits": [ 104 ] + }, + "DOB12": { + "direction": "output", + "bits": [ 105 ] + }, + "DOB11": { + "direction": "output", + "bits": [ 106 ] + }, + "DOB10": { + "direction": "output", + "bits": [ 107 ] + }, + "DOB9": { + "direction": "output", + "bits": [ 108 ] + }, + "DOB8": { + "direction": "output", + "bits": [ 109 ] + }, + "DOB7": { + "direction": "output", + "bits": [ 110 ] + }, + "DOB6": { + "direction": "output", + "bits": [ 111 ] + }, + "DOB5": { + "direction": "output", + "bits": [ 112 ] + }, + "DOB4": { + "direction": "output", + "bits": [ 113 ] + }, + "DOB3": { + "direction": "output", + "bits": [ 114 ] + }, + "DOB2": { + "direction": "output", + "bits": [ 115 ] + }, + "DOB1": { + "direction": "output", + "bits": [ 116 ] + }, + "DOB0": { + "direction": "output", + "bits": [ 117 ] + } + }, + "cells": { + }, + "netnames": { + "ADA0": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.91-7.95" + } + }, + "ADA1": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.85-7.89" + } + }, + "ADA10": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.30-7.35" + } + }, + "ADA11": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.23-7.28" + } + }, + "ADA12": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.16-7.21" + } + }, + "ADA13": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.9-7.14" + } + }, + "ADA2": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.79-7.83" + } + }, + "ADA3": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.73-7.77" + } + }, + "ADA4": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.67-7.71" + } + }, + "ADA5": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.61-7.65" + } + }, + "ADA6": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.55-7.59" + } + }, + "ADA7": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.49-7.53" + } + }, + "ADA8": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.43-7.47" + } + }, + "ADA9": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.37-7.41" + } + }, + "ADB0": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.91-13.95" + } + }, + "ADB1": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.85-13.89" + } + }, + "ADB10": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.30-13.35" + } + }, + "ADB11": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.23-13.28" + } + }, + "ADB12": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.16-13.21" + } + }, + "ADB13": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.9-13.14" + } + }, + "ADB2": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.79-13.83" + } + }, + "ADB3": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.73-13.77" + } + }, + "ADB4": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.67-13.71" + } + }, + "ADB5": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.61-13.65" + } + }, + "ADB6": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.55-13.59" + } + }, + "ADB7": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.49-13.53" + } + }, + "ADB8": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.43-13.47" + } + }, + "ADB9": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.37-13.41" + } + }, + "CEA": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.9-8.12" + } + }, + "CEB": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.9-14.12" + } + }, + "CLKA": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.20-8.24" + } + }, + "CLKB": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.20-14.24" + } + }, + "CSA0": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:9.21-9.25" + } + }, + "CSA1": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:9.15-9.19" + } + }, + "CSA2": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:9.9-9.13" + } + }, + "CSB0": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:15.21-15.25" + } + }, + "CSB1": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:15.15-15.19" + } + }, + "CSB2": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:15.9-15.13" + } + }, + "DIA0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.119-6.123" + } + }, + "DIA1": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.113-6.117" + } + }, + "DIA10": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.58-6.63" + } + }, + "DIA11": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.51-6.56" + } + }, + "DIA12": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.44-6.49" + } + }, + "DIA13": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.37-6.42" + } + }, + "DIA14": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.30-6.35" + } + }, + "DIA15": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.23-6.28" + } + }, + "DIA16": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.16-6.21" + } + }, + "DIA17": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.9-6.14" + } + }, + "DIA2": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.107-6.111" + } + }, + "DIA3": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.101-6.105" + } + }, + "DIA4": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.95-6.99" + } + }, + "DIA5": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.89-6.93" + } + }, + "DIA6": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.83-6.87" + } + }, + "DIA7": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.77-6.81" + } + }, + "DIA8": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.71-6.75" + } + }, + "DIA9": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.65-6.69" + } + }, + "DIB0": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.119-12.123" + } + }, + "DIB1": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.113-12.117" + } + }, + "DIB10": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.58-12.63" + } + }, + "DIB11": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.51-12.56" + } + }, + "DIB12": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.44-12.49" + } + }, + "DIB13": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.37-12.42" + } + }, + "DIB14": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.30-12.35" + } + }, + "DIB15": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.23-12.28" + } + }, + "DIB16": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.16-12.21" + } + }, + "DIB17": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.9-12.14" + } + }, + "DIB2": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.107-12.111" + } + }, + "DIB3": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.101-12.105" + } + }, + "DIB4": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.95-12.99" + } + }, + "DIB5": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.89-12.93" + } + }, + "DIB6": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.83-12.87" + } + }, + "DIB7": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.77-12.81" + } + }, + "DIB8": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.71-12.75" + } + }, + "DIB9": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.65-12.69" + } + }, + "DOA0": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.120-10.124" + } + }, + "DOA1": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.114-10.118" + } + }, + "DOA10": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.59-10.64" + } + }, + "DOA11": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.52-10.57" + } + }, + "DOA12": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.45-10.50" + } + }, + "DOA13": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.38-10.43" + } + }, + "DOA14": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.31-10.36" + } + }, + "DOA15": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.24-10.29" + } + }, + "DOA16": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.17-10.22" + } + }, + "DOA17": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.10-10.15" + } + }, + "DOA2": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.108-10.112" + } + }, + "DOA3": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.102-10.106" + } + }, + "DOA4": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.96-10.100" + } + }, + "DOA5": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.90-10.94" + } + }, + "DOA6": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.84-10.88" + } + }, + "DOA7": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.78-10.82" + } + }, + "DOA8": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.72-10.76" + } + }, + "DOA9": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.66-10.70" + } + }, + "DOB0": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.120-16.124" + } + }, + "DOB1": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.114-16.118" + } + }, + "DOB10": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.59-16.64" + } + }, + "DOB11": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.52-16.57" + } + }, + "DOB12": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.45-16.50" + } + }, + "DOB13": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.38-16.43" + } + }, + "DOB14": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.31-16.36" + } + }, + "DOB15": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.24-16.29" + } + }, + "DOB16": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.17-16.22" + } + }, + "DOB17": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.10-16.15" + } + }, + "DOB2": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.108-16.112" + } + }, + "DOB3": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.102-16.106" + } + }, + "DOB4": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.96-16.100" + } + }, + "DOB5": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.90-16.94" + } + }, + "DOB6": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.84-16.88" + } + }, + "DOB7": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.78-16.82" + } + }, + "DOB8": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.72-16.76" + } + }, + "DOB9": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.66-16.70" + } + }, + "OCEA": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.14-8.18" + } + }, + "OCEB": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.14-14.18" + } + }, + "RSTA": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.31-8.35" + } + }, + "RSTB": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.31-14.35" + } + }, + "WEA": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.26-8.29" + } + }, + "WEB": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.26-14.29" + } + } + } + }, + "DPR16X4C": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000110", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:174.1-233.10" + }, + "parameter_default_values": { + "INITVAL": "0x0000000000000000 " + }, + "ports": { + "DI": { + "direction": "input", + "bits": [ 2, 3, 4, 5 ] + }, + "WCK": { + "direction": "input", + "bits": [ 6 ] + }, + "WRE": { + "direction": "input", + "bits": [ 7 ] + }, + "RAD": { + "direction": "input", + "bits": [ 8, 9, 10, 11 ] + }, + "WAD": { + "direction": "input", + "bits": [ 12, 13, 14, 15 ] + }, + "DO": { + "direction": "output", + "bits": [ 16, 17, 18, 19 ] + } + }, + "cells": { + }, + "netnames": { + "DI": { + "hide_name": 0, + "bits": [ 2, 3, 4, 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:175.15-175.17" + } + }, + "DO": { + "hide_name": 0, + "bits": [ 16, 17, 18, 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:179.16-179.18" + } + }, + "RAD": { + "hide_name": 0, + "bits": [ 8, 9, 10, 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:177.15-177.18" + } + }, + "WAD": { + "hide_name": 0, + "bits": [ 12, 13, 14, 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:178.15-178.18" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:176.9-176.12" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:176.14-176.17" + } + } + } + }, + "DQSBUFM": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1091.1-1136.10" + }, + "parameter_default_values": { + "DQS_LI_DEL_ADJ": "FACTORYONLY", + "DQS_LI_DEL_VAL": "00000000000000000000000000000100", + "DQS_LO_DEL_ADJ": "FACTORYONLY", + "DQS_LO_DEL_VAL": "00000000000000000000000000000000", + "GSR": "ENABLED" + }, + "ports": { + "DQSI": { + "direction": "input", + "bits": [ 2 ] + }, + "READ1": { + "direction": "input", + "bits": [ 3 ] + }, + "READ0": { + "direction": "input", + "bits": [ 4 ] + }, + "READCLKSEL2": { + "direction": "input", + "bits": [ 5 ] + }, + "READCLKSEL1": { + "direction": "input", + "bits": [ 6 ] + }, + "READCLKSEL0": { + "direction": "input", + "bits": [ 7 ] + }, + "DDRDEL": { + "direction": "input", + "bits": [ 8 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 9 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "RST": { + "direction": "input", + "bits": [ 11 ] + }, + "DYNDELAY7": { + "direction": "input", + "bits": [ 12 ] + }, + "DYNDELAY6": { + "direction": "input", + "bits": [ 13 ] + }, + "DYNDELAY5": { + "direction": "input", + "bits": [ 14 ] + }, + "DYNDELAY4": { + "direction": "input", + "bits": [ 15 ] + }, + "DYNDELAY3": { + "direction": "input", + "bits": [ 16 ] + }, + "DYNDELAY2": { + "direction": "input", + "bits": [ 17 ] + }, + "DYNDELAY1": { + "direction": "input", + "bits": [ 18 ] + }, + "DYNDELAY0": { + "direction": "input", + "bits": [ 19 ] + }, + "PAUSE": { + "direction": "input", + "bits": [ 20 ] + }, + "RDLOADN": { + "direction": "input", + "bits": [ 21 ] + }, + "RDMOVE": { + "direction": "input", + "bits": [ 22 ] + }, + "RDDIRECTION": { + "direction": "input", + "bits": [ 23 ] + }, + "WRLOADN": { + "direction": "input", + "bits": [ 24 ] + }, + "WRMOVE": { + "direction": "input", + "bits": [ 25 ] + }, + "WRDIRECTION": { + "direction": "input", + "bits": [ 26 ] + }, + "DQSR90": { + "direction": "output", + "bits": [ 27 ] + }, + "DQSW": { + "direction": "output", + "bits": [ 28 ] + }, + "DQSW270": { + "direction": "output", + "bits": [ 29 ] + }, + "RDPNTR2": { + "direction": "output", + "bits": [ 30 ] + }, + "RDPNTR1": { + "direction": "output", + "bits": [ 31 ] + }, + "RDPNTR0": { + "direction": "output", + "bits": [ 32 ] + }, + "WRPNTR2": { + "direction": "output", + "bits": [ 33 ] + }, + "WRPNTR1": { + "direction": "output", + "bits": [ 34 ] + }, + "WRPNTR0": { + "direction": "output", + "bits": [ 35 ] + }, + "DATAVALID": { + "direction": "output", + "bits": [ 36 ] + }, + "BURSTDET": { + "direction": "output", + "bits": [ 37 ] + }, + "RDCFLAG": { + "direction": "output", + "bits": [ 38 ] + }, + "WRCFLAG": { + "direction": "output", + "bits": [ 39 ] + } + }, + "cells": { + }, + "netnames": { + "BURSTDET": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1133.12-1133.20" + } + }, + "DATAVALID": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1132.12-1132.21" + } + }, + "DDRDEL": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1104.11-1104.17" + } + }, + "DQSI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1098.11-1098.15" + } + }, + "DQSR90": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1123.12-1123.18" + } + }, + "DQSW": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1124.12-1124.16" + } + }, + "DQSW270": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1125.12-1125.19" + } + }, + "DYNDELAY0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1115.11-1115.20" + } + }, + "DYNDELAY1": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1114.11-1114.20" + } + }, + "DYNDELAY2": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1113.11-1113.20" + } + }, + "DYNDELAY3": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1112.11-1112.20" + } + }, + "DYNDELAY4": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1111.11-1111.20" + } + }, + "DYNDELAY5": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1110.11-1110.20" + } + }, + "DYNDELAY6": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1109.11-1109.20" + } + }, + "DYNDELAY7": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1108.11-1108.20" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1105.11-1105.15" + } + }, + "PAUSE": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1116.11-1116.16" + } + }, + "RDCFLAG": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1134.12-1134.19" + } + }, + "RDDIRECTION": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1119.11-1119.22" + } + }, + "RDLOADN": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1117.11-1117.18" + } + }, + "RDMOVE": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1118.11-1118.17" + } + }, + "RDPNTR0": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1128.12-1128.19" + } + }, + "RDPNTR1": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1127.12-1127.19" + } + }, + "RDPNTR2": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1126.12-1126.19" + } + }, + "READ0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1100.11-1100.16" + } + }, + "READ1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1099.11-1099.16" + } + }, + "READCLKSEL0": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1103.11-1103.22" + } + }, + "READCLKSEL1": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1102.11-1102.22" + } + }, + "READCLKSEL2": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1101.11-1101.22" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1107.11-1107.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1106.11-1106.15" + } + }, + "WRCFLAG": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1135.12-1135.19" + } + }, + "WRDIRECTION": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1122.11-1122.22" + } + }, + "WRLOADN": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1120.11-1120.18" + } + }, + "WRMOVE": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1121.11-1121.17" + } + }, + "WRPNTR0": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1131.12-1131.19" + } + }, + "WRPNTR1": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1130.12-1130.19" + } + }, + "WRPNTR2": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1129.12-1129.19" + } + } + } + }, + "DTR": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1399.1-1410.10" + }, + "parameter_default_values": { + "DTR_TEMP": "00000000000000000000000000011001" + }, + "ports": { + "STARTPULSE": { + "direction": "input", + "bits": [ 2 ] + }, + "DTROUT7": { + "direction": "output", + "bits": [ 3 ] + }, + "DTROUT6": { + "direction": "output", + "bits": [ 4 ] + }, + "DTROUT5": { + "direction": "output", + "bits": [ 5 ] + }, + "DTROUT4": { + "direction": "output", + "bits": [ 6 ] + }, + "DTROUT3": { + "direction": "output", + "bits": [ 7 ] + }, + "DTROUT2": { + "direction": "output", + "bits": [ 8 ] + }, + "DTROUT1": { + "direction": "output", + "bits": [ 9 ] + }, + "DTROUT0": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "DTROUT0": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1409.12-1409.19" + } + }, + "DTROUT1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1408.12-1408.19" + } + }, + "DTROUT2": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1407.12-1407.19" + } + }, + "DTROUT3": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1406.12-1406.19" + } + }, + "DTROUT4": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1405.12-1405.19" + } + }, + "DTROUT5": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1404.12-1404.19" + } + }, + "DTROUT6": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1403.12-1403.19" + } + }, + "DTROUT7": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1402.12-1402.19" + } + }, + "STARTPULSE": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1401.11-1401.21" + } + } + } + }, + "ECLKBRIDGECS": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1057.1-1062.10" + }, + "ports": { + "CLK0": { + "direction": "input", + "bits": [ 2 ] + }, + "CLK1": { + "direction": "input", + "bits": [ 3 ] + }, + "SEL": { + "direction": "input", + "bits": [ 4 ] + }, + "ECSOUT": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CLK0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1058.11-1058.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1059.11-1059.15" + } + }, + "ECSOUT": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1061.12-1061.18" + } + }, + "SEL": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1060.11-1060.14" + } + } + } + }, + "ECLKSYNCB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1050.1-1054.10" + }, + "ports": { + "ECLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "STOP": { + "direction": "input", + "bits": [ 3 ] + }, + "ECLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "ECLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1051.11-1051.16" + } + }, + "ECLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1053.12-1053.17" + } + }, + "STOP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1052.11-1052.15" + } + } + } + }, + "EHXPLLL": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1336.1-1396.10" + }, + "parameter_default_values": { + "CLKFB_DIV": "00000000000000000000000000000001", + "CLKI_DIV": "00000000000000000000000000000001", + "CLKOP_CPHASE": "00000000000000000000000000000000", + "CLKOP_DIV": "00000000000000000000000000001000", + "CLKOP_ENABLE": "ENABLED", + "CLKOP_FPHASE": "00000000000000000000000000000000", + "CLKOP_TRIM_DELAY": "00000000000000000000000000000000", + "CLKOP_TRIM_POL": "RISING", + "CLKOS2_CPHASE": "00000000000000000000000000000000", + "CLKOS2_DIV": "00000000000000000000000000001000", + "CLKOS2_ENABLE": "DISABLED", + "CLKOS2_FPHASE": "00000000000000000000000000000000", + "CLKOS3_CPHASE": "00000000000000000000000000000000", + "CLKOS3_DIV": "00000000000000000000000000001000", + "CLKOS3_ENABLE": "DISABLED", + "CLKOS3_FPHASE": "00000000000000000000000000000000", + "CLKOS_CPHASE": "00000000000000000000000000000000", + "CLKOS_DIV": "00000000000000000000000000001000", + "CLKOS_ENABLE": "DISABLED", + "CLKOS_FPHASE": "00000000000000000000000000000000", + "CLKOS_TRIM_DELAY": "00000000000000000000000000000000", + "CLKOS_TRIM_POL": "RISING", + "DPHASE_SOURCE": "DISABLED", + "FEEDBK_PATH": "CLKOP", + "INTFB_WAKE": "DISABLED", + "INT_LOCK_STICKY": "ENABLED", + "OUTDIVIDER_MUXA": "DIVA", + "OUTDIVIDER_MUXB": "DIVB", + "OUTDIVIDER_MUXC": "DIVC", + "OUTDIVIDER_MUXD": "DIVD", + "PLLRST_ENA": "DISABLED", + "PLL_LOCK_DELAY": "00000000000000000000000011001000", + "PLL_LOCK_MODE": "00000000000000000000000000000000", + "REFIN_RESET": "DISABLED", + "STDBY_ENABLE": "DISABLED", + "SYNC_ENABLE": "DISABLED" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "CLKFB": { + "direction": "input", + "bits": [ 3 ] + }, + "PHASESEL1": { + "direction": "input", + "bits": [ 4 ] + }, + "PHASESEL0": { + "direction": "input", + "bits": [ 5 ] + }, + "PHASEDIR": { + "direction": "input", + "bits": [ 6 ] + }, + "PHASESTEP": { + "direction": "input", + "bits": [ 7 ] + }, + "PHASELOADREG": { + "direction": "input", + "bits": [ 8 ] + }, + "STDBY": { + "direction": "input", + "bits": [ 9 ] + }, + "PLLWAKESYNC": { + "direction": "input", + "bits": [ 10 ] + }, + "RST": { + "direction": "input", + "bits": [ 11 ] + }, + "ENCLKOP": { + "direction": "input", + "bits": [ 12 ] + }, + "ENCLKOS": { + "direction": "input", + "bits": [ 13 ] + }, + "ENCLKOS2": { + "direction": "input", + "bits": [ 14 ] + }, + "ENCLKOS3": { + "direction": "input", + "bits": [ 15 ] + }, + "CLKOP": { + "direction": "output", + "bits": [ 16 ] + }, + "CLKOS": { + "direction": "output", + "bits": [ 17 ] + }, + "CLKOS2": { + "direction": "output", + "bits": [ 18 ] + }, + "CLKOS3": { + "direction": "output", + "bits": [ 19 ] + }, + "LOCK": { + "direction": "output", + "bits": [ 20 ] + }, + "INTLOCK": { + "direction": "output", + "bits": [ 21 ] + }, + "REFCLK": { + "direction": "output", + "bits": [ 22 ] + }, + "CLKINTFB": { + "direction": "output", + "bits": [ 23 ] + } + }, + "cells": { + }, + "netnames": { + "CLKFB": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1375.11-1375.16" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1374.11-1374.15" + } + }, + "CLKINTFB": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1395.12-1395.20" + } + }, + "CLKOP": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1388.12-1388.17" + } + }, + "CLKOS": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1389.12-1389.17" + } + }, + "CLKOS2": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1390.12-1390.18" + } + }, + "CLKOS3": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1391.12-1391.18" + } + }, + "ENCLKOP": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1384.11-1384.18" + } + }, + "ENCLKOS": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1385.11-1385.18" + } + }, + "ENCLKOS2": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1386.11-1386.19" + } + }, + "ENCLKOS3": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1387.11-1387.19" + } + }, + "INTLOCK": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1393.12-1393.19" + } + }, + "LOCK": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1392.12-1392.16" + } + }, + "PHASEDIR": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1378.11-1378.19" + } + }, + "PHASELOADREG": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1380.11-1380.23" + } + }, + "PHASESEL0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1377.11-1377.20" + } + }, + "PHASESEL1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1376.11-1376.20" + } + }, + "PHASESTEP": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1379.11-1379.20" + } + }, + "PLLWAKESYNC": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1382.11-1382.22" + } + }, + "REFCLK": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1394.12-1394.18" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1383.11-1383.14" + } + }, + "STDBY": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1381.11-1381.16" + } + } + } + }, + "EXTREFB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1419.1-1428.10" + }, + "parameter_default_values": { + "REFCK_DCBIAS_EN": "DONTCARE", + "REFCK_PWDNB": "DONTCARE", + "REFCK_RTERM": "DONTCARE" + }, + "ports": { + "REFCLKP": { + "direction": "input", + "bits": [ 2 ] + }, + "REFCLKN": { + "direction": "input", + "bits": [ 3 ] + }, + "REFCLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "REFCLKN": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1426.11-1426.18" + } + }, + "REFCLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1427.12-1427.19" + } + }, + "REFCLKP": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1424.11-1424.18" + } + } + } + }, + "FD1P3AX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SP": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.33-2.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.26-2.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.44-2.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.29-2.31" + } + } + } + }, + "FD1P3AY": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SP": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.33-3.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.26-3.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.44-3.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.29-3.31" + } + } + } + }, + "FD1P3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.33-4.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.26-4.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.22-4.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.44-4.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.29-4.31" + } + } + } + }, + "FD1P3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.22-5.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.33-5.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.26-5.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.44-5.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.29-5.31" + } + } + } + }, + "FD1P3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.22-6.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.33-6.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.26-6.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.44-6.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.29-6.31" + } + } + } + }, + "FD1P3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.33-7.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.26-7.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.22-7.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.44-7.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.29-7.31" + } + } + } + }, + "FD1S3AX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "CK": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.33-8.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.26-8.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.44-8.45" + } + } + } + }, + "FD1S3AY": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "CK": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.33-9.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.26-9.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.44-9.45" + } + } + } + }, + "FD1S3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.33-10.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.26-10.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.22-10.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.44-10.45" + } + } + } + }, + "FD1S3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.22-11.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.33-11.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.26-11.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.44-11.45" + } + } + } + }, + "FD1S3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.22-12.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.33-12.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.26-12.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.44-12.45" + } + } + } + }, + "FD1S3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.33-13.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.26-13.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.22-13.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.44-13.45" + } + } + } + }, + "GSR": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:4.1-6.10" + }, + "ports": { + "GSR": { + "direction": "input", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "GSR": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:5.11-5.14" + } + } + } + }, + "IB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.45-2.46" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.59-2.60" + } + } + } + }, + "IBPD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.45-4.46" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.59-4.60" + } + } + } + }, + "IBPU": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.45-3.46" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.59-3.60" + } + } + } + }, + "IDDR71B": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1194.1-1208.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 3 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 4 ] + }, + "RST": { + "direction": "input", + "bits": [ 5 ] + }, + "ALIGNWD": { + "direction": "input", + "bits": [ 6 ] + }, + "Q6": { + "direction": "output", + "bits": [ 7 ] + }, + "Q5": { + "direction": "output", + "bits": [ 8 ] + }, + "Q4": { + "direction": "output", + "bits": [ 9 ] + }, + "Q3": { + "direction": "output", + "bits": [ 10 ] + }, + "Q2": { + "direction": "output", + "bits": [ 11 ] + }, + "Q1": { + "direction": "output", + "bits": [ 12 ] + }, + "Q0": { + "direction": "output", + "bits": [ 13 ] + } + }, + "cells": { + }, + "netnames": { + "ALIGNWD": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1200.11-1200.18" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1196.11-1196.12" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1198.11-1198.15" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1207.12-1207.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1206.12-1206.14" + } + }, + "Q2": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1205.12-1205.14" + } + }, + "Q3": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1204.12-1204.14" + } + }, + "Q4": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1203.12-1203.14" + } + }, + "Q5": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1202.12-1202.14" + } + }, + "Q6": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1201.12-1201.14" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1199.11-1199.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1197.11-1197.15" + } + } + } + }, + "IDDRX1F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1170.1-1177.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 3 ] + }, + "RST": { + "direction": "input", + "bits": [ 4 ] + }, + "Q0": { + "direction": "output", + "bits": [ 5 ] + }, + "Q1": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1172.11-1172.12" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1175.12-1175.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1176.12-1176.14" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1174.11-1174.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1173.11-1173.15" + } + } + } + }, + "IDDRX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1211.1-1229.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 3 ] + }, + "DQSR90": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "RST": { + "direction": "input", + "bits": [ 6 ] + }, + "RDPNTR2": { + "direction": "input", + "bits": [ 7 ] + }, + "RDPNTR1": { + "direction": "input", + "bits": [ 8 ] + }, + "RDPNTR0": { + "direction": "input", + "bits": [ 9 ] + }, + "WRPNTR2": { + "direction": "input", + "bits": [ 10 ] + }, + "WRPNTR1": { + "direction": "input", + "bits": [ 11 ] + }, + "WRPNTR0": { + "direction": "input", + "bits": [ 12 ] + }, + "Q3": { + "direction": "output", + "bits": [ 13 ] + }, + "Q2": { + "direction": "output", + "bits": [ 14 ] + }, + "Q1": { + "direction": "output", + "bits": [ 15 ] + }, + "Q0": { + "direction": "output", + "bits": [ 16 ] + }, + "QWL": { + "direction": "output", + "bits": [ 17 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1216.11-1216.12" + } + }, + "DQSR90": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1215.11-1215.17" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1214.11-1214.15" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1227.12-1227.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1226.12-1226.14" + } + }, + "Q2": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1225.12-1225.14" + } + }, + "Q3": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1224.12-1224.14" + } + }, + "QWL": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1228.12-1228.15" + } + }, + "RDPNTR0": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1220.11-1220.18" + } + }, + "RDPNTR1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1219.11-1219.18" + } + }, + "RDPNTR2": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1218.11-1218.18" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1217.11-1217.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1213.11-1213.15" + } + }, + "WRPNTR0": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1223.11-1223.18" + } + }, + "WRPNTR1": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1222.11-1222.18" + } + }, + "WRPNTR2": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1221.11-1221.18" + } + } + } + }, + "IDDRX2F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1180.1-1191.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 3 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 4 ] + }, + "RST": { + "direction": "input", + "bits": [ 5 ] + }, + "ALIGNWD": { + "direction": "input", + "bits": [ 6 ] + }, + "Q3": { + "direction": "output", + "bits": [ 7 ] + }, + "Q2": { + "direction": "output", + "bits": [ 8 ] + }, + "Q1": { + "direction": "output", + "bits": [ 9 ] + }, + "Q0": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "ALIGNWD": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1186.11-1186.18" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1182.11-1182.12" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1184.11-1184.15" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1190.12-1190.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1189.12-1189.14" + } + }, + "Q2": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1188.12-1188.14" + } + }, + "Q3": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1187.12-1187.14" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1185.11-1185.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1183.11-1183.15" + } + } + } + }, + "IFS1P3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.27-26.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.23-26.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.47-26.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.34-26.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.30-26.32" + } + } + } + }, + "IFS1P3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.23-27.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.27-27.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.47-27.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.34-27.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.30-27.32" + } + } + } + }, + "IFS1P3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.23-28.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.27-28.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.47-28.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.34-28.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.30-28.32" + } + } + } + }, + "IFS1P3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.27-29.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.23-29.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.47-29.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.34-29.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.30-29.32" + } + } + } + }, + "ILVDS": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "AN": { + "direction": "input", + "bits": [ 3 ] + }, + "Z": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.20-13.21" + } + }, + "AN": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.23-13.25" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.59-13.60" + } + } + } + }, + "INV": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:348.1-350.10" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "Z": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:348.18-348.19" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:348.28-348.29" + } + } + } + }, + "JTAGG": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1431.1-1453.10" + }, + "parameter_default_values": { + "ER1": "ENABLED", + "ER2": "ENABLED" + }, + "ports": { + "TCK": { + "direction": "input", + "bits": [ 2 ] + }, + "TMS": { + "direction": "input", + "bits": [ 3 ] + }, + "TDI": { + "direction": "input", + "bits": [ 4 ] + }, + "JTDO2": { + "direction": "input", + "bits": [ 5 ] + }, + "JTDO1": { + "direction": "input", + "bits": [ 6 ] + }, + "TDO": { + "direction": "output", + "bits": [ 7 ] + }, + "JTDI": { + "direction": "output", + "bits": [ 8 ] + }, + "JTCK": { + "direction": "output", + "bits": [ 9 ] + }, + "JRTI2": { + "direction": "output", + "bits": [ 10 ] + }, + "JRTI1": { + "direction": "output", + "bits": [ 11 ] + }, + "JSHIFT": { + "direction": "output", + "bits": [ 12 ] + }, + "JUPDATE": { + "direction": "output", + "bits": [ 13 ] + }, + "JRSTN": { + "direction": "output", + "bits": [ 14 ] + }, + "JCE2": { + "direction": "output", + "bits": [ 15 ] + }, + "JCE1": { + "direction": "output", + "bits": [ 16 ] + } + }, + "cells": { + }, + "netnames": { + "JCE1": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1452.12-1452.16" + } + }, + "JCE2": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1451.12-1451.16" + } + }, + "JRSTN": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1450.12-1450.17" + } + }, + "JRTI1": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1447.12-1447.17" + } + }, + "JRTI2": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1446.12-1446.17" + } + }, + "JSHIFT": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1448.12-1448.18" + } + }, + "JTCK": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1445.12-1445.16" + } + }, + "JTDI": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1444.12-1444.16" + } + }, + "JTDO1": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1441.11-1441.16" + } + }, + "JTDO2": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1440.11-1440.16" + } + }, + "JUPDATE": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1449.12-1449.19" + } + }, + "TCK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1435.11-1435.14" + } + }, + "TDI": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1439.11-1439.14" + } + }, + "TDO": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1443.12-1443.15" + } + }, + "TMS": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1437.11-1437.14" + } + } + } + }, + "L6MUX21": { + "attributes": { + "abc9_box_id": "00000000000000000000000000001001", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.1-72.10" + }, + "ports": { + "D0": { + "direction": "input", + "bits": [ 2 ] + }, + "D1": { + "direction": "input", + "bits": [ 3 ] + }, + "SD": { + "direction": "input", + "bits": [ 4 ] + }, + "Z": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.23-65.25" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.27-65.29" + } + }, + "SD": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.31-65.33" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.42-65.43" + } + } + } + }, + "LUT2": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.1-242.10" + }, + "parameter_default_values": { + "INIT": "0000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "B": { + "direction": "input", + "bits": [ 3 ] + }, + "Z": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.19-238.20" + } + }, + "B": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.22-238.23" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.32-238.33" + } + } + } + }, + "LUT4": { + "attributes": { + "abc9_lut": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.1-16.10" + }, + "parameter_default_values": { + "INIT": "0000000000000000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "B": { + "direction": "input", + "bits": [ 3 ] + }, + "C": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "Z": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.19-4.20" + } + }, + "B": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.22-4.23" + } + }, + "C": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.25-4.26" + } + }, + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.28-4.29" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.38-4.39" + } + } + } + }, + "MULT18X18D": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:216.1-486.10" + }, + "parameter_default_values": { + "CAS_MATCH_REG": "FALSE", + "CLK0_DIV": "ENABLED", + "CLK1_DIV": "ENABLED", + "CLK2_DIV": "ENABLED", + "CLK3_DIV": "ENABLED", + "GSR": "ENABLED", + "HIGHSPEED_CLK": "NONE", + "MULT_BYPASS": "DISABLED", + "REG_INPUTA_CE": "CE0", + "REG_INPUTA_CLK": "NONE", + "REG_INPUTA_RST": "RST0", + "REG_INPUTB_CE": "CE0", + "REG_INPUTB_CLK": "NONE", + "REG_INPUTB_RST": "RST0", + "REG_INPUTC_CE": "CE0", + "REG_INPUTC_CLK": "NONE", + "REG_INPUTC_RST": "RST0", + "REG_OUTPUT_CE": "CE0", + "REG_OUTPUT_CLK": "NONE", + "REG_OUTPUT_RST": "RST0", + "REG_PIPELINE_CE": "CE0", + "REG_PIPELINE_CLK": "NONE", + "REG_PIPELINE_RST": "RST0", + "RESETMODE": "SYNC", + "SOURCEB_MODE": "B_SHIFT" + }, + "ports": { + "A17": { + "direction": "input", + "bits": [ 2 ] + }, + "A16": { + "direction": "input", + "bits": [ 3 ] + }, + "A15": { + "direction": "input", + "bits": [ 4 ] + }, + "A14": { + "direction": "input", + "bits": [ 5 ] + }, + "A13": { + "direction": "input", + "bits": [ 6 ] + }, + "A12": { + "direction": "input", + "bits": [ 7 ] + }, + "A11": { + "direction": "input", + "bits": [ 8 ] + }, + "A10": { + "direction": "input", + "bits": [ 9 ] + }, + "A9": { + "direction": "input", + "bits": [ 10 ] + }, + "A8": { + "direction": "input", + "bits": [ 11 ] + }, + "A7": { + "direction": "input", + "bits": [ 12 ] + }, + "A6": { + "direction": "input", + "bits": [ 13 ] + }, + "A5": { + "direction": "input", + "bits": [ 14 ] + }, + "A4": { + "direction": "input", + "bits": [ 15 ] + }, + "A3": { + "direction": "input", + "bits": [ 16 ] + }, + "A2": { + "direction": "input", + "bits": [ 17 ] + }, + "A1": { + "direction": "input", + "bits": [ 18 ] + }, + "A0": { + "direction": "input", + "bits": [ 19 ] + }, + "B17": { + "direction": "input", + "bits": [ 20 ] + }, + "B16": { + "direction": "input", + "bits": [ 21 ] + }, + "B15": { + "direction": "input", + "bits": [ 22 ] + }, + "B14": { + "direction": "input", + "bits": [ 23 ] + }, + "B13": { + "direction": "input", + "bits": [ 24 ] + }, + "B12": { + "direction": "input", + "bits": [ 25 ] + }, + "B11": { + "direction": "input", + "bits": [ 26 ] + }, + "B10": { + "direction": "input", + "bits": [ 27 ] + }, + "B9": { + "direction": "input", + "bits": [ 28 ] + }, + "B8": { + "direction": "input", + "bits": [ 29 ] + }, + "B7": { + "direction": "input", + "bits": [ 30 ] + }, + "B6": { + "direction": "input", + "bits": [ 31 ] + }, + "B5": { + "direction": "input", + "bits": [ 32 ] + }, + "B4": { + "direction": "input", + "bits": [ 33 ] + }, + "B3": { + "direction": "input", + "bits": [ 34 ] + }, + "B2": { + "direction": "input", + "bits": [ 35 ] + }, + "B1": { + "direction": "input", + "bits": [ 36 ] + }, + "B0": { + "direction": "input", + "bits": [ 37 ] + }, + "C17": { + "direction": "input", + "bits": [ 38 ] + }, + "C16": { + "direction": "input", + "bits": [ 39 ] + }, + "C15": { + "direction": "input", + "bits": [ 40 ] + }, + "C14": { + "direction": "input", + "bits": [ 41 ] + }, + "C13": { + "direction": "input", + "bits": [ 42 ] + }, + "C12": { + "direction": "input", + "bits": [ 43 ] + }, + "C11": { + "direction": "input", + "bits": [ 44 ] + }, + "C10": { + "direction": "input", + "bits": [ 45 ] + }, + "C9": { + "direction": "input", + "bits": [ 46 ] + }, + "C8": { + "direction": "input", + "bits": [ 47 ] + }, + "C7": { + "direction": "input", + "bits": [ 48 ] + }, + "C6": { + "direction": "input", + "bits": [ 49 ] + }, + "C5": { + "direction": "input", + "bits": [ 50 ] + }, + "C4": { + "direction": "input", + "bits": [ 51 ] + }, + "C3": { + "direction": "input", + "bits": [ 52 ] + }, + "C2": { + "direction": "input", + "bits": [ 53 ] + }, + "C1": { + "direction": "input", + "bits": [ 54 ] + }, + "C0": { + "direction": "input", + "bits": [ 55 ] + }, + "SIGNEDA": { + "direction": "input", + "bits": [ 56 ] + }, + "SIGNEDB": { + "direction": "input", + "bits": [ 57 ] + }, + "SOURCEA": { + "direction": "input", + "bits": [ 58 ] + }, + "SOURCEB": { + "direction": "input", + "bits": [ 59 ] + }, + "CLK3": { + "direction": "input", + "bits": [ 60 ] + }, + "CLK2": { + "direction": "input", + "bits": [ 61 ] + }, + "CLK1": { + "direction": "input", + "bits": [ 62 ] + }, + "CLK0": { + "direction": "input", + "bits": [ 63 ] + }, + "CE3": { + "direction": "input", + "bits": [ 64 ] + }, + "CE2": { + "direction": "input", + "bits": [ 65 ] + }, + "CE1": { + "direction": "input", + "bits": [ 66 ] + }, + "CE0": { + "direction": "input", + "bits": [ 67 ] + }, + "RST3": { + "direction": "input", + "bits": [ 68 ] + }, + "RST2": { + "direction": "input", + "bits": [ 69 ] + }, + "RST1": { + "direction": "input", + "bits": [ 70 ] + }, + "RST0": { + "direction": "input", + "bits": [ 71 ] + }, + "SRIA17": { + "direction": "input", + "bits": [ 72 ] + }, + "SRIA16": { + "direction": "input", + "bits": [ 73 ] + }, + "SRIA15": { + "direction": "input", + "bits": [ 74 ] + }, + "SRIA14": { + "direction": "input", + "bits": [ 75 ] + }, + "SRIA13": { + "direction": "input", + "bits": [ 76 ] + }, + "SRIA12": { + "direction": "input", + "bits": [ 77 ] + }, + "SRIA11": { + "direction": "input", + "bits": [ 78 ] + }, + "SRIA10": { + "direction": "input", + "bits": [ 79 ] + }, + "SRIA9": { + "direction": "input", + "bits": [ 80 ] + }, + "SRIA8": { + "direction": "input", + "bits": [ 81 ] + }, + "SRIA7": { + "direction": "input", + "bits": [ 82 ] + }, + "SRIA6": { + "direction": "input", + "bits": [ 83 ] + }, + "SRIA5": { + "direction": "input", + "bits": [ 84 ] + }, + "SRIA4": { + "direction": "input", + "bits": [ 85 ] + }, + "SRIA3": { + "direction": "input", + "bits": [ 86 ] + }, + "SRIA2": { + "direction": "input", + "bits": [ 87 ] + }, + "SRIA1": { + "direction": "input", + "bits": [ 88 ] + }, + "SRIA0": { + "direction": "input", + "bits": [ 89 ] + }, + "SRIB17": { + "direction": "input", + "bits": [ 90 ] + }, + "SRIB16": { + "direction": "input", + "bits": [ 91 ] + }, + "SRIB15": { + "direction": "input", + "bits": [ 92 ] + }, + "SRIB14": { + "direction": "input", + "bits": [ 93 ] + }, + "SRIB13": { + "direction": "input", + "bits": [ 94 ] + }, + "SRIB12": { + "direction": "input", + "bits": [ 95 ] + }, + "SRIB11": { + "direction": "input", + "bits": [ 96 ] + }, + "SRIB10": { + "direction": "input", + "bits": [ 97 ] + }, + "SRIB9": { + "direction": "input", + "bits": [ 98 ] + }, + "SRIB8": { + "direction": "input", + "bits": [ 99 ] + }, + "SRIB7": { + "direction": "input", + "bits": [ 100 ] + }, + "SRIB6": { + "direction": "input", + "bits": [ 101 ] + }, + "SRIB5": { + "direction": "input", + "bits": [ 102 ] + }, + "SRIB4": { + "direction": "input", + "bits": [ 103 ] + }, + "SRIB3": { + "direction": "input", + "bits": [ 104 ] + }, + "SRIB2": { + "direction": "input", + "bits": [ 105 ] + }, + "SRIB1": { + "direction": "input", + "bits": [ 106 ] + }, + "SRIB0": { + "direction": "input", + "bits": [ 107 ] + }, + "SROA17": { + "direction": "output", + "bits": [ 108 ] + }, + "SROA16": { + "direction": "output", + "bits": [ 109 ] + }, + "SROA15": { + "direction": "output", + "bits": [ 110 ] + }, + "SROA14": { + "direction": "output", + "bits": [ 111 ] + }, + "SROA13": { + "direction": "output", + "bits": [ 112 ] + }, + "SROA12": { + "direction": "output", + "bits": [ 113 ] + }, + "SROA11": { + "direction": "output", + "bits": [ 114 ] + }, + "SROA10": { + "direction": "output", + "bits": [ 115 ] + }, + "SROA9": { + "direction": "output", + "bits": [ 116 ] + }, + "SROA8": { + "direction": "output", + "bits": [ 117 ] + }, + "SROA7": { + "direction": "output", + "bits": [ 118 ] + }, + "SROA6": { + "direction": "output", + "bits": [ 119 ] + }, + "SROA5": { + "direction": "output", + "bits": [ 120 ] + }, + "SROA4": { + "direction": "output", + "bits": [ 121 ] + }, + "SROA3": { + "direction": "output", + "bits": [ 122 ] + }, + "SROA2": { + "direction": "output", + "bits": [ 123 ] + }, + "SROA1": { + "direction": "output", + "bits": [ 124 ] + }, + "SROA0": { + "direction": "output", + "bits": [ 125 ] + }, + "SROB17": { + "direction": "output", + "bits": [ 126 ] + }, + "SROB16": { + "direction": "output", + "bits": [ 127 ] + }, + "SROB15": { + "direction": "output", + "bits": [ 128 ] + }, + "SROB14": { + "direction": "output", + "bits": [ 129 ] + }, + "SROB13": { + "direction": "output", + "bits": [ 130 ] + }, + "SROB12": { + "direction": "output", + "bits": [ 131 ] + }, + "SROB11": { + "direction": "output", + "bits": [ 132 ] + }, + "SROB10": { + "direction": "output", + "bits": [ 133 ] + }, + "SROB9": { + "direction": "output", + "bits": [ 134 ] + }, + "SROB8": { + "direction": "output", + "bits": [ 135 ] + }, + "SROB7": { + "direction": "output", + "bits": [ 136 ] + }, + "SROB6": { + "direction": "output", + "bits": [ 137 ] + }, + "SROB5": { + "direction": "output", + "bits": [ 138 ] + }, + "SROB4": { + "direction": "output", + "bits": [ 139 ] + }, + "SROB3": { + "direction": "output", + "bits": [ 140 ] + }, + "SROB2": { + "direction": "output", + "bits": [ 141 ] + }, + "SROB1": { + "direction": "output", + "bits": [ 142 ] + }, + "SROB0": { + "direction": "output", + "bits": [ 143 ] + }, + "ROA17": { + "direction": "output", + "bits": [ 144 ] + }, + "ROA16": { + "direction": "output", + "bits": [ 145 ] + }, + "ROA15": { + "direction": "output", + "bits": [ 146 ] + }, + "ROA14": { + "direction": "output", + "bits": [ 147 ] + }, + "ROA13": { + "direction": "output", + "bits": [ 148 ] + }, + "ROA12": { + "direction": "output", + "bits": [ 149 ] + }, + "ROA11": { + "direction": "output", + "bits": [ 150 ] + }, + "ROA10": { + "direction": "output", + "bits": [ 151 ] + }, + "ROA9": { + "direction": "output", + "bits": [ 152 ] + }, + "ROA8": { + "direction": "output", + "bits": [ 153 ] + }, + "ROA7": { + "direction": "output", + "bits": [ 154 ] + }, + "ROA6": { + "direction": "output", + "bits": [ 155 ] + }, + "ROA5": { + "direction": "output", + "bits": [ 156 ] + }, + "ROA4": { + "direction": "output", + "bits": [ 157 ] + }, + "ROA3": { + "direction": "output", + "bits": [ 158 ] + }, + "ROA2": { + "direction": "output", + "bits": [ 159 ] + }, + "ROA1": { + "direction": "output", + "bits": [ 160 ] + }, + "ROA0": { + "direction": "output", + "bits": [ 161 ] + }, + "ROB17": { + "direction": "output", + "bits": [ 162 ] + }, + "ROB16": { + "direction": "output", + "bits": [ 163 ] + }, + "ROB15": { + "direction": "output", + "bits": [ 164 ] + }, + "ROB14": { + "direction": "output", + "bits": [ 165 ] + }, + "ROB13": { + "direction": "output", + "bits": [ 166 ] + }, + "ROB12": { + "direction": "output", + "bits": [ 167 ] + }, + "ROB11": { + "direction": "output", + "bits": [ 168 ] + }, + "ROB10": { + "direction": "output", + "bits": [ 169 ] + }, + "ROB9": { + "direction": "output", + "bits": [ 170 ] + }, + "ROB8": { + "direction": "output", + "bits": [ 171 ] + }, + "ROB7": { + "direction": "output", + "bits": [ 172 ] + }, + "ROB6": { + "direction": "output", + "bits": [ 173 ] + }, + "ROB5": { + "direction": "output", + "bits": [ 174 ] + }, + "ROB4": { + "direction": "output", + "bits": [ 175 ] + }, + "ROB3": { + "direction": "output", + "bits": [ 176 ] + }, + "ROB2": { + "direction": "output", + "bits": [ 177 ] + }, + "ROB1": { + "direction": "output", + "bits": [ 178 ] + }, + "ROB0": { + "direction": "output", + "bits": [ 179 ] + }, + "ROC17": { + "direction": "output", + "bits": [ 180 ] + }, + "ROC16": { + "direction": "output", + "bits": [ 181 ] + }, + "ROC15": { + "direction": "output", + "bits": [ 182 ] + }, + "ROC14": { + "direction": "output", + "bits": [ 183 ] + }, + "ROC13": { + "direction": "output", + "bits": [ 184 ] + }, + "ROC12": { + "direction": "output", + "bits": [ 185 ] + }, + "ROC11": { + "direction": "output", + "bits": [ 186 ] + }, + "ROC10": { + "direction": "output", + "bits": [ 187 ] + }, + "ROC9": { + "direction": "output", + "bits": [ 188 ] + }, + "ROC8": { + "direction": "output", + "bits": [ 189 ] + }, + "ROC7": { + "direction": "output", + "bits": [ 190 ] + }, + "ROC6": { + "direction": "output", + "bits": [ 191 ] + }, + "ROC5": { + "direction": "output", + "bits": [ 192 ] + }, + "ROC4": { + "direction": "output", + "bits": [ 193 ] + }, + "ROC3": { + "direction": "output", + "bits": [ 194 ] + }, + "ROC2": { + "direction": "output", + "bits": [ 195 ] + }, + "ROC1": { + "direction": "output", + "bits": [ 196 ] + }, + "ROC0": { + "direction": "output", + "bits": [ 197 ] + }, + "P35": { + "direction": "output", + "bits": [ 198 ] + }, + "P34": { + "direction": "output", + "bits": [ 199 ] + }, + "P33": { + "direction": "output", + "bits": [ 200 ] + }, + "P32": { + "direction": "output", + "bits": [ 201 ] + }, + "P31": { + "direction": "output", + "bits": [ 202 ] + }, + "P30": { + "direction": "output", + "bits": [ 203 ] + }, + "P29": { + "direction": "output", + "bits": [ 204 ] + }, + "P28": { + "direction": "output", + "bits": [ 205 ] + }, + "P27": { + "direction": "output", + "bits": [ 206 ] + }, + "P26": { + "direction": "output", + "bits": [ 207 ] + }, + "P25": { + "direction": "output", + "bits": [ 208 ] + }, + "P24": { + "direction": "output", + "bits": [ 209 ] + }, + "P23": { + "direction": "output", + "bits": [ 210 ] + }, + "P22": { + "direction": "output", + "bits": [ 211 ] + }, + "P21": { + "direction": "output", + "bits": [ 212 ] + }, + "P20": { + "direction": "output", + "bits": [ 213 ] + }, + "P19": { + "direction": "output", + "bits": [ 214 ] + }, + "P18": { + "direction": "output", + "bits": [ 215 ] + }, + "P17": { + "direction": "output", + "bits": [ 216 ] + }, + "P16": { + "direction": "output", + "bits": [ 217 ] + }, + "P15": { + "direction": "output", + "bits": [ 218 ] + }, + "P14": { + "direction": "output", + "bits": [ 219 ] + }, + "P13": { + "direction": "output", + "bits": [ 220 ] + }, + "P12": { + "direction": "output", + "bits": [ 221 ] + }, + "P11": { + "direction": "output", + "bits": [ 222 ] + }, + "P10": { + "direction": "output", + "bits": [ 223 ] + }, + "P9": { + "direction": "output", + "bits": [ 224 ] + }, + "P8": { + "direction": "output", + "bits": [ 225 ] + }, + "P7": { + "direction": "output", + "bits": [ 226 ] + }, + "P6": { + "direction": "output", + "bits": [ 227 ] + }, + "P5": { + "direction": "output", + "bits": [ 228 ] + }, + "P4": { + "direction": "output", + "bits": [ 229 ] + }, + "P3": { + "direction": "output", + "bits": [ 230 ] + }, + "P2": { + "direction": "output", + "bits": [ 231 ] + }, + "P1": { + "direction": "output", + "bits": [ 232 ] + }, + "P0": { + "direction": "output", + "bits": [ 233 ] + }, + "SIGNEDP": { + "direction": "output", + "bits": [ 234 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:270.11-270.13" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:269.11-269.13" + } + }, + "A10": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:260.11-260.14" + } + }, + "A11": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:259.11-259.14" + } + }, + "A12": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:258.11-258.14" + } + }, + "A13": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:257.11-257.14" + } + }, + "A14": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:256.11-256.14" + } + }, + "A15": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:255.11-255.14" + } + }, + "A16": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:254.11-254.14" + } + }, + "A17": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:253.11-253.14" + } + }, + "A2": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:268.11-268.13" + } + }, + "A3": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:267.11-267.13" + } + }, + "A4": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:266.11-266.13" + } + }, + "A5": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:265.11-265.13" + } + }, + "A6": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:264.11-264.13" + } + }, + "A7": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:263.11-263.13" + } + }, + "A8": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:262.11-262.13" + } + }, + "A9": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:261.11-261.13" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:288.11-288.13" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:287.11-287.13" + } + }, + "B10": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:278.11-278.14" + } + }, + "B11": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:277.11-277.14" + } + }, + "B12": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:276.11-276.14" + } + }, + "B13": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:275.11-275.14" + } + }, + "B14": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:274.11-274.14" + } + }, + "B15": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:273.11-273.14" + } + }, + "B16": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:272.11-272.14" + } + }, + "B17": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:271.11-271.14" + } + }, + "B2": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:286.11-286.13" + } + }, + "B3": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:285.11-285.13" + } + }, + "B4": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:284.11-284.13" + } + }, + "B5": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:283.11-283.13" + } + }, + "B6": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:282.11-282.13" + } + }, + "B7": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:281.11-281.13" + } + }, + "B8": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:280.11-280.13" + } + }, + "B9": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:279.11-279.13" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:306.11-306.13" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:305.11-305.13" + } + }, + "C10": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:296.11-296.14" + } + }, + "C11": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:295.11-295.14" + } + }, + "C12": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:294.11-294.14" + } + }, + "C13": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:293.11-293.14" + } + }, + "C14": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:292.11-292.14" + } + }, + "C15": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:291.11-291.14" + } + }, + "C16": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:290.11-290.14" + } + }, + "C17": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:289.11-289.14" + } + }, + "C2": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:304.11-304.13" + } + }, + "C3": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:303.11-303.13" + } + }, + "C4": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:302.11-302.13" + } + }, + "C5": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:301.11-301.13" + } + }, + "C6": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:300.11-300.13" + } + }, + "C7": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:299.11-299.13" + } + }, + "C8": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:298.11-298.13" + } + }, + "C9": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:297.11-297.13" + } + }, + "CE0": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:318.11-318.14" + } + }, + "CE1": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:317.11-317.14" + } + }, + "CE2": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:316.11-316.14" + } + }, + "CE3": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:315.11-315.14" + } + }, + "CLK0": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:314.11-314.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:313.11-313.15" + } + }, + "CLK2": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:312.11-312.15" + } + }, + "CLK3": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:311.11-311.15" + } + }, + "P0": { + "hide_name": 0, + "bits": [ 233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:484.12-484.14" + } + }, + "P1": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:483.12-483.14" + } + }, + "P10": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:474.12-474.15" + } + }, + "P11": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:473.12-473.15" + } + }, + "P12": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:472.12-472.15" + } + }, + "P13": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:471.12-471.15" + } + }, + "P14": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:470.12-470.15" + } + }, + "P15": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:469.12-469.15" + } + }, + "P16": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:468.12-468.15" + } + }, + "P17": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:467.12-467.15" + } + }, + "P18": { + "hide_name": 0, + "bits": [ 215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:466.12-466.15" + } + }, + "P19": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:465.12-465.15" + } + }, + "P2": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:482.12-482.14" + } + }, + "P20": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:464.12-464.15" + } + }, + "P21": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:463.12-463.15" + } + }, + "P22": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:462.12-462.15" + } + }, + "P23": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:461.12-461.15" + } + }, + "P24": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:460.12-460.15" + } + }, + "P25": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:459.12-459.15" + } + }, + "P26": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:458.12-458.15" + } + }, + "P27": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:457.12-457.15" + } + }, + "P28": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:456.12-456.15" + } + }, + "P29": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:455.12-455.15" + } + }, + "P3": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:481.12-481.14" + } + }, + "P30": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:454.12-454.15" + } + }, + "P31": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:453.12-453.15" + } + }, + "P32": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:452.12-452.15" + } + }, + "P33": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:451.12-451.15" + } + }, + "P34": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:450.12-450.15" + } + }, + "P35": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:449.12-449.15" + } + }, + "P4": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:480.12-480.14" + } + }, + "P5": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:479.12-479.14" + } + }, + "P6": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:478.12-478.14" + } + }, + "P7": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:477.12-477.14" + } + }, + "P8": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:476.12-476.14" + } + }, + "P9": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:475.12-475.14" + } + }, + "ROA0": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:412.12-412.16" + } + }, + "ROA1": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:411.12-411.16" + } + }, + "ROA10": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:402.12-402.17" + } + }, + "ROA11": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:401.12-401.17" + } + }, + "ROA12": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:400.12-400.17" + } + }, + "ROA13": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:399.12-399.17" + } + }, + "ROA14": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:398.12-398.17" + } + }, + "ROA15": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:397.12-397.17" + } + }, + "ROA16": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:396.12-396.17" + } + }, + "ROA17": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:395.12-395.17" + } + }, + "ROA2": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:410.12-410.16" + } + }, + "ROA3": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:409.12-409.16" + } + }, + "ROA4": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:408.12-408.16" + } + }, + "ROA5": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:407.12-407.16" + } + }, + "ROA6": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:406.12-406.16" + } + }, + "ROA7": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:405.12-405.16" + } + }, + "ROA8": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:404.12-404.16" + } + }, + "ROA9": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:403.12-403.16" + } + }, + "ROB0": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:430.12-430.16" + } + }, + "ROB1": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:429.12-429.16" + } + }, + "ROB10": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:420.12-420.17" + } + }, + "ROB11": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:419.12-419.17" + } + }, + "ROB12": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:418.12-418.17" + } + }, + "ROB13": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:417.12-417.17" + } + }, + "ROB14": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:416.12-416.17" + } + }, + "ROB15": { + "hide_name": 0, + "bits": [ 164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:415.12-415.17" + } + }, + "ROB16": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:414.12-414.17" + } + }, + "ROB17": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:413.12-413.17" + } + }, + "ROB2": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:428.12-428.16" + } + }, + "ROB3": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:427.12-427.16" + } + }, + "ROB4": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:426.12-426.16" + } + }, + "ROB5": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:425.12-425.16" + } + }, + "ROB6": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:424.12-424.16" + } + }, + "ROB7": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:423.12-423.16" + } + }, + "ROB8": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:422.12-422.16" + } + }, + "ROB9": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:421.12-421.16" + } + }, + "ROC0": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:448.12-448.16" + } + }, + "ROC1": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:447.12-447.16" + } + }, + "ROC10": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:438.12-438.17" + } + }, + "ROC11": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:437.12-437.17" + } + }, + "ROC12": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:436.12-436.17" + } + }, + "ROC13": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:435.12-435.17" + } + }, + "ROC14": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:434.12-434.17" + } + }, + "ROC15": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:433.12-433.17" + } + }, + "ROC16": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:432.12-432.17" + } + }, + "ROC17": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:431.12-431.17" + } + }, + "ROC2": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:446.12-446.16" + } + }, + "ROC3": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:445.12-445.16" + } + }, + "ROC4": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:444.12-444.16" + } + }, + "ROC5": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:443.12-443.16" + } + }, + "ROC6": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:442.12-442.16" + } + }, + "ROC7": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:441.12-441.16" + } + }, + "ROC8": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:440.12-440.16" + } + }, + "ROC9": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:439.12-439.16" + } + }, + "RST0": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:322.11-322.15" + } + }, + "RST1": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:321.11-321.15" + } + }, + "RST2": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:320.11-320.15" + } + }, + "RST3": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:319.11-319.15" + } + }, + "SIGNEDA": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:307.11-307.18" + } + }, + "SIGNEDB": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:308.11-308.18" + } + }, + "SIGNEDP": { + "hide_name": 0, + "bits": [ 234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:485.12-485.19" + } + }, + "SOURCEA": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:309.11-309.18" + } + }, + "SOURCEB": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:310.11-310.18" + } + }, + "SRIA0": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:340.11-340.16" + } + }, + "SRIA1": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:339.11-339.16" + } + }, + "SRIA10": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:330.11-330.17" + } + }, + "SRIA11": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:329.11-329.17" + } + }, + "SRIA12": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:328.11-328.17" + } + }, + "SRIA13": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:327.11-327.17" + } + }, + "SRIA14": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:326.11-326.17" + } + }, + "SRIA15": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:325.11-325.17" + } + }, + "SRIA16": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:324.11-324.17" + } + }, + "SRIA17": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:323.11-323.17" + } + }, + "SRIA2": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:338.11-338.16" + } + }, + "SRIA3": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:337.11-337.16" + } + }, + "SRIA4": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:336.11-336.16" + } + }, + "SRIA5": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:335.11-335.16" + } + }, + "SRIA6": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:334.11-334.16" + } + }, + "SRIA7": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:333.11-333.16" + } + }, + "SRIA8": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:332.11-332.16" + } + }, + "SRIA9": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:331.11-331.16" + } + }, + "SRIB0": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:358.11-358.16" + } + }, + "SRIB1": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:357.11-357.16" + } + }, + "SRIB10": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:348.11-348.17" + } + }, + "SRIB11": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:347.11-347.17" + } + }, + "SRIB12": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:346.11-346.17" + } + }, + "SRIB13": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:345.11-345.17" + } + }, + "SRIB14": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:344.11-344.17" + } + }, + "SRIB15": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:343.11-343.17" + } + }, + "SRIB16": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:342.11-342.17" + } + }, + "SRIB17": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:341.11-341.17" + } + }, + "SRIB2": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:356.11-356.16" + } + }, + "SRIB3": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:355.11-355.16" + } + }, + "SRIB4": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:354.11-354.16" + } + }, + "SRIB5": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:353.11-353.16" + } + }, + "SRIB6": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:352.11-352.16" + } + }, + "SRIB7": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:351.11-351.16" + } + }, + "SRIB8": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:350.11-350.16" + } + }, + "SRIB9": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:349.11-349.16" + } + }, + "SROA0": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:376.12-376.17" + } + }, + "SROA1": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:375.12-375.17" + } + }, + "SROA10": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:366.12-366.18" + } + }, + "SROA11": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:365.12-365.18" + } + }, + "SROA12": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:364.12-364.18" + } + }, + "SROA13": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:363.12-363.18" + } + }, + "SROA14": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:362.12-362.18" + } + }, + "SROA15": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:361.12-361.18" + } + }, + "SROA16": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:360.12-360.18" + } + }, + "SROA17": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:359.12-359.18" + } + }, + "SROA2": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:374.12-374.17" + } + }, + "SROA3": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:373.12-373.17" + } + }, + "SROA4": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:372.12-372.17" + } + }, + "SROA5": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:371.12-371.17" + } + }, + "SROA6": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:370.12-370.17" + } + }, + "SROA7": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:369.12-369.17" + } + }, + "SROA8": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:368.12-368.17" + } + }, + "SROA9": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:367.12-367.17" + } + }, + "SROB0": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:394.12-394.17" + } + }, + "SROB1": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:393.12-393.17" + } + }, + "SROB10": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:384.12-384.18" + } + }, + "SROB11": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:383.12-383.18" + } + }, + "SROB12": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:382.12-382.18" + } + }, + "SROB13": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:381.12-381.18" + } + }, + "SROB14": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:380.12-380.18" + } + }, + "SROB15": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:379.12-379.18" + } + }, + "SROB16": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:378.12-378.18" + } + }, + "SROB17": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:377.12-377.18" + } + }, + "SROB2": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:392.12-392.17" + } + }, + "SROB3": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:391.12-391.17" + } + }, + "SROB4": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:390.12-390.17" + } + }, + "SROB5": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:389.12-389.17" + } + }, + "SROB6": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:388.12-388.17" + } + }, + "SROB7": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:387.12-387.17" + } + }, + "SROB8": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:386.12-386.17" + } + }, + "SROB9": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:385.12-385.17" + } + } + } + }, + "OB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.20-5.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.59-5.60" + } + } + } + }, + "OBCO": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "OT": { + "direction": "output", + "bits": [ 3 ] + }, + "OC": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.20-9.21" + } + }, + "OC": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.38-9.40" + } + }, + "OT": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.34-9.36" + } + } + } + }, + "OBZ": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.20-6.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.59-6.60" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.23-6.24" + } + } + } + }, + "OBZPD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.20-8.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.59-8.60" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.23-8.24" + } + } + } + }, + "OBZPU": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.20-7.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.59-7.60" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.23-7.24" + } + } + } + }, + "ODDR71B": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1255.1-1268.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 3 ] + }, + "RST": { + "direction": "input", + "bits": [ 4 ] + }, + "D6": { + "direction": "input", + "bits": [ 5 ] + }, + "D5": { + "direction": "input", + "bits": [ 6 ] + }, + "D4": { + "direction": "input", + "bits": [ 7 ] + }, + "D3": { + "direction": "input", + "bits": [ 8 ] + }, + "D2": { + "direction": "input", + "bits": [ 9 ] + }, + "D1": { + "direction": "input", + "bits": [ 10 ] + }, + "D0": { + "direction": "input", + "bits": [ 11 ] + }, + "Q": { + "direction": "output", + "bits": [ 12 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1266.11-1266.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1265.11-1265.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1264.11-1264.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1263.11-1263.13" + } + }, + "D4": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1262.11-1262.13" + } + }, + "D5": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1261.11-1261.13" + } + }, + "D6": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1260.11-1260.13" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1258.11-1258.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1267.12-1267.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1259.11-1259.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1257.11-1257.15" + } + } + } + }, + "ODDRX1F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1232.1-1239.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "D0": { + "direction": "input", + "bits": [ 4 ] + }, + "D1": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1236.11-1236.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1237.11-1237.13" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1238.12-1238.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1235.11-1235.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1234.11-1234.15" + } + } + } + }, + "ODDRX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1308.1-1319.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D3": { + "direction": "input", + "bits": [ 2 ] + }, + "D2": { + "direction": "input", + "bits": [ 3 ] + }, + "D1": { + "direction": "input", + "bits": [ 4 ] + }, + "D0": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW270": { + "direction": "input", + "bits": [ 6 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 7 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 8 ] + }, + "RST": { + "direction": "input", + "bits": [ 9 ] + }, + "Q": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1313.11-1313.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1312.11-1312.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1311.11-1311.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1310.11-1310.13" + } + }, + "DQSW270": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1314.11-1314.18" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1316.11-1316.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1318.12-1318.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1317.11-1317.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1315.11-1315.15" + } + } + } + }, + "ODDRX2DQSB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1322.1-1333.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D3": { + "direction": "input", + "bits": [ 2 ] + }, + "D2": { + "direction": "input", + "bits": [ 3 ] + }, + "D1": { + "direction": "input", + "bits": [ 4 ] + }, + "D0": { + "direction": "input", + "bits": [ 5 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 6 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 7 ] + }, + "DQSW": { + "direction": "input", + "bits": [ 8 ] + }, + "RST": { + "direction": "input", + "bits": [ 9 ] + }, + "Q": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1327.11-1327.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1326.11-1326.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1325.11-1325.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1324.11-1324.13" + } + }, + "DQSW": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1330.11-1330.15" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1329.11-1329.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1332.12-1332.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1331.11-1331.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1328.11-1328.15" + } + } + } + }, + "ODDRX2F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1242.1-1252.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 3 ] + }, + "RST": { + "direction": "input", + "bits": [ 4 ] + }, + "D3": { + "direction": "input", + "bits": [ 5 ] + }, + "D2": { + "direction": "input", + "bits": [ 6 ] + }, + "D1": { + "direction": "input", + "bits": [ 7 ] + }, + "D0": { + "direction": "input", + "bits": [ 8 ] + }, + "Q": { + "direction": "output", + "bits": [ 9 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1250.11-1250.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1249.11-1249.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1248.11-1248.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1247.11-1247.13" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1245.11-1245.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1251.12-1251.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1246.11-1246.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1244.11-1244.15" + } + } + } + }, + "OFS1P3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.27-31.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.23-31.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.47-31.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.34-31.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.30-31.32" + } + } + } + }, + "OFS1P3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.23-32.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.27-32.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.47-32.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.34-32.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.30-32.32" + } + } + } + }, + "OFS1P3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.23-33.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.27-33.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.47-33.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.34-33.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.30-33.32" + } + } + } + }, + "OFS1P3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.27-34.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.23-34.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.47-34.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.34-34.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.30-34.32" + } + } + } + }, + "OLVDS": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "Z": { + "direction": "output", + "bits": [ 3 ] + }, + "ZN": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.20-14.21" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.59-14.60" + } + }, + "ZN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.69-14.71" + } + } + } + }, + "OSCG": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1413.1-1416.10" + }, + "parameter_default_values": { + "DIV": "00000000000000000000000010000000" + }, + "ports": { + "OSC": { + "direction": "output", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "OSC": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1415.12-1415.15" + } + } + } + }, + "OSHX2A": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1271.1-1279.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D1": { + "direction": "input", + "bits": [ 2 ] + }, + "D0": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "RST": { + "direction": "input", + "bits": [ 6 ] + }, + "Q": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1274.11-1274.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1273.11-1273.13" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1276.11-1276.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1278.12-1278.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1277.11-1277.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1275.11-1275.15" + } + } + } + }, + "PCSCLKDIV": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1020.1-1029.10" + }, + "parameter_default_values": { + "GSR": "DISABLED" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "SEL2": { + "direction": "input", + "bits": [ 4 ] + }, + "SEL1": { + "direction": "input", + "bits": [ 5 ] + }, + "SEL0": { + "direction": "input", + "bits": [ 6 ] + }, + "CDIV1": { + "direction": "output", + "bits": [ 7 ] + }, + "CDIVX": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "CDIV1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1027.12-1027.17" + } + }, + "CDIVX": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1028.12-1028.17" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1022.11-1022.15" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1023.11-1023.14" + } + }, + "SEL0": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1026.11-1026.15" + } + }, + "SEL1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1025.11-1025.15" + } + }, + "SEL2": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1024.11-1024.15" + } + } + } + }, + "PDPW16KD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:21.1-213.10" + }, + "parameter_default_values": { + "ASYNC_RESET_RELEASE": "SYNC", + "CLKRMUX": "CLKR", + "CLKWMUX": "CLKW", + "CSDECODE_R": "0b000", + "CSDECODE_W": "0b000", + "DATA_WIDTH_R": "00000000000000000000000000100100", + "DATA_WIDTH_W": "00000000000000000000000000100100", + "GSR": "ENABLED", + "INITVAL_00": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_01": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_02": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_03": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_04": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_05": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_06": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_07": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_08": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_09": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_10": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_11": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_12": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_13": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_14": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_15": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_16": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_17": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_18": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_19": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_20": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_21": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_22": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_23": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_24": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_25": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_26": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_27": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_28": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_29": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_30": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_31": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_32": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_33": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_34": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_35": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_36": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_37": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_38": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_39": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INIT_DATA": "STATIC", + "REGMODE": "NOREG", + "RESETMODE": "SYNC" + }, + "ports": { + "DI35": { + "direction": "input", + "bits": [ 2 ] + }, + "DI34": { + "direction": "input", + "bits": [ 3 ] + }, + "DI33": { + "direction": "input", + "bits": [ 4 ] + }, + "DI32": { + "direction": "input", + "bits": [ 5 ] + }, + "DI31": { + "direction": "input", + "bits": [ 6 ] + }, + "DI30": { + "direction": "input", + "bits": [ 7 ] + }, + "DI29": { + "direction": "input", + "bits": [ 8 ] + }, + "DI28": { + "direction": "input", + "bits": [ 9 ] + }, + "DI27": { + "direction": "input", + "bits": [ 10 ] + }, + "DI26": { + "direction": "input", + "bits": [ 11 ] + }, + "DI25": { + "direction": "input", + "bits": [ 12 ] + }, + "DI24": { + "direction": "input", + "bits": [ 13 ] + }, + "DI23": { + "direction": "input", + "bits": [ 14 ] + }, + "DI22": { + "direction": "input", + "bits": [ 15 ] + }, + "DI21": { + "direction": "input", + "bits": [ 16 ] + }, + "DI20": { + "direction": "input", + "bits": [ 17 ] + }, + "DI19": { + "direction": "input", + "bits": [ 18 ] + }, + "DI18": { + "direction": "input", + "bits": [ 19 ] + }, + "DI17": { + "direction": "input", + "bits": [ 20 ] + }, + "DI16": { + "direction": "input", + "bits": [ 21 ] + }, + "DI15": { + "direction": "input", + "bits": [ 22 ] + }, + "DI14": { + "direction": "input", + "bits": [ 23 ] + }, + "DI13": { + "direction": "input", + "bits": [ 24 ] + }, + "DI12": { + "direction": "input", + "bits": [ 25 ] + }, + "DI11": { + "direction": "input", + "bits": [ 26 ] + }, + "DI10": { + "direction": "input", + "bits": [ 27 ] + }, + "DI9": { + "direction": "input", + "bits": [ 28 ] + }, + "DI8": { + "direction": "input", + "bits": [ 29 ] + }, + "DI7": { + "direction": "input", + "bits": [ 30 ] + }, + "DI6": { + "direction": "input", + "bits": [ 31 ] + }, + "DI5": { + "direction": "input", + "bits": [ 32 ] + }, + "DI4": { + "direction": "input", + "bits": [ 33 ] + }, + "DI3": { + "direction": "input", + "bits": [ 34 ] + }, + "DI2": { + "direction": "input", + "bits": [ 35 ] + }, + "DI1": { + "direction": "input", + "bits": [ 36 ] + }, + "DI0": { + "direction": "input", + "bits": [ 37 ] + }, + "ADW8": { + "direction": "input", + "bits": [ 38 ] + }, + "ADW7": { + "direction": "input", + "bits": [ 39 ] + }, + "ADW6": { + "direction": "input", + "bits": [ 40 ] + }, + "ADW5": { + "direction": "input", + "bits": [ 41 ] + }, + "ADW4": { + "direction": "input", + "bits": [ 42 ] + }, + "ADW3": { + "direction": "input", + "bits": [ 43 ] + }, + "ADW2": { + "direction": "input", + "bits": [ 44 ] + }, + "ADW1": { + "direction": "input", + "bits": [ 45 ] + }, + "ADW0": { + "direction": "input", + "bits": [ 46 ] + }, + "BE3": { + "direction": "input", + "bits": [ 47 ] + }, + "BE2": { + "direction": "input", + "bits": [ 48 ] + }, + "BE1": { + "direction": "input", + "bits": [ 49 ] + }, + "BE0": { + "direction": "input", + "bits": [ 50 ] + }, + "CEW": { + "direction": "input", + "bits": [ 51 ] + }, + "CLKW": { + "direction": "input", + "bits": [ 52 ] + }, + "CSW2": { + "direction": "input", + "bits": [ 53 ] + }, + "CSW1": { + "direction": "input", + "bits": [ 54 ] + }, + "CSW0": { + "direction": "input", + "bits": [ 55 ] + }, + "ADR13": { + "direction": "input", + "bits": [ 56 ] + }, + "ADR12": { + "direction": "input", + "bits": [ 57 ] + }, + "ADR11": { + "direction": "input", + "bits": [ 58 ] + }, + "ADR10": { + "direction": "input", + "bits": [ 59 ] + }, + "ADR9": { + "direction": "input", + "bits": [ 60 ] + }, + "ADR8": { + "direction": "input", + "bits": [ 61 ] + }, + "ADR7": { + "direction": "input", + "bits": [ 62 ] + }, + "ADR6": { + "direction": "input", + "bits": [ 63 ] + }, + "ADR5": { + "direction": "input", + "bits": [ 64 ] + }, + "ADR4": { + "direction": "input", + "bits": [ 65 ] + }, + "ADR3": { + "direction": "input", + "bits": [ 66 ] + }, + "ADR2": { + "direction": "input", + "bits": [ 67 ] + }, + "ADR1": { + "direction": "input", + "bits": [ 68 ] + }, + "ADR0": { + "direction": "input", + "bits": [ 69 ] + }, + "CER": { + "direction": "input", + "bits": [ 70 ] + }, + "OCER": { + "direction": "input", + "bits": [ 71 ] + }, + "CLKR": { + "direction": "input", + "bits": [ 72 ] + }, + "CSR2": { + "direction": "input", + "bits": [ 73 ] + }, + "CSR1": { + "direction": "input", + "bits": [ 74 ] + }, + "CSR0": { + "direction": "input", + "bits": [ 75 ] + }, + "RST": { + "direction": "input", + "bits": [ 76 ] + }, + "DO35": { + "direction": "output", + "bits": [ 77 ] + }, + "DO34": { + "direction": "output", + "bits": [ 78 ] + }, + "DO33": { + "direction": "output", + "bits": [ 79 ] + }, + "DO32": { + "direction": "output", + "bits": [ 80 ] + }, + "DO31": { + "direction": "output", + "bits": [ 81 ] + }, + "DO30": { + "direction": "output", + "bits": [ 82 ] + }, + "DO29": { + "direction": "output", + "bits": [ 83 ] + }, + "DO28": { + "direction": "output", + "bits": [ 84 ] + }, + "DO27": { + "direction": "output", + "bits": [ 85 ] + }, + "DO26": { + "direction": "output", + "bits": [ 86 ] + }, + "DO25": { + "direction": "output", + "bits": [ 87 ] + }, + "DO24": { + "direction": "output", + "bits": [ 88 ] + }, + "DO23": { + "direction": "output", + "bits": [ 89 ] + }, + "DO22": { + "direction": "output", + "bits": [ 90 ] + }, + "DO21": { + "direction": "output", + "bits": [ 91 ] + }, + "DO20": { + "direction": "output", + "bits": [ 92 ] + }, + "DO19": { + "direction": "output", + "bits": [ 93 ] + }, + "DO18": { + "direction": "output", + "bits": [ 94 ] + }, + "DO17": { + "direction": "output", + "bits": [ 95 ] + }, + "DO16": { + "direction": "output", + "bits": [ 96 ] + }, + "DO15": { + "direction": "output", + "bits": [ 97 ] + }, + "DO14": { + "direction": "output", + "bits": [ 98 ] + }, + "DO13": { + "direction": "output", + "bits": [ 99 ] + }, + "DO12": { + "direction": "output", + "bits": [ 100 ] + }, + "DO11": { + "direction": "output", + "bits": [ 101 ] + }, + "DO10": { + "direction": "output", + "bits": [ 102 ] + }, + "DO9": { + "direction": "output", + "bits": [ 103 ] + }, + "DO8": { + "direction": "output", + "bits": [ 104 ] + }, + "DO7": { + "direction": "output", + "bits": [ 105 ] + }, + "DO6": { + "direction": "output", + "bits": [ 106 ] + }, + "DO5": { + "direction": "output", + "bits": [ 107 ] + }, + "DO4": { + "direction": "output", + "bits": [ 108 ] + }, + "DO3": { + "direction": "output", + "bits": [ 109 ] + }, + "DO2": { + "direction": "output", + "bits": [ 110 ] + }, + "DO1": { + "direction": "output", + "bits": [ 111 ] + }, + "DO0": { + "direction": "output", + "bits": [ 112 ] + } + }, + "cells": { + }, + "netnames": { + "ADR0": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:169.11-169.15" + } + }, + "ADR1": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:168.11-168.15" + } + }, + "ADR10": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:159.11-159.16" + } + }, + "ADR11": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:158.11-158.16" + } + }, + "ADR12": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:157.11-157.16" + } + }, + "ADR13": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:156.11-156.16" + } + }, + "ADR2": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:167.11-167.15" + } + }, + "ADR3": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:166.11-166.15" + } + }, + "ADR4": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:165.11-165.15" + } + }, + "ADR5": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:164.11-164.15" + } + }, + "ADR6": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:163.11-163.15" + } + }, + "ADR7": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:162.11-162.15" + } + }, + "ADR8": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:161.11-161.15" + } + }, + "ADR9": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:160.11-160.15" + } + }, + "ADW0": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:146.11-146.15" + } + }, + "ADW1": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:145.11-145.15" + } + }, + "ADW2": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:144.11-144.15" + } + }, + "ADW3": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:143.11-143.15" + } + }, + "ADW4": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:142.11-142.15" + } + }, + "ADW5": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:141.11-141.15" + } + }, + "ADW6": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:140.11-140.15" + } + }, + "ADW7": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:139.11-139.15" + } + }, + "ADW8": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:138.11-138.15" + } + }, + "BE0": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:150.11-150.14" + } + }, + "BE1": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:149.11-149.14" + } + }, + "BE2": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:148.11-148.14" + } + }, + "BE3": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:147.11-147.14" + } + }, + "CER": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:170.11-170.14" + } + }, + "CEW": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:151.11-151.14" + } + }, + "CLKR": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:172.11-172.15" + } + }, + "CLKW": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:152.11-152.15" + } + }, + "CSR0": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:175.11-175.15" + } + }, + "CSR1": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:174.11-174.15" + } + }, + "CSR2": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:173.11-173.15" + } + }, + "CSW0": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:155.11-155.15" + } + }, + "CSW1": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:154.11-154.15" + } + }, + "CSW2": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:153.11-153.15" + } + }, + "DI0": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:137.11-137.14" + } + }, + "DI1": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:136.11-136.14" + } + }, + "DI10": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:127.11-127.15" + } + }, + "DI11": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:126.11-126.15" + } + }, + "DI12": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:125.11-125.15" + } + }, + "DI13": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:124.11-124.15" + } + }, + "DI14": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:123.11-123.15" + } + }, + "DI15": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:122.11-122.15" + } + }, + "DI16": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:121.11-121.15" + } + }, + "DI17": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:120.11-120.15" + } + }, + "DI18": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:119.11-119.15" + } + }, + "DI19": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:118.11-118.15" + } + }, + "DI2": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:135.11-135.14" + } + }, + "DI20": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:117.11-117.15" + } + }, + "DI21": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:116.11-116.15" + } + }, + "DI22": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:115.11-115.15" + } + }, + "DI23": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:114.11-114.15" + } + }, + "DI24": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:113.11-113.15" + } + }, + "DI25": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:112.11-112.15" + } + }, + "DI26": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:111.11-111.15" + } + }, + "DI27": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:110.11-110.15" + } + }, + "DI28": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:109.11-109.15" + } + }, + "DI29": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:108.11-108.15" + } + }, + "DI3": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:134.11-134.14" + } + }, + "DI30": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:107.11-107.15" + } + }, + "DI31": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:106.11-106.15" + } + }, + "DI32": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:105.11-105.15" + } + }, + "DI33": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:104.11-104.15" + } + }, + "DI34": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:103.11-103.15" + } + }, + "DI35": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:102.11-102.15" + } + }, + "DI4": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:133.11-133.14" + } + }, + "DI5": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:132.11-132.14" + } + }, + "DI6": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:131.11-131.14" + } + }, + "DI7": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:130.11-130.14" + } + }, + "DI8": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:129.11-129.14" + } + }, + "DI9": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:128.11-128.14" + } + }, + "DO0": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:212.12-212.15" + } + }, + "DO1": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:211.12-211.15" + } + }, + "DO10": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:202.12-202.16" + } + }, + "DO11": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:201.12-201.16" + } + }, + "DO12": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:200.12-200.16" + } + }, + "DO13": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:199.12-199.16" + } + }, + "DO14": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:198.12-198.16" + } + }, + "DO15": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:197.12-197.16" + } + }, + "DO16": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:196.12-196.16" + } + }, + "DO17": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:195.12-195.16" + } + }, + "DO18": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:194.12-194.16" + } + }, + "DO19": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:193.12-193.16" + } + }, + "DO2": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:210.12-210.15" + } + }, + "DO20": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:192.12-192.16" + } + }, + "DO21": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:191.12-191.16" + } + }, + "DO22": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:190.12-190.16" + } + }, + "DO23": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:189.12-189.16" + } + }, + "DO24": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:188.12-188.16" + } + }, + "DO25": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:187.12-187.16" + } + }, + "DO26": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:186.12-186.16" + } + }, + "DO27": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:185.12-185.16" + } + }, + "DO28": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:184.12-184.16" + } + }, + "DO29": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:183.12-183.16" + } + }, + "DO3": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:209.12-209.15" + } + }, + "DO30": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:182.12-182.16" + } + }, + "DO31": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:181.12-181.16" + } + }, + "DO32": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:180.12-180.16" + } + }, + "DO33": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:179.12-179.16" + } + }, + "DO34": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:178.12-178.16" + } + }, + "DO35": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:177.12-177.16" + } + }, + "DO4": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:208.12-208.15" + } + }, + "DO5": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:207.12-207.15" + } + }, + "DO6": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:206.12-206.15" + } + }, + "DO7": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:205.12-205.15" + } + }, + "DO8": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:204.12-204.15" + } + }, + "DO9": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:203.12-203.15" + } + }, + "OCER": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:171.11-171.15" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:176.11-176.14" + } + } + } + }, + "PFUMX": { + "attributes": { + "abc9_box_id": "00000000000000000000000000001000", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.1-124.10" + }, + "ports": { + "ALUT": { + "direction": "input", + "bits": [ 2 ] + }, + "BLUT": { + "direction": "input", + "bits": [ 3 ] + }, + "C0": { + "direction": "input", + "bits": [ 4 ] + }, + "Z": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "ALUT": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.21-117.25" + } + }, + "BLUT": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.27-117.31" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.33-117.35" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.44-117.45" + } + } + } + }, + "PUR": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:9.1-12.10" + }, + "parameter_default_values": { + "RST_PULSE": "00000000000000000000000000000001" + }, + "ports": { + "PUR": { + "direction": "input", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "PUR": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:11.11-11.14" + } + } + } + }, + "SGSR": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:15.1-18.10" + }, + "ports": { + "GSR": { + "direction": "input", + "bits": [ 2 ] + }, + "CLK": { + "direction": "input", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "CLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:17.11-17.14" + } + }, + "GSR": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:16.11-16.14" + } + } + } + }, + "TRELLIS_COMB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:354.1-395.10" + }, + "parameter_default_values": { + "CCU2_INJECT1": "NO", + "INITVAL": "0000000000000000", + "IS_Z1": "0", + "MODE": "LOGIC", + "WREMUX": "WRE" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "B": { + "direction": "input", + "bits": [ 3 ] + }, + "C": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "M": { + "direction": "input", + "bits": [ 6 ] + }, + "FCI": { + "direction": "input", + "bits": [ 7 ] + }, + "F1": { + "direction": "input", + "bits": [ 8 ] + }, + "FXA": { + "direction": "input", + "bits": [ 9 ] + }, + "FXB": { + "direction": "input", + "bits": [ 10 ] + }, + "WD": { + "direction": "input", + "bits": [ 11 ] + }, + "WAD0": { + "direction": "input", + "bits": [ 12 ] + }, + "WAD1": { + "direction": "input", + "bits": [ 13 ] + }, + "WAD2": { + "direction": "input", + "bits": [ 14 ] + }, + "WAD3": { + "direction": "input", + "bits": [ 15 ] + }, + "WRE": { + "direction": "input", + "bits": [ 16 ] + }, + "WCK": { + "direction": "input", + "bits": [ 17 ] + }, + "F": { + "direction": "output", + "bits": [ 18 ] + }, + "FCO": { + "direction": "output", + "bits": [ 19 ] + }, + "OFX": { + "direction": "output", + "bits": [ 20 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.8-355.9" + } + }, + "B": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.11-355.12" + } + }, + "C": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.14-355.15" + } + }, + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.17-355.18" + } + }, + "F": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:360.9-360.10" + } + }, + "F1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.13-356.15" + } + }, + "FCI": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.8-356.11" + } + }, + "FCO": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:360.12-360.15" + } + }, + "FXA": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.17-356.20" + } + }, + "FXB": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.22-356.25" + } + }, + "M": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.20-355.21" + } + }, + "OFX": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:360.17-360.20" + } + }, + "WAD0": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.8-358.12" + } + }, + "WAD1": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.14-358.18" + } + }, + "WAD2": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.20-358.24" + } + }, + "WAD3": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.26-358.30" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:359.13-359.16" + } + }, + "WD": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:357.8-357.10" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:359.8-359.11" + } + } + } + }, + "TRELLIS_DPR16X4": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000111", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:128.1-169.10" + }, + "parameter_default_values": { + "INITVAL": "0000000000000000000000000000000000000000000000000000000000000000", + "WCKMUX": "WCK", + "WREMUX": "WRE" + }, + "ports": { + "DI": { + "direction": "input", + "bits": [ 2, 3, 4, 5 ] + }, + "WAD": { + "direction": "input", + "bits": [ 6, 7, 8, 9 ] + }, + "WRE": { + "direction": "input", + "bits": [ 10 ] + }, + "WCK": { + "direction": "input", + "bits": [ 11 ] + }, + "RAD": { + "direction": "input", + "bits": [ 12, 13, 14, 15 ] + }, + "DO": { + "direction": "output", + "bits": [ 16, 17, 18, 19 ] + } + }, + "cells": { + }, + "netnames": { + "DI": { + "hide_name": 0, + "bits": [ 2, 3, 4, 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:129.15-129.17" + } + }, + "DO": { + "hide_name": 0, + "bits": [ 16, 17, 18, 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:134.15-134.17" + } + }, + "RAD": { + "hide_name": 0, + "bits": [ 12, 13, 14, 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:133.15-133.18" + } + }, + "WAD": { + "hide_name": 0, + "bits": [ 6, 7, 8, 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:130.15-130.18" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:132.15-132.18" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:131.15-131.18" + } + } + } + }, + "TRELLIS_FF": { + "attributes": { + "abc9_flop": "1", + "abc9_box": "0", + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.1-314.10" + }, + "parameter_default_values": { + "CEMUX": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110001", + "CLKMUX": "CLK", + "GSR": "ENABLED", + "LSRMODE": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000101001101010010", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "ports": { + "CLK": { + "direction": "input", + "bits": [ 2 ] + }, + "LSR": { + "direction": "input", + "bits": [ 3 ] + }, + "CE": { + "direction": "input", + "bits": [ 4 ] + }, + "DI": { + "direction": "input", + "bits": [ 5 ] + }, + "M": { + "direction": "input", + "bits": [ 6 ] + }, + "Q": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "CE": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.35-249.37" + } + }, + "CLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.25-249.28" + } + }, + "DI": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.39-249.41" + } + }, + "LSR": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.30-249.33" + } + }, + "M": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.43-249.44" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.57-249.58" + } + } + } + }, + "TRELLIS_IO": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:318.1-344.10" + }, + "parameter_default_values": { + "DIR": "INPUT" + }, + "ports": { + "B": { + "direction": "inout", + "bits": [ 2 ] + }, + "I": { + "direction": "input", + "bits": [ 3 ] + }, + "T": { + "direction": "input", + "bits": [ 4 ] + }, + "O": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:320.8-320.9" + } + }, + "I": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:321.8-321.9" + } + }, + "O": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:323.9-323.10" + } + }, + "T": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:322.8-322.9" + } + } + } + }, + "TRELLIS_RAM16X2": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:76.1-113.10" + }, + "parameter_default_values": { + "INITVAL_0": "0000000000000000", + "INITVAL_1": "0000000000000000", + "WCKMUX": "WCK", + "WREMUX": "WRE" + }, + "ports": { + "DI0": { + "direction": "input", + "bits": [ 2 ] + }, + "DI1": { + "direction": "input", + "bits": [ 3 ] + }, + "WAD0": { + "direction": "input", + "bits": [ 4 ] + }, + "WAD1": { + "direction": "input", + "bits": [ 5 ] + }, + "WAD2": { + "direction": "input", + "bits": [ 6 ] + }, + "WAD3": { + "direction": "input", + "bits": [ 7 ] + }, + "WRE": { + "direction": "input", + "bits": [ 8 ] + }, + "WCK": { + "direction": "input", + "bits": [ 9 ] + }, + "RAD0": { + "direction": "input", + "bits": [ 10 ] + }, + "RAD1": { + "direction": "input", + "bits": [ 11 ] + }, + "RAD2": { + "direction": "input", + "bits": [ 12 ] + }, + "RAD3": { + "direction": "input", + "bits": [ 13 ] + }, + "DO0": { + "direction": "output", + "bits": [ 14 ] + }, + "DO1": { + "direction": "output", + "bits": [ 15 ] + } + }, + "cells": { + }, + "netnames": { + "DI0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:77.8-77.11" + } + }, + "DI1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:77.13-77.16" + } + }, + "DO0": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:81.9-81.12" + } + }, + "DO1": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:81.14-81.17" + } + }, + "RAD0": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.8-80.12" + } + }, + "RAD1": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.14-80.18" + } + }, + "RAD2": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.20-80.24" + } + }, + "RAD3": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.26-80.30" + } + }, + "WAD0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.8-78.12" + } + }, + "WAD1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.14-78.18" + } + }, + "WAD2": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.20-78.24" + } + }, + "WAD3": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.26-78.30" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:79.13-79.16" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:79.8-79.11" + } + } + } + }, + "TSHX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1282.1-1292.10" + }, + "parameter_default_values": { + "GSR": "ENABLED", + "REGSET": "SET" + }, + "ports": { + "T1": { + "direction": "input", + "bits": [ 2 ] + }, + "T0": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW270": { + "direction": "input", + "bits": [ 6 ] + }, + "RST": { + "direction": "input", + "bits": [ 7 ] + }, + "Q": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "DQSW270": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1289.11-1289.18" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1288.11-1288.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1291.12-1291.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1290.11-1290.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1287.11-1287.15" + } + }, + "T0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1286.11-1286.13" + } + }, + "T1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1285.11-1285.13" + } + } + } + }, + "TSHX2DQSA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1295.1-1305.10" + }, + "parameter_default_values": { + "GSR": "ENABLED", + "REGSET": "SET" + }, + "ports": { + "T1": { + "direction": "input", + "bits": [ 2 ] + }, + "T0": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW": { + "direction": "input", + "bits": [ 6 ] + }, + "RST": { + "direction": "input", + "bits": [ 7 ] + }, + "Q": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "DQSW": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1302.11-1302.15" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1301.11-1301.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1304.12-1304.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1303.11-1303.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1300.11-1300.15" + } + }, + "T0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1299.11-1299.13" + } + }, + "T1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1298.11-1298.13" + } + } + } + }, + "USRMCLK": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1085.1-1088.10" + }, + "ports": { + "USRMCLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "USRMCLKTS": { + "direction": "input", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "USRMCLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1086.11-1086.19" + } + }, + "USRMCLKTS": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1087.11-1087.20" + } + } + } + }, + "VHI": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:402.1-404.10" + }, + "ports": { + "Z": { + "direction": "output", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "Z": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:402.19-402.20" + } + } + } + }, + "VLO": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:398.1-400.10" + }, + "ports": { + "Z": { + "direction": "output", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "Z": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:398.19-398.20" + } + } + } + }, + "top": { + "attributes": { + "dynports": "00000000000000000000000000000001", + "top": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:1.1-78.10" + }, + "ports": { + "clk": { + "direction": "input", + "bits": [ 2 ] + }, + "rst": { + "direction": "input", + "bits": [ 3 ] + }, + "start": { + "direction": "input", + "bits": [ 4 ] + }, + "y_bus": { + "direction": "output", + "signed": 1, + "bits": [ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 ] + }, + "busy": { + "direction": "output", + "bits": [ 37 ] + }, + "done": { + "direction": "output", + "bits": [ 38 ] + } + }, + "cells": { + "busy_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 39 ], + "B": [ 40 ], + "C": [ 41 ], + "D": [ 42 ], + "Z": [ 37 ] + } + }, + "done_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 43 ], + "B": [ 44 ], + "C": [ 45 ], + "D": [ 46 ], + "Z": [ 38 ] + } + }, + "start_LUT4_B": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 39 ], + "Z": [ 47 ] + } + }, + "start_LUT4_B_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 42 ], + "Z": [ 48 ] + } + }, + "start_LUT4_B_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 40 ], + "Z": [ 49 ] + } + }, + "u_layer": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:66.7-76.6", + "module": "$paramod$ac0ae258bf48dd039043ace30267dbd7219333fc\\layer", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "layer", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:1.1-81.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron", + "module": "$paramod$8b1cd44cf999e41637c5c45ad312808a2703769c\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 50 ], + "LSR": [ 51 ], + "Q": [ 52 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 53 ], + "LSR": [ 51 ], + "Q": [ 54 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 55 ], + "LSR": [ 51 ], + "Q": [ 56 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 57 ], + "LSR": [ 51 ], + "Q": [ 58 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 59 ], + "LSR": [ 51 ], + "Q": [ 60 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 61 ], + "LSR": [ 51 ], + "Q": [ 62 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 63 ], + "LSR": [ 51 ], + "Q": [ 64 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 65 ], + "LSR": [ 51 ], + "Q": [ 66 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 67 ], + "LSR": [ 51 ], + "Q": [ 68 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 69 ], + "LSR": [ 51 ], + "Q": [ 70 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 71 ], + "LSR": [ 51 ], + "Q": [ 72 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 73 ], + "LSR": [ 51 ], + "Q": [ 74 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 75 ], + "LSR": [ 51 ], + "Q": [ 76 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 77 ], + "LSR": [ 51 ], + "Q": [ 78 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 79 ], + "LSR": [ 51 ], + "Q": [ 80 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 81 ], + "LSR": [ 51 ], + "Q": [ 82 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 83 ], + "LSR": [ 51 ], + "Q": [ 84 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 85 ], + "LSR": [ 51 ], + "Q": [ 86 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 87 ], + "LSR": [ 51 ], + "Q": [ 88 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 89 ], + "LSR": [ 51 ], + "Q": [ 90 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 91 ], + "LSR": [ 51 ], + "Q": [ 92 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 93 ], + "LSR": [ 51 ], + "Q": [ 94 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_29": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 95 ], + "LSR": [ 51 ], + "Q": [ 96 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 97 ], + "LSR": [ 51 ], + "Q": [ 98 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_30": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 99 ], + "LSR": [ 51 ], + "Q": [ 100 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_31": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 101 ], + "LSR": [ 51 ], + "Q": [ 102 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 103 ], + "LSR": [ 51 ], + "Q": [ 104 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 105 ], + "LSR": [ 51 ], + "Q": [ 106 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 107 ], + "LSR": [ 51 ], + "Q": [ 108 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 109 ], + "LSR": [ 51 ], + "Q": [ 110 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 111 ], + "LSR": [ 51 ], + "Q": [ 112 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 41 ], + "CLK": [ 2 ], + "DI": [ 113 ], + "LSR": [ 51 ], + "Q": [ 114 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 115 ], + "A1": [ 116 ], + "B0": [ 117 ], + "B1": [ 118 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 119 ], + "COUT": [ 120 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 55 ], + "S1": [ 57 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 121 ], + "A1": [ 122 ], + "B0": [ 123 ], + "B1": [ 124 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 125 ], + "COUT": [ 126 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 63 ], + "S1": [ 65 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 127 ], + "A1": [ 128 ], + "B0": [ 129 ], + "B1": [ 130 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 131 ], + "COUT": [ 119 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 111 ], + "S1": [ 113 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 112 ], + "C": [ 132 ], + "D": [ 133 ], + "Z": [ 127 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 114 ], + "C": [ 134 ], + "D": [ 135 ], + "Z": [ 128 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 110 ], + "C": [ 136 ], + "D": [ 137 ], + "Z": [ 129 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 112 ], + "C": [ 132 ], + "D": [ 133 ], + "Z": [ 130 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 138 ], + "A1": [ 139 ], + "B0": [ 140 ], + "B1": [ 141 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 142 ], + "COUT": [ 143 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 75 ], + "S1": [ 97 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 76 ], + "C": [ 144 ], + "D": [ 145 ], + "Z": [ 138 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 98 ], + "C": [ 146 ], + "D": [ 147 ], + "Z": [ 139 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 54 ], + "C": [ 148 ], + "D": [ 149 ], + "Z": [ 140 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 76 ], + "C": [ 144 ], + "D": [ 145 ], + "Z": [ 141 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 150 ], + "A1": [ 151 ], + "B0": [ 152 ], + "B1": [ 153 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 154 ], + "COUT": [ 131 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 107 ], + "S1": [ 109 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 108 ], + "C": [ 155 ], + "D": [ 156 ], + "Z": [ 150 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 110 ], + "C": [ 136 ], + "D": [ 137 ], + "Z": [ 151 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 106 ], + "C": [ 157 ], + "D": [ 158 ], + "Z": [ 152 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 108 ], + "C": [ 155 ], + "D": [ 156 ], + "Z": [ 153 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 159 ], + "A1": [ 160 ], + "B0": [ 161 ], + "B1": [ 162 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 143 ], + "COUT": [ 154 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 103 ], + "S1": [ 105 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 104 ], + "C": [ 163 ], + "D": [ 164 ], + "Z": [ 159 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 106 ], + "C": [ 157 ], + "D": [ 158 ], + "Z": [ 160 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 98 ], + "C": [ 146 ], + "D": [ 147 ], + "Z": [ 161 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 104 ], + "C": [ 163 ], + "D": [ 164 ], + "Z": [ 162 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 165 ], + "A1": [ 166 ], + "B0": [ 167 ], + "B1": [ 168 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 120 ], + "COUT": [ 125 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 59 ], + "S1": [ 61 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 60 ], + "C": [ 169 ], + "D": [ 170 ], + "Z": [ 165 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 62 ], + "C": [ 171 ], + "D": [ 172 ], + "Z": [ 166 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 58 ], + "C": [ 173 ], + "D": [ 174 ], + "Z": [ 167 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 60 ], + "C": [ 169 ], + "D": [ 170 ], + "Z": [ 168 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 175 ], + "A1": [ 176 ], + "B0": [ 177 ], + "B1": [ 178 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 179 ], + "COUT": [ 180 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 95 ], + "S1": [ 99 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 96 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 175 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 100 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 176 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 94 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 177 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 96 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 178 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 64 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 121 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 66 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 122 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 62 ], + "C": [ 171 ], + "D": [ 172 ], + "Z": [ 123 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 64 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 124 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 183 ], + "A1": [ 184 ], + "B0": [ 185 ], + "B1": [ 186 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 126 ], + "COUT": [ 187 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 67 ], + "S1": [ 69 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 68 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 183 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 70 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 184 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 66 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 185 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 68 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 186 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 188 ], + "A1": [ 189 ], + "B0": [ 190 ], + "B1": [ 191 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 187 ], + "COUT": [ 192 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 73 ], + "S1": [ 77 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 74 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 188 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 78 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 189 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 70 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 190 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 74 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 191 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 193 ], + "A1": [ 194 ], + "B0": [ 195 ], + "B1": [ 196 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 197 ], + "COUT": [ 198 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 83 ], + "S1": [ 85 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 84 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 193 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 86 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 194 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 82 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 195 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 84 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 196 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 199 ], + "A1": [ 200 ], + "B0": [ 201 ], + "B1": [ 202 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 192 ], + "COUT": [ 197 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 79 ], + "S1": [ 81 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 80 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 199 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 82 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 200 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 78 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 201 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 80 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 202 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_6": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 101 ], + "A1": [ 203 ], + "B0": [ "0" ], + "B1": [ 204 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 205 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 206 ], + "S1": [ 71 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_6_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 72 ], + "C": [ 207 ], + "D": [ 208 ], + "Z": [ 203 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_6_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 102 ], + "C": [ 209 ], + "D": [ 210 ], + "Z": [ 204 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 211 ], + "A1": [ 212 ], + "B0": [ 213 ], + "B1": [ 214 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 205 ], + "COUT": [ 142 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 50 ], + "S1": [ 53 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 52 ], + "C": [ 215 ], + "D": [ 216 ], + "Z": [ 211 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 54 ], + "C": [ 148 ], + "D": [ 149 ], + "Z": [ 212 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 72 ], + "C": [ 207 ], + "D": [ 208 ], + "Z": [ 213 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 52 ], + "C": [ 215 ], + "D": [ 216 ], + "Z": [ 214 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 217 ], + "A1": [ 218 ], + "B0": [ 219 ], + "B1": [ 220 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 198 ], + "COUT": [ 221 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 87 ], + "S1": [ 89 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 88 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 217 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 90 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 218 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 86 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 219 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 88 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 220 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 222 ], + "A1": [ 223 ], + "B0": [ 224 ], + "B1": [ 225 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 221 ], + "COUT": [ 179 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 91 ], + "S1": [ 93 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 92 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 222 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 94 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 223 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 90 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 224 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 92 ], + "C": [ 181 ], + "D": [ 182 ], + "Z": [ 225 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 56 ], + "C": [ 226 ], + "D": [ 227 ], + "Z": [ 115 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 58 ], + "C": [ 173 ], + "D": [ 174 ], + "Z": [ 116 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 114 ], + "C": [ 134 ], + "D": [ 135 ], + "Z": [ 117 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 56 ], + "C": [ 226 ], + "D": [ 227 ], + "Z": [ 118 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 102 ], + "C": [ 209 ], + "D": [ 210 ], + "Z": [ 101 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 228 ], + "A1": [ 229 ], + "B0": [ 230 ], + "B1": [ 231 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 232 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 209 ], + "S1": [ 207 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 233 ], + "A1": [ 234 ], + "B0": [ 235 ], + "B1": [ 236 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 237 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 210 ], + "S1": [ 208 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 238 ], + "A1": [ 239 ], + "B0": [ 240 ], + "B1": [ 241 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 232 ], + "COUT": [ 242 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 215 ], + "S1": [ 148 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 243 ], + "A1": [ 244 ], + "B0": [ 245 ], + "B1": [ 246 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 242 ], + "COUT": [ 247 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 144 ], + "S1": [ 146 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 248 ], + "A1": [ 249 ], + "B0": [ 250 ], + "B1": [ 251 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 247 ], + "COUT": [ 252 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 163 ], + "S1": [ 157 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 253 ], + "A1": [ 254 ], + "B0": [ 255 ], + "B1": [ 256 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 252 ], + "COUT": [ 257 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 155 ], + "S1": [ 136 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 258 ], + "A1": [ 259 ], + "B0": [ 260 ], + "B1": [ 261 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 257 ], + "COUT": [ 262 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 132 ], + "S1": [ 134 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 263 ], + "A1": [ 264 ], + "B0": [ 265 ], + "B1": [ 266 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 262 ], + "COUT": [ 267 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 226 ], + "S1": [ 173 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 268 ], + "A1": [ 269 ], + "B0": [ 270 ], + "B1": [ 271 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 267 ], + "COUT": [ 272 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 169 ], + "S1": [ 171 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 269 ], + "A1": [ "0" ], + "B0": [ 271 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 272 ], + "COUT": [ 273 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 181 ], + "S1": [ 274 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 275 ], + "A1": [ "0" ], + "B0": [ 276 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 277 ], + "COUT": [ 278 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 182 ], + "S1": [ 279 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 280 ], + "A1": [ 275 ], + "B0": [ 281 ], + "B1": [ 276 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 282 ], + "COUT": [ 277 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 170 ], + "S1": [ 172 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 283 ], + "A1": [ 284 ], + "B0": [ 285 ], + "B1": [ 286 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 287 ], + "COUT": [ 282 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 227 ], + "S1": [ 174 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 288 ], + "A1": [ 289 ], + "B0": [ 290 ], + "B1": [ 291 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 292 ], + "COUT": [ 287 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 133 ], + "S1": [ 135 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 293 ], + "A1": [ 294 ], + "B0": [ 295 ], + "B1": [ 296 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 297 ], + "COUT": [ 292 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 156 ], + "S1": [ 137 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 298 ], + "A1": [ 299 ], + "B0": [ 300 ], + "B1": [ 301 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 302 ], + "COUT": [ 297 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 164 ], + "S1": [ 158 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 303 ], + "A1": [ 304 ], + "B0": [ 305 ], + "B1": [ 306 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 307 ], + "COUT": [ 302 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 145 ], + "S1": [ 147 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 308 ], + "A1": [ 309 ], + "B0": [ 310 ], + "B1": [ 311 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 237 ], + "COUT": [ 307 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 216 ], + "S1": [ 149 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 312 ], + "LSR": [ 3 ], + "Q": [ 41 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 41 ], + "D": [ 313 ], + "Z": [ 312 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 314 ], + "LSR": [ 315 ], + "Q": [ 46 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 41 ], + "D": [ 314 ], + "Z": [ 316 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 41 ], + "D": [ 314 ], + "Z": [ 313 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 41 ], + "Z": [ 51 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 317 ], + "C": [ 318 ], + "D": [ 319 ], + "Z": [ 314 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 320 ], + "B": [ 321 ], + "C": [ 322 ], + "D": [ 323 ], + "Z": [ 319 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 41 ], + "Z": [ 315 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 313 ], + "CLK": [ 2 ], + "DI": [ 324 ], + "LSR": [ 51 ], + "Q": [ 318 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 313 ], + "CLK": [ 2 ], + "DI": [ 325 ], + "LSR": [ 51 ], + "Q": [ 317 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 313 ], + "CLK": [ 2 ], + "DI": [ 326 ], + "LSR": [ 51 ], + "Q": [ 323 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 313 ], + "CLK": [ 2 ], + "DI": [ 327 ], + "LSR": [ 51 ], + "Q": [ 322 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 313 ], + "CLK": [ 2 ], + "DI": [ 328 ], + "LSR": [ 51 ], + "Q": [ 321 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 313 ], + "CLK": [ 2 ], + "DI": [ 329 ], + "LSR": [ 51 ], + "Q": [ 320 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 321 ], + "B1": [ 320 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 330 ], + "COUT": [ 331 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 328 ], + "S1": [ 329 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 318 ], + "B1": [ 317 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 332 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 333 ], + "S1": [ 325 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 323 ], + "B1": [ 322 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 332 ], + "COUT": [ 330 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 326 ], + "S1": [ 327 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 318 ], + "Z": [ 324 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8", + "module": "$paramod$20e373d74dd35704a68fa9d31f078ebc648ae4d9\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ 334 ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 235 ], + "P1": [ 236 ], + "P10": [ 290 ], + "P11": [ 291 ], + "P12": [ 285 ], + "P13": [ 286 ], + "P14": [ 281 ], + "P15": [ 276 ], + "P16": [ 335 ], + "P17": [ 336 ], + "P18": [ 337 ], + "P19": [ 338 ], + "P2": [ 310 ], + "P20": [ 339 ], + "P21": [ 340 ], + "P22": [ 341 ], + "P23": [ 342 ], + "P24": [ 343 ], + "P25": [ 344 ], + "P26": [ 345 ], + "P27": [ 346 ], + "P28": [ 347 ], + "P29": [ 348 ], + "P3": [ 311 ], + "P30": [ 349 ], + "P31": [ 350 ], + "P32": [ 351 ], + "P33": [ 352 ], + "P34": [ 353 ], + "P35": [ 354 ], + "P4": [ 305 ], + "P5": [ 306 ], + "P6": [ 300 ], + "P7": [ 301 ], + "P8": [ 295 ], + "P9": [ 296 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ 334 ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 233 ], + "P1": [ 234 ], + "P10": [ 288 ], + "P11": [ 289 ], + "P12": [ 283 ], + "P13": [ 284 ], + "P14": [ 280 ], + "P15": [ 275 ], + "P16": [ 355 ], + "P17": [ 356 ], + "P18": [ 357 ], + "P19": [ 358 ], + "P2": [ 308 ], + "P20": [ 359 ], + "P21": [ 360 ], + "P22": [ 361 ], + "P23": [ 362 ], + "P24": [ 363 ], + "P25": [ 364 ], + "P26": [ 365 ], + "P27": [ 366 ], + "P28": [ 367 ], + "P29": [ 368 ], + "P3": [ 309 ], + "P30": [ 369 ], + "P31": [ 370 ], + "P32": [ 371 ], + "P33": [ 372 ], + "P34": [ 373 ], + "P35": [ 374 ], + "P4": [ 303 ], + "P5": [ 304 ], + "P6": [ 298 ], + "P7": [ 299 ], + "P8": [ 293 ], + "P9": [ 294 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ 334 ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 230 ], + "P1": [ 231 ], + "P10": [ 260 ], + "P11": [ 261 ], + "P12": [ 265 ], + "P13": [ 266 ], + "P14": [ 270 ], + "P15": [ 271 ], + "P16": [ 375 ], + "P17": [ 376 ], + "P18": [ 377 ], + "P19": [ 378 ], + "P2": [ 240 ], + "P20": [ 379 ], + "P21": [ 380 ], + "P22": [ 381 ], + "P23": [ 382 ], + "P24": [ 383 ], + "P25": [ 384 ], + "P26": [ 385 ], + "P27": [ 386 ], + "P28": [ 387 ], + "P29": [ 388 ], + "P3": [ 241 ], + "P30": [ 389 ], + "P31": [ 390 ], + "P32": [ 391 ], + "P33": [ 392 ], + "P34": [ 393 ], + "P35": [ 394 ], + "P4": [ 245 ], + "P5": [ 246 ], + "P6": [ 250 ], + "P7": [ 251 ], + "P8": [ 255 ], + "P9": [ 256 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ 334 ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 228 ], + "P1": [ 229 ], + "P10": [ 258 ], + "P11": [ 259 ], + "P12": [ 263 ], + "P13": [ 264 ], + "P14": [ 268 ], + "P15": [ 269 ], + "P16": [ 395 ], + "P17": [ 396 ], + "P18": [ 397 ], + "P19": [ 398 ], + "P2": [ 238 ], + "P20": [ 399 ], + "P21": [ 400 ], + "P22": [ 401 ], + "P23": [ 402 ], + "P24": [ 403 ], + "P25": [ 404 ], + "P26": [ 405 ], + "P27": [ 406 ], + "P28": [ 407 ], + "P29": [ 408 ], + "P3": [ 239 ], + "P30": [ 409 ], + "P31": [ 410 ], + "P32": [ 411 ], + "P33": [ 412 ], + "P34": [ 413 ], + "P35": [ 414 ], + "P4": [ 243 ], + "P5": [ 244 ], + "P6": [ 248 ], + "P7": [ 249 ], + "P8": [ 253 ], + "P9": [ 254 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 415 ], + "LSR": [ 416 ], + "Q": [ 334 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100111111011101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 322 ], + "B": [ 51 ], + "C": [ 327 ], + "D": [ 313 ], + "Z": [ 415 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1110000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 328 ], + "B": [ 329 ], + "C": [ 417 ], + "D": [ 313 ], + "Z": [ 416 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_C_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 320 ], + "B": [ 321 ], + "C": [ 41 ], + "D": [ 51 ], + "Z": [ 417 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 418 ], + "LSR": [ 3 ], + "Q": [ 5 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 419 ], + "LSR": [ 3 ], + "Q": [ 6 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 420 ], + "LSR": [ 3 ], + "Q": [ 7 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 421 ], + "LSR": [ 3 ], + "Q": [ 8 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 422 ], + "LSR": [ 3 ], + "Q": [ 9 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 423 ], + "LSR": [ 3 ], + "Q": [ 10 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 424 ], + "LSR": [ 3 ], + "Q": [ 11 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ "0" ], + "LSR": [ 3 ], + "Q": [ 12 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 71 ], + "C": [ 425 ], + "D": [ 99 ], + "Z": [ 419 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 50 ], + "C": [ 425 ], + "D": [ 99 ], + "Z": [ 420 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 53 ], + "C": [ 425 ], + "D": [ 99 ], + "Z": [ 421 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 75 ], + "C": [ 425 ], + "D": [ 99 ], + "Z": [ 422 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 97 ], + "C": [ 425 ], + "D": [ 99 ], + "Z": [ 423 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 103 ], + "C": [ 425 ], + "D": [ 99 ], + "Z": [ 424 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 101 ], + "C": [ 425 ], + "D": [ 99 ], + "Z": [ 418 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 95 ], + "D": [ 426 ], + "Z": [ 425 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 91 ], + "A1": [ 93 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 427 ], + "COUT": [ 426 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 428 ], + "S1": [ 429 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 87 ], + "A1": [ 89 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 430 ], + "COUT": [ 427 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 431 ], + "S1": [ 432 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 83 ], + "A1": [ 85 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 433 ], + "COUT": [ 430 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 434 ], + "S1": [ 435 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 79 ], + "A1": [ 81 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 436 ], + "COUT": [ 433 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 437 ], + "S1": [ 438 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 73 ], + "A1": [ 77 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 439 ], + "COUT": [ 436 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 440 ], + "S1": [ 441 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 67 ], + "A1": [ 69 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 442 ], + "COUT": [ 439 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 443 ], + "S1": [ 444 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 63 ], + "A1": [ 65 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 445 ], + "COUT": [ 442 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 446 ], + "S1": [ 447 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 59 ], + "A1": [ 61 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 448 ], + "COUT": [ 445 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 449 ], + "S1": [ 450 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 55 ], + "A1": [ 57 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 451 ], + "COUT": [ 448 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 452 ], + "S1": [ 453 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 111 ], + "A1": [ 113 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 454 ], + "COUT": [ 451 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 455 ], + "S1": [ 456 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 107 ], + "A1": [ 109 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 457 ], + "COUT": [ 454 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 458 ], + "S1": [ 459 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 103 ], + "A1": [ 105 ], + "B0": [ "1" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 460 ], + "COUT": [ 457 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 461 ], + "S1": [ 462 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 75 ], + "A1": [ 97 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 463 ], + "COUT": [ 460 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 464 ], + "S1": [ 465 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 50 ], + "A1": [ 53 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 466 ], + "COUT": [ 463 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 467 ], + "S1": [ 468 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 101 ], + "A1": [ 71 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ "1" ], + "COUT": [ 466 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 469 ], + "S1": [ 470 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron", + "module": "$paramod$8b1cd44cf999e41637c5c45ad312808a2703769c\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 471 ], + "LSR": [ 49 ], + "Q": [ 472 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 473 ], + "LSR": [ 49 ], + "Q": [ 474 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 475 ], + "LSR": [ 49 ], + "Q": [ 476 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 477 ], + "LSR": [ 49 ], + "Q": [ 478 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 479 ], + "LSR": [ 49 ], + "Q": [ 480 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 481 ], + "LSR": [ 49 ], + "Q": [ 482 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 483 ], + "LSR": [ 49 ], + "Q": [ 484 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 485 ], + "LSR": [ 49 ], + "Q": [ 486 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 487 ], + "LSR": [ 49 ], + "Q": [ 488 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 489 ], + "LSR": [ 49 ], + "Q": [ 490 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 491 ], + "LSR": [ 49 ], + "Q": [ 492 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 493 ], + "LSR": [ 49 ], + "Q": [ 494 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 495 ], + "LSR": [ 49 ], + "Q": [ 496 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 497 ], + "LSR": [ 49 ], + "Q": [ 498 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 499 ], + "LSR": [ 49 ], + "Q": [ 500 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 501 ], + "LSR": [ 49 ], + "Q": [ 502 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 503 ], + "LSR": [ 49 ], + "Q": [ 504 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 505 ], + "LSR": [ 49 ], + "Q": [ 506 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 507 ], + "LSR": [ 49 ], + "Q": [ 508 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 509 ], + "LSR": [ 49 ], + "Q": [ 510 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 511 ], + "LSR": [ 49 ], + "Q": [ 512 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 513 ], + "LSR": [ 49 ], + "Q": [ 514 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_29": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 515 ], + "LSR": [ 49 ], + "Q": [ 516 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 517 ], + "LSR": [ 49 ], + "Q": [ 518 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_30": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 519 ], + "LSR": [ 49 ], + "Q": [ 520 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_31": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 521 ], + "LSR": [ 49 ], + "Q": [ 522 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 523 ], + "LSR": [ 49 ], + "Q": [ 524 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 525 ], + "LSR": [ 49 ], + "Q": [ 526 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 527 ], + "LSR": [ 49 ], + "Q": [ 528 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 529 ], + "LSR": [ 49 ], + "Q": [ 530 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 531 ], + "LSR": [ 49 ], + "Q": [ 532 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 40 ], + "CLK": [ 2 ], + "DI": [ 533 ], + "LSR": [ 49 ], + "Q": [ 534 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 471 ], + "A1": [ 535 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ "1" ], + "COUT": [ 536 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 537 ], + "S1": [ 538 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 471 ], + "A1": [ 539 ], + "B0": [ "0" ], + "B1": [ 540 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 541 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 542 ], + "S1": [ 543 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 474 ], + "C": [ 544 ], + "D": [ 545 ], + "Z": [ 539 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 472 ], + "C": [ 546 ], + "D": [ 547 ], + "Z": [ 540 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 548 ], + "A1": [ 549 ], + "B0": [ 550 ], + "B1": [ 551 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 541 ], + "COUT": [ 552 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 553 ], + "S1": [ 554 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 496 ], + "C": [ 555 ], + "D": [ 556 ], + "Z": [ 548 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 518 ], + "C": [ 557 ], + "D": [ 558 ], + "Z": [ 549 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 474 ], + "C": [ 544 ], + "D": [ 545 ], + "Z": [ 550 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 496 ], + "C": [ 555 ], + "D": [ 556 ], + "Z": [ 551 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S0_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 543 ], + "B1": [ 553 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 559 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 560 ], + "S1": [ 561 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 562 ], + "C": [ 563 ], + "D": [ 564 ], + "Z": [ 565 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S0_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 566 ], + "B": [ 567 ], + "C": [ 568 ], + "D": [ 569 ], + "Z": [ 564 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 554 ], + "B1": [ 570 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 559 ], + "COUT": [ 571 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 572 ], + "S1": [ 573 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 574 ], + "A1": [ 575 ], + "B0": [ 576 ], + "B1": [ 577 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 552 ], + "COUT": [ 578 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 570 ], + "S1": [ 579 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 524 ], + "C": [ 580 ], + "D": [ 581 ], + "Z": [ 574 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 526 ], + "C": [ 582 ], + "D": [ 583 ], + "Z": [ 575 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 518 ], + "C": [ 557 ], + "D": [ 558 ], + "Z": [ 576 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 524 ], + "C": [ 580 ], + "D": [ 581 ], + "Z": [ 577 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 579 ], + "B1": [ 584 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 571 ], + "COUT": [ 585 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 586 ], + "S1": [ 587 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 588 ], + "A1": [ 589 ], + "B0": [ 590 ], + "B1": [ 591 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 578 ], + "COUT": [ 592 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 584 ], + "S1": [ 593 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 528 ], + "C": [ 594 ], + "D": [ 595 ], + "Z": [ 588 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 530 ], + "C": [ 596 ], + "D": [ 597 ], + "Z": [ 589 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 526 ], + "C": [ 582 ], + "D": [ 583 ], + "Z": [ 590 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 528 ], + "C": [ 594 ], + "D": [ 595 ], + "Z": [ 591 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 593 ], + "B1": [ 598 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 585 ], + "COUT": [ 599 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 600 ], + "S1": [ 601 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 602 ], + "A1": [ 603 ], + "B0": [ 604 ], + "B1": [ 605 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 592 ], + "COUT": [ 606 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 598 ], + "S1": [ 607 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 532 ], + "C": [ 608 ], + "D": [ 609 ], + "Z": [ 602 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 534 ], + "C": [ 610 ], + "D": [ 611 ], + "Z": [ 603 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 530 ], + "C": [ 596 ], + "D": [ 597 ], + "Z": [ 604 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 532 ], + "C": [ 608 ], + "D": [ 609 ], + "Z": [ 605 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 607 ], + "B1": [ 612 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 599 ], + "COUT": [ 613 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 614 ], + "S1": [ 615 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 616 ], + "A1": [ 617 ], + "B0": [ 618 ], + "B1": [ 619 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 606 ], + "COUT": [ 620 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 612 ], + "S1": [ 621 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 476 ], + "C": [ 622 ], + "D": [ 623 ], + "Z": [ 616 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 478 ], + "C": [ 624 ], + "D": [ 625 ], + "Z": [ 617 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 534 ], + "C": [ 610 ], + "D": [ 611 ], + "Z": [ 618 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 476 ], + "C": [ 622 ], + "D": [ 623 ], + "Z": [ 619 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 621 ], + "B1": [ 626 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 613 ], + "COUT": [ 627 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 628 ], + "S1": [ 629 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 630 ], + "A1": [ 631 ], + "B0": [ 632 ], + "B1": [ 633 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 620 ], + "COUT": [ 634 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 626 ], + "S1": [ 635 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 480 ], + "C": [ 636 ], + "D": [ 637 ], + "Z": [ 630 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 482 ], + "C": [ 638 ], + "D": [ 639 ], + "Z": [ 631 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 478 ], + "C": [ 624 ], + "D": [ 625 ], + "Z": [ 632 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 480 ], + "C": [ 636 ], + "D": [ 637 ], + "Z": [ 633 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 635 ], + "B1": [ 640 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 627 ], + "COUT": [ 641 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 642 ], + "S1": [ 643 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 644 ], + "A1": [ 645 ], + "B0": [ 646 ], + "B1": [ 647 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 634 ], + "COUT": [ 648 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 640 ], + "S1": [ 649 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 484 ], + "C": [ 650 ], + "D": [ 651 ], + "Z": [ 644 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 486 ], + "C": [ 652 ], + "D": [ 653 ], + "Z": [ 645 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 482 ], + "C": [ 638 ], + "D": [ 639 ], + "Z": [ 646 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 484 ], + "C": [ 650 ], + "D": [ 651 ], + "Z": [ 647 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 649 ], + "B1": [ 654 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 641 ], + "COUT": [ 655 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 656 ], + "S1": [ 657 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 658 ], + "A1": [ 659 ], + "B0": [ 660 ], + "B1": [ 661 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 648 ], + "COUT": [ 662 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 654 ], + "S1": [ 663 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 488 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 658 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 490 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 659 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 486 ], + "C": [ 652 ], + "D": [ 653 ], + "Z": [ 660 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 488 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 661 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 663 ], + "B1": [ 666 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 655 ], + "COUT": [ 667 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 668 ], + "S1": [ 669 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 670 ], + "A1": [ 671 ], + "B0": [ 672 ], + "B1": [ 673 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 662 ], + "COUT": [ 674 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 666 ], + "S1": [ 675 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 492 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 670 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 494 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 671 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 490 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 672 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 492 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 673 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 675 ], + "B1": [ 676 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 667 ], + "COUT": [ 677 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 678 ], + "S1": [ 679 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 680 ], + "A1": [ 681 ], + "B0": [ 682 ], + "B1": [ 683 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 674 ], + "COUT": [ 684 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 676 ], + "S1": [ 685 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 498 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 680 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 500 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 681 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 494 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 682 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 498 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 683 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 685 ], + "B1": [ 686 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 677 ], + "COUT": [ 687 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 688 ], + "S1": [ 689 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 690 ], + "A1": [ 691 ], + "B0": [ 692 ], + "B1": [ 693 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 684 ], + "COUT": [ 694 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 686 ], + "S1": [ 695 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 502 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 690 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 504 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 691 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 500 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 692 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 502 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 693 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 695 ], + "B1": [ 696 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 687 ], + "COUT": [ 697 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 698 ], + "S1": [ 699 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 700 ], + "A1": [ 701 ], + "B0": [ 702 ], + "B1": [ 703 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 694 ], + "COUT": [ 704 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 696 ], + "S1": [ 705 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 506 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 700 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 508 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 701 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 504 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 702 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 506 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 703 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 705 ], + "B1": [ 706 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 697 ], + "COUT": [ 707 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 708 ], + "S1": [ 709 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 710 ], + "A1": [ 711 ], + "B0": [ 712 ], + "B1": [ 713 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 704 ], + "COUT": [ 714 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 706 ], + "S1": [ 715 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 510 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 710 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 512 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 711 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 508 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 712 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 510 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 713 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 715 ], + "B1": [ 716 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 707 ], + "COUT": [ 717 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 718 ], + "S1": [ 719 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 720 ], + "A1": [ 721 ], + "B0": [ 722 ], + "B1": [ 723 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 714 ], + "COUT": [ 724 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 716 ], + "S1": [ 725 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 514 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 720 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 516 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 721 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 512 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 722 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 514 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 723 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 725 ], + "B1": [ 726 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 717 ], + "COUT": [ 727 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 728 ], + "S1": [ 729 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 730 ], + "A1": [ 731 ], + "B0": [ 732 ], + "B1": [ 733 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 724 ], + "COUT": [ 734 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 726 ], + "S1": [ 735 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 520 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 730 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 522 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 731 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 516 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 732 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 520 ], + "C": [ 664 ], + "D": [ 665 ], + "Z": [ 733 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 735 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 727 ], + "COUT": [ 736 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 737 ], + "S1": [ 738 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 565 ], + "D": [ 543 ], + "Z": [ 473 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 725 ], + "D": [ 728 ], + "Z": [ 515 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 716 ], + "D": [ 719 ], + "Z": [ 513 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_10": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 553 ], + "D": [ 561 ], + "Z": [ 495 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_11": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 554 ], + "D": [ 572 ], + "Z": [ 517 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_12": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 570 ], + "D": [ 573 ], + "Z": [ 523 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_13": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 579 ], + "D": [ 586 ], + "Z": [ 525 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_14": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 584 ], + "D": [ 587 ], + "Z": [ 527 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_15": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 593 ], + "D": [ 600 ], + "Z": [ 529 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_16": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 598 ], + "D": [ 601 ], + "Z": [ 531 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_17": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 607 ], + "D": [ 614 ], + "Z": [ 533 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_18": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 612 ], + "D": [ 615 ], + "Z": [ 475 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_19": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 621 ], + "D": [ 628 ], + "Z": [ 477 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 696 ], + "D": [ 699 ], + "Z": [ 505 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_20": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 626 ], + "D": [ 629 ], + "Z": [ 479 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_21": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 635 ], + "D": [ 642 ], + "Z": [ 481 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_22": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 640 ], + "D": [ 643 ], + "Z": [ 483 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_23": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 649 ], + "D": [ 656 ], + "Z": [ 485 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_24": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 654 ], + "D": [ 657 ], + "Z": [ 487 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_25": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 663 ], + "D": [ 668 ], + "Z": [ 489 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_26": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 666 ], + "D": [ 669 ], + "Z": [ 491 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_27": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 675 ], + "D": [ 678 ], + "Z": [ 493 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_28": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 676 ], + "D": [ 679 ], + "Z": [ 497 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_29": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 685 ], + "D": [ 688 ], + "Z": [ 499 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 705 ], + "D": [ 708 ], + "Z": [ 507 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 706 ], + "D": [ 709 ], + "Z": [ 509 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 726 ], + "D": [ 729 ], + "Z": [ 519 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 715 ], + "D": [ 718 ], + "Z": [ 511 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_7": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 686 ], + "D": [ 689 ], + "Z": [ 501 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_8": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 735 ], + "D": [ 737 ], + "Z": [ 521 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z_LUT4_Z_9": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110000110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 565 ], + "C": [ 695 ], + "D": [ 698 ], + "Z": [ 503 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 543 ], + "Z": [ 535 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 561 ], + "A1": [ 572 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 536 ], + "COUT": [ 739 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 740 ], + "S1": [ 741 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 573 ], + "A1": [ 586 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 739 ], + "COUT": [ 742 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 743 ], + "S1": [ 744 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 587 ], + "A1": [ 600 ], + "B0": [ "1" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 742 ], + "COUT": [ 745 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 746 ], + "S1": [ 747 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 601 ], + "A1": [ 614 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 745 ], + "COUT": [ 748 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 749 ], + "S1": [ 750 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 615 ], + "A1": [ 628 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 748 ], + "COUT": [ 751 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 752 ], + "S1": [ 753 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 629 ], + "A1": [ 642 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 751 ], + "COUT": [ 754 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 755 ], + "S1": [ 756 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 643 ], + "A1": [ 656 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 754 ], + "COUT": [ 757 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 758 ], + "S1": [ 759 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 657 ], + "A1": [ 668 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 757 ], + "COUT": [ 760 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 761 ], + "S1": [ 762 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 669 ], + "A1": [ 678 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 760 ], + "COUT": [ 763 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 764 ], + "S1": [ 765 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 679 ], + "A1": [ 688 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 763 ], + "COUT": [ 766 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 767 ], + "S1": [ 768 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 689 ], + "A1": [ 698 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 766 ], + "COUT": [ 769 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 770 ], + "S1": [ 771 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 699 ], + "A1": [ 708 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 769 ], + "COUT": [ 772 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 773 ], + "S1": [ 774 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 709 ], + "A1": [ 718 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 772 ], + "COUT": [ 775 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 776 ], + "S1": [ 777 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 719 ], + "A1": [ 728 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 775 ], + "COUT": [ 778 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 779 ], + "S1": [ 780 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 729 ], + "D": [ 778 ], + "Z": [ 781 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 471 ], + "C": [ 781 ], + "D": [ 737 ], + "Z": [ 782 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 543 ], + "C": [ 781 ], + "D": [ 737 ], + "Z": [ 783 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 561 ], + "C": [ 781 ], + "D": [ 737 ], + "Z": [ 784 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 572 ], + "C": [ 781 ], + "D": [ 737 ], + "Z": [ 785 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 573 ], + "C": [ 781 ], + "D": [ 737 ], + "Z": [ 786 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 586 ], + "C": [ 781 ], + "D": [ 737 ], + "Z": [ 787 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 587 ], + "C": [ 781 ], + "D": [ 737 ], + "Z": [ 788 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 472 ], + "C": [ 546 ], + "D": [ 547 ], + "Z": [ 471 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 789 ], + "A1": [ 790 ], + "B0": [ 791 ], + "B1": [ 792 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 793 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 547 ], + "S1": [ 545 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 794 ], + "A1": [ 795 ], + "B0": [ 796 ], + "B1": [ 797 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 798 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 546 ], + "S1": [ 544 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 799 ], + "A1": [ 800 ], + "B0": [ 801 ], + "B1": [ 802 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 798 ], + "COUT": [ 803 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 555 ], + "S1": [ 557 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 804 ], + "A1": [ 805 ], + "B0": [ 806 ], + "B1": [ 807 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 803 ], + "COUT": [ 808 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 580 ], + "S1": [ 582 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 809 ], + "A1": [ 810 ], + "B0": [ 811 ], + "B1": [ 812 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 808 ], + "COUT": [ 813 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 594 ], + "S1": [ 596 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 814 ], + "A1": [ 815 ], + "B0": [ 816 ], + "B1": [ 817 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 813 ], + "COUT": [ 818 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 608 ], + "S1": [ 610 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 819 ], + "A1": [ 820 ], + "B0": [ 821 ], + "B1": [ 822 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 818 ], + "COUT": [ 823 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 622 ], + "S1": [ 624 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 824 ], + "A1": [ 825 ], + "B0": [ 826 ], + "B1": [ 827 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 823 ], + "COUT": [ 828 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 636 ], + "S1": [ 638 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 829 ], + "A1": [ 830 ], + "B0": [ 831 ], + "B1": [ 832 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 828 ], + "COUT": [ 833 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 650 ], + "S1": [ 652 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 830 ], + "A1": [ "0" ], + "B0": [ 832 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 833 ], + "COUT": [ 834 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 664 ], + "S1": [ 835 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 836 ], + "A1": [ "0" ], + "B0": [ 837 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 838 ], + "COUT": [ 839 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 665 ], + "S1": [ 840 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 841 ], + "A1": [ 836 ], + "B0": [ 842 ], + "B1": [ 837 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 843 ], + "COUT": [ 838 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 651 ], + "S1": [ 653 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 844 ], + "A1": [ 845 ], + "B0": [ 846 ], + "B1": [ 847 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 848 ], + "COUT": [ 843 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 637 ], + "S1": [ 639 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 849 ], + "A1": [ 850 ], + "B0": [ 851 ], + "B1": [ 852 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 853 ], + "COUT": [ 848 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 623 ], + "S1": [ 625 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 854 ], + "A1": [ 855 ], + "B0": [ 856 ], + "B1": [ 857 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 858 ], + "COUT": [ 853 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 609 ], + "S1": [ 611 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 859 ], + "A1": [ 860 ], + "B0": [ 861 ], + "B1": [ 862 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 863 ], + "COUT": [ 858 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 595 ], + "S1": [ 597 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 864 ], + "A1": [ 865 ], + "B0": [ 866 ], + "B1": [ 867 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 868 ], + "COUT": [ 863 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 581 ], + "S1": [ 583 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 869 ], + "A1": [ 870 ], + "B0": [ 871 ], + "B1": [ 872 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 793 ], + "COUT": [ 868 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 556 ], + "S1": [ 558 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 873 ], + "LSR": [ 3 ], + "Q": [ 40 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 40 ], + "D": [ 565 ], + "Z": [ 873 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 565 ], + "LSR": [ 874 ], + "Q": [ 44 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 40 ], + "Z": [ 874 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 875 ], + "CLK": [ 2 ], + "DI": [ 876 ], + "LSR": [ 49 ], + "Q": [ 563 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 875 ], + "CLK": [ 2 ], + "DI": [ 877 ], + "LSR": [ 49 ], + "Q": [ 562 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 875 ], + "CLK": [ 2 ], + "DI": [ 878 ], + "LSR": [ 49 ], + "Q": [ 569 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 875 ], + "CLK": [ 2 ], + "DI": [ 879 ], + "LSR": [ 49 ], + "Q": [ 568 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 875 ], + "CLK": [ 2 ], + "DI": [ 880 ], + "LSR": [ 49 ], + "Q": [ 567 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 875 ], + "CLK": [ 2 ], + "DI": [ 881 ], + "LSR": [ 49 ], + "Q": [ 566 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_CE_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 40 ], + "D": [ 565 ], + "Z": [ 875 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 569 ], + "B1": [ 568 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 882 ], + "COUT": [ 883 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 878 ], + "S1": [ 879 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 563 ], + "B1": [ 562 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 882 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 884 ], + "S1": [ 877 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 567 ], + "B1": [ 566 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 883 ], + "COUT": [ 885 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 880 ], + "S1": [ 881 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 563 ], + "Z": [ 876 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8", + "module": "$paramod$20e373d74dd35704a68fa9d31f078ebc648ae4d9\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 791 ], + "P1": [ 792 ], + "P10": [ 851 ], + "P11": [ 852 ], + "P12": [ 846 ], + "P13": [ 847 ], + "P14": [ 842 ], + "P15": [ 837 ], + "P16": [ 886 ], + "P17": [ 887 ], + "P18": [ 888 ], + "P19": [ 889 ], + "P2": [ 871 ], + "P20": [ 890 ], + "P21": [ 891 ], + "P22": [ 892 ], + "P23": [ 893 ], + "P24": [ 894 ], + "P25": [ 895 ], + "P26": [ 896 ], + "P27": [ 897 ], + "P28": [ 898 ], + "P29": [ 899 ], + "P3": [ 872 ], + "P30": [ 900 ], + "P31": [ 901 ], + "P32": [ 902 ], + "P33": [ 903 ], + "P34": [ 904 ], + "P35": [ 905 ], + "P4": [ 866 ], + "P5": [ 867 ], + "P6": [ 861 ], + "P7": [ 862 ], + "P8": [ 856 ], + "P9": [ 857 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 789 ], + "P1": [ 790 ], + "P10": [ 849 ], + "P11": [ 850 ], + "P12": [ 844 ], + "P13": [ 845 ], + "P14": [ 841 ], + "P15": [ 836 ], + "P16": [ 906 ], + "P17": [ 907 ], + "P18": [ 908 ], + "P19": [ 909 ], + "P2": [ 869 ], + "P20": [ 910 ], + "P21": [ 911 ], + "P22": [ 912 ], + "P23": [ 913 ], + "P24": [ 914 ], + "P25": [ 915 ], + "P26": [ 916 ], + "P27": [ 917 ], + "P28": [ 918 ], + "P29": [ 919 ], + "P3": [ 870 ], + "P30": [ 920 ], + "P31": [ 921 ], + "P32": [ 922 ], + "P33": [ 923 ], + "P34": [ 924 ], + "P35": [ 925 ], + "P4": [ 864 ], + "P5": [ 865 ], + "P6": [ 859 ], + "P7": [ 860 ], + "P8": [ 854 ], + "P9": [ 855 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 796 ], + "P1": [ 797 ], + "P10": [ 821 ], + "P11": [ 822 ], + "P12": [ 826 ], + "P13": [ 827 ], + "P14": [ 831 ], + "P15": [ 832 ], + "P16": [ 926 ], + "P17": [ 927 ], + "P18": [ 928 ], + "P19": [ 929 ], + "P2": [ 801 ], + "P20": [ 930 ], + "P21": [ 931 ], + "P22": [ 932 ], + "P23": [ 933 ], + "P24": [ 934 ], + "P25": [ 935 ], + "P26": [ 936 ], + "P27": [ 937 ], + "P28": [ 938 ], + "P29": [ 939 ], + "P3": [ 802 ], + "P30": [ 940 ], + "P31": [ 941 ], + "P32": [ 942 ], + "P33": [ 943 ], + "P34": [ 944 ], + "P35": [ 945 ], + "P4": [ 806 ], + "P5": [ 807 ], + "P6": [ 811 ], + "P7": [ 812 ], + "P8": [ 816 ], + "P9": [ 817 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ "0" ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 794 ], + "P1": [ 795 ], + "P10": [ 819 ], + "P11": [ 820 ], + "P12": [ 824 ], + "P13": [ 825 ], + "P14": [ 829 ], + "P15": [ 830 ], + "P16": [ 946 ], + "P17": [ 947 ], + "P18": [ 948 ], + "P19": [ 949 ], + "P2": [ 799 ], + "P20": [ 950 ], + "P21": [ 951 ], + "P22": [ 952 ], + "P23": [ 953 ], + "P24": [ 954 ], + "P25": [ 955 ], + "P26": [ 956 ], + "P27": [ 957 ], + "P28": [ 958 ], + "P29": [ 959 ], + "P3": [ 800 ], + "P30": [ 960 ], + "P31": [ 961 ], + "P32": [ 962 ], + "P33": [ 963 ], + "P34": [ 964 ], + "P35": [ 965 ], + "P4": [ 804 ], + "P5": [ 805 ], + "P6": [ 809 ], + "P7": [ 810 ], + "P8": [ 814 ], + "P9": [ 815 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 966 ], + "CLK": [ 2 ], + "DI": [ 782 ], + "LSR": [ 3 ], + "Q": [ 13 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 966 ], + "CLK": [ 2 ], + "DI": [ 783 ], + "LSR": [ 3 ], + "Q": [ 14 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 966 ], + "CLK": [ 2 ], + "DI": [ 784 ], + "LSR": [ 3 ], + "Q": [ 15 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 966 ], + "CLK": [ 2 ], + "DI": [ 785 ], + "LSR": [ 3 ], + "Q": [ 16 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 966 ], + "CLK": [ 2 ], + "DI": [ 786 ], + "LSR": [ 3 ], + "Q": [ 17 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 966 ], + "CLK": [ 2 ], + "DI": [ 787 ], + "LSR": [ 3 ], + "Q": [ 18 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 966 ], + "CLK": [ 2 ], + "DI": [ 788 ], + "LSR": [ 3 ], + "Q": [ 19 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 966 ], + "CLK": [ 2 ], + "DI": [ "0" ], + "LSR": [ 3 ], + "Q": [ 20 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_CE_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 40 ], + "D": [ 565 ], + "Z": [ 966 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron", + "module": "$paramod$8b1cd44cf999e41637c5c45ad312808a2703769c\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 967 ], + "LSR": [ 47 ], + "Q": [ 968 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 969 ], + "LSR": [ 47 ], + "Q": [ 970 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 971 ], + "LSR": [ 47 ], + "Q": [ 972 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 973 ], + "LSR": [ 47 ], + "Q": [ 974 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 975 ], + "LSR": [ 47 ], + "Q": [ 976 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 977 ], + "LSR": [ 47 ], + "Q": [ 978 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 979 ], + "LSR": [ 47 ], + "Q": [ 980 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 981 ], + "LSR": [ 47 ], + "Q": [ 982 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 983 ], + "LSR": [ 47 ], + "Q": [ 984 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 985 ], + "LSR": [ 47 ], + "Q": [ 986 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 987 ], + "LSR": [ 47 ], + "Q": [ 988 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 989 ], + "LSR": [ 47 ], + "Q": [ 990 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 991 ], + "LSR": [ 47 ], + "Q": [ 992 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 993 ], + "LSR": [ 47 ], + "Q": [ 994 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 995 ], + "LSR": [ 47 ], + "Q": [ 996 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 997 ], + "LSR": [ 47 ], + "Q": [ 998 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 999 ], + "LSR": [ 47 ], + "Q": [ 1000 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1001 ], + "LSR": [ 47 ], + "Q": [ 1002 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1003 ], + "LSR": [ 47 ], + "Q": [ 1004 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1005 ], + "LSR": [ 47 ], + "Q": [ 1006 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1007 ], + "LSR": [ 47 ], + "Q": [ 1008 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1009 ], + "LSR": [ 47 ], + "Q": [ 1010 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_29": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1011 ], + "LSR": [ 47 ], + "Q": [ 1012 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1013 ], + "LSR": [ 47 ], + "Q": [ 1014 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_30": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1015 ], + "LSR": [ 47 ], + "Q": [ 1016 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_31": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1017 ], + "LSR": [ 47 ], + "Q": [ 1018 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1019 ], + "LSR": [ 47 ], + "Q": [ 1020 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1021 ], + "LSR": [ 47 ], + "Q": [ 1022 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1023 ], + "LSR": [ 47 ], + "Q": [ 1024 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1025 ], + "LSR": [ 47 ], + "Q": [ 1026 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1027 ], + "LSR": [ 47 ], + "Q": [ 1028 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 39 ], + "CLK": [ 2 ], + "DI": [ 1029 ], + "LSR": [ 47 ], + "Q": [ 1030 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1031 ], + "A1": [ 1032 ], + "B0": [ 1033 ], + "B1": [ 1034 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1035 ], + "COUT": [ 1036 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 991 ], + "S1": [ 1013 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1037 ], + "A1": [ 1038 ], + "B0": [ 1039 ], + "B1": [ 1040 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1041 ], + "COUT": [ 1042 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 993 ], + "S1": [ 995 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1043 ], + "A1": [ 1044 ], + "B0": [ 1045 ], + "B1": [ 1046 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1047 ], + "COUT": [ 1048 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 975 ], + "S1": [ 977 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 976 ], + "C": [ 1049 ], + "D": [ 1050 ], + "Z": [ 1043 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 978 ], + "C": [ 1051 ], + "D": [ 1052 ], + "Z": [ 1044 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 974 ], + "C": [ 1053 ], + "D": [ 1054 ], + "Z": [ 1045 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 976 ], + "C": [ 1049 ], + "D": [ 1050 ], + "Z": [ 1046 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1055 ], + "A1": [ 1056 ], + "B0": [ 1057 ], + "B1": [ 1058 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1059 ], + "COUT": [ 1035 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 967 ], + "S1": [ 969 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 968 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1055 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 970 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1056 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1018 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1057 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 968 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1058 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1062 ], + "A1": [ 1063 ], + "B0": [ 1064 ], + "B1": [ 1065 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1066 ], + "COUT": [ 1041 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 987 ], + "S1": [ 989 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 988 ], + "C": [ 1067 ], + "D": [ 1068 ], + "Z": [ 1062 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 990 ], + "C": [ 1069 ], + "D": [ 1070 ], + "Z": [ 1063 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 986 ], + "C": [ 1071 ], + "D": [ 1072 ], + "Z": [ 1064 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 988 ], + "C": [ 1067 ], + "D": [ 1068 ], + "Z": [ 1065 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1073 ], + "A1": [ 1074 ], + "B0": [ 1075 ], + "B1": [ 1076 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1077 ], + "COUT": [ 1078 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1023 ], + "S1": [ 1025 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1024 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1073 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1026 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1074 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1022 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1075 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1024 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1076 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1079 ], + "A1": [ 1080 ], + "B0": [ 1081 ], + "B1": [ 1082 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1083 ], + "COUT": [ 1066 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 983 ], + "S1": [ 985 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 984 ], + "C": [ 1084 ], + "D": [ 1085 ], + "Z": [ 1079 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 986 ], + "C": [ 1071 ], + "D": [ 1072 ], + "Z": [ 1080 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 982 ], + "C": [ 1086 ], + "D": [ 1087 ], + "Z": [ 1081 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 984 ], + "C": [ 1084 ], + "D": [ 1085 ], + "Z": [ 1082 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1088 ], + "A1": [ 1089 ], + "B0": [ 1090 ], + "B1": [ 1091 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1092 ], + "COUT": [ 1093 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1009 ], + "S1": [ 1011 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1010 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1088 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1012 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1089 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1008 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1090 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1010 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1091 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 994 ], + "C": [ 1094 ], + "D": [ 1095 ], + "Z": [ 1037 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 996 ], + "C": [ 1096 ], + "D": [ 1097 ], + "Z": [ 1038 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 990 ], + "C": [ 1069 ], + "D": [ 1070 ], + "Z": [ 1039 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 994 ], + "C": [ 1094 ], + "D": [ 1095 ], + "Z": [ 1040 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1029 ], + "A1": [ 1098 ], + "B0": [ "0" ], + "B1": [ 1099 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 1047 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1100 ], + "S1": [ 973 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 974 ], + "C": [ 1053 ], + "D": [ 1054 ], + "Z": [ 1098 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1030 ], + "C": [ 1101 ], + "D": [ 1102 ], + "Z": [ 1099 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1103 ], + "A1": [ 1104 ], + "B0": [ 1105 ], + "B1": [ 1106 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1036 ], + "COUT": [ 1077 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1019 ], + "S1": [ 1021 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1020 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1103 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1022 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1104 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1014 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1105 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1020 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1106 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1107 ], + "A1": [ 1108 ], + "B0": [ 1109 ], + "B1": [ 1110 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1042 ], + "COUT": [ 1111 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 997 ], + "S1": [ 999 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 998 ], + "C": [ 1112 ], + "D": [ 1113 ], + "Z": [ 1107 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1000 ], + "C": [ 1114 ], + "D": [ 1115 ], + "Z": [ 1108 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 996 ], + "C": [ 1096 ], + "D": [ 1097 ], + "Z": [ 1109 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 998 ], + "C": [ 1112 ], + "D": [ 1113 ], + "Z": [ 1110 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1116 ], + "A1": [ 1117 ], + "B0": [ 1118 ], + "B1": [ 1119 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1111 ], + "COUT": [ 1120 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1001 ], + "S1": [ 1003 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1002 ], + "C": [ 1121 ], + "D": [ 1122 ], + "Z": [ 1116 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1004 ], + "C": [ 1123 ], + "D": [ 1124 ], + "Z": [ 1117 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1000 ], + "C": [ 1114 ], + "D": [ 1115 ], + "Z": [ 1118 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1002 ], + "C": [ 1121 ], + "D": [ 1122 ], + "Z": [ 1119 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1125 ], + "A1": [ 1126 ], + "B0": [ 1127 ], + "B1": [ 1128 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1048 ], + "COUT": [ 1083 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 979 ], + "S1": [ 981 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 980 ], + "C": [ 1129 ], + "D": [ 1130 ], + "Z": [ 1125 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 982 ], + "C": [ 1086 ], + "D": [ 1087 ], + "Z": [ 1126 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 978 ], + "C": [ 1051 ], + "D": [ 1052 ], + "Z": [ 1127 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 980 ], + "C": [ 1129 ], + "D": [ 1130 ], + "Z": [ 1128 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1131 ], + "A1": [ 1132 ], + "B0": [ 1133 ], + "B1": [ 1134 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1120 ], + "COUT": [ 1092 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1005 ], + "S1": [ 1007 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1006 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1131 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1008 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1132 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1004 ], + "C": [ 1123 ], + "D": [ 1124 ], + "Z": [ 1133 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1006 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1134 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1135 ], + "A1": [ 1136 ], + "B0": [ 1137 ], + "B1": [ 1138 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1093 ], + "COUT": [ 1059 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1015 ], + "S1": [ 1017 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1016 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1135 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1018 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1136 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1012 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1137 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1016 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1138 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1139 ], + "A1": [ 1140 ], + "B0": [ 1141 ], + "B1": [ 1142 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1078 ], + "COUT": [ 1143 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1027 ], + "S1": [ 971 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1028 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1139 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 972 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1140 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1026 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1141 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1028 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1142 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 992 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1031 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1014 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1032 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 970 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1033 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 992 ], + "C": [ 1060 ], + "D": [ 1061 ], + "Z": [ 1034 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1030 ], + "C": [ 1101 ], + "D": [ 1102 ], + "Z": [ 1029 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1144 ], + "A1": [ 1145 ], + "B0": [ 1146 ], + "B1": [ 1147 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 1148 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1101 ], + "S1": [ 1053 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1149 ], + "A1": [ 1150 ], + "B0": [ 1151 ], + "B1": [ 1152 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 1153 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1102 ], + "S1": [ 1054 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1154 ], + "A1": [ 1155 ], + "B0": [ 1156 ], + "B1": [ 1157 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1153 ], + "COUT": [ 1158 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1050 ], + "S1": [ 1052 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1159 ], + "A1": [ 1160 ], + "B0": [ 1161 ], + "B1": [ 1162 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1158 ], + "COUT": [ 1163 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1130 ], + "S1": [ 1087 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1164 ], + "A1": [ 1165 ], + "B0": [ 1166 ], + "B1": [ 1167 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1163 ], + "COUT": [ 1168 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1085 ], + "S1": [ 1072 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1169 ], + "A1": [ 1170 ], + "B0": [ 1171 ], + "B1": [ 1172 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1168 ], + "COUT": [ 1173 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1068 ], + "S1": [ 1070 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1174 ], + "A1": [ 1175 ], + "B0": [ 1176 ], + "B1": [ 1177 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1173 ], + "COUT": [ 1178 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1095 ], + "S1": [ 1097 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1179 ], + "A1": [ 1180 ], + "B0": [ 1181 ], + "B1": [ 1182 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1178 ], + "COUT": [ 1183 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1113 ], + "S1": [ 1115 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1184 ], + "A1": [ 1185 ], + "B0": [ 1186 ], + "B1": [ 1187 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1183 ], + "COUT": [ 1188 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1122 ], + "S1": [ 1124 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1185 ], + "A1": [ "0" ], + "B0": [ 1187 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1188 ], + "COUT": [ 1189 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1061 ], + "S1": [ 1190 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1191 ], + "A1": [ "0" ], + "B0": [ 1192 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1193 ], + "COUT": [ 1194 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1060 ], + "S1": [ 1195 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1196 ], + "A1": [ 1191 ], + "B0": [ 1197 ], + "B1": [ 1192 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1198 ], + "COUT": [ 1193 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1121 ], + "S1": [ 1123 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1199 ], + "A1": [ 1200 ], + "B0": [ 1201 ], + "B1": [ 1202 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1203 ], + "COUT": [ 1198 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1112 ], + "S1": [ 1114 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1204 ], + "A1": [ 1205 ], + "B0": [ 1206 ], + "B1": [ 1207 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1208 ], + "COUT": [ 1203 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1094 ], + "S1": [ 1096 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1209 ], + "A1": [ 1210 ], + "B0": [ 1211 ], + "B1": [ 1212 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1213 ], + "COUT": [ 1208 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1067 ], + "S1": [ 1069 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1214 ], + "A1": [ 1215 ], + "B0": [ 1216 ], + "B1": [ 1217 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1218 ], + "COUT": [ 1213 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1084 ], + "S1": [ 1071 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1219 ], + "A1": [ 1220 ], + "B0": [ 1221 ], + "B1": [ 1222 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1223 ], + "COUT": [ 1218 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1129 ], + "S1": [ 1086 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1224 ], + "A1": [ 1225 ], + "B0": [ 1226 ], + "B1": [ 1227 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1148 ], + "COUT": [ 1223 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1049 ], + "S1": [ 1051 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1228 ], + "LSR": [ 3 ], + "Q": [ 39 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 39 ], + "D": [ 1229 ], + "Z": [ 1228 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1229 ], + "LSR": [ 1230 ], + "Q": [ 43 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 39 ], + "D": [ 1229 ], + "Z": [ 1231 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 39 ], + "D": [ 1229 ], + "Z": [ 1232 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1233 ], + "C": [ 1234 ], + "D": [ 1235 ], + "Z": [ 1229 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1236 ], + "B": [ 1237 ], + "C": [ 1238 ], + "D": [ 1239 ], + "Z": [ 1235 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 39 ], + "Z": [ 1230 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1231 ], + "CLK": [ 2 ], + "DI": [ 1240 ], + "LSR": [ 47 ], + "Q": [ 1234 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1231 ], + "CLK": [ 2 ], + "DI": [ 1241 ], + "LSR": [ 47 ], + "Q": [ 1233 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1231 ], + "CLK": [ 2 ], + "DI": [ 1242 ], + "LSR": [ 47 ], + "Q": [ 1238 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1231 ], + "CLK": [ 2 ], + "DI": [ 1243 ], + "LSR": [ 47 ], + "Q": [ 1237 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1231 ], + "CLK": [ 2 ], + "DI": [ 1244 ], + "LSR": [ 47 ], + "Q": [ 1236 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1231 ], + "CLK": [ 2 ], + "DI": [ 1245 ], + "LSR": [ 47 ], + "Q": [ 1239 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 1239 ], + "B1": [ 1238 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1246 ], + "COUT": [ 1247 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1245 ], + "S1": [ 1242 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 1237 ], + "B1": [ 1236 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1247 ], + "COUT": [ 1248 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1243 ], + "S1": [ 1244 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 1234 ], + "B1": [ 1233 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 1246 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1249 ], + "S1": [ 1241 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1234 ], + "Z": [ 1240 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8", + "module": "$paramod$20e373d74dd35704a68fa9d31f078ebc648ae4d9\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "1" ], + "B1": [ "1" ], + "B10": [ "1" ], + "B11": [ "1" ], + "B12": [ "1" ], + "B13": [ "1" ], + "B14": [ "1" ], + "B15": [ "1" ], + "B16": [ "1" ], + "B17": [ "1" ], + "B2": [ "1" ], + "B3": [ "1" ], + "B4": [ "1" ], + "B5": [ "1" ], + "B6": [ "1" ], + "B7": [ "1" ], + "B8": [ "1" ], + "B9": [ "1" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 1151 ], + "P1": [ 1152 ], + "P10": [ 1176 ], + "P11": [ 1177 ], + "P12": [ 1181 ], + "P13": [ 1182 ], + "P14": [ 1186 ], + "P15": [ 1187 ], + "P16": [ 1250 ], + "P17": [ 1251 ], + "P18": [ 1252 ], + "P19": [ 1253 ], + "P2": [ 1156 ], + "P20": [ 1254 ], + "P21": [ 1255 ], + "P22": [ 1256 ], + "P23": [ 1257 ], + "P24": [ 1258 ], + "P25": [ 1259 ], + "P26": [ 1260 ], + "P27": [ 1261 ], + "P28": [ 1262 ], + "P29": [ 1263 ], + "P3": [ 1157 ], + "P30": [ 1264 ], + "P31": [ 1265 ], + "P32": [ 1266 ], + "P33": [ 1267 ], + "P34": [ 1268 ], + "P35": [ 1269 ], + "P4": [ 1161 ], + "P5": [ 1162 ], + "P6": [ 1166 ], + "P7": [ 1167 ], + "P8": [ 1171 ], + "P9": [ 1172 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "1" ], + "B1": [ "1" ], + "B10": [ "1" ], + "B11": [ "1" ], + "B12": [ "1" ], + "B13": [ "1" ], + "B14": [ "1" ], + "B15": [ "1" ], + "B16": [ "1" ], + "B17": [ "1" ], + "B2": [ "1" ], + "B3": [ "1" ], + "B4": [ "1" ], + "B5": [ "1" ], + "B6": [ "1" ], + "B7": [ "1" ], + "B8": [ "1" ], + "B9": [ "1" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 1149 ], + "P1": [ 1150 ], + "P10": [ 1174 ], + "P11": [ 1175 ], + "P12": [ 1179 ], + "P13": [ 1180 ], + "P14": [ 1184 ], + "P15": [ 1185 ], + "P16": [ 1270 ], + "P17": [ 1271 ], + "P18": [ 1272 ], + "P19": [ 1273 ], + "P2": [ 1154 ], + "P20": [ 1274 ], + "P21": [ 1275 ], + "P22": [ 1276 ], + "P23": [ 1277 ], + "P24": [ 1278 ], + "P25": [ 1279 ], + "P26": [ 1280 ], + "P27": [ 1281 ], + "P28": [ 1282 ], + "P29": [ 1283 ], + "P3": [ 1155 ], + "P30": [ 1284 ], + "P31": [ 1285 ], + "P32": [ 1286 ], + "P33": [ 1287 ], + "P34": [ 1288 ], + "P35": [ 1289 ], + "P4": [ 1159 ], + "P5": [ 1160 ], + "P6": [ 1164 ], + "P7": [ 1165 ], + "P8": [ 1169 ], + "P9": [ 1170 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "1" ], + "B1": [ "1" ], + "B10": [ "1" ], + "B11": [ "1" ], + "B12": [ "1" ], + "B13": [ "1" ], + "B14": [ "1" ], + "B15": [ "1" ], + "B16": [ "1" ], + "B17": [ "1" ], + "B2": [ "1" ], + "B3": [ "1" ], + "B4": [ "1" ], + "B5": [ "1" ], + "B6": [ "1" ], + "B7": [ "1" ], + "B8": [ "1" ], + "B9": [ "1" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 1146 ], + "P1": [ 1147 ], + "P10": [ 1206 ], + "P11": [ 1207 ], + "P12": [ 1201 ], + "P13": [ 1202 ], + "P14": [ 1197 ], + "P15": [ 1192 ], + "P16": [ 1290 ], + "P17": [ 1291 ], + "P18": [ 1292 ], + "P19": [ 1293 ], + "P2": [ 1226 ], + "P20": [ 1294 ], + "P21": [ 1295 ], + "P22": [ 1296 ], + "P23": [ 1297 ], + "P24": [ 1298 ], + "P25": [ 1299 ], + "P26": [ 1300 ], + "P27": [ 1301 ], + "P28": [ 1302 ], + "P29": [ 1303 ], + "P3": [ 1227 ], + "P30": [ 1304 ], + "P31": [ 1305 ], + "P32": [ 1306 ], + "P33": [ 1307 ], + "P34": [ 1308 ], + "P35": [ 1309 ], + "P4": [ 1221 ], + "P5": [ 1222 ], + "P6": [ 1216 ], + "P7": [ 1217 ], + "P8": [ 1211 ], + "P9": [ 1212 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "1" ], + "B1": [ "1" ], + "B10": [ "1" ], + "B11": [ "1" ], + "B12": [ "1" ], + "B13": [ "1" ], + "B14": [ "1" ], + "B15": [ "1" ], + "B16": [ "1" ], + "B17": [ "1" ], + "B2": [ "1" ], + "B3": [ "1" ], + "B4": [ "1" ], + "B5": [ "1" ], + "B6": [ "1" ], + "B7": [ "1" ], + "B8": [ "1" ], + "B9": [ "1" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 1144 ], + "P1": [ 1145 ], + "P10": [ 1204 ], + "P11": [ 1205 ], + "P12": [ 1199 ], + "P13": [ 1200 ], + "P14": [ 1196 ], + "P15": [ 1191 ], + "P16": [ 1310 ], + "P17": [ 1311 ], + "P18": [ 1312 ], + "P19": [ 1313 ], + "P2": [ 1224 ], + "P20": [ 1314 ], + "P21": [ 1315 ], + "P22": [ 1316 ], + "P23": [ 1317 ], + "P24": [ 1318 ], + "P25": [ 1319 ], + "P26": [ 1320 ], + "P27": [ 1321 ], + "P28": [ 1322 ], + "P29": [ 1323 ], + "P3": [ 1225 ], + "P30": [ 1324 ], + "P31": [ 1325 ], + "P32": [ 1326 ], + "P33": [ 1327 ], + "P34": [ 1328 ], + "P35": [ 1329 ], + "P4": [ 1219 ], + "P5": [ 1220 ], + "P6": [ 1214 ], + "P7": [ 1215 ], + "P8": [ 1209 ], + "P9": [ 1210 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1232 ], + "CLK": [ 2 ], + "DI": [ 1330 ], + "LSR": [ 3 ], + "Q": [ 21 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1232 ], + "CLK": [ 2 ], + "DI": [ 1331 ], + "LSR": [ 3 ], + "Q": [ 22 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1232 ], + "CLK": [ 2 ], + "DI": [ 1332 ], + "LSR": [ 3 ], + "Q": [ 23 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1232 ], + "CLK": [ 2 ], + "DI": [ 1333 ], + "LSR": [ 3 ], + "Q": [ 24 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1232 ], + "CLK": [ 2 ], + "DI": [ 1334 ], + "LSR": [ 3 ], + "Q": [ 25 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1232 ], + "CLK": [ 2 ], + "DI": [ 1335 ], + "LSR": [ 3 ], + "Q": [ 26 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1232 ], + "CLK": [ 2 ], + "DI": [ 1336 ], + "LSR": [ 3 ], + "Q": [ 27 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1232 ], + "CLK": [ 2 ], + "DI": [ "0" ], + "LSR": [ 3 ], + "Q": [ 28 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 973 ], + "C": [ 1337 ], + "D": [ 971 ], + "Z": [ 1331 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 975 ], + "C": [ 1337 ], + "D": [ 971 ], + "Z": [ 1332 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 977 ], + "C": [ 1337 ], + "D": [ 971 ], + "Z": [ 1333 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1029 ], + "C": [ 1337 ], + "D": [ 971 ], + "Z": [ 1330 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 979 ], + "C": [ 1337 ], + "D": [ 971 ], + "Z": [ 1334 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 981 ], + "C": [ 1337 ], + "D": [ 971 ], + "Z": [ 1335 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 983 ], + "C": [ 1337 ], + "D": [ 971 ], + "Z": [ 1336 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1027 ], + "D": [ 1338 ], + "Z": [ 1337 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1023 ], + "A1": [ 1025 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1339 ], + "COUT": [ 1338 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1340 ], + "S1": [ 1341 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1019 ], + "A1": [ 1021 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1342 ], + "COUT": [ 1339 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1343 ], + "S1": [ 1344 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 991 ], + "A1": [ 1013 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1345 ], + "COUT": [ 1342 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1346 ], + "S1": [ 1347 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 967 ], + "A1": [ 969 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1348 ], + "COUT": [ 1345 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1349 ], + "S1": [ 1350 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1015 ], + "A1": [ 1017 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1351 ], + "COUT": [ 1348 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1352 ], + "S1": [ 1353 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1009 ], + "A1": [ 1011 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1354 ], + "COUT": [ 1351 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1355 ], + "S1": [ 1356 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1005 ], + "A1": [ 1007 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1357 ], + "COUT": [ 1354 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1358 ], + "S1": [ 1359 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1001 ], + "A1": [ 1003 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1360 ], + "COUT": [ 1357 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1361 ], + "S1": [ 1362 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 997 ], + "A1": [ 999 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1363 ], + "COUT": [ 1360 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1364 ], + "S1": [ 1365 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 993 ], + "A1": [ 995 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1366 ], + "COUT": [ 1363 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1367 ], + "S1": [ 1368 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 987 ], + "A1": [ 989 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1369 ], + "COUT": [ 1366 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1370 ], + "S1": [ 1371 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 983 ], + "A1": [ 985 ], + "B0": [ "1" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1372 ], + "COUT": [ 1369 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1373 ], + "S1": [ 1374 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 979 ], + "A1": [ 981 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1375 ], + "COUT": [ 1372 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1376 ], + "S1": [ 1377 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 975 ], + "A1": [ 977 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1378 ], + "COUT": [ 1375 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1379 ], + "S1": [ 1380 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1029 ], + "A1": [ 973 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ "1" ], + "COUT": [ 1378 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1381 ], + "S1": [ 1382 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron", + "module": "$paramod$8b1cd44cf999e41637c5c45ad312808a2703769c\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1383 ], + "LSR": [ 48 ], + "Q": [ 1384 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1385 ], + "LSR": [ 48 ], + "Q": [ 1386 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1387 ], + "LSR": [ 48 ], + "Q": [ 1388 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1389 ], + "LSR": [ 48 ], + "Q": [ 1390 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1391 ], + "LSR": [ 48 ], + "Q": [ 1392 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1393 ], + "LSR": [ 48 ], + "Q": [ 1394 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1395 ], + "LSR": [ 48 ], + "Q": [ 1396 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1397 ], + "LSR": [ 48 ], + "Q": [ 1398 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1399 ], + "LSR": [ 48 ], + "Q": [ 1400 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1401 ], + "LSR": [ 48 ], + "Q": [ 1402 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1403 ], + "LSR": [ 48 ], + "Q": [ 1404 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1405 ], + "LSR": [ 48 ], + "Q": [ 1406 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1407 ], + "LSR": [ 48 ], + "Q": [ 1408 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1409 ], + "LSR": [ 48 ], + "Q": [ 1410 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1411 ], + "LSR": [ 48 ], + "Q": [ 1412 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1413 ], + "LSR": [ 48 ], + "Q": [ 1414 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1415 ], + "LSR": [ 48 ], + "Q": [ 1416 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1417 ], + "LSR": [ 48 ], + "Q": [ 1418 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1419 ], + "LSR": [ 48 ], + "Q": [ 1420 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1421 ], + "LSR": [ 48 ], + "Q": [ 1422 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1423 ], + "LSR": [ 48 ], + "Q": [ 1424 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1425 ], + "LSR": [ 48 ], + "Q": [ 1426 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_29": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1427 ], + "LSR": [ 48 ], + "Q": [ 1428 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1429 ], + "LSR": [ 48 ], + "Q": [ 1430 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_30": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1431 ], + "LSR": [ 48 ], + "Q": [ 1432 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_31": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1433 ], + "LSR": [ 48 ], + "Q": [ 1434 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1435 ], + "LSR": [ 48 ], + "Q": [ 1436 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1437 ], + "LSR": [ 48 ], + "Q": [ 1438 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1439 ], + "LSR": [ 48 ], + "Q": [ 1440 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1441 ], + "LSR": [ 48 ], + "Q": [ 1442 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1443 ], + "LSR": [ 48 ], + "Q": [ 1444 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 42 ], + "CLK": [ 2 ], + "DI": [ 1445 ], + "LSR": [ 48 ], + "Q": [ 1446 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1447 ], + "A1": [ 1448 ], + "B0": [ 1449 ], + "B1": [ 1450 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1451 ], + "COUT": [ 1452 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1417 ], + "S1": [ 1419 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1453 ], + "A1": [ 1454 ], + "B0": [ 1455 ], + "B1": [ 1456 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1452 ], + "COUT": [ 1457 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1421 ], + "S1": [ 1423 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1458 ], + "A1": [ 1459 ], + "B0": [ 1460 ], + "B1": [ 1461 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1462 ], + "COUT": [ 1463 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1409 ], + "S1": [ 1411 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1410 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1458 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1412 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1459 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1406 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1460 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1410 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1461 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1466 ], + "A1": [ 1467 ], + "B0": [ 1468 ], + "B1": [ 1469 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1470 ], + "COUT": [ 1471 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1443 ], + "S1": [ 1445 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1444 ], + "C": [ 1472 ], + "D": [ 1473 ], + "Z": [ 1466 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1446 ], + "C": [ 1474 ], + "D": [ 1475 ], + "Z": [ 1467 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1442 ], + "C": [ 1476 ], + "D": [ 1477 ], + "Z": [ 1468 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1444 ], + "C": [ 1472 ], + "D": [ 1473 ], + "Z": [ 1469 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_12": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1407 ], + "A1": [ 1478 ], + "B0": [ "0" ], + "B1": [ 1479 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 1480 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1481 ], + "S1": [ 1435 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_12_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1436 ], + "C": [ 1482 ], + "D": [ 1483 ], + "Z": [ 1478 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_12_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1408 ], + "C": [ 1484 ], + "D": [ 1485 ], + "Z": [ 1479 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1486 ], + "A1": [ 1487 ], + "B0": [ 1488 ], + "B1": [ 1489 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1480 ], + "COUT": [ 1490 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1383 ], + "S1": [ 1429 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1384 ], + "C": [ 1491 ], + "D": [ 1492 ], + "Z": [ 1486 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1430 ], + "C": [ 1493 ], + "D": [ 1494 ], + "Z": [ 1487 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1436 ], + "C": [ 1482 ], + "D": [ 1483 ], + "Z": [ 1488 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1384 ], + "C": [ 1491 ], + "D": [ 1492 ], + "Z": [ 1489 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1495 ], + "A1": [ 1496 ], + "B0": [ 1497 ], + "B1": [ 1498 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1490 ], + "COUT": [ 1499 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1385 ], + "S1": [ 1437 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1386 ], + "C": [ 1500 ], + "D": [ 1501 ], + "Z": [ 1495 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1438 ], + "C": [ 1502 ], + "D": [ 1503 ], + "Z": [ 1496 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1430 ], + "C": [ 1493 ], + "D": [ 1494 ], + "Z": [ 1497 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1386 ], + "C": [ 1500 ], + "D": [ 1501 ], + "Z": [ 1498 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1504 ], + "A1": [ 1505 ], + "B0": [ 1506 ], + "B1": [ 1507 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1499 ], + "COUT": [ 1470 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1439 ], + "S1": [ 1441 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1440 ], + "C": [ 1508 ], + "D": [ 1509 ], + "Z": [ 1504 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1442 ], + "C": [ 1476 ], + "D": [ 1477 ], + "Z": [ 1505 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1438 ], + "C": [ 1502 ], + "D": [ 1503 ], + "Z": [ 1506 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1440 ], + "C": [ 1508 ], + "D": [ 1509 ], + "Z": [ 1507 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1422 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1453 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1424 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1454 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1420 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1455 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1422 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1456 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1510 ], + "A1": [ 1511 ], + "B0": [ 1512 ], + "B1": [ 1513 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1457 ], + "COUT": [ 1514 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1425 ], + "S1": [ 1427 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1426 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1510 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1428 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1511 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1424 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1512 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1426 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1513 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1515 ], + "A1": [ 1516 ], + "B0": [ 1517 ], + "B1": [ 1518 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1519 ], + "COUT": [ 1520 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1391 ], + "S1": [ 1393 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1392 ], + "C": [ 1521 ], + "D": [ 1522 ], + "Z": [ 1515 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1394 ], + "C": [ 1523 ], + "D": [ 1524 ], + "Z": [ 1516 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1390 ], + "C": [ 1525 ], + "D": [ 1526 ], + "Z": [ 1517 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1392 ], + "C": [ 1521 ], + "D": [ 1522 ], + "Z": [ 1518 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1527 ], + "A1": [ 1528 ], + "B0": [ 1529 ], + "B1": [ 1530 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1520 ], + "COUT": [ 1531 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1395 ], + "S1": [ 1397 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1396 ], + "C": [ 1532 ], + "D": [ 1533 ], + "Z": [ 1527 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1398 ], + "C": [ 1534 ], + "D": [ 1535 ], + "Z": [ 1528 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1394 ], + "C": [ 1523 ], + "D": [ 1524 ], + "Z": [ 1529 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1396 ], + "C": [ 1532 ], + "D": [ 1533 ], + "Z": [ 1530 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1536 ], + "A1": [ 1537 ], + "B0": [ 1538 ], + "B1": [ 1539 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1514 ], + "COUT": [ 1540 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1431 ], + "S1": [ 1433 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1432 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1536 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1434 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1537 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1428 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1538 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1432 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1539 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1541 ], + "A1": [ 1542 ], + "B0": [ 1543 ], + "B1": [ 1544 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1463 ], + "COUT": [ 1451 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1413 ], + "S1": [ 1415 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1414 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1541 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1416 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1542 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1412 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1543 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1414 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1544 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1545 ], + "A1": [ 1546 ], + "B0": [ 1547 ], + "B1": [ 1548 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1471 ], + "COUT": [ 1519 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1387 ], + "S1": [ 1389 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1388 ], + "C": [ 1549 ], + "D": [ 1550 ], + "Z": [ 1545 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1390 ], + "C": [ 1525 ], + "D": [ 1526 ], + "Z": [ 1546 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1446 ], + "C": [ 1474 ], + "D": [ 1475 ], + "Z": [ 1547 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1388 ], + "C": [ 1549 ], + "D": [ 1550 ], + "Z": [ 1548 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1551 ], + "A1": [ 1552 ], + "B0": [ 1553 ], + "B1": [ 1554 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1531 ], + "COUT": [ 1555 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1399 ], + "S1": [ 1401 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1400 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1551 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1402 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1552 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1398 ], + "C": [ 1534 ], + "D": [ 1535 ], + "Z": [ 1553 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1400 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1554 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1556 ], + "A1": [ 1557 ], + "B0": [ 1558 ], + "B1": [ 1559 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1555 ], + "COUT": [ 1462 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1403 ], + "S1": [ 1405 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1404 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1556 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1406 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1557 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1402 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1558 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1404 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1559 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_A0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1418 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1447 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_A1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1420 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1448 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_B0_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1416 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1449 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_B1_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111110011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1418 ], + "C": [ 1464 ], + "D": [ 1465 ], + "Z": [ 1450 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1408 ], + "C": [ 1484 ], + "D": [ 1485 ], + "Z": [ 1407 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1560 ], + "A1": [ 1561 ], + "B0": [ 1562 ], + "B1": [ 1563 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 1564 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1485 ], + "S1": [ 1483 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1565 ], + "A1": [ 1566 ], + "B0": [ 1567 ], + "B1": [ 1568 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 1569 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1484 ], + "S1": [ 1482 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1570 ], + "A1": [ 1571 ], + "B0": [ 1572 ], + "B1": [ 1573 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1564 ], + "COUT": [ 1574 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1492 ], + "S1": [ 1494 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1575 ], + "A1": [ 1576 ], + "B0": [ 1577 ], + "B1": [ 1578 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1574 ], + "COUT": [ 1579 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1501 ], + "S1": [ 1503 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1580 ], + "A1": [ 1581 ], + "B0": [ 1582 ], + "B1": [ 1583 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1579 ], + "COUT": [ 1584 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1509 ], + "S1": [ 1477 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1585 ], + "A1": [ 1586 ], + "B0": [ 1587 ], + "B1": [ 1588 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1584 ], + "COUT": [ 1589 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1473 ], + "S1": [ 1475 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1590 ], + "A1": [ 1591 ], + "B0": [ 1592 ], + "B1": [ 1593 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1589 ], + "COUT": [ 1594 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1550 ], + "S1": [ 1526 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1595 ], + "A1": [ 1596 ], + "B0": [ 1597 ], + "B1": [ 1598 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1594 ], + "COUT": [ 1599 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1522 ], + "S1": [ 1524 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1600 ], + "A1": [ 1601 ], + "B0": [ 1602 ], + "B1": [ 1603 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1599 ], + "COUT": [ 1604 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1533 ], + "S1": [ 1535 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1601 ], + "A1": [ "0" ], + "B0": [ 1603 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1604 ], + "COUT": [ 1605 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1465 ], + "S1": [ 1606 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1607 ], + "A1": [ "0" ], + "B0": [ 1608 ], + "B1": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1609 ], + "COUT": [ 1610 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1464 ], + "S1": [ 1611 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1612 ], + "A1": [ 1607 ], + "B0": [ 1613 ], + "B1": [ 1608 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1614 ], + "COUT": [ 1609 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1532 ], + "S1": [ 1534 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1615 ], + "A1": [ 1616 ], + "B0": [ 1617 ], + "B1": [ 1618 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1619 ], + "COUT": [ 1614 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1521 ], + "S1": [ 1523 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1620 ], + "A1": [ 1621 ], + "B0": [ 1622 ], + "B1": [ 1623 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1624 ], + "COUT": [ 1619 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1549 ], + "S1": [ 1525 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1625 ], + "A1": [ 1626 ], + "B0": [ 1627 ], + "B1": [ 1628 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1629 ], + "COUT": [ 1624 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1472 ], + "S1": [ 1474 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1630 ], + "A1": [ 1631 ], + "B0": [ 1632 ], + "B1": [ 1633 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1634 ], + "COUT": [ 1629 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1508 ], + "S1": [ 1476 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1635 ], + "A1": [ 1636 ], + "B0": [ 1637 ], + "B1": [ 1638 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1639 ], + "COUT": [ 1634 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1500 ], + "S1": [ 1502 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1640 ], + "A1": [ 1641 ], + "B0": [ 1642 ], + "B1": [ 1643 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1569 ], + "COUT": [ 1639 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1491 ], + "S1": [ 1493 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1644 ], + "LSR": [ 3 ], + "Q": [ 42 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 42 ], + "D": [ 1645 ], + "Z": [ 1644 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1646 ], + "LSR": [ 1647 ], + "Q": [ 45 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 42 ], + "D": [ 1646 ], + "Z": [ 1648 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 42 ], + "D": [ 1646 ], + "Z": [ 1645 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1649 ], + "C": [ 1650 ], + "D": [ 1651 ], + "Z": [ 1646 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1652 ], + "B": [ 1653 ], + "C": [ 1654 ], + "D": [ 1655 ], + "Z": [ 1651 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 42 ], + "Z": [ 1647 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1645 ], + "CLK": [ 2 ], + "DI": [ 1656 ], + "LSR": [ 48 ], + "Q": [ 1650 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1645 ], + "CLK": [ 2 ], + "DI": [ 1657 ], + "LSR": [ 48 ], + "Q": [ 1649 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1645 ], + "CLK": [ 2 ], + "DI": [ 1658 ], + "LSR": [ 48 ], + "Q": [ 1655 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1645 ], + "CLK": [ 2 ], + "DI": [ 1659 ], + "LSR": [ 48 ], + "Q": [ 1654 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1645 ], + "CLK": [ 2 ], + "DI": [ 1660 ], + "LSR": [ 48 ], + "Q": [ 1653 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1645 ], + "CLK": [ 2 ], + "DI": [ 1661 ], + "LSR": [ 48 ], + "Q": [ 1652 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "B0": [ 1650 ], + "B1": [ 1649 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ "0" ], + "COUT": [ 1662 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1663 ], + "S1": [ 1657 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 1655 ], + "B1": [ 1654 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1662 ], + "COUT": [ 1664 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1658 ], + "S1": [ 1659 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_2": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ "0" ], + "A1": [ "0" ], + "B0": [ 1653 ], + "B1": [ 1652 ], + "C0": [ "0" ], + "C1": [ "0" ], + "CIN": [ 1664 ], + "COUT": [ 1665 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1660 ], + "S1": [ 1661 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1650 ], + "Z": [ 1656 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8", + "module": "$paramod$20e373d74dd35704a68fa9d31f078ebc648ae4d9\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ 1666 ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 1562 ], + "P1": [ 1563 ], + "P10": [ 1592 ], + "P11": [ 1593 ], + "P12": [ 1597 ], + "P13": [ 1598 ], + "P14": [ 1602 ], + "P15": [ 1603 ], + "P16": [ 1667 ], + "P17": [ 1668 ], + "P18": [ 1669 ], + "P19": [ 1670 ], + "P2": [ 1572 ], + "P20": [ 1671 ], + "P21": [ 1672 ], + "P22": [ 1673 ], + "P23": [ 1674 ], + "P24": [ 1675 ], + "P25": [ 1676 ], + "P26": [ 1677 ], + "P27": [ 1678 ], + "P28": [ 1679 ], + "P29": [ 1680 ], + "P3": [ 1573 ], + "P30": [ 1681 ], + "P31": [ 1682 ], + "P32": [ 1683 ], + "P33": [ 1684 ], + "P34": [ 1685 ], + "P35": [ 1686 ], + "P4": [ 1577 ], + "P5": [ 1578 ], + "P6": [ 1582 ], + "P7": [ 1583 ], + "P8": [ 1587 ], + "P9": [ 1588 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ 1666 ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 1560 ], + "P1": [ 1561 ], + "P10": [ 1590 ], + "P11": [ 1591 ], + "P12": [ 1595 ], + "P13": [ 1596 ], + "P14": [ 1600 ], + "P15": [ 1601 ], + "P16": [ 1687 ], + "P17": [ 1688 ], + "P18": [ 1689 ], + "P19": [ 1690 ], + "P2": [ 1570 ], + "P20": [ 1691 ], + "P21": [ 1692 ], + "P22": [ 1693 ], + "P23": [ 1694 ], + "P24": [ 1695 ], + "P25": [ 1696 ], + "P26": [ 1697 ], + "P27": [ 1698 ], + "P28": [ 1699 ], + "P29": [ 1700 ], + "P3": [ 1571 ], + "P30": [ 1701 ], + "P31": [ 1702 ], + "P32": [ 1703 ], + "P33": [ 1704 ], + "P34": [ 1705 ], + "P35": [ 1706 ], + "P4": [ 1575 ], + "P5": [ 1576 ], + "P6": [ 1580 ], + "P7": [ 1581 ], + "P8": [ 1585 ], + "P9": [ 1586 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ 1666 ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 1567 ], + "P1": [ 1568 ], + "P10": [ 1622 ], + "P11": [ 1623 ], + "P12": [ 1617 ], + "P13": [ 1618 ], + "P14": [ 1613 ], + "P15": [ 1608 ], + "P16": [ 1707 ], + "P17": [ 1708 ], + "P18": [ 1709 ], + "P19": [ 1710 ], + "P2": [ 1642 ], + "P20": [ 1711 ], + "P21": [ 1712 ], + "P22": [ 1713 ], + "P23": [ 1714 ], + "P24": [ 1715 ], + "P25": [ 1716 ], + "P26": [ 1717 ], + "P27": [ 1718 ], + "P28": [ 1719 ], + "P29": [ 1720 ], + "P3": [ 1643 ], + "P30": [ 1721 ], + "P31": [ 1722 ], + "P32": [ 1723 ], + "P33": [ 1724 ], + "P34": [ 1725 ], + "P35": [ 1726 ], + "P4": [ 1637 ], + "P5": [ 1638 ], + "P6": [ 1632 ], + "P7": [ 1633 ], + "P8": [ 1627 ], + "P9": [ 1628 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_MULT18X18D_P9": { + "hide_name": 0, + "type": "MULT18X18D", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:9.13-16.3" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "A10": "input", + "A11": "input", + "A12": "input", + "A13": "input", + "A14": "input", + "A15": "input", + "A16": "input", + "A17": "input", + "A2": "input", + "A3": "input", + "A4": "input", + "A5": "input", + "A6": "input", + "A7": "input", + "A8": "input", + "A9": "input", + "B0": "input", + "B1": "input", + "B10": "input", + "B11": "input", + "B12": "input", + "B13": "input", + "B14": "input", + "B15": "input", + "B16": "input", + "B17": "input", + "B2": "input", + "B3": "input", + "B4": "input", + "B5": "input", + "B6": "input", + "B7": "input", + "B8": "input", + "B9": "input", + "C0": "input", + "C1": "input", + "C10": "input", + "C11": "input", + "C12": "input", + "C13": "input", + "C14": "input", + "C15": "input", + "C16": "input", + "C17": "input", + "C2": "input", + "C3": "input", + "C4": "input", + "C5": "input", + "C6": "input", + "C7": "input", + "C8": "input", + "C9": "input", + "P0": "output", + "P1": "output", + "P10": "output", + "P11": "output", + "P12": "output", + "P13": "output", + "P14": "output", + "P15": "output", + "P16": "output", + "P17": "output", + "P18": "output", + "P19": "output", + "P2": "output", + "P20": "output", + "P21": "output", + "P22": "output", + "P23": "output", + "P24": "output", + "P25": "output", + "P26": "output", + "P27": "output", + "P28": "output", + "P29": "output", + "P3": "output", + "P30": "output", + "P31": "output", + "P32": "output", + "P33": "output", + "P34": "output", + "P35": "output", + "P4": "output", + "P5": "output", + "P6": "output", + "P7": "output", + "P8": "output", + "P9": "output", + "SIGNEDA": "input", + "SIGNEDB": "input", + "SOURCEA": "input", + "SOURCEB": "input" + }, + "connections": { + "A0": [ "1" ], + "A1": [ "0" ], + "A10": [ "0" ], + "A11": [ "0" ], + "A12": [ "0" ], + "A13": [ "0" ], + "A14": [ "0" ], + "A15": [ "0" ], + "A16": [ "0" ], + "A17": [ "0" ], + "A2": [ "0" ], + "A3": [ "0" ], + "A4": [ "0" ], + "A5": [ "0" ], + "A6": [ "0" ], + "A7": [ "0" ], + "A8": [ "0" ], + "A9": [ "0" ], + "B0": [ "0" ], + "B1": [ "0" ], + "B10": [ "0" ], + "B11": [ "0" ], + "B12": [ "0" ], + "B13": [ "0" ], + "B14": [ "0" ], + "B15": [ "0" ], + "B16": [ "0" ], + "B17": [ "0" ], + "B2": [ 1666 ], + "B3": [ "0" ], + "B4": [ "0" ], + "B5": [ "0" ], + "B6": [ "0" ], + "B7": [ "0" ], + "B8": [ "0" ], + "B9": [ "0" ], + "C0": [ "0" ], + "C1": [ "0" ], + "C10": [ "0" ], + "C11": [ "0" ], + "C12": [ "0" ], + "C13": [ "0" ], + "C14": [ "0" ], + "C15": [ "0" ], + "C16": [ "0" ], + "C17": [ "0" ], + "C2": [ "0" ], + "C3": [ "0" ], + "C4": [ "0" ], + "C5": [ "0" ], + "C6": [ "0" ], + "C7": [ "0" ], + "C8": [ "0" ], + "C9": [ "0" ], + "P0": [ 1565 ], + "P1": [ 1566 ], + "P10": [ 1620 ], + "P11": [ 1621 ], + "P12": [ 1615 ], + "P13": [ 1616 ], + "P14": [ 1612 ], + "P15": [ 1607 ], + "P16": [ 1727 ], + "P17": [ 1728 ], + "P18": [ 1729 ], + "P19": [ 1730 ], + "P2": [ 1640 ], + "P20": [ 1731 ], + "P21": [ 1732 ], + "P22": [ 1733 ], + "P23": [ 1734 ], + "P24": [ 1735 ], + "P25": [ 1736 ], + "P26": [ 1737 ], + "P27": [ 1738 ], + "P28": [ 1739 ], + "P29": [ 1740 ], + "P3": [ 1641 ], + "P30": [ 1741 ], + "P31": [ 1742 ], + "P32": [ 1743 ], + "P33": [ 1744 ], + "P34": [ 1745 ], + "P35": [ 1746 ], + "P4": [ 1635 ], + "P5": [ 1636 ], + "P6": [ 1630 ], + "P7": [ 1631 ], + "P8": [ 1625 ], + "P9": [ 1626 ], + "SIGNEDA": [ "1" ], + "SIGNEDB": [ "1" ], + "SOURCEA": [ "0" ], + "SOURCEB": [ "0" ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1747 ], + "LSR": [ 1748 ], + "Q": [ 1666 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100111111011101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1654 ], + "B": [ 48 ], + "C": [ 1659 ], + "D": [ 1645 ], + "Z": [ 1747 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1110000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1660 ], + "B": [ 1661 ], + "C": [ 1749 ], + "D": [ 1645 ], + "Z": [ 1748 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_C_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1652 ], + "B": [ 1653 ], + "C": [ 42 ], + "D": [ 48 ], + "Z": [ 1749 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1648 ], + "CLK": [ 2 ], + "DI": [ 1750 ], + "LSR": [ 3 ], + "Q": [ 29 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1648 ], + "CLK": [ 2 ], + "DI": [ 1751 ], + "LSR": [ 3 ], + "Q": [ 33 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1648 ], + "CLK": [ 2 ], + "DI": [ 1752 ], + "LSR": [ 3 ], + "Q": [ 34 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1648 ], + "CLK": [ 2 ], + "DI": [ 1753 ], + "LSR": [ 3 ], + "Q": [ 35 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1648 ], + "CLK": [ 2 ], + "DI": [ "0" ], + "LSR": [ 3 ], + "Q": [ 36 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1648 ], + "CLK": [ 2 ], + "DI": [ 1754 ], + "LSR": [ 3 ], + "Q": [ 30 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1648 ], + "CLK": [ 2 ], + "DI": [ 1755 ], + "LSR": [ 3 ], + "Q": [ 31 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1648 ], + "CLK": [ 2 ], + "DI": [ 1756 ], + "LSR": [ 3 ], + "Q": [ 32 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1435 ], + "C": [ 1757 ], + "D": [ 1433 ], + "Z": [ 1754 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1383 ], + "C": [ 1757 ], + "D": [ 1433 ], + "Z": [ 1755 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1429 ], + "C": [ 1757 ], + "D": [ 1433 ], + "Z": [ 1756 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1385 ], + "C": [ 1757 ], + "D": [ 1433 ], + "Z": [ 1751 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1437 ], + "C": [ 1757 ], + "D": [ 1433 ], + "Z": [ 1752 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1439 ], + "C": [ 1757 ], + "D": [ 1433 ], + "Z": [ 1753 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1407 ], + "C": [ 1757 ], + "D": [ 1433 ], + "Z": [ 1750 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1431 ], + "D": [ 1758 ], + "Z": [ 1757 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1425 ], + "A1": [ 1427 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1759 ], + "COUT": [ 1758 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1760 ], + "S1": [ 1761 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1421 ], + "A1": [ 1423 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1762 ], + "COUT": [ 1759 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1763 ], + "S1": [ 1764 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1417 ], + "A1": [ 1419 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1765 ], + "COUT": [ 1762 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1766 ], + "S1": [ 1767 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1413 ], + "A1": [ 1415 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1768 ], + "COUT": [ 1765 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1769 ], + "S1": [ 1770 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1409 ], + "A1": [ 1411 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1771 ], + "COUT": [ 1768 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1772 ], + "S1": [ 1773 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1403 ], + "A1": [ 1405 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1774 ], + "COUT": [ 1771 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1775 ], + "S1": [ 1776 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1399 ], + "A1": [ 1401 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1777 ], + "COUT": [ 1774 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1778 ], + "S1": [ 1779 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1395 ], + "A1": [ 1397 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1780 ], + "COUT": [ 1777 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1781 ], + "S1": [ 1782 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1391 ], + "A1": [ 1393 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1783 ], + "COUT": [ 1780 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1784 ], + "S1": [ 1785 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1387 ], + "A1": [ 1389 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1786 ], + "COUT": [ 1783 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1787 ], + "S1": [ 1788 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1443 ], + "A1": [ 1445 ], + "B0": [ "0" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1789 ], + "COUT": [ 1786 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1790 ], + "S1": [ 1791 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1439 ], + "A1": [ 1441 ], + "B0": [ "1" ], + "B1": [ "0" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1792 ], + "COUT": [ 1789 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1793 ], + "S1": [ 1794 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1385 ], + "A1": [ 1437 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1795 ], + "COUT": [ 1792 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1796 ], + "S1": [ 1797 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1383 ], + "A1": [ 1429 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ 1798 ], + "COUT": [ 1795 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1799 ], + "S1": [ 1800 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT": { + "hide_name": 0, + "type": "CCU2C", + "parameters": { + "INIT0": "1001011010101010", + "INIT1": "1001011010101010", + "INJECT1_0": "NO", + "INJECT1_1": "NO" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4" + }, + "port_directions": { + "A0": "input", + "A1": "input", + "B0": "input", + "B1": "input", + "C0": "input", + "C1": "input", + "CIN": "input", + "COUT": "output", + "D0": "input", + "D1": "input", + "S0": "output", + "S1": "output" + }, + "connections": { + "A0": [ 1407 ], + "A1": [ 1435 ], + "B0": [ "1" ], + "B1": [ "1" ], + "C0": [ "1" ], + "C1": [ "1" ], + "CIN": [ "1" ], + "COUT": [ 1798 ], + "D0": [ "1" ], + "D1": [ "1" ], + "S0": [ 1801 ], + "S1": [ 1802 ] + } + } + }, + "netnames": { + "bias_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:19.43-19.51" + } + }, + "busy": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:7.12-7.16" + } + }, + "clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:2.11-2.14" + } + }, + "done": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:8.12-8.16" + } + }, + "i": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:21.13-21.14" + } + }, + "rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:3.11-3.14" + } + }, + "start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:4.11-4.16" + } + }, + "start_LUT4_B_1_Z": { + "hide_name": 0, + "bits": [ 1654, 48, 1659, 1645 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "start_LUT4_B_2_Z": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + } + }, + "start_LUT4_B_Z": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc": { + "hide_name": 0, + "bits": [ 102, 72, 52, 54, 76, 98, 104, 106, 108, 110, 112, 114, 56, 58, 60, 62, 64, 66, 68, 70, 74, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 100 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ 101, 71, 50, 53, 75, 97, 103, 105, 107, 109, 111, 113, 55, 57, 59, 61, 63, 65, 67, 69, 73, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 99 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_A0": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_A1": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_B0": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_B1": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_COUT": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_A0": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_A1": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_B0": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_B1": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_11_COUT": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_A0": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_A1": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_B0": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_B1": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_COUT": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A1": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_B0": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_B1": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_COUT": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_A0": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_A1": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_B0": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_B1": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_COUT": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_A0": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_A1": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_B0": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_B1": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_15_COUT": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_A0": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_A1": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_B0": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_B1": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_A0": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_A1": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_B0": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_B1": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_A0": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_A1": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_B0": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_B1": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3_COUT": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_A0": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_A1": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_B0": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_B1": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_4_COUT": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_A0": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_A1": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_B0": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_B1": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_5_COUT": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_6_A1": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_6_B1": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_6_COUT": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_6_S0": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_A0": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_A1": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_B0": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_B1": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_7_COUT": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_A0": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_A1": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B0": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_B1": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_8_COUT": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_A0": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_A1": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_B0": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_B1": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_9_COUT": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_A0": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_A1": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_B0": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_B1": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 102, 209, 210 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT": { + "hide_name": 0, + "bits": [ 237 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 242 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 247 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 252 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 257 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 262 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 267 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 272 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 273 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 64, 181, 182 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 278 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 279 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 274 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 60, 169, 170 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 62, 171, 172 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 277 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 56, 226, 227 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 58, 173, 174 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 282 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 112, 132, 133 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 114, 134, 135 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 287 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 108, 155, 156 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 110, 136, 137 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 292 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 104, 163, 164 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 106, 157, 158 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 297 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 76, 144, 145 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 98, 146, 147 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 302 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 52, 215, 216 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 54, 148, 149 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 307 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 72, 207, 208 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 312 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 41, 314 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z": { + "hide_name": 0, + "bits": [ 322, 51, 327, 313 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 316 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 317, 318, 319 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 315 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ 101, 71, 50, 53, 75, 97, 103, 105, 107, 109, 111, 113, 55, 57, 59, 61, 63, 65, 67, 69, 73, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 99 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 318, 317, 323, 322, 321, 320 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 324, 325, 326, 327, 328, 329 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:34.26-34.27" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 332 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1_S0": { + "hide_name": 0, + "bits": [ 333 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 330 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 331 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 235, 236, 310, 311, 305, 306, 300, 301, 295, 296, 290, 291, 285, 286, 281, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ 235, 236, 310, 311, 305, 306, 300, 301, 295, 296, 290, 291, 285, 286, 281, 276 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1803, 1804, 1805, 1806, 1807, 1808, 1809, 1810, 1811, 1812, 1813, 1814, 1815, 1816, 1817, 1818, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 235, 236, 310, 311, 305, 306, 300, 301, 295, 296, 290, 291, 285, 286, 281, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ 334, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 233, 234, 308, 309, 303, 304, 298, 299, 293, 294, 288, 289, 283, 284, 280, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ 233, 234, 308, 309, 303, 304, 298, 299, 293, 294, 288, 289, 283, 284, 280, 275 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1819, 1820, 1821, 1822, 1823, 1824, 1825, 1826, 1827, 1828, 1829, 1830, 1831, 1832, 1833, 1834, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 233, 234, 308, 309, 303, 304, 298, 299, 293, 294, 288, 289, 283, 284, 280, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ 334, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 230, 231, 240, 241, 245, 246, 250, 251, 255, 256, 260, 261, 265, 266, 270, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.product": { + "hide_name": 0, + "bits": [ 230, 231, 240, 241, 245, 246, 250, 251, 255, 256, 260, 261, 265, 266, 270, 271 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1835, 1836, 1837, 1838, 1839, 1840, 1841, 1842, 1843, 1844, 1845, 1846, 1847, 1848, 1849, 1850, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 230, 231, 240, 241, 245, 246, 250, 251, 255, 256, 260, 261, 265, 266, 270, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.w": { + "hide_name": 0, + "bits": [ 334, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 228, 229, 238, 239, 243, 244, 248, 249, 253, 254, 258, 259, 263, 264, 268, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.product": { + "hide_name": 0, + "bits": [ 228, 229, 238, 239, 243, 244, 248, 249, 253, 254, 258, 259, 263, 264, 268, 269 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1851, 1852, 1853, 1854, 1855, 1856, 1857, 1858, 1859, 1860, 1861, 1862, 1863, 1864, 1865, 1866, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 228, 229, 238, 239, 243, 244, 248, 249, 253, 254, 258, 259, 263, 264, 268, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.w": { + "hide_name": 0, + "bits": [ 334, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ 102, 72, 52, 54, 76, 98, 104, 106, 108, 110, 112, 114, 56, 58, 60, 62, 64, 66, 68, 70, 74, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 100 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ 101, 71, 50, 53, 75, 97, 103, 105, 107, 109, 111, 113, 55, 57, 59, 61, 63, 65, 67, 69, 73, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 99 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ 235, 236, 310, 311, 305, 306, 300, 301, 295, 296, 290, 291, 285, 286, 281, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ 233, 234, 308, 309, 303, 304, 298, 299, 293, 294, 288, 289, 283, 284, 280, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[2]": { + "hide_name": 0, + "bits": [ 230, 231, 240, 241, 245, 246, 250, 251, 255, 256, 260, 261, 265, 266, 270, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[3]": { + "hide_name": 0, + "bits": [ 228, 229, 238, 239, 243, 244, 248, 249, 253, 254, 258, 259, 263, 264, 268, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ 235, 236, 310, 311, 305, 306, 300, 301, 295, 296, 290, 291, 285, 286, 281, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276, 276 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ 233, 234, 308, 309, 303, 304, 298, 299, 293, 294, 288, 289, 283, 284, 280, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275, 275 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ 230, 231, 240, 241, 245, 246, 250, 251, 255, 256, 260, 261, 265, 266, 270, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271, 271 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[3]": { + "hide_name": 0, + "bits": [ 228, 229, 238, 239, 243, 244, 248, 249, 253, 254, 258, 259, 263, 264, 268, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269, 269 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[4]": { + "hide_name": 0, + "bits": [ 1867, 1868, 1869, 1870, 1871, 1872, 1873, 1874, 1875, 1876, 1877, 1878, 1879, 1880, 1881, 1882, 1883, 1883, 1883, 1883, 1883, 1883, 1883, 1883, 1883, 1883, 1883, 1883, 1883, 1883, 1883, 1883 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[5]": { + "hide_name": 0, + "bits": [ 1884, 1885, 1886, 1887, 1888, 1889, 1890, 1891, 1892, 1893, 1894, 1895, 1896, 1897, 1898, 1899, 1900, 1900, 1900, 1900, 1900, 1900, 1900, 1900, 1900, 1900, 1900, 1900, 1900, 1900, 1900, 1900 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ 334, "0", "0", "0", "0", "0", "0", "0", 334, "0", "0", "0", "0", "0", "0", "0", 334, "0", "0", "0", "0", "0", "0", "0", 334, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 415 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 416 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 328, 329, 417, 313 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.w_group": { + "hide_name": 0, + "bits": [ 334, "0", "0", "0", "0", "0", "0", "0", 334, "0", "0", "0", "0", "0", "0", "0", 334, "0", "0", "0", "0", "0", "0", "0", 334, "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y": { + "hide_name": 0, + "bits": [ 5, 6, 7, 8, 9, 10, 11, 12 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 418, 419, 420, 421, 422, 423, 424, "0" ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 71, 425, 99 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 426 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 427 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 430 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 433 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 436 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 439 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 442 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 445 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 448 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 451 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 454 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 457 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 460 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 463 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 466 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 469 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 470 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 467 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 468 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 464 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 465 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 461 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 462 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 458 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 459 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 455 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 456 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 452 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 453 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 449 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 450 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 446 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 447 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 443 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 444 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 440 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 441 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 437 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 438 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 434 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 435 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 431 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 432 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 428 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 429 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc": { + "hide_name": 0, + "bits": [ 472, 474, 496, 518, 524, 526, 528, 530, 532, 534, 476, 478, 480, 482, 484, 486, 488, 490, 492, 494, 498, 500, 502, 504, 506, 508, 510, 512, 514, 516, 520, 522 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ 471, 1901, 1902, 1903, 1904, 1905, 1906, 1907, 1908, 1909, 1910, 1911, 1912, 1913, 1914, 1915, 1916, 1917, 1918, 1919, 1920, 1921, 1922, 1923, 1924, 1925, 1926, 1927, 1928, 1929, 1930, 1931 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41", + "unused_bits": "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_A1": { + "hide_name": 0, + "bits": [ 539 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_B1": { + "hide_name": 0, + "bits": [ 540 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT": { + "hide_name": 0, + "bits": [ 541 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_A0": { + "hide_name": 0, + "bits": [ 548 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_A1": { + "hide_name": 0, + "bits": [ 549 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_B0": { + "hide_name": 0, + "bits": [ 550 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_B1": { + "hide_name": 0, + "bits": [ 551 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 552 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 565, 553, 561 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S0_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 559 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S0_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 560 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S0_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 562, 563, 564 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 565, 554, 572 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 571 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 570, 573 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 574 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 575 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 576 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 577 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 578 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 579, 586 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 585 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 584, 587 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 588 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 589 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 590 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 591 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 592 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 593, 600 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 599 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 598, 601 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 602 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 603 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 604 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 605 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 606 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 607, 614 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 613 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 612, 615 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 616 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 617 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 618 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 619 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 620 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 621, 628 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 627 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 626, 629 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 630 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 631 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 632 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 633 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 634 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 635, 642 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 641 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 640, 643 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 644 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 645 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 646 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 647 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 648 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 649, 656 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 655 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 654, 657 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 658 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 659 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 660 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 661 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 662 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 663, 668 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 667 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 666, 669 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 670 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 671 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 672 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 673 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 674 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 675, 678 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 677 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 676, 679 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 680 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 681 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 682 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 683 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 684 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 685, 688 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 687 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 686, 689 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 690 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 691 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 692 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 693 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 694 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 695, 698 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 697 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 696, 699 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 700 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 701 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 702 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 703 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 704 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 705, 708 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 707 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 706, 709 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 710 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 711 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 712 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 713 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 714 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 715, 718 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 717 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 716, 719 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 720 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 721 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 722 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 723 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 724 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 725, 728 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 727 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 726, 729 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A0": { + "hide_name": 0, + "bits": [ 730 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_A1": { + "hide_name": 0, + "bits": [ 731 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B0": { + "hide_name": 0, + "bits": [ 732 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_B1": { + "hide_name": 0, + "bits": [ 733 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 734 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 565, 735, 737 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 736 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.24-93.43|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_COUT_CCU2C_CIN_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 738 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S0": { + "hide_name": 0, + "bits": [ 542 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1": { + "hide_name": 0, + "bits": [ 543 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "single_bit_vector": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_1_S1_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 473, 495, 517, 523, 525, 527, 529, 531, 533, 475, 477, 479, 481, 483, 485, 487, 489, 491, 493, 497, 499, 501, 503, 505, 507, 509, 511, 513, 515, 519, 521 ], + "offset": 1, + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_A1": { + "hide_name": 0, + "bits": [ 535 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT": { + "hide_name": 0, + "bits": [ 536 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 739 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 742 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 745 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 748 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 751 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 754 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 757 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 760 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 763 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 766 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 769 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 772 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 775 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 778 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 471, 781, 737 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 779 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 780 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 776 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 777 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 773 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 774 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 770 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 771 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 767 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 768 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 764 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 765 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 761 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 762 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 758 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 759 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 755 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 756 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 752 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 753 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 749 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 750 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 746 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 747 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 743 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 744 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 740 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 741 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_S0": { + "hide_name": 0, + "bits": [ 537 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_CCU2C_A0_S1": { + "hide_name": 0, + "bits": [ 538 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_B_Z": { + "hide_name": 0, + "bits": [ 782, 783, 784, 785, 786, 787, 788, "0" ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 472, 546, 547 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT": { + "hide_name": 0, + "bits": [ 798 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 803 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 808 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 813 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 818 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 823 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 828 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 833 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 834 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 488, 664, 665 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 839 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 840 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 835 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 484, 650, 651 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 486, 652, 653 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 838 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 480, 636, 637 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 482, 638, 639 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 843 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 476, 622, 623 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 478, 624, 625 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 848 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 532, 608, 609 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 534, 610, 611 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 853 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 528, 594, 595 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 530, 596, 597 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 858 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 524, 580, 581 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 526, 582, 583 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 863 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 496, 555, 556 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 518, 557, 558 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 868 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 793 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 474, 544, 545 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "1", "0", "1", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 873 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 874 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ 471, 1932, 1933, 1934, 1935, 1936, 1937, 1938, 1939, 1940, 1941, 1942, 1943, 1944, 1945, 1946, 1947, 1948, 1949, 1950, 1951, 1952, 1953, 1954, 1955, 1956, 1957, 1958, 1959, 1960, 1961, 1962 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42", + "unused_bits": "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 563, 562, 569, 568, 567, 566 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_CE": { + "hide_name": 0, + "bits": [ 875 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 876, 877, 878, 879, 880, 881 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:34.26-34.27" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 882 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1_S0": { + "hide_name": 0, + "bits": [ 884 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 885 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 883 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 791, 792, 871, 872, 866, 867, 861, 862, 856, 857, 851, 852, 846, 847, 842, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ 791, 792, 871, 872, 866, 867, 861, 862, 856, 857, 851, 852, 846, 847, 842, 837 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1963, 1964, 1965, 1966, 1967, 1968, 1969, 1970, 1971, 1972, 1973, 1974, 1975, 1976, 1977, 1978, 886, 887, 888, 889, 890, 891, 892, 893, 894, 895, 896, 897, 898, 899, 900, 901, 902, 903, 904, 905 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 791, 792, 871, 872, 866, 867, 861, 862, 856, 857, 851, 852, 846, 847, 842, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 789, 790, 869, 870, 864, 865, 859, 860, 854, 855, 849, 850, 844, 845, 841, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ 789, 790, 869, 870, 864, 865, 859, 860, 854, 855, 849, 850, 844, 845, 841, 836 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1979, 1980, 1981, 1982, 1983, 1984, 1985, 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 906, 907, 908, 909, 910, 911, 912, 913, 914, 915, 916, 917, 918, 919, 920, 921, 922, 923, 924, 925 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 789, 790, 869, 870, 864, 865, 859, 860, 854, 855, 849, 850, 844, 845, 841, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 796, 797, 801, 802, 806, 807, 811, 812, 816, 817, 821, 822, 826, 827, 831, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.product": { + "hide_name": 0, + "bits": [ 796, 797, 801, 802, 806, 807, 811, 812, 816, 817, 821, 822, 826, 827, 831, 832 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 926, 927, 928, 929, 930, 931, 932, 933, 934, 935, 936, 937, 938, 939, 940, 941, 942, 943, 944, 945 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 796, 797, 801, 802, 806, 807, 811, 812, 816, 817, 821, 822, 826, 827, 831, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 794, 795, 799, 800, 804, 805, 809, 810, 814, 815, 819, 820, 824, 825, 829, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.product": { + "hide_name": 0, + "bits": [ 794, 795, 799, 800, 804, 805, 809, 810, 814, 815, 819, 820, 824, 825, 829, 830 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023, 2024, 2025, 2026, 946, 947, 948, 949, 950, 951, 952, 953, 954, 955, 956, 957, 958, 959, 960, 961, 962, 963, 964, 965 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 794, 795, 799, 800, 804, 805, 809, 810, 814, 815, 819, 820, 824, 825, 829, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ 472, 474, 496, 518, 524, 526, 528, 530, 532, 534, 476, 478, 480, 482, 484, 486, 488, 490, 492, 494, 498, 500, 502, 504, 506, 508, 510, 512, 514, 516, 520, 522 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ 471, 1901, 1902, 1903, 1904, 1905, 1906, 1907, 1908, 1909, 1910, 1911, 1912, 1913, 1914, 1915, 1916, 1917, 1918, 1919, 1920, 1921, 1922, 1923, 1924, 1925, 1926, 1927, 1928, 1929, 1930, 1931 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42", + "unused_bits": "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ 791, 792, 871, 872, 866, 867, 861, 862, 856, 857, 851, 852, 846, 847, 842, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ 789, 790, 869, 870, 864, 865, 859, 860, 854, 855, 849, 850, 844, 845, 841, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[2]": { + "hide_name": 0, + "bits": [ 796, 797, 801, 802, 806, 807, 811, 812, 816, 817, 821, 822, 826, 827, 831, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[3]": { + "hide_name": 0, + "bits": [ 794, 795, 799, 800, 804, 805, 809, 810, 814, 815, 819, 820, 824, 825, 829, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ 791, 792, 871, 872, 866, 867, 861, 862, 856, 857, 851, 852, 846, 847, 842, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837, 837 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ 789, 790, 869, 870, 864, 865, 859, 860, 854, 855, 849, 850, 844, 845, 841, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836, 836 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ 796, 797, 801, 802, 806, 807, 811, 812, 816, 817, 821, 822, 826, 827, 831, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832, 832 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[3]": { + "hide_name": 0, + "bits": [ 794, 795, 799, 800, 804, 805, 809, 810, 814, 815, 819, 820, 824, 825, 829, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830, 830 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[4]": { + "hide_name": 0, + "bits": [ 2027, 2028, 2029, 2030, 2031, 2032, 2033, 2034, 2035, 2036, 2037, 2038, 2039, 2040, 2041, 2042, 2043, 2043, 2043, 2043, 2043, 2043, 2043, 2043, 2043, 2043, 2043, 2043, 2043, 2043, 2043, 2043 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[5]": { + "hide_name": 0, + "bits": [ 2044, 2045, 2046, 2047, 2048, 2049, 2050, 2051, 2052, 2053, 2054, 2055, 2056, 2057, 2058, 2059, 2060, 2060, 2060, 2060, 2060, 2060, 2060, 2060, 2060, 2060, 2060, 2060, 2060, 2060, 2060, 2060 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y": { + "hide_name": 0, + "bits": [ 13, 14, 15, 16, 17, 18, 19, 20 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_CE": { + "hide_name": 0, + "bits": [ 966 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc": { + "hide_name": 0, + "bits": [ 1030, 974, 976, 978, 980, 982, 984, 986, 988, 990, 994, 996, 998, 1000, 1002, 1004, 1006, 1008, 1010, 1012, 1016, 1018, 968, 970, 992, 1014, 1020, 1022, 1024, 1026, 1028, 972 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ 1029, 973, 975, 977, 979, 981, 983, 985, 987, 989, 993, 995, 997, 999, 1001, 1003, 1005, 1007, 1009, 1011, 1015, 1017, 967, 969, 991, 1013, 1019, 1021, 1023, 1025, 1027, 971 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_A0": { + "hide_name": 0, + "bits": [ 1043 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_A1": { + "hide_name": 0, + "bits": [ 1044 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_B0": { + "hide_name": 0, + "bits": [ 1045 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_B1": { + "hide_name": 0, + "bits": [ 1046 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_10_COUT": { + "hide_name": 0, + "bits": [ 1048 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_A0": { + "hide_name": 0, + "bits": [ 1055 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_A1": { + "hide_name": 0, + "bits": [ 1056 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_B0": { + "hide_name": 0, + "bits": [ 1057 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_B1": { + "hide_name": 0, + "bits": [ 1058 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_11_COUT": { + "hide_name": 0, + "bits": [ 1035 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_A0": { + "hide_name": 0, + "bits": [ 1062 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_A1": { + "hide_name": 0, + "bits": [ 1063 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_B0": { + "hide_name": 0, + "bits": [ 1064 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_B1": { + "hide_name": 0, + "bits": [ 1065 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_12_COUT": { + "hide_name": 0, + "bits": [ 1041 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_A0": { + "hide_name": 0, + "bits": [ 1073 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_A1": { + "hide_name": 0, + "bits": [ 1074 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_B0": { + "hide_name": 0, + "bits": [ 1075 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_B1": { + "hide_name": 0, + "bits": [ 1076 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_13_COUT": { + "hide_name": 0, + "bits": [ 1078 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_A0": { + "hide_name": 0, + "bits": [ 1079 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_A1": { + "hide_name": 0, + "bits": [ 1080 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_B0": { + "hide_name": 0, + "bits": [ 1081 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_B1": { + "hide_name": 0, + "bits": [ 1082 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_14_COUT": { + "hide_name": 0, + "bits": [ 1066 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_A0": { + "hide_name": 0, + "bits": [ 1088 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_A1": { + "hide_name": 0, + "bits": [ 1089 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_B0": { + "hide_name": 0, + "bits": [ 1090 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_B1": { + "hide_name": 0, + "bits": [ 1091 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_15_COUT": { + "hide_name": 0, + "bits": [ 1093 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_A0": { + "hide_name": 0, + "bits": [ 1037 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_A1": { + "hide_name": 0, + "bits": [ 1038 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B0": { + "hide_name": 0, + "bits": [ 1039 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_B1": { + "hide_name": 0, + "bits": [ 1040 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 1042 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_A1": { + "hide_name": 0, + "bits": [ 1098 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_B1": { + "hide_name": 0, + "bits": [ 1099 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 1047 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_2_S0": { + "hide_name": 0, + "bits": [ 1100 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_A0": { + "hide_name": 0, + "bits": [ 1103 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_A1": { + "hide_name": 0, + "bits": [ 1104 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_B0": { + "hide_name": 0, + "bits": [ 1105 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_B1": { + "hide_name": 0, + "bits": [ 1106 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_3_COUT": { + "hide_name": 0, + "bits": [ 1077 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_A0": { + "hide_name": 0, + "bits": [ 1107 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_A1": { + "hide_name": 0, + "bits": [ 1108 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_B0": { + "hide_name": 0, + "bits": [ 1109 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_B1": { + "hide_name": 0, + "bits": [ 1110 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_4_COUT": { + "hide_name": 0, + "bits": [ 1111 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_A0": { + "hide_name": 0, + "bits": [ 1116 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_A1": { + "hide_name": 0, + "bits": [ 1117 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_B0": { + "hide_name": 0, + "bits": [ 1118 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_B1": { + "hide_name": 0, + "bits": [ 1119 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_5_COUT": { + "hide_name": 0, + "bits": [ 1120 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_A0": { + "hide_name": 0, + "bits": [ 1125 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_A1": { + "hide_name": 0, + "bits": [ 1126 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_B0": { + "hide_name": 0, + "bits": [ 1127 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_B1": { + "hide_name": 0, + "bits": [ 1128 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_6_COUT": { + "hide_name": 0, + "bits": [ 1083 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_A0": { + "hide_name": 0, + "bits": [ 1131 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_A1": { + "hide_name": 0, + "bits": [ 1132 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_B0": { + "hide_name": 0, + "bits": [ 1133 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_B1": { + "hide_name": 0, + "bits": [ 1134 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_7_COUT": { + "hide_name": 0, + "bits": [ 1092 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_A0": { + "hide_name": 0, + "bits": [ 1135 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_A1": { + "hide_name": 0, + "bits": [ 1136 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_B0": { + "hide_name": 0, + "bits": [ 1137 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_B1": { + "hide_name": 0, + "bits": [ 1138 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_8_COUT": { + "hide_name": 0, + "bits": [ 1059 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_A0": { + "hide_name": 0, + "bits": [ 1139 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_A1": { + "hide_name": 0, + "bits": [ 1140 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_B0": { + "hide_name": 0, + "bits": [ 1141 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_B1": { + "hide_name": 0, + "bits": [ 1142 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_9_COUT": { + "hide_name": 0, + "bits": [ 1143 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_A0": { + "hide_name": 0, + "bits": [ 1031 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_A1": { + "hide_name": 0, + "bits": [ 1032 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_B0": { + "hide_name": 0, + "bits": [ 1033 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_B1": { + "hide_name": 0, + "bits": [ 1034 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1036 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1030, 1101, 1102 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT": { + "hide_name": 0, + "bits": [ 1153 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1158 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1163 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1168 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1173 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1178 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1183 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1188 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1189 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1006, 1060, 1061 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 1194 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 1195 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1190 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1002, 1121, 1122 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1004, 1123, 1124 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1193 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 998, 1112, 1113 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1000, 1114, 1115 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1198 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 994, 1094, 1095 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 996, 1096, 1097 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1203 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 988, 1067, 1068 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 990, 1069, 1070 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1208 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 984, 1084, 1085 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 986, 1071, 1072 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1213 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 980, 1129, 1130 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 982, 1086, 1087 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1218 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 976, 1049, 1050 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 978, 1051, 1052 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1223 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 1148 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 974, 1053, 1054 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1228 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 39, 1229 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z": { + "hide_name": 0, + "bits": [ 1232 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 1231 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1233, 1234, 1235 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 1230 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ 1029, 973, 975, 977, 979, 981, 983, 985, 987, 989, 993, 995, 997, 999, 1001, 1003, 1005, 1007, 1009, 1011, 1015, 1017, 967, 969, 991, 1013, 1019, 1021, 1023, 1025, 1027, 971 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 1234, 1233, 1239, 1238, 1237, 1236 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1240, 1241, 1245, 1242, 1243, 1244 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:34.26-34.27" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 1248 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 1246 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_2_S0": { + "hide_name": 0, + "bits": [ 1249 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1247 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 1151, 1152, 1156, 1157, 1161, 1162, 1166, 1167, 1171, 1172, 1176, 1177, 1181, 1182, 1186, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ 1151, 1152, 1156, 1157, 1161, 1162, 1166, 1167, 1171, 1172, 1176, 1177, 1181, 1182, 1186, 1187 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 2061, 2062, 2063, 2064, 2065, 2066, 2067, 2068, 2069, 2070, 2071, 2072, 2073, 2074, 2075, 2076, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, 1264, 1265, 1266, 1267, 1268, 1269 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 1151, 1152, 1156, 1157, 1161, 1162, 1166, 1167, 1171, 1172, 1176, 1177, 1181, 1182, 1186, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 1149, 1150, 1154, 1155, 1159, 1160, 1164, 1165, 1169, 1170, 1174, 1175, 1179, 1180, 1184, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ 1149, 1150, 1154, 1155, 1159, 1160, 1164, 1165, 1169, 1170, 1174, 1175, 1179, 1180, 1184, 1185 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 2077, 2078, 2079, 2080, 2081, 2082, 2083, 2084, 2085, 2086, 2087, 2088, 2089, 2090, 2091, 2092, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 1149, 1150, 1154, 1155, 1159, 1160, 1164, 1165, 1169, 1170, 1174, 1175, 1179, 1180, 1184, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 1146, 1147, 1226, 1227, 1221, 1222, 1216, 1217, 1211, 1212, 1206, 1207, 1201, 1202, 1197, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.product": { + "hide_name": 0, + "bits": [ 1146, 1147, 1226, 1227, 1221, 1222, 1216, 1217, 1211, 1212, 1206, 1207, 1201, 1202, 1197, 1192 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 2093, 2094, 2095, 2096, 2097, 2098, 2099, 2100, 2101, 2102, 2103, 2104, 2105, 2106, 2107, 2108, 1290, 1291, 1292, 1293, 1294, 1295, 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 1146, 1147, 1226, 1227, 1221, 1222, 1216, 1217, 1211, 1212, 1206, 1207, 1201, 1202, 1197, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 1144, 1145, 1224, 1225, 1219, 1220, 1214, 1215, 1209, 1210, 1204, 1205, 1199, 1200, 1196, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.product": { + "hide_name": 0, + "bits": [ 1144, 1145, 1224, 1225, 1219, 1220, 1214, 1215, 1209, 1210, 1204, 1205, 1199, 1200, 1196, 1191 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 2109, 2110, 2111, 2112, 2113, 2114, 2115, 2116, 2117, 2118, 2119, 2120, 2121, 2122, 2123, 2124, 1310, 1311, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 1144, 1145, 1224, 1225, 1219, 1220, 1214, 1215, 1209, 1210, 1204, 1205, 1199, 1200, 1196, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ 1030, 974, 976, 978, 980, 982, 984, 986, 988, 990, 994, 996, 998, 1000, 1002, 1004, 1006, 1008, 1010, 1012, 1016, 1018, 968, 970, 992, 1014, 1020, 1022, 1024, 1026, 1028, 972 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ 1029, 973, 975, 977, 979, 981, 983, 985, 987, 989, 993, 995, 997, 999, 1001, 1003, 1005, 1007, 1009, 1011, 1015, 1017, 967, 969, 991, 1013, 1019, 1021, 1023, 1025, 1027, 971 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ 1151, 1152, 1156, 1157, 1161, 1162, 1166, 1167, 1171, 1172, 1176, 1177, 1181, 1182, 1186, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ 1149, 1150, 1154, 1155, 1159, 1160, 1164, 1165, 1169, 1170, 1174, 1175, 1179, 1180, 1184, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[2]": { + "hide_name": 0, + "bits": [ 1146, 1147, 1226, 1227, 1221, 1222, 1216, 1217, 1211, 1212, 1206, 1207, 1201, 1202, 1197, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[3]": { + "hide_name": 0, + "bits": [ 1144, 1145, 1224, 1225, 1219, 1220, 1214, 1215, 1209, 1210, 1204, 1205, 1199, 1200, 1196, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ 1151, 1152, 1156, 1157, 1161, 1162, 1166, 1167, 1171, 1172, 1176, 1177, 1181, 1182, 1186, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187, 1187 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ 1149, 1150, 1154, 1155, 1159, 1160, 1164, 1165, 1169, 1170, 1174, 1175, 1179, 1180, 1184, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185, 1185 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ 1146, 1147, 1226, 1227, 1221, 1222, 1216, 1217, 1211, 1212, 1206, 1207, 1201, 1202, 1197, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192, 1192 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[3]": { + "hide_name": 0, + "bits": [ 1144, 1145, 1224, 1225, 1219, 1220, 1214, 1215, 1209, 1210, 1204, 1205, 1199, 1200, 1196, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191, 1191 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[4]": { + "hide_name": 0, + "bits": [ 2125, 2126, 2127, 2128, 2129, 2130, 2131, 2132, 2133, 2134, 2135, 2136, 2137, 2138, 2139, 2140, 2141, 2141, 2141, 2141, 2141, 2141, 2141, 2141, 2141, 2141, 2141, 2141, 2141, 2141, 2141, 2141 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[5]": { + "hide_name": 0, + "bits": [ 2142, 2143, 2144, 2145, 2146, 2147, 2148, 2149, 2150, 2151, 2152, 2153, 2154, 2155, 2156, 2157, 2158, 2158, 2158, 2158, 2158, 2158, 2158, 2158, 2158, 2158, 2158, 2158, 2158, 2158, 2158, 2158 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y": { + "hide_name": 0, + "bits": [ 21, 22, 23, 24, 25, 26, 27, 28 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1330, 1331, 1332, 1333, 1334, 1335, 1336, "0" ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 973, 1337, 971 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1338 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1339 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1342 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1345 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1348 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1351 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1354 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1357 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1360 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1363 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1366 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1369 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1372 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1375 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1378 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1381 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1382 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1379 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1380 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1376 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1377 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1373 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1374 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1370 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1371 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1367 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1368 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1364 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1365 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1361 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1362 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1358 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1359 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1355 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1356 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1352 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1353 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1349 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1350 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1346 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1347 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1343 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1344 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1340 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1341 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc": { + "hide_name": 0, + "bits": [ 1408, 1436, 1384, 1430, 1386, 1438, 1440, 1442, 1444, 1446, 1388, 1390, 1392, 1394, 1396, 1398, 1400, 1402, 1404, 1406, 1410, 1412, 1414, 1416, 1418, 1420, 1422, 1424, 1426, 1428, 1432, 1434 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ 1407, 1435, 1383, 1429, 1385, 1437, 1439, 1441, 1443, 1445, 1387, 1389, 1391, 1393, 1395, 1397, 1399, 1401, 1403, 1405, 1409, 1411, 1413, 1415, 1417, 1419, 1421, 1423, 1425, 1427, 1431, 1433 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_A0": { + "hide_name": 0, + "bits": [ 1458 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_A1": { + "hide_name": 0, + "bits": [ 1459 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_B0": { + "hide_name": 0, + "bits": [ 1460 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_B1": { + "hide_name": 0, + "bits": [ 1461 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_COUT": { + "hide_name": 0, + "bits": [ 1463 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_A0": { + "hide_name": 0, + "bits": [ 1466 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_A1": { + "hide_name": 0, + "bits": [ 1467 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_B0": { + "hide_name": 0, + "bits": [ 1468 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_B1": { + "hide_name": 0, + "bits": [ 1469 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11_COUT": { + "hide_name": 0, + "bits": [ 1471 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_12_A1": { + "hide_name": 0, + "bits": [ 1478 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_12_B1": { + "hide_name": 0, + "bits": [ 1479 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_12_COUT": { + "hide_name": 0, + "bits": [ 1480 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_12_S0": { + "hide_name": 0, + "bits": [ 1481 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_A0": { + "hide_name": 0, + "bits": [ 1486 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_A1": { + "hide_name": 0, + "bits": [ 1487 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_B0": { + "hide_name": 0, + "bits": [ 1488 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_B1": { + "hide_name": 0, + "bits": [ 1489 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_13_COUT": { + "hide_name": 0, + "bits": [ 1490 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_A0": { + "hide_name": 0, + "bits": [ 1495 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_A1": { + "hide_name": 0, + "bits": [ 1496 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_B0": { + "hide_name": 0, + "bits": [ 1497 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_B1": { + "hide_name": 0, + "bits": [ 1498 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_14_COUT": { + "hide_name": 0, + "bits": [ 1499 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_A0": { + "hide_name": 0, + "bits": [ 1504 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_A1": { + "hide_name": 0, + "bits": [ 1505 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_B0": { + "hide_name": 0, + "bits": [ 1506 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_B1": { + "hide_name": 0, + "bits": [ 1507 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_15_COUT": { + "hide_name": 0, + "bits": [ 1470 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_A0": { + "hide_name": 0, + "bits": [ 1453 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_A1": { + "hide_name": 0, + "bits": [ 1454 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_B0": { + "hide_name": 0, + "bits": [ 1455 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_B1": { + "hide_name": 0, + "bits": [ 1456 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 1457 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_A0": { + "hide_name": 0, + "bits": [ 1510 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_A1": { + "hide_name": 0, + "bits": [ 1511 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_B0": { + "hide_name": 0, + "bits": [ 1512 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_B1": { + "hide_name": 0, + "bits": [ 1513 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 1514 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_A0": { + "hide_name": 0, + "bits": [ 1515 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_A1": { + "hide_name": 0, + "bits": [ 1516 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B0": { + "hide_name": 0, + "bits": [ 1517 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1": { + "hide_name": 0, + "bits": [ 1518 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_COUT": { + "hide_name": 0, + "bits": [ 1520 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_A0": { + "hide_name": 0, + "bits": [ 1527 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_A1": { + "hide_name": 0, + "bits": [ 1528 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B0": { + "hide_name": 0, + "bits": [ 1529 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1": { + "hide_name": 0, + "bits": [ 1530 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_COUT": { + "hide_name": 0, + "bits": [ 1531 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_A0": { + "hide_name": 0, + "bits": [ 1536 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_A1": { + "hide_name": 0, + "bits": [ 1537 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B0": { + "hide_name": 0, + "bits": [ 1538 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1": { + "hide_name": 0, + "bits": [ 1539 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_COUT": { + "hide_name": 0, + "bits": [ 1540 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_A0": { + "hide_name": 0, + "bits": [ 1541 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_A1": { + "hide_name": 0, + "bits": [ 1542 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B0": { + "hide_name": 0, + "bits": [ 1543 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1": { + "hide_name": 0, + "bits": [ 1544 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_COUT": { + "hide_name": 0, + "bits": [ 1451 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_A0": { + "hide_name": 0, + "bits": [ 1545 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_A1": { + "hide_name": 0, + "bits": [ 1546 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B0": { + "hide_name": 0, + "bits": [ 1547 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1": { + "hide_name": 0, + "bits": [ 1548 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_COUT": { + "hide_name": 0, + "bits": [ 1519 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_A0": { + "hide_name": 0, + "bits": [ 1551 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_A1": { + "hide_name": 0, + "bits": [ 1552 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B0": { + "hide_name": 0, + "bits": [ 1553 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1": { + "hide_name": 0, + "bits": [ 1554 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_COUT": { + "hide_name": 0, + "bits": [ 1555 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_A0": { + "hide_name": 0, + "bits": [ 1556 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_A1": { + "hide_name": 0, + "bits": [ 1557 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_B0": { + "hide_name": 0, + "bits": [ 1558 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_B1": { + "hide_name": 0, + "bits": [ 1559 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_COUT": { + "hide_name": 0, + "bits": [ 1462 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_A0": { + "hide_name": 0, + "bits": [ 1447 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_A1": { + "hide_name": 0, + "bits": [ 1448 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_B0": { + "hide_name": 0, + "bits": [ 1449 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_B1": { + "hide_name": 0, + "bits": [ 1450 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1452 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1408, 1484, 1485 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_1_COUT": { + "hide_name": 0, + "bits": [ 1569 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 1564 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1574 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1579 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1584 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1589 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1594 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1599 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1604 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT": { + "hide_name": 0, + "bits": [ 1605 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1400, 1464, 1465 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT": { + "hide_name": 0, + "bits": [ 1610 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 1611 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1606 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1396, 1532, 1533 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1398, 1534, 1535 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1609 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1392, 1521, 1522 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1394, 1523, 1524 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1614 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1388, 1549, 1550 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1390, 1525, 1526 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1619 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1444, 1472, 1473 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1446, 1474, 1475 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1624 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1440, 1508, 1509 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1442, 1476, 1477 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1629 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1386, 1500, 1501 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1438, 1502, 1503 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1634 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S0": { + "hide_name": 0, + "bits": [ 1384, 1491, 1492 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1": { + "hide_name": 0, + "bits": [ 1430, 1493, 1494 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1639 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_S1": { + "hide_name": 0, + "bits": [ 1436, 1482, 1483 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1644 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 42, 1646 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z": { + "hide_name": 0, + "bits": [ 4, 42, 1645 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 1648 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1649, 1650, 1651 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 1647 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ 1407, 1435, 1383, 1429, 1385, 1437, 1439, 1441, 1443, 1445, 1387, 1389, 1391, 1393, 1395, 1397, 1399, 1401, 1403, 1405, 1409, 1411, 1413, 1415, 1417, 1419, 1421, 1423, 1425, 1427, 1431, 1433 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 1650, 1649, 1655, 1654, 1653, 1652 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1656, 1657, 1658, 1659, 1660, 1661 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:34.26-34.27" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_1_COUT": { + "hide_name": 0, + "bits": [ 1664 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_2_COUT": { + "hide_name": 0, + "bits": [ 1665 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13", + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_COUT": { + "hide_name": 0, + "bits": [ 1662 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI_CCU2C_S1_S0": { + "hide_name": 0, + "bits": [ 1663 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 1562, 1563, 1572, 1573, 1577, 1578, 1582, 1583, 1587, 1588, 1592, 1593, 1597, 1598, 1602, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ 1562, 1563, 1572, 1573, 1577, 1578, 1582, 1583, 1587, 1588, 1592, 1593, 1597, 1598, 1602, 1603 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 2159, 2160, 2161, 2162, 2163, 2164, 2165, 2166, 2167, 2168, 2169, 2170, 2171, 2172, 2173, 2174, 1667, 1668, 1669, 1670, 1671, 1672, 1673, 1674, 1675, 1676, 1677, 1678, 1679, 1680, 1681, 1682, 1683, 1684, 1685, 1686 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 1562, 1563, 1572, 1573, 1577, 1578, 1582, 1583, 1587, 1588, 1592, 1593, 1597, 1598, 1602, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", 1666, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 1560, 1561, 1570, 1571, 1575, 1576, 1580, 1581, 1585, 1586, 1590, 1591, 1595, 1596, 1600, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ 1560, 1561, 1570, 1571, 1575, 1576, 1580, 1581, 1585, 1586, 1590, 1591, 1595, 1596, 1600, 1601 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 2175, 2176, 2177, 2178, 2179, 2180, 2181, 2182, 2183, 2184, 2185, 2186, 2187, 2188, 2189, 2190, 1687, 1688, 1689, 1690, 1691, 1692, 1693, 1694, 1695, 1696, 1697, 1698, 1699, 1700, 1701, 1702, 1703, 1704, 1705, 1706 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 1560, 1561, 1570, 1571, 1575, 1576, 1580, 1581, 1585, 1586, 1590, 1591, 1595, 1596, 1600, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", 1666, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 1567, 1568, 1642, 1643, 1637, 1638, 1632, 1633, 1627, 1628, 1622, 1623, 1617, 1618, 1613, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.product": { + "hide_name": 0, + "bits": [ 1567, 1568, 1642, 1643, 1637, 1638, 1632, 1633, 1627, 1628, 1622, 1623, 1617, 1618, 1613, 1608 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 2191, 2192, 2193, 2194, 2195, 2196, 2197, 2198, 2199, 2200, 2201, 2202, 2203, 2204, 2205, 2206, 1707, 1708, 1709, 1710, 1711, 1712, 1713, 1714, 1715, 1716, 1717, 1718, 1719, 1720, 1721, 1722, 1723, 1724, 1725, 1726 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 1567, 1568, 1642, 1643, 1637, 1638, 1632, 1633, 1627, 1628, 1622, 1623, 1617, 1618, 1613, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", 1666, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_out": { + "hide_name": 0, + "bits": [ 1565, 1566, 1640, 1641, 1635, 1636, 1630, 1631, 1625, 1626, 1620, 1621, 1615, 1616, 1612, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.product": { + "hide_name": 0, + "bits": [ 1565, 1566, 1640, 1641, 1635, 1636, 1630, 1631, 1625, 1626, 1620, 1621, 1615, 1616, 1612, 1607 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_MULT18X18D_P9_P35": { + "hide_name": 0, + "bits": [ 2207, 2208, 2209, 2210, 2211, 2212, 2213, 2214, 2215, 2216, 2217, 2218, 2219, 2220, 2221, 2222, 1727, 1728, 1729, 1730, 1731, 1732, 1733, 1734, 1735, 1736, 1737, 1738, 1739, 1740, 1741, 1742, 1743, 1744, 1745, 1746 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16.22-16.27|/opt/homebrew/bin/../share/yosys/mul2dsp.v:255.6-259.5|/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v:1.68-1.69", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_ext": { + "hide_name": 0, + "bits": [ 1565, 1566, 1640, 1641, 1635, 1636, 1630, 1631, 1625, 1626, 1620, 1621, 1615, 1616, 1612, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", 1666, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ 1408, 1436, 1384, 1430, 1386, 1438, 1440, 1442, 1444, 1446, 1388, 1390, 1392, 1394, 1396, 1398, 1400, 1402, 1404, 1406, 1410, 1412, 1414, 1416, 1418, 1420, 1422, 1424, 1426, 1428, 1432, 1434 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ 1407, 1435, 1383, 1429, 1385, 1437, 1439, 1441, 1443, 1445, 1387, 1389, 1391, 1393, 1395, 1397, 1399, 1401, 1403, 1405, 1409, 1411, 1413, 1415, 1417, 1419, 1421, 1423, 1425, 1427, 1431, 1433 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ 1562, 1563, 1572, 1573, 1577, 1578, 1582, 1583, 1587, 1588, 1592, 1593, 1597, 1598, 1602, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ 1560, 1561, 1570, 1571, 1575, 1576, 1580, 1581, 1585, 1586, 1590, 1591, 1595, 1596, 1600, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[2]": { + "hide_name": 0, + "bits": [ 1567, 1568, 1642, 1643, 1637, 1638, 1632, 1633, 1627, 1628, 1622, 1623, 1617, 1618, 1613, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[3]": { + "hide_name": 0, + "bits": [ 1565, 1566, 1640, 1641, 1635, 1636, 1630, 1631, 1625, 1626, 1620, 1621, 1615, 1616, 1612, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ 1562, 1563, 1572, 1573, 1577, 1578, 1582, 1583, 1587, 1588, 1592, 1593, 1597, 1598, 1602, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603, 1603 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ 1560, 1561, 1570, 1571, 1575, 1576, 1580, 1581, 1585, 1586, 1590, 1591, 1595, 1596, 1600, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601, 1601 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ 1567, 1568, 1642, 1643, 1637, 1638, 1632, 1633, 1627, 1628, 1622, 1623, 1617, 1618, 1613, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608, 1608 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[3]": { + "hide_name": 0, + "bits": [ 1565, 1566, 1640, 1641, 1635, 1636, 1630, 1631, 1625, 1626, 1620, 1621, 1615, 1616, 1612, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607, 1607 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[4]": { + "hide_name": 0, + "bits": [ 2223, 2224, 2225, 2226, 2227, 2228, 2229, 2230, 2231, 2232, 2233, 2234, 2235, 2236, 2237, 2238, 2239, 2239, 2239, 2239, 2239, 2239, 2239, 2239, 2239, 2239, 2239, 2239, 2239, 2239, 2239, 2239 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[5]": { + "hide_name": 0, + "bits": [ 2240, 2241, 2242, 2243, 2244, 2245, 2246, 2247, 2248, 2249, 2250, 2251, 2252, 2253, 2254, 2255, 2256, 2256, 2256, 2256, 2256, 2256, 2256, 2256, 2256, 2256, 2256, 2256, 2256, 2256, 2256, 2256 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13", + "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", 1666, "0", "0", "0", "0", "0", "0", "0", 1666, "0", "0", "0", "0", "0", "0", "0", 1666, "0", "0", "0", "0", "0", "0", "0", 1666, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1747 ], + "offset": 2, + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 1748 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 1660, 1661, 1749, 1645 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "0", "0", 1666, "0", "0", "0", "0", "0", "0", "0", 1666, "0", "0", "0", "0", "0", "0", "0", 1666, "0", "0", "0", "0", "0", "0", "0", 1666, "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y": { + "hide_name": 0, + "bits": [ 29, 30, 31, 32, 33, 34, 35, 36 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1750, 1754, 1755, 1756, 1751, 1752, 1753, "0" ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 1435, 1757, 1433 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1758 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1759 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1762 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1765 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1768 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1771 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1774 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1777 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1780 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1783 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1786 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1789 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1792 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1795 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN": { + "hide_name": 0, + "bits": [ 1798 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45|/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4|/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1801 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1802 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1799 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1800 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1796 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1797 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1793 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1794 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1790 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1791 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1787 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1788 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1784 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1785 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1781 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1782 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1778 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1779 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1775 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1776 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1772 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1773 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1769 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1770 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1766 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1767 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1763 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1764 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_S0": { + "hide_name": 0, + "bits": [ 1760 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_S1": { + "hide_name": 0, + "bits": [ 1761 ], + "attributes": { + "unused_bits": "0 " + } + }, + "u_layer.bias_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer bias_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:18.9-18.17" + } + }, + "u_layer.busy": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "hdlname": "u_layer busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:23.12-23.16" + } + }, + "u_layer.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:8.11-8.14" + } + }, + "u_layer.done": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "hdlname": "u_layer done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:24.12-24.16" + } + }, + "u_layer.neuron_busy": { + "hide_name": 0, + "bits": [ 41, 40, 39, 42 ], + "attributes": { + "hdlname": "u_layer neuron_busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:27.26-27.37" + } + }, + "u_layer.neuron_done": { + "hide_name": 0, + "bits": [ 46, 44, 43, 45 ], + "attributes": { + "hdlname": "u_layer neuron_done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:28.26-28.37" + } + }, + "u_layer.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:9.11-9.14" + } + }, + "u_layer.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:10.11-10.16" + } + }, + "u_layer.weights_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer weights_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:15.9-15.20" + } + }, + "u_layer.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:12.44-12.49" + } + }, + "u_layer.y_bus": { + "hide_name": 0, + "bits": [ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer y_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:21.9-21.14" + } + }, + "weights_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:18.52-18.63" + } + }, + "x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:17.42-17.47" + } + }, + "y_bus": { + "hide_name": 0, + "bits": [ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:6.26-6.31" + } + } + } + } + } +} diff --git a/synth/ecp5/p4/top.lpf b/synth/ecp5/p4/top.lpf new file mode 100644 index 0000000..e69de29 diff --git a/synth/ecp5/p4/top.v b/synth/ecp5/p4/top.v new file mode 100644 index 0000000..5200b4d --- /dev/null +++ b/synth/ecp5/p4/top.v @@ -0,0 +1,78 @@ +module top ( + input clk, + input rst, + input start, + + output signed [31:0] y_bus, + output busy, + output done +); + + localparam DATA_WIDTH = 8; + localparam N_INPUTS = 256; + localparam N_NEURONS = 4; + localparam PARALLEL = 4; + localparam ACC_WIDTH = 32; + + reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus; + reg signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0] weights_bus; + reg signed [DATA_WIDTH*N_NEURONS-1:0] bias_bus; + + integer i; + + initial begin + x_bus = 0; + weights_bus = 0; + bias_bus = 0; + + // X = 1 + for (i = 0; i < N_INPUTS; i = i + 1) + x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1; + + // Neuron 0: first 32 weights = +1 + for (i = 0; i < 32; i = i + 1) + weights_bus[ + 0*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = 8'sd1; + + // Neuron 1: all zero, bias = 10 + bias_bus[1*DATA_WIDTH +: DATA_WIDTH] = 8'sd10; + + // Neuron 2: all weights = -1 + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 2*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = -8'sd1; + + // Neuron 3: first 32 weights = +4 + for (i = 0; i < 32; i = i + 1) + weights_bus[ + 3*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = 8'sd4; + end + + layer #( + .DATA_WIDTH(DATA_WIDTH), + .N_INPUTS(N_INPUTS), + .N_NEURONS(N_NEURONS), + .PARALLEL(PARALLEL), + .ACC_WIDTH(ACC_WIDTH) + ) u_layer ( + .clk(clk), + .rst(rst), + .start(start), + .x_bus(x_bus), + .weights_bus(weights_bus), + .bias_bus(bias_bus), + .y_bus(y_bus), + .busy(busy), + .done(done) + ); + +endmodule diff --git a/synth/ecp5/p4/yosys.log b/synth/ecp5/p4/yosys.log new file mode 100644 index 0000000..e69de29 diff --git a/synth/ecp5/p8/nextpnr.log b/synth/ecp5/p8/nextpnr.log new file mode 100644 index 0000000..272a9d6 --- /dev/null +++ b/synth/ecp5/p8/nextpnr.log @@ -0,0 +1,10364 @@ +Warning: IO 'y_bus[31]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[30]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[29]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[28]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[27]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[26]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[25]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[24]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[23]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[22]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[21]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[20]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[19]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[18]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[17]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[16]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[15]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[14]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[13]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[12]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[11]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[10]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[9]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[8]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[7]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[6]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[5]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[4]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[3]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[2]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[1]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[0]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1099]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1098]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1097]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1096]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1095]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1094]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1093]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1092]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1091]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1090]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1089]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1088]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1087]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1086]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1085]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1084]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1083]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1082]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1081]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1080]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1079]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1078]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1077]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1076]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1075]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1074]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1073]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1072]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1071]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1070]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1069]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1068]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1067]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1066]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1065]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1064]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1063]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1062]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1061]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1060]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1059]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1058]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1057]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1056]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1055]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1054]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1053]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1052]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1051]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1050]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1049]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1048]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[99]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[98]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[97]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[96]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[95]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[94]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[93]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[92]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[91]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[90]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[89]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[88]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[87]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[86]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[85]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[84]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[83]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[82]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[81]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[80]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[79]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[78]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[77]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[76]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[75]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[74]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[73]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[72]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[71]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[70]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[69]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[68]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[67]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[66]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[65]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[64]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[63]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[62]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[61]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[60]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[59]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[58]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[57]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[56]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[55]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[54]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[53]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[52]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[51]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[50]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[49]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[48]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[47]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[46]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[45]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[44]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[43]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[42]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[41]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[40]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[39]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[38]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[37]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[36]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[35]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[34]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[33]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[32]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[31]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[30]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[29]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[28]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[27]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[26]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[25]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[24]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[23]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[22]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[21]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[20]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[19]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[18]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[17]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[16]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[15]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[14]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[13]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[12]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[11]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[10]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[9]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[8]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[7]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[6]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[5]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[4]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[3]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[2]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[1]' is unconstrained in LPF and will be automatically placed +Warning: IO 'x_bus[0]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8099]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8098]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8097]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8096]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8095]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8094]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8093]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8092]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8091]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8090]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8089]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8088]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8087]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8086]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8085]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8084]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8083]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8082]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8081]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8080]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8079]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8078]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8077]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8076]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8075]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8074]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8073]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8072]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8071]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8070]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8069]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8068]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8067]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8066]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8065]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8064]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8063]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8062]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8061]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8060]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8059]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8058]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8057]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8056]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8055]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8054]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8053]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8052]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8051]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8050]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8049]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8048]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7099]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7098]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7097]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7096]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7095]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7094]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7093]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7092]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7091]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7090]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7089]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7088]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7087]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7086]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7085]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7084]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7083]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7082]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7081]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7080]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7079]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7078]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7077]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7076]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7075]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7074]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7073]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7072]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7071]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7070]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7069]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7068]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7067]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7066]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7065]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7064]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7063]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7062]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7061]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7060]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7059]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7058]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7057]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7056]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7055]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7054]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7053]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7052]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7051]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7050]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7049]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7048]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6099]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6098]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6097]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6096]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6095]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6094]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6093]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6092]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6091]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6090]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6089]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6088]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6087]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6086]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6085]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6084]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6083]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6082]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6081]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6080]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6079]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6078]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6077]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6076]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6075]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6074]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6073]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6072]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6071]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6070]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6069]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6068]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6067]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6066]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6065]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6064]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6063]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6062]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6061]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6060]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6059]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6058]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6057]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6056]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6055]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6054]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6053]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6052]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6051]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6050]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6049]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6048]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5099]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5098]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5097]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5096]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5095]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5094]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5093]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5092]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5091]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5090]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5089]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5088]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5087]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5086]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5085]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5084]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5083]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5082]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5081]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5080]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5079]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5078]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5077]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5076]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5075]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5074]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5073]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5072]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5071]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5070]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5069]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5068]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5067]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5066]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5065]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5064]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5063]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5062]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5061]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5060]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5059]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5058]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5057]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5056]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5055]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5054]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5053]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5052]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5051]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5050]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5049]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5048]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4099]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4098]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4097]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4096]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4095]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4094]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4093]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4092]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4091]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4090]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4089]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4088]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4087]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4086]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4085]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4084]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4083]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4082]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4081]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4080]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4079]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4078]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4077]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4076]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4075]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4074]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4073]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4072]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4071]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4070]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4069]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4068]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4067]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4066]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4065]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4064]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4063]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4062]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4061]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4060]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4059]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4058]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4057]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4056]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4055]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4054]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4053]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4052]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4051]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4050]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4049]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4048]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3099]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3098]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3097]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3096]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3095]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3094]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3093]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3092]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3091]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3090]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3089]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3088]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3087]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3086]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3085]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3084]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3083]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3082]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3081]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3080]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3079]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3078]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3077]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3076]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3075]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3074]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3073]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3072]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3071]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3070]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3069]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3068]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3067]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3066]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3065]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3064]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3063]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3062]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3061]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3060]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3059]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3058]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3057]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3056]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3055]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3054]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3053]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3052]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3051]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3050]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3049]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3048]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2099]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2098]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2097]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2096]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2095]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2094]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2093]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2092]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2091]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2090]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2089]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2088]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2087]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2086]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2085]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2084]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2083]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2082]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2081]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2080]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2079]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2078]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2077]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2076]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2075]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2074]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2073]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2072]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2071]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2070]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2069]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2068]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2067]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2066]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2065]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2064]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2063]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2062]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2061]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2060]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2059]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2058]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2057]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2056]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2055]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2054]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2053]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2052]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2051]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2050]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2049]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2048]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1099]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1098]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1097]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1096]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1095]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1094]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1093]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1092]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1091]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1090]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1089]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1088]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1087]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1086]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1085]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1084]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1083]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1082]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1081]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1080]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1079]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1078]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1077]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1076]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1075]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1074]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1073]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1072]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1071]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1070]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1069]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1068]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1067]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1066]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1065]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1064]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1063]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1062]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1061]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1060]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1059]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1058]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1057]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1056]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1055]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1054]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1053]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1052]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1051]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1050]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1049]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1048]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1047]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1046]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1045]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1044]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1043]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1042]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1041]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1040]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1039]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1038]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1037]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1036]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1035]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1034]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1033]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1032]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1031]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1030]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1029]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1028]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1027]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1026]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1025]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1024]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1023]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1022]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1021]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1020]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1019]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1018]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1017]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1016]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1015]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1014]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1013]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1012]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1011]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1010]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1009]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1008]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1007]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1006]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1005]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1004]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1003]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1002]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1001]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1000]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[999]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[998]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[997]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[996]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[995]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[994]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[993]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[992]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[991]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[990]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[989]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[988]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[987]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[986]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[985]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[984]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[983]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[982]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[981]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[980]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[979]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[978]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[977]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[976]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[975]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[974]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[973]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[972]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[971]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[970]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[969]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[968]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[967]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[966]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[965]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[964]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[963]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[962]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[961]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[960]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[959]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[958]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[957]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[956]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[955]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[954]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[953]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[952]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[951]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[950]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[949]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[948]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[947]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[946]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[945]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[944]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[943]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[942]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[941]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[940]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[939]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[938]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[937]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[936]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[935]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[934]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[933]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[932]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[931]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[930]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[929]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[928]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[927]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[926]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[925]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[924]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[923]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[922]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[921]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[920]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[919]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[918]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[917]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[916]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[915]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[914]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[913]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[912]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[911]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[910]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[909]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[908]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[907]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[906]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[905]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[904]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[903]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[902]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[901]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[900]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[899]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[898]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[897]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[896]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[895]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[894]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[893]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[892]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[891]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[890]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[889]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[888]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[887]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[886]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[885]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[884]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[883]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[882]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[881]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[880]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[879]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[878]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[877]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[876]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[875]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[874]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[873]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[872]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[871]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[870]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[869]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[868]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[867]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[866]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[865]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[864]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[863]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[862]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[861]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[860]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[859]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[858]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[857]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[856]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[855]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[854]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[853]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[852]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[851]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[850]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[849]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[848]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[847]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[846]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[845]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[844]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[843]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[842]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[841]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[840]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[839]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[838]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[837]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[836]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[835]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[834]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[833]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[832]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[831]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[830]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[829]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[828]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[827]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[826]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[825]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[824]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[823]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[822]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[821]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[820]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[819]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[818]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[817]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[816]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[815]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[814]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[813]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[812]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[811]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[810]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[809]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[808]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[807]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[806]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[805]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[804]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[803]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[802]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[801]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[800]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[799]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[798]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[797]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[796]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[795]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[794]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[793]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[792]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[791]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[790]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[789]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[788]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[787]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[786]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[785]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[784]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[783]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[782]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[781]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[780]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[779]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[778]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[777]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[776]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[775]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[774]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[773]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[772]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[771]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[770]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[769]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[768]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[767]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[766]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[765]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[764]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[763]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[762]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[761]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[760]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[759]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[758]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[757]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[756]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[755]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[754]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[753]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[752]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[751]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[750]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[749]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[748]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[747]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[746]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[745]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[744]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[743]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[742]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[741]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[740]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[739]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[738]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[737]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[736]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[735]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[734]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[733]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[732]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[731]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[730]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[729]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[728]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[727]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[726]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[725]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[724]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[723]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[722]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[721]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[720]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[719]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[718]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[717]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[716]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[715]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[714]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[713]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[712]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[711]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[710]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[709]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[708]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[707]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[706]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[705]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[704]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[703]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[702]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[701]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[700]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[699]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[698]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[697]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[696]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[695]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[694]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[693]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[692]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[691]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[690]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[689]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[688]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[687]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[686]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[685]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[684]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[683]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[682]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[681]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[680]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[679]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[678]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[677]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[676]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[675]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[674]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[673]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[672]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[671]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[670]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[669]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[668]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[667]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[666]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[665]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[664]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[663]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[662]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[661]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[660]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[659]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[658]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[657]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[656]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[655]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[654]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[653]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[652]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[651]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[650]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[649]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[648]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[647]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[646]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[645]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[644]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[643]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[642]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[641]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[640]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[639]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[638]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[637]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[636]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[635]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[634]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[633]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[632]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[631]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[630]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[629]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[628]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[627]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[626]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[625]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[624]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[623]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[622]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[621]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[620]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[619]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[618]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[617]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[616]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[615]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[614]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[613]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[612]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[611]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[610]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[609]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[608]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[607]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[606]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[605]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[604]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[603]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[602]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[601]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[600]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[599]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[598]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[597]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[596]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[595]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[594]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[593]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[592]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[591]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[590]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[589]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[588]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[587]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[586]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[585]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[584]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[583]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[582]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[581]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[580]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[579]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[578]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[577]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[576]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[575]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[574]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[573]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[572]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[571]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[570]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[569]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[568]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[567]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[566]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[565]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[564]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[563]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[562]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[561]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[560]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[559]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[558]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[557]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[556]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[555]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[554]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[553]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[552]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[551]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[550]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[549]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[548]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[547]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[546]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[545]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[544]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[543]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[542]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[541]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[540]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[539]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[538]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[537]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[536]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[535]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[534]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[533]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[532]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[531]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[530]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[529]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[528]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[527]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[526]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[525]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[524]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[523]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[522]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[521]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[520]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[519]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[518]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[517]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[516]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[515]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[514]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[513]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[512]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[511]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[510]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[509]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[508]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[507]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[506]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[505]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[504]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[503]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[502]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[501]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[500]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[499]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[498]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[497]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[496]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[495]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[494]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[493]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[492]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[491]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[490]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[489]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[488]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[487]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[486]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[485]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[484]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[483]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[482]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[481]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[480]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[479]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[478]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[477]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[476]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[475]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[474]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[473]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[472]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[471]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[470]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[469]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[468]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[467]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[466]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[465]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[464]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[463]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[462]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[461]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[460]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[459]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[458]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[457]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[456]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[455]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[454]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[453]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[452]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[451]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[450]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[449]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[448]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[447]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[446]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[445]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[444]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[443]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[442]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[441]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[440]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[439]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[438]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[437]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[436]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[435]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[434]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[433]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[432]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[431]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[430]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[429]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[428]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[427]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[426]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[425]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[424]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[423]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[422]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[421]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[420]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[419]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[418]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[417]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[416]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[415]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[414]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[413]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[412]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[411]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[410]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[409]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[408]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[407]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[406]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[405]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[404]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[403]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[402]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[401]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[400]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[399]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[398]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[397]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[396]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[395]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[394]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[393]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[392]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[391]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[390]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[389]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[388]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[387]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[386]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[385]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[384]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[383]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[382]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[381]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[380]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[379]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[378]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[377]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[376]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[375]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[374]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[373]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[372]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[371]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[370]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[369]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[368]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[367]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[366]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[365]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[364]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[363]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[362]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[361]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[360]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[359]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[358]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[357]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[356]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[355]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[354]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[353]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[352]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[351]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[350]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[349]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[348]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[347]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[346]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[345]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[344]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[343]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[342]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[341]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[340]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[339]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[338]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[337]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[336]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[335]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[334]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[333]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[332]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[331]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[330]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[329]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[328]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[327]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[326]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[325]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[324]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[323]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[322]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[321]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[320]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[319]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[318]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[317]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[316]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[315]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[314]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[313]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[312]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[311]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[310]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[309]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[308]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[307]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[306]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[305]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[304]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[303]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[302]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[301]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[300]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[299]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[298]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[297]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[296]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[295]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[294]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[293]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[292]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[291]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[290]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[289]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[288]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[287]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[286]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[285]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[284]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[283]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[282]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[281]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[280]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[279]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[278]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[277]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[276]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[275]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[274]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[273]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[272]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[271]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[270]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[269]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[268]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[267]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[266]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[265]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[264]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[263]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[262]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[261]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[260]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[259]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[258]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[257]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[256]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[255]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[254]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[253]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[252]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[251]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[250]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[249]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[248]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[247]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[246]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[245]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[244]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[243]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[242]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[241]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[240]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[239]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[238]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[237]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[236]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[235]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[234]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[233]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[232]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[231]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[230]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[229]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[228]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[227]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[226]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[225]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[224]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[223]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[222]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[221]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[220]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[219]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[218]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[217]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[216]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[215]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[214]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[213]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[212]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[211]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[210]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[209]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[208]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[207]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[206]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[205]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[204]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[203]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[202]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[201]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[200]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[199]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[198]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[197]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[196]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[195]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[194]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[193]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[192]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[191]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[190]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[189]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[188]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[187]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[186]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[185]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[184]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[183]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[182]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[181]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[180]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[179]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[178]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[177]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[176]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[175]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[174]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[173]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[172]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[171]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[170]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[169]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[168]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[167]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[166]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[165]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[164]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[163]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[162]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[161]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[160]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[159]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[158]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[157]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[156]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[155]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[154]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[153]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[152]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[151]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[150]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[149]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[148]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[147]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[146]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[145]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[144]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[143]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[142]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[141]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[140]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[139]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[138]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[137]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[136]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[135]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[134]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[133]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[132]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[131]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[130]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[129]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[128]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[127]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[126]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[125]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[124]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[123]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[122]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[121]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[120]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[119]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[118]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[117]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[116]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[115]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[114]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[113]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[112]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[111]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[110]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[109]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[108]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[107]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[106]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[105]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[104]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[103]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[102]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[101]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[100]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[99]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[98]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[97]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[96]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[95]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[94]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[93]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[92]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[91]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[90]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[89]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[88]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[87]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[86]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[85]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[84]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[83]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[82]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[81]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[80]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[79]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[78]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[77]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[76]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[75]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[74]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[73]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[72]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[71]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[70]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[69]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[68]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[67]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[66]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[65]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[64]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[63]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[62]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[61]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[60]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[59]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[58]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[57]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[56]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[55]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[54]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[53]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[52]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[51]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[50]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[49]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[48]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[47]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[46]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[45]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[44]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[43]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[42]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[41]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[40]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[39]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[38]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[37]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[36]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[35]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[34]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[33]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[32]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[31]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[30]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[29]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[28]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[27]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[26]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[25]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[24]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[23]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[22]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[21]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[20]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[19]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[18]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[17]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[16]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[15]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[14]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[13]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[12]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[11]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[10]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[9]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[8]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[7]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[6]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[5]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[4]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[3]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[2]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[1]' is unconstrained in LPF and will be automatically placed +Warning: IO 'weights_bus[0]' is unconstrained in LPF and will be automatically placed +Warning: IO 'start' is unconstrained in LPF and will be automatically placed +Warning: IO 'rst' is unconstrained in LPF and will be automatically placed +Warning: IO 'done' is unconstrained in LPF and will be automatically placed +Warning: IO 'clk' is unconstrained in LPF and will be automatically placed +Warning: IO 'busy' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[31]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[30]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[29]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[28]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[27]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[26]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[25]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[24]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[23]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[22]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[21]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[20]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[19]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[18]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[17]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[16]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[15]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[14]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[13]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[12]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[11]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[10]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[9]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[8]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[7]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[6]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[5]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[4]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[3]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[2]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[1]' is unconstrained in LPF and will be automatically placed +Warning: IO 'bias_bus[0]' is unconstrained in LPF and will be automatically placed + +Info: Logic utilisation before packing: +Info: Total LUT4s: 34864/43848 79% +Info: logic LUTs: 34864/43848 79% +Info: carry LUTs: 0/43848 0% +Info: RAM LUTs: 0/ 5481 0% +Info: RAMW LUTs: 0/10962 0% + +Info: Total DFFs: 184/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 137 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0xb8be0656 + +Info: Device utilisation: +Info: TRELLIS_IO: 10309/ 245 4207% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 108 0% +Info: MULT18X18D: 0/ 72 0% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 184/ 43848 0% +Info: TRELLIS_COMB: 34865/ 43848 79% +Info: TRELLIS_RAMW: 0/ 5481 0% + +Info: Placed 0 cells based on constraints. +ERROR: Unable to place cell 'weights_bus[6617]$tr_io', no BELs remaining to implement cell type 'TRELLIS_IO' +10309 warnings, 1 error diff --git a/synth/ecp5/p8/report.txt b/synth/ecp5/p8/report.txt new file mode 100644 index 0000000..4ca8fc6 --- /dev/null +++ b/synth/ecp5/p8/report.txt @@ -0,0 +1,275 @@ +Warning: IO 'y_bus[31]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[30]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[29]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[28]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[27]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[26]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[25]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[24]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[23]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[22]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[21]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[20]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[19]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[18]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[17]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[16]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[15]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[14]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[13]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[12]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[11]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[10]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[9]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[8]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[7]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[6]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[5]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[4]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[3]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[2]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[1]' is unconstrained in LPF and will be automatically placed +Warning: IO 'y_bus[0]' is unconstrained in LPF and will be automatically placed +Warning: IO 'start' is unconstrained in LPF and will be automatically placed +Warning: IO 'rst' is unconstrained in LPF and will be automatically placed +Warning: IO 'done' is unconstrained in LPF and will be automatically placed +Warning: IO 'clk' is unconstrained in LPF and will be automatically placed +Warning: IO 'busy' is unconstrained in LPF and will be automatically placed + +Info: Logic utilisation before packing: +Info: Total LUT4s: 737/43848 1% +Info: logic LUTs: 737/43848 1% +Info: carry LUTs: 0/43848 0% +Info: RAM LUTs: 0/ 5481 0% +Info: RAMW LUTs: 0/10962 0% + +Info: Total DFFs: 164/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 143 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0xba108497 + +Info: Device utilisation: +Info: TRELLIS_IO: 37/ 245 15% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 108 0% +Info: MULT18X18D: 0/ 72 0% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 164/ 43848 0% +Info: TRELLIS_COMB: 738/ 43848 1% +Info: TRELLIS_RAMW: 0/ 5481 0% + +Info: Placed 0 cells based on constraints. +Info: Creating initial analytic placement for 316 cells, random placement wirelen = 29789. +Info: at initial placer iter 0, wirelen = 1963 +Info: at initial placer iter 1, wirelen = 1613 +Info: at initial placer iter 2, wirelen = 1586 +Info: at initial placer iter 3, wirelen = 1563 +Info: Running main analytical placer, max placement attempts per cell = 110450. +Info: at iteration #1, type ALL: wirelen solved = 1570, spread = 2941, legal = 3088; time = 0.01s +Info: at iteration #2, type ALL: wirelen solved = 1684, spread = 2706, legal = 2843; time = 0.01s +Info: at iteration #3, type ALL: wirelen solved = 1708, spread = 2620, legal = 2790; time = 0.01s +Info: at iteration #4, type ALL: wirelen solved = 1737, spread = 2552, legal = 2659; time = 0.01s +Info: at iteration #5, type ALL: wirelen solved = 1777, spread = 2535, legal = 2630; time = 0.01s +Info: at iteration #6, type ALL: wirelen solved = 1824, spread = 2651, legal = 2719; time = 0.01s +Info: at iteration #7, type ALL: wirelen solved = 1832, spread = 2550, legal = 2667; time = 0.01s +Info: at iteration #8, type ALL: wirelen solved = 1864, spread = 2610, legal = 2719; time = 0.01s +Info: at iteration #9, type ALL: wirelen solved = 1928, spread = 2544, legal = 2641; time = 0.01s +Info: at iteration #10, type ALL: wirelen solved = 1940, spread = 2863, legal = 2901; time = 0.01s +Info: HeAP Placer Time: 0.10s +Info: of which solving equations: 0.07s +Info: of which spreading cells: 0.01s +Info: of which strict legalisation: 0.00s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 96, wirelen = 2630 +Info: at iteration #5: temp = 0.000000, timing cost = 138, wirelen = 2016 +Info: at iteration #10: temp = 0.000000, timing cost = 108, wirelen = 1947 +Info: at iteration #15: temp = 0.000000, timing cost = 100, wirelen = 1917 +Info: at iteration #17: temp = 0.000000, timing cost = 118, wirelen = 1911 +Info: SA placement time 0.21s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 132.89 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.99 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 6.41 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 4975, 5323) |*****+ +Info: [ 5323, 5671) | +Info: [ 5671, 6019) |****+ +Info: [ 6019, 6367) |*********+ +Info: [ 6367, 6715) |*******+ +Info: [ 6715, 7063) |*******+ +Info: [ 7063, 7411) |******+ +Info: [ 7411, 7759) |*****+ +Info: [ 7759, 8107) |*******************+ +Info: [ 8107, 8455) |*****************+ +Info: [ 8455, 8803) |***************************+ +Info: [ 8803, 9151) |************+ +Info: [ 9151, 9499) |***********+ +Info: [ 9499, 9847) |**************************+ +Info: [ 9847, 10195) |****************************************************+ +Info: [ 10195, 10543) |************************************************************ +Info: [ 10543, 10891) |***********************+ +Info: [ 10891, 11239) |**************************************+ +Info: [ 11239, 11587) |************************************+ +Info: [ 11587, 11935) |*****+ +Info: Checksum: 0xf1666ddb +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 2723 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 341 658 | 341 658 | 2076| 0.08 0.08| +Info: 2000 | 540 1426 | 199 768 | 1288| 0.04 0.12| +Info: 3000 | 602 2280 | 62 854 | 350| 0.03 0.15| +Info: 3372 | 625 2485 | 23 205 | 0| 0.07 0.22| +Info: Routing complete. +Info: Router1 time 0.22s +Info: Checksum: 0x3dbc8311 + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q.Q +Info: routing 0.84 1.24 Net u_layer.GEN_NEURON[1].u_neuron.acc[2] (21,30) -> (20,30) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_ALUT_LUT4_Z.D +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42 +Info: logic 0.18 1.42 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_ALUT_LUT4_Z.F +Info: routing 0.00 1.42 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_ALUT (20,30) -> (20,30) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z.F1 +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24 +Info: logic 0.13 1.54 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.78 2.33 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D[6] (20,30) -> (22,27) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.19 2.52 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.58 3.10 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_Z[6] (22,27) -> (21,26) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.19 3.29 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.00 3.29 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1 (21,26) -> (21,26) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72 +Info: logic 0.18 3.47 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.53 4.00 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z[6] (21,26) -> (20,27) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.19 4.20 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.53 4.73 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z[6] (20,27) -> (18,27) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.19 4.92 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.68 5.60 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z[3] (18,27) -> (18,28) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.31 5.91 Source u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.00 5.91 Net u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0 (18,28) -> (18,28) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52 +Info: logic 0.18 6.09 Source u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.00 6.09 Net u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0 (18,28) -> (18,28) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68 +Info: logic 0.18 6.27 Source u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.51 6.77 Net u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI (18,28) -> (18,27) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3.M +Info: setup 0.00 6.77 Source u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3.M +Info: 2.32 ns logic, 4.46 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': +Info: type curr total name +Info: source 0.00 0.00 Source rst$tr_io.O +Info: routing 2.64 2.64 Net rst$TRELLIS_IO_IN (44,0) -> (20,21) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_D.C +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:9.11-9.14 +Info: logic 0.18 2.82 Source u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_D.F +Info: routing 1.19 4.01 Net u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_D_Z (20,21) -> (16,30) +Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_29.LSR +Info: setup 0.29 4.29 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_29.LSR +Info: 0.47 ns logic, 3.83 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q.Q +Info: routing 3.92 4.31 Net y_bus[0]$TRELLIS_IO_OUT (31,7) -> (90,29) +Info: Sink y_bus[2]$tr_io.I +Info: Defined in: +Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:6.26-6.31 +Info: 0.40 ns logic, 3.92 ns routing + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 147.62 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.29 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.31 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 5726, 6025) |**+ +Info: [ 6025, 6324) |******+ +Info: [ 6324, 6623) |*********+ +Info: [ 6623, 6922) |****+ +Info: [ 6922, 7221) |**********+ +Info: [ 7221, 7520) |********+ +Info: [ 7520, 7819) |***********+ +Info: [ 7819, 8118) |***+ +Info: [ 8118, 8417) |*******+ +Info: [ 8417, 8716) |***********************+ +Info: [ 8716, 9015) |****************************+ +Info: [ 9015, 9314) |****************+ +Info: [ 9314, 9613) |******************+ +Info: [ 9613, 9912) |**************+ +Info: [ 9912, 10211) |********+ +Info: [ 10211, 10510) |******************************************************+ +Info: [ 10510, 10809) |***************************************************+ +Info: [ 10809, 11108) |*********************************+ +Info: [ 11108, 11407) |************************************************************ +Info: [ 11407, 11706) |**************+ +37 warnings, 0 errors + +Info: Program finished normally. diff --git a/synth/ecp5/p8/synth.log b/synth/ecp5/p8/synth.log new file mode 100644 index 0000000..9f65ec1 --- /dev/null +++ b/synth/ecp5/p8/synth.log @@ -0,0 +1 @@ +ERROR: Module `top' not found! diff --git a/synth/ecp5/p8/synth.ys b/synth/ecp5/p8/synth.ys new file mode 100644 index 0000000..42a167d --- /dev/null +++ b/synth/ecp5/p8/synth.ys @@ -0,0 +1,20 @@ +read_verilog -sv \ +/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v \ +/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v \ +/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v \ +/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v \ +/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v + +hierarchy -top top + +proc +flatten +opt +memory +opt +techmap +opt +abc -g simple +clean + +synth_ecp5 -top top -json /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.json diff --git a/synth/ecp5/p8/top.config b/synth/ecp5/p8/top.config new file mode 100644 index 0000000..73e17af --- /dev/null +++ b/synth/ecp5/p8/top.config @@ -0,0 +1,11777 @@ +.device LFE5U-45F + +.comment Part: LFE5U-45F-8CABGA381 + +.tile CIB_R10C30:CIB_EBR +arc: N1_V02N0201 N1_V01S0000 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R11C1:CIB_LR +arc: JA0 E1_H02W0501 +arc: JA3 E1_H02W0701 +arc: S1_V02S0501 E3_H06W0303 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R11C89:CIB_LR +arc: JA0 N1_V02S0701 +arc: S1_V02S0701 W1_H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R13C1:CIB_LR +arc: JA3 N1_V02S0501 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N3_V06S0103 +enum: CIB.JB3MUX 0 + +.tile CIB_R13C89:CIB_LR +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R16C89:CIB_LR +arc: JA0 H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R19C1:CIB_LR +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 + +.tile CIB_R1C15:CIB +arc: JA0 H02W0501 +arc: S3_V06S0203 E3_H06W0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C16:CIB +arc: S3_V06S0003 E3_H06W0003 +arc: W1_H02W0501 S1_V02N0501 + +.tile CIB_R1C18:CIB +arc: S3_V06S0203 H06W0203 + +.tile CIB_R1C19:CIB +arc: S3_V06S0003 H06W0003 + +.tile CIB_R1C20:CIB +arc: JA0 V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C21:CIB +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 + +.tile CIB_R1C22:CIB +arc: E1_H02E0701 S1_V02N0701 +arc: S3_V06S0003 JQ0 +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C23:CIB +arc: E1_H02E0701 V01N0101 +arc: JA0 H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C24:CIB +arc: S1_V02S0101 H06W0103 +arc: S3_V06S0103 H06W0103 + +.tile CIB_R1C25:CIB +arc: JA0 W1_H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C27:CIB +arc: W3_H06W0103 E3_H06W0103 + +.tile CIB_R1C29:CIB +arc: JA0 S1_V02N0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C31:CIB +arc: E1_H02E0301 V06N0003 + +.tile CIB_R1C32:CIB +arc: H00L0100 H02E0301 +arc: JA0 H00L0100 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C33:CIB +arc: S3_V06S0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0003 + +.tile CIB_R1C39:CIB +arc: W3_H06W0003 E3_H06W0003 + +.tile CIB_R1C41:CIB +arc: E1_H02E0701 V06N0203 + +.tile CIB_R1C42:CIB +arc: E1_H01E0101 JQ0 +arc: E1_H02E0501 V02N0501 + +.tile CIB_R1C43:CIB +arc: E3_H06E0303 H01E0101 +arc: JA0 W1_H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C44:CIB +arc: JA0 W1_H02E0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C45:CIB +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C47:CIB +arc: JA0 E1_H02W0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C48:CIB +arc: JD7 E1_H01W0100 + +.tile CIB_R1C49:CIB +arc: H01W0100 W3_H06E0303 +arc: JA0 V02N0701 +arc: W1_H02W0701 V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C50:CIB +arc: JA0 V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C64:CIB +arc: E1_H02E0701 S3_V06N0203 + +.tile CIB_R1C66:CIB +arc: E1_H02E0701 W1_H02E0701 + +.tile CIB_R1C67:CIB +arc: JA0 H02E0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R25C1:CIB_LR +arc: S1_V02S0701 N3_V06S0203 +arc: V01S0000 N3_V06S0103 + +.tile CIB_R26C1:CIB_LR +arc: JA0 E1_H02W0501 +arc: JA3 E1_H02W0501 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0203 N1_V01S0000 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R26C89:CIB_LR +arc: JA3 V02N0501 +enum: CIB.JB3MUX 0 + +.tile CIB_R27C1:CIB_LR +arc: S1_V02S0701 N1_V02S0701 + +.tile CIB_R27C89:CIB_LR +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0701 H02E0701 + +.tile CIB_R28C1:CIB_LR +arc: JA0 N1_V02S0501 +arc: JA3 N1_V02S0501 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R28C89:CIB_LR +arc: JA3 W1_H02E0701 +enum: CIB.JB3MUX 0 + +.tile CIB_R29C1:CIB_LR +arc: JA0 N1_V02S0701 +arc: JA3 N1_V02S0701 +arc: S1_V02S0501 H06W0303 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R29C89:CIB_LR +arc: JA3 N1_V02S0701 +arc: S1_V02S0501 H06E0303 +enum: CIB.JB3MUX 0 + +.tile CIB_R31C1:CIB_LR +arc: JA0 N1_V02S0501 +arc: JA3 E1_H02W0501 +arc: S1_V02S0701 V01N0101 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R31C89:CIB_LR +arc: JA3 N1_V02S0501 +enum: CIB.JB3MUX 0 + +.tile CIB_R32C1:CIB_LR +arc: JA0 V02S0701 +arc: JA3 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +enum: CIB.JB0MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R34C1:CIB_LR_S +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R5C1:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C89:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C18:CIB +arc: JA0 N1_V02S0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R70C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C69:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C70:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C71:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C72:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C73:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C74:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C75:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C76:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C77:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C78:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C79:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R70C80:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C87:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R7C1:CIB_LR +arc: S3_V06S0103 E3_H06W0103 + +.tile CIB_R7C89:CIB_LR +arc: S1_V02S0701 W1_H02E0701 + +.tile CIB_R9C89:CIB_LR +arc: S1_V02S0701 N1_V02S0701 + +.tile MIB_R0C15:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C20:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C22:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C23:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C25:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C29:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C32:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C3:BANKREF0 +enum: BANK.VCCIO 3V3 + +.tile MIB_R0C40:TMID_0 +arc: G_TDCC0CLKI G_JTRQPCLKCIB1 + +.tile MIB_R0C42:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C43:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C44:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C45:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C47:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C49:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C50:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C67:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C87:BANKREF1 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C12:EBR_SPINE_UL1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C30:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C40:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R10C41:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R10C90:BANKREF2 +enum: BANK.VCCIO 3V3 + +.tile MIB_R11C0:PICL0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R11C90:PICR0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R12C0:PICL1 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R12C90:PICR1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R13C0:PICL2 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R13C90:PICR2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R15C90:PICR1_DQS0 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R16C90:PICR2_DQS1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C15:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C20:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C22:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C23:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C25:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C29:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C32:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C42:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C43:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C44:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C45:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C47:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C49:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C50:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C67:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R26C0:PICL0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R26C90:PICR0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R27C0:PICL1_DQS0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R27C90:PICR1_DQS0 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R28C0:PICL2_DQS1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R28C90:PICR2_DQS1 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R29C0:PICL0_DQS2 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R29C90:PICR0_DQS2 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R30C0:PICL1_DQS3 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R30C90:PICR1_DQS3 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R31C0:PICL2 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R31C90:PICR2 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R32C0:PICL0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R33C0:PICL1 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R34C0:MIB_CIB_LR +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R58C40:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R58C41:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R71C18:SPICB0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R71C3:BANKREF8 +enum: BANK.VCCIO 3V3 + +.tile MIB_R71C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile R11C11:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R11C13:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R11C15:PLC2 +arc: E1_H02E0401 S1_V02N0401 + +.tile R11C17:PLC2 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0701 +arc: C0 E1_H01W0000 +arc: C1 W1_H02E0401 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0201 +arc: E1_H01E0001 F0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0100 F1 +arc: V01S0000 F0 +word: SLICEA.K1.INIT 1111000011111111 +word: SLICEA.K0.INIT 1010000010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R11C18:PLC2 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 H02W0001 +arc: A2 F5 +arc: A5 E1_H01W0000 +arc: B5 H00L0000 +arc: C1 H00L0100 +arc: C5 V00T0000 +arc: C7 H01E0001 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D5 H00L0100 +arc: D7 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 F7 +arc: H01W0000 Q2 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000111100000000 +word: SLICEB.K0.INIT 0101010110101010 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000111111110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R11C19:PLC2 +arc: H00R0100 H02E0501 +arc: A1 H00L0100 +arc: A2 H00L0100 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A7 V00T0100 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: B7 V00T0000 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 E1_H02W0601 +arc: C4 V00T0100 +arc: C5 H02W0401 +arc: C7 E1_H02W0401 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H02E0001 +arc: D4 H02E0001 +arc: D5 W1_H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0501 F7 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: LSR1 H02W0501 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 F2 +arc: V00T0000 Q0 +arc: V00T0100 Q1 +arc: V01S0000 F2 +arc: W1_H02W0001 Q0 +arc: W3_H06W0303 F5 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 0110101010101010 +word: SLICEB.K0.INIT 0000000001000000 +word: SLICEA.K0.INIT 0011110011110000 +word: SLICED.K1.INIT 0000000000010000 +word: SLICEC.K0.INIT 0000000000000101 +word: SLICEC.K1.INIT 1000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R11C20:PLC2 +arc: E1_H02E0601 H01E0001 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: V00B0100 V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 V01N0101 +arc: B1 V01N0001 +arc: C1 V02N0601 +arc: D1 V02N0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: S1_V02S0301 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R11C21:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 V02N0201 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0501 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 H02E0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: A0 E1_H02W0701 +arc: A1 V01N0101 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0701 +arc: A4 V00T0000 +arc: A5 V00T0000 +arc: A6 E1_H02W0701 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C7 V00B0100 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: E3_H06E0203 Q7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: LSR1 V00T0100 +arc: M0 H02E0601 +arc: M1 H02W0001 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H02W0001 +arc: M6 V00B0000 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +word: SLICEA.K0.INIT 1001000101010101 +word: SLICEA.K1.INIT 0100001100110011 +word: SLICEB.K0.INIT 0101010101010100 +word: SLICEB.K1.INIT 0101010101010001 +word: SLICEC.K0.INIT 1010010100001111 +word: SLICEC.K1.INIT 1010010100001111 +word: SLICED.K0.INIT 0101010101010101 +word: SLICED.K1.INIT 0000111100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R11C22:PLC2 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 H02E0201 +arc: H00R0000 V02N0401 +arc: H00R0100 V02N0701 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 H02E0601 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 V01N0001 +arc: A0 H00L0000 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0501 +arc: A3 V00T0000 +arc: A4 E1_H01W0000 +arc: A5 E1_H01W0000 +arc: B0 S1_V02N0101 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: B3 S1_V02N0301 +arc: C0 E1_H01W0000 +arc: C1 H02W0401 +arc: C2 V02N0601 +arc: C3 H02W0401 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0401 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: LSR1 H02E0501 +arc: M0 H02E0601 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0701 Q7 +word: SLICED.K1.INIT 0000000011111111 +word: SLICED.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 1000001100110011 +word: SLICEA.K1.INIT 0001010110010101 +word: SLICEB.K0.INIT 0101010101010100 +word: SLICEB.K1.INIT 0011001000110011 +word: SLICEC.K0.INIT 1010000001011111 +word: SLICEC.K1.INIT 1010000001011111 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R11C23:PLC2 +arc: H00L0100 V02N0301 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 V02N0701 +arc: B0 V01N0001 +arc: B1 S1_V02N0301 +arc: C0 H02E0601 +arc: C1 H00L0100 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0011111111000000 +word: SLICEA.K1.INIT 1111111111111110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R11C24:PLC2 +arc: W1_H02W0201 N1_V02S0201 + +.tile R11C27:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R11C33:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R11C39:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R11C3:PLC2 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 E1_H02W0601 + +.tile R11C45:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R11C51:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R11C57:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R11C5:PLC2 +arc: W1_H02W0601 E3_H06W0303 + +.tile R11C63:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R11C69:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R11C75:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R11C7:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R11C81:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R11C87:PLC2 +arc: E1_H02E0701 W3_H06E0203 + +.tile R12C17:PLC2 +arc: B0 V02N0101 +arc: C0 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0000110011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R12C18:PLC2 +arc: E1_H02E0401 H01E0001 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: A1 V01N0101 +arc: A6 H00L0000 +arc: B1 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: C1 H00L0000 +arc: C6 V01N0101 +arc: D1 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M1 H00L0100 +arc: M2 E1_H02W0601 +arc: M3 H02W0201 +arc: M4 E1_H02W0401 +arc: M5 H00L0100 +arc: M6 E1_H02W0401 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R12C19:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: H00L0000 V02S0201 +arc: H00L0100 H02W0301 +arc: N1_V02N0301 S3_V06N0003 +arc: S1_V02S0001 V01N0001 +arc: W1_H02W0201 N1_V01S0000 +arc: A1 V02N0701 +arc: B1 E1_H01W0100 +arc: C1 E1_H01W0000 +arc: D1 H02W0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H00L0100 +arc: M2 H02W0601 +arc: M3 H00L0000 +arc: M4 H02W0401 +arc: M5 H00L0100 +arc: M6 H02W0401 +arc: S1_V02S0101 F3 +arc: V01S0000 F3 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R12C20:PLC2 +arc: E1_H02E0501 V02N0501 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0401 E1_H01W0000 +arc: V00T0100 V02N0501 +arc: A0 F5 +arc: A1 F5 +arc: A2 F5 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C0 N1_V01N0001 +arc: C2 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 E1_H01E0101 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: E1_H01E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0601 Q4 +arc: V00B0000 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 Q4 +word: SLICEC.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 0101101010101010 +word: SLICEA.K1.INIT 0101010110101010 +word: SLICEA.K0.INIT 0101101011110000 +word: SLICEB.K1.INIT 0011001111001100 +word: SLICEB.K0.INIT 0111111110000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R12C21:PLC2 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 V01N0101 +arc: V00T0100 V02S0501 +arc: A5 V02N0101 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B3 E1_H02W0301 +arc: B5 V02N0501 +arc: B7 V02N0701 +arc: C1 V02S0601 +arc: C2 H00L0000 +arc: C5 E1_H01E0101 +arc: C7 V02N0001 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V02N0201 +arc: D3 V02S0001 +arc: D5 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: LSR0 H02E0501 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q2 +arc: V00T0000 Q0 +arc: V01S0000 F7 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0011001111001100 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K1.INIT 1000000100000011 +word: SLICEA.K1.INIT 0000000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R12C22:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 H02E0201 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: V00T0000 V02N0601 +arc: V00T0100 H02W0101 +arc: A1 S1_V02N0701 +arc: A5 V00T0100 +arc: A7 H00L0000 +arc: B1 E1_H01W0100 +arc: B5 S1_V02N0501 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C5 V00T0000 +arc: C7 V02N0001 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D5 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: N1_V02N0701 F5 +arc: S3_V06S0203 F7 +arc: V01S0000 F7 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 1000000000000111 +word: SLICEA.K0.INIT 0000000000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R12C23:PLC2 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 S1_V02N0401 +arc: A1 H02E0501 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 S1_V02N0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H01E0101 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0110110011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R13C10:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R13C15:PLC2 +arc: N1_V02N0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 + +.tile R13C16:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R13C17:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 + +.tile R13C18:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0000 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0100 E1_H02W0301 +arc: B1 Q1 +arc: C1 H02W0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D1 V00T0100 +arc: E1_H01E0101 Q1 +arc: F1 F1_SLICE +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q1 +arc: V01S0100 Q1 +word: SLICEA.K1.INIT 0000111100001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R13C19:PLC2 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 V02S0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 W1_H02E0001 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 V02N0501 +arc: A3 V00B0000 +arc: A4 N1_V01S0100 +arc: A5 V02N0301 +arc: A7 E1_H02W0701 +arc: B1 S1_V02N0301 +arc: B3 S1_V02N0101 +arc: B4 H00R0000 +arc: B5 N1_V01S0000 +arc: C1 V02N0601 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: C7 V02S0001 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D3 H02E0201 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: LSR1 V00B0100 +arc: M0 H02E0601 +arc: M1 H00L0100 +arc: M2 H02E0601 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: V00B0000 Q4 +arc: V00B0100 F7 +arc: V01S0000 Q4 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0110110011001100 +word: SLICED.K1.INIT 1010101011111010 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R13C20:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 V02N0201 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02E0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0501 H01E0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H01E0001 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 H01E0101 +arc: A0 H00L0000 +arc: A1 H00L0000 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0101 +arc: C0 V02N0401 +arc: C1 V02N0401 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R13C21:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02S0201 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0701 N3_V06S0203 +arc: A1 V02N0501 +arc: A2 V02N0701 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: C1 H00L0000 +arc: C3 H00L0000 +arc: C4 S1_V02N0201 +arc: C5 S1_V02N0201 +arc: C6 S1_V02N0201 +arc: C7 S1_V02N0201 +arc: D0 V02S0001 +arc: D1 S1_V02N0001 +arc: D2 V02S0001 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H02E0001 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M5 H02E0001 +arc: M6 V00T0000 +arc: N1_V02N0101 F3 +word: SLICED.K1.INIT 0000000000001111 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEC.K1.INIT 0000000000001111 +word: SLICEC.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 0000000001010101 +word: SLICEA.K1.INIT 1000000100000101 +word: SLICEA.K0.INIT 0000000000110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R13C22:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 H02E0401 +arc: V00B0100 V02N0301 +arc: A3 S1_V02N0501 +arc: B3 W1_H02E0101 +arc: C3 H02E0601 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D3 H01E0101 +arc: E3_H06E0203 Q7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: LSR1 V00B0000 +arc: M0 V00B0100 +arc: M1 E1_H02W0001 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICED.K1.INIT 1111111111111111 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0111111111111111 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R13C23:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 W3_H06E0203 +arc: S1_V02S0001 H06E0003 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: A1 V02S0501 +arc: B1 V02S0101 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D1 V02S0201 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: LSR1 W1_H02E0501 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H02E0201 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 Q7 +word: SLICEB.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +word: SLICEA.K1.INIT 0111100011110000 +word: SLICEA.K0.INIT 1111000011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R13C24:PLC2 +arc: W1_H02W0001 H01E0001 + +.tile R13C28:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R13C34:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R13C40:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R13C46:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R13C4:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R13C52:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R13C58:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R13C64:PLC2 +arc: E3_H06E0103 W3_H06E0103 +arc: N3_V06N0103 W3_H06E0103 + +.tile R13C70:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R13C76:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R13C82:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R13C88:PLC2 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 W3_H06E0303 + +.tile R14C18:PLC2 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 E1_H02W0701 +arc: V00T0100 H02W0101 +arc: B1 Q1 +arc: C0 N1_V01N0001 +arc: C1 N1_V01N0001 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K1.INIT 0011110011001100 +word: SLICEA.K0.INIT 0000111111110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R14C19:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 V02S0501 +arc: A1 V01N0101 +arc: B1 V01N0001 +arc: C1 V02N0601 +arc: D1 N1_V01S0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H01E0001 +arc: M1 H02E0001 +arc: M2 V00T0100 +arc: M3 H00L0100 +arc: M4 V00T0100 +arc: M5 H02E0001 +arc: M6 V00T0100 +arc: V01S0000 F3 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R14C20:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 H02E0401 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0701 V02S0701 +arc: A1 V02N0501 +arc: B1 W1_H02E0301 +arc: C1 H02E0601 +arc: D1 V02N0201 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R14C21:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 V01N0101 +arc: A1 V01N0101 +arc: B1 V01N0001 +arc: C1 V02N0601 +arc: D1 S1_V02N0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 H00L0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: N1_V01N0001 F3 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R14C22:PLC2 +arc: H00L0100 H02E0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H01E0001 +arc: V00T0000 H02E0201 +arc: A1 V01N0101 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: D1 H02W0001 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0000 +arc: M1 H00L0100 +arc: M2 V00T0000 +arc: N1_V02N0301 F1 +word: SLICEB.K1.INIT 0000001100000011 +word: SLICEB.K0.INIT 0000001100000011 +word: SLICEA.K1.INIT 1000000000010011 +word: SLICEA.K0.INIT 0000001100000011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R14C23:PLC2 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 N1_V02S0101 +arc: B0 H01W0100 +arc: C0 V02N0401 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0011110011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R15C16:PLC2 +arc: N3_V06N0303 S3_V06N0203 + +.tile R15C19:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0601 E1_H01W0000 +arc: V00T0100 N1_V02S0501 +arc: A0 F7 +arc: A3 N1_V02S0701 +arc: C0 E1_H01W0000 +arc: C7 E1_H01E0101 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 V01S0100 +arc: D7 H00R0100 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 Q3 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +arc: V01S0100 Q3 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 0101111110100000 +word: SLICEB.K1.INIT 0101010110101010 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R15C20:PLC2 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: V00B0100 H02E0501 +arc: V00T0000 N1_V02S0401 +arc: B1 Q1 +arc: C0 H00L0000 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: D2 Q2 +arc: E1_H01E0001 Q1 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0011110011001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R15C21:PLC2 +arc: E1_H02E0101 V06S0103 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: V00T0100 N1_V02S0501 +arc: A0 E1_H01E0001 +arc: A2 F5 +arc: A4 F5 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B5 H02E0101 +arc: B7 H02E0101 +arc: C0 N1_V01S0100 +arc: C5 W1_H02E0401 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D4 H01W0000 +arc: D5 H02E0201 +arc: D6 H01W0000 +arc: D7 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q2 +arc: LSR0 V00T0100 +arc: M6 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 F6 +arc: V01S0000 F4 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICEA.K0.INIT 0000111100001000 +word: SLICED.K1.INIT 1000000100000101 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEB.K0.INIT 0101010110101010 +word: SLICEC.K1.INIT 1100000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R15C22:PLC2 +arc: E1_H02E0401 V06S0203 +arc: H00R0000 H02W0601 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H01W0000 +arc: V00T0000 H02W0001 +arc: B0 H02E0101 +arc: C0 H00L0000 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0011110011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R15C23:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 H02E0401 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0601 V02S0601 +arc: C0 H02E0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0000111111110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R16C20:PLC2 +arc: E1_H02E0301 V06S0003 + +.tile R16C21:PLC2 +arc: H00R0000 E1_H02W0601 +arc: C0 N1_V01N0001 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: F0 F0_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000111111110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R16C23:PLC2 +arc: W1_H02W0601 N1_V02S0601 + +.tile R16C88:PLC2 +arc: E1_H02E0501 V06S0303 + +.tile R18C16:PLC2 +arc: S3_V06S0003 H06W0003 + +.tile R18C19:PLC2 +arc: S1_V02S0001 E1_H01W0000 +arc: C0 E1_H01W0000 +arc: C1 V02N0601 +arc: C2 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 V02N0001 +arc: D2 F0 +arc: E1_H01E0001 F2 +arc: E1_H02E0201 F2 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S1_V02S0201 F2 +arc: S3_V06S0003 F0 +arc: V00T0100 F1 +arc: W3_H06W0003 F0 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 1111000011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R18C20:PLC2 +arc: H00L0000 H02E0201 +arc: S1_V02S0201 H01E0001 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: A0 V02N0501 +arc: A2 V00T0000 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 V02N0101 +arc: C0 H00L0100 +arc: C1 H00L0100 +arc: C2 H00L0100 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 V02N0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F2 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V00T0000 Q0 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0111111110000000 +word: SLICEA.K1.INIT 0011110011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R18C22:PLC2 +arc: S3_V06S0003 H06E0003 + +.tile R19C15:PLC2 +arc: S3_V06S0003 N3_V06S0303 + +.tile R19C18:PLC2 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 + +.tile R19C19:PLC2 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: B1 Q1 +arc: CE0 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0000 Q1 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0011001111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C20:PLC2 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0501 H01E0101 +arc: S1_V02S0101 E1_H02W0101 +arc: C0 N1_V01N0001 +arc: CE0 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: F0 F0_SLICE +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0000111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R19C21:PLC2 +arc: S1_V02S0501 N3_V06S0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N3_V06S0303 + +.tile R19C22:PLC2 +arc: W1_H02W0101 N3_V06S0103 + +.tile R19C23:PLC2 +arc: N3_V06N0003 S1_V02N0301 + +.tile R19C88:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R20C19:PLC2 +arc: N1_V02N0001 N1_V01S0000 + +.tile R20C20:PLC2 +arc: N1_V02N0201 V01N0001 + +.tile R21C14:PLC2 +arc: S3_V06S0003 E3_H06W0003 + +.tile R21C16:PLC2 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0103 H06W0103 + +.tile R21C19:PLC2 +arc: E1_H02E0001 V06S0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: W3_H06W0103 E1_H01W0100 + +.tile R21C20:PLC2 +arc: A3 H02W0501 +arc: B0 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D3 V01S0100 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: V01S0100 Q0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000110011111100 +word: SLICEB.K1.INIT 1010101011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R21C21:PLC2 +arc: N1_V02N0301 H01E0101 +arc: S3_V06S0303 N1_V02S0501 +arc: W1_H02W0501 N1_V02S0501 + +.tile R21C23:PLC2 +arc: N1_V02N0301 H06E0003 + +.tile R23C20:PLC2 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0101 + +.tile R24C14:PLC2 +arc: S1_V02S0601 E3_H06W0303 + +.tile R24C16:PLC2 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0103 N3_V06S0003 + +.tile R24C17:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: S3_V06S0303 H06W0303 + +.tile R24C18:PLC2 +arc: H00R0000 E1_H02W0601 +arc: S1_V02S0301 H02W0301 +arc: B0 H02W0301 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 1100110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R24C19:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: W3_H06W0103 E1_H01W0100 + +.tile R24C20:PLC2 +arc: E1_H02E0301 V06S0003 +arc: H00L0000 H02E0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0003 V06S0003 +arc: A0 H00L0000 +arc: B0 V01N0001 +arc: C0 V02N0401 +arc: C6 V02S0001 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D6 H02E0001 +arc: E1_H02E0401 F6 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F6 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0401 F6 +arc: S3_V06S0303 F6 +arc: V01S0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0601 F6 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0010001000100000 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R24C21:PLC2 +arc: H00R0000 H02E0601 +arc: S1_V02S0001 W1_H02E0001 +arc: B0 H02W0301 +arc: C0 V02N0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0000110011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C22:PLC2 +arc: H00R0000 W1_H02E0401 +arc: N1_V01N0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0003 +arc: W1_H02W0301 N3_V06S0003 +arc: B0 H02W0301 +arc: C0 N1_V01N0001 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0011000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R24C23:PLC2 +arc: W1_H02W0301 V01N0101 + +.tile R25C14:PLC2 +arc: E1_H02E0301 S1_V02N0301 + +.tile R25C15:PLC2 +arc: S3_V06S0003 N3_V06S0003 + +.tile R25C16:PLC2 +arc: S1_V02S0301 E1_H02W0301 +arc: A1 F5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 V01S0000 +arc: C0 V02N0401 +arc: CE0 V02S0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D5 V02N0401 +arc: E1_H02E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0011110000000000 +word: SLICEA.K1.INIT 0110011000000000 +word: SLICEC.K1.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R25C17:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0100 V02S0501 +arc: V00B0100 V02S0301 +arc: A0 H00L0000 +arc: B0 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0010001000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C18:PLC2 +arc: H00L0100 V02S0301 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0301 N1_V01S0100 +arc: A0 H00L0100 +arc: B0 H02W0101 +arc: C0 V02N0601 +arc: CE0 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000101000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R25C19:PLC2 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0401 +arc: V00B0000 V02N0201 +arc: W1_H02W0601 V01N0001 +arc: A1 S1_V02N0501 +arc: B1 V02S0301 +arc: C1 S1_V02N0401 +arc: D1 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00L0100 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: V01S0000 F3 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R25C20:PLC2 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0401 E1_H01W0000 +arc: S1_V02S0001 H02W0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 V01N0101 +arc: B1 V02N0101 +arc: C1 V02N0401 +arc: D1 N1_V01S0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M3 H00L0100 +arc: M4 V00B0100 +arc: M5 H02W0001 +arc: M6 V00B0100 +arc: N1_V01N0001 F3 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: V01S0000 F3 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R25C21:PLC2 +arc: H00R0100 V02N0701 +arc: N1_V02N0401 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: W1_H02W0001 N1_V01S0000 +arc: A1 V02N0501 +arc: B1 V02N0101 +arc: C1 V02N0601 +arc: D1 S1_V02N0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: M3 E1_H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: W1_H02W0301 F3 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R25C22:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 S1_V02N0701 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 V02N0301 +arc: A1 V01N0101 +arc: B1 E1_H01W0100 +arc: C1 S1_V02N0401 +arc: D1 N1_V01S0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00B0100 +arc: M1 E1_H02W0001 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: V01S0000 F3 +arc: V01S0100 F3 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R25C23:PLC2 +arc: H00R0000 H02E0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0201 S1_V02N0201 +arc: A0 H00L0000 +arc: A2 F5 +arc: B0 H02E0301 +arc: B2 S1_V02N0101 +arc: C0 H02E0601 +arc: C5 V02N0001 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 H02E0001 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0101 F2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0501 F5 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1000100000000000 +word: SLICEA.K0.INIT 0100100010001000 +word: SLICEC.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R25C24:PLC2 +arc: W1_H02W0001 S1_V02N0001 + +.tile R25C88:PLC2 +arc: S1_V02S0701 N3_V06S0203 + +.tile R26C14:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 N1_V02S0601 + +.tile R26C15:PLC2 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 H02E0601 +arc: S1_V02S0201 H06W0103 +arc: B0 E1_H02W0101 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: E1_H02E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 1100110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R26C16:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 H02W0501 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0100 V02S0301 +arc: A1 V02N0701 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B1 V02S0301 +arc: C1 N1_V01S0100 +arc: C4 V00B0100 +arc: D0 V00B0100 +arc: D1 V02S0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 E1_H02W0601 +arc: M1 H00R0100 +arc: M2 E1_H02W0601 +arc: M3 E1_H02W0201 +arc: M4 E1_H02W0401 +arc: M5 H00R0100 +arc: M6 E1_H02W0401 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0110110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1010101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R26C17:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 H02W0601 +arc: N1_V02N0201 H01E0001 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0501 N1_V01S0100 +arc: A1 H02E0501 +arc: B1 V00B0000 +arc: C1 N1_V02S0601 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 W1_H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 H02E0601 +arc: M1 H00R0000 +arc: M2 H02E0601 +arc: M3 E1_H02W0201 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 H02E0401 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: V01S0000 F3 +arc: W1_H02W0101 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0111111110000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R26C18:PLC2 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 W1_H02E0701 +arc: B1 V02S0301 +arc: C1 N1_V01S0100 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F1 +arc: M0 V00B0100 +arc: M1 E1_H02W0001 +arc: M2 V00B0100 +arc: S1_V02S0301 F1 +arc: S3_V06S0103 F1 +arc: V01S0000 F1 +arc: W1_H02W0301 F1 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0110101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R26C19:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0203 H01E0001 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0201 N1_V01S0000 +arc: A1 V02N0701 +arc: B1 E1_H01W0100 +arc: C1 V02N0401 +arc: D1 S1_V02N0001 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00T0000 +arc: M1 E1_H02W0001 +arc: M2 V00T0000 +arc: M3 E1_H02W0201 +arc: M4 V00T0000 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: N1_V01N0001 F3 +arc: S1_V02S0101 F3 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R26C20:PLC2 +arc: H00L0000 H02E0001 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 H01E0001 +arc: A1 F7 +arc: A3 F7 +arc: B0 F3 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B6 F3 +arc: C0 N1_V01N0001 +arc: C2 H00L0000 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 V00T0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: S1_V02S0401 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0011000011000000 +word: SLICED.K0.INIT 1100000011000000 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEA.K0.INIT 0011110000000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0110011000000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C21:PLC2 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 V01N0001 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 S1_V02N0301 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 E1_H02W0001 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 V00T0000 +arc: M5 E1_H02W0001 +arc: M6 V00T0000 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R26C22:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V02N0201 +arc: H00R0000 N1_V02S0401 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0001 N1_V01S0000 +arc: A0 E1_H01E0001 +arc: A1 H02W0501 +arc: B0 V01N0001 +arc: B1 N1_V02S0301 +arc: C0 N1_V01S0100 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V01S0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q0 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: S1_V02S0301 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0000111000000000 +word: SLICEA.K1.INIT 0100010010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R26C23:PLC2 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 V01N0001 +arc: V00T0100 H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 V02S0501 +arc: A1 H01E0001 +arc: A6 V02N0101 +arc: B1 V02N0101 +arc: B6 N1_V01S0000 +arc: C1 N1_V01S0100 +arc: C6 H01E0001 +arc: D1 H02E0001 +arc: D6 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +arc: M3 H02E0201 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M6 V00T0100 +arc: W1_H02W0101 F3 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R26C2:PLC2 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: H01W0100 F2 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R26C3:PLC2 +arc: W1_H02W0501 H01E0101 + +.tile R27C14:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 + +.tile R27C15:PLC2 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 H02W0201 +arc: B0 H02W0101 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1100110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R27C16:PLC2 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0601 H02W0601 +arc: V00B0100 V02N0301 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: A7 N1_V01S0100 +arc: B7 S1_V02N0501 +arc: C7 E1_H02W0601 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D7 V02S0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: LSR0 V00B0100 +arc: M0 V00T0100 +arc: M1 E1_H02W0001 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 V00T0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0100 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N3_V06N0203 Q7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111111111111 +word: SLICEC.K1.INIT 1111111111111111 +word: SLICED.K0.INIT 1111111111111111 +word: SLICED.K1.INIT 1111111111111110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C17:PLC2 +arc: H00R0100 S1_V02N0701 +arc: S1_V02S0201 H02W0201 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 V06S0303 +arc: A2 V02S0701 +arc: B2 V02S0301 +arc: C2 E1_H01W0000 +arc: CE1 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: D2 N1_V01S0000 +arc: E3_H06E0003 Q3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: H01W0100 F1 +arc: LSR0 V00T0000 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H01W0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111111101111 +word: SLICEB.K1.INIT 1111111111111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C18:PLC2 +arc: H00L0100 V02N0101 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 H06E0003 +arc: S1_V02S0401 N1_V01S0000 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: B1 N1_V02S0301 +arc: B2 N1_V02S0301 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D1 N1_V02S0001 +arc: D2 N1_V02S0001 +arc: E3_H06E0203 Q7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: LSR1 V00B0000 +arc: M0 V00B0100 +arc: M1 E1_H02W0001 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F3 +arc: S3_V06S0003 F3 +arc: V01S0000 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R27C19:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 V02S0401 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: A1 S1_V02N0501 +arc: B1 V02N0301 +arc: C1 V02S0601 +arc: D1 H00R0000 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0100 +arc: M1 H00L0100 +arc: M2 V00B0100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R27C20:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0003 N3_V06S0003 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0000 V02N0001 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0501 V06S0303 +arc: A1 V02N0701 +arc: A2 V02N0501 +arc: B1 V02S0101 +arc: B2 V02S0101 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: D1 V02S0201 +arc: D2 V02S0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: M1 E1_H02W0001 +arc: M2 V00B0000 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 E1_H02W0001 +arc: M6 V00B0000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R27C21:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0001 V01N0001 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 V01N0101 +arc: A1 H02E0701 +arc: B1 V01N0001 +arc: C1 H02E0601 +arc: D1 V02S0201 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 E1_H02W0001 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: N1_V01N0001 F3 +arc: W1_H02W0101 F3 +word: SLICED.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R27C22:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0501 E1_H01W0100 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V01N0001 +arc: A1 N1_V02S0701 +arc: B1 H02W0101 +arc: C1 N1_V01S0100 +arc: D1 V02S0201 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00L0000 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M5 H00L0000 +arc: M6 V00T0000 +arc: N1_V01N0001 F3 +word: SLICED.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R27C23:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 N1_V02S0001 +arc: A0 H02E0701 +arc: A1 N1_V02S0501 +arc: B1 H02E0301 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q1 +arc: V01S0000 Q0 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +word: SLICEA.K1.INIT 0111100000000000 +word: SLICEA.K0.INIT 0101101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R27C24:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0001 H01E0001 + +.tile R27C29:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R27C30:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R27C35:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R27C36:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R27C41:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R27C42:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R27C47:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R27C48:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R27C53:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R27C54:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R27C59:PLC2 +arc: E3_H06E0203 W3_H06E0203 + +.tile R27C60:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R27C65:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R27C66:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R27C71:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R27C72:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R27C77:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R27C78:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R27C83:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R27C84:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R27C87:PLC2 +arc: S1_V02S0701 H06E0203 + +.tile R27C88:PLC2 +arc: E1_H02E0701 N1_V02S0701 + +.tile R28C15:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: W3_H06W0303 E1_H01W0100 + +.tile R28C16:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: H00R0100 V02N0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0100 N1_V02S0101 +arc: A6 N1_V02S0301 +arc: B6 H02W0101 +arc: C6 V00B0100 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D6 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: H01W0100 Q7 +arc: LSR1 H02E0301 +arc: M0 E1_H02W0601 +arc: M1 H00R0100 +arc: M2 E1_H02W0601 +arc: M3 H02W0201 +arc: M4 E1_H02W0401 +arc: M5 H00R0100 +arc: M6 E1_H02W0401 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +word: SLICEA.K0.INIT 1111111111111111 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111011111111 +word: SLICED.K1.INIT 1111111111111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C17:PLC2 +arc: E1_H02E0301 V06S0003 +arc: H00L0100 H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: A1 S1_V02N0701 +arc: B1 S1_V02N0301 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C1 W1_H02E0401 +arc: C4 V00B0100 +arc: C6 V00B0100 +arc: D0 V00B0100 +arc: D1 N1_V02S0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M3 E1_H02W0201 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00T0100 +arc: N1_V02N0301 F3 +arc: S1_V02S0101 F3 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0110110011001100 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100110011001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1100110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R28C18:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 E1_H02W0301 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 H01E0001 +arc: A6 N1_V02S0101 +arc: B6 N1_V01S0000 +arc: C6 N1_V02S0201 +arc: D6 V02S0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H01E0001 +arc: M1 W1_H02E0001 +arc: M2 V00T0100 +arc: M3 H00L0100 +arc: M4 V00T0100 +arc: M5 W1_H02E0001 +arc: M6 V00T0100 +arc: N1_V02N0101 F3 +word: SLICEA.K0.INIT 1111111111111111 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111111111011 +word: SLICED.K1.INIT 1111111111111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R28C19:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H02W0701 +arc: B1 H02E0301 +arc: C1 H02E0401 +arc: D1 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: S1_V02S0301 F3 +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICED.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R28C20:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 N1_V02S0001 +arc: V00B0000 V02N0201 +arc: A1 V01N0101 +arc: B1 S1_V02N0101 +arc: C1 H02E0601 +arc: D1 W1_H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00L0000 +arc: M6 V00B0000 +arc: W1_H02W0301 F3 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R28C21:PLC2 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 S1_V02N0201 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 H00L0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 N1_V02S0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +word: SLICEA.K0.INIT 0110101000000000 +word: SLICEA.K1.INIT 0011110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R28C22:PLC2 +arc: H00R0100 S1_V02N0701 +arc: V00B0000 V02N0001 +arc: A1 V02S0501 +arc: B1 N1_V02S0301 +arc: C1 H02W0401 +arc: D1 N1_V02S0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 W1_H02E0001 +arc: M2 V00B0000 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 W1_H02E0001 +arc: M6 V00B0000 +arc: N1_V01N0001 F3 +word: SLICED.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R28C23:PLC2 +arc: N1_V02N0401 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 + +.tile R28C3:PLC2 +arc: S3_V06S0303 E3_H06W0303 + +.tile R28C87:PLC2 +arc: E1_H02E0701 V02S0701 + +.tile R28C9:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R29C10:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R29C15:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 E3_H06W0303 + +.tile R29C16:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V02S0401 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0501 H01E0101 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 V02S0001 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V01N0101 +arc: A7 H00R0000 +arc: B1 S1_V02N0301 +arc: B7 H02E0301 +arc: C1 V02N0401 +arc: C3 V02N0601 +arc: C7 V01N0101 +arc: D1 H02E0001 +arc: D3 S1_V02N0001 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: M1 H00L0000 +arc: M2 H02E0601 +arc: N1_V01N0001 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0501 F7 +arc: V01S0000 F7 +word: SLICED.K1.INIT 0110101010101010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0010000100000011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R29C17:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0101 H02W0101 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0101 +arc: A6 E1_H02W0701 +arc: B6 H02W0301 +arc: C6 H02E0401 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D6 V02S0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: H01W0100 Q7 +arc: LSR0 V00B0000 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +word: SLICEA.K0.INIT 1111111111111111 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111111111011 +word: SLICED.K1.INIT 1111111111111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C18:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0301 E1_H02W0301 +arc: V00B0100 V02S0301 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 N1_V02S0301 +arc: A6 N1_V02S0101 +arc: B6 W1_H02E0301 +arc: C6 V00B0100 +arc: D6 H02E0001 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 H00L0100 +arc: M4 H02E0401 +arc: M5 H00R0100 +arc: M6 H02E0401 +word: SLICEA.K0.INIT 1111111111111111 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111111111101 +word: SLICED.K1.INIT 1111111111111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R29C19:PLC2 +arc: H00L0100 V02S0301 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02E0301 +arc: W1_H02W0701 V06S0203 +arc: A0 V02N0701 +arc: B0 V02N0301 +arc: B2 V02N0101 +arc: C0 V02N0401 +arc: C2 V02N0401 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 F1 +arc: LSR0 V00T0000 +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +word: SLICEA.K0.INIT 1000001000001010 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000110000001100 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R29C20:PLC2 +arc: H00R0000 V02N0601 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0100 N1_V02S0301 +arc: A1 F7 +arc: A2 V00T0000 +arc: B1 V02N0301 +arc: B2 F3 +arc: B3 V02S0101 +arc: B7 V00T0000 +arc: C0 E1_H01W0000 +arc: C1 H00L0100 +arc: C7 E1_H01E0101 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 S1_V02N0001 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q2 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0201 Q2 +arc: S1_V02S0001 Q0 +arc: V00T0000 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0301 Q1 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 0110011000000000 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1100000011000000 +word: SLICEA.K1.INIT 0111100000000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R29C21:PLC2 +arc: H00R0100 V02N0501 +arc: V00T0000 V02N0401 +arc: A0 V01N0101 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 E1_H01W0000 +arc: B0 V02N0101 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B6 V02N0701 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C6 H01E0001 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D6 V02N0601 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 0110011010101010 +word: SLICED.K0.INIT 0000000011111100 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R29C22:PLC2 +arc: H00R0100 V02N0501 +arc: N1_V02N0701 H01E0101 +arc: V00B0100 V02N0301 +arc: C0 H02E0401 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 1111000000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R29C25:PLC2 +arc: E3_H06E0303 W3_H06E0203 + +.tile R29C31:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R29C37:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R29C43:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R29C49:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R29C4:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R29C55:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R29C61:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R29C67:PLC2 +arc: E3_H06E0003 W3_H06E0003 + +.tile R29C73:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R29C79:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R29C85:PLC2 +arc: E1_H01E0101 W3_H06E0203 + +.tile R29C86:PLC2 +arc: E3_H06E0303 H01E0101 + +.tile R2C15:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R2C20:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0701 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 H02W0101 +arc: A0 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: B0 V02N0301 +arc: B1 E1_H02W0301 +arc: B2 V02N0301 +arc: B3 E1_H02W0101 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0301 +arc: C0 V02N0401 +arc: C2 V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: LSR0 V00T0100 +arc: M0 E1_H02W0601 +arc: M1 H00R0100 +arc: M2 E1_H02W0601 +arc: M3 H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0701 Q7 +word: SLICEA.K0.INIT 0101010110001010 +word: SLICEA.K1.INIT 0011001100000000 +word: SLICEB.K0.INIT 0000000011101111 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0011110000111100 +word: SLICEC.K1.INIT 0011110000111100 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 0000111100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C21:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0201 E1_H01W0000 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H01W0000 +arc: A0 V02N0501 +arc: A1 H02W0501 +arc: A2 V02N0501 +arc: A3 H02W0501 +arc: B0 H02W0101 +arc: B2 H02W0301 +arc: B4 H02W0101 +arc: B5 H02W0301 +arc: C0 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: LSR1 V00B0100 +arc: M0 E1_H02W0601 +arc: M1 E1_H02W0001 +arc: M2 E1_H02W0601 +arc: M3 E1_H02W0201 +arc: M4 V00B0000 +arc: M5 E1_H02W0001 +arc: M6 V00B0000 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 0011001101001100 +word: SLICEA.K1.INIT 0101010100000000 +word: SLICEB.K0.INIT 0000000011011111 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICEC.K0.INIT 0011001111001100 +word: SLICEC.K1.INIT 0011001111001100 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C22:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 S1_V02N0501 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M3 H00R0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +word: SLICED.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000110011 +word: SLICEA.K1.INIT 0000000000110011 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R2C23:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 V02N0001 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: V00T0000 V02N0601 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V02N0601 +arc: A0 H02E0701 +arc: A2 V02N0701 +arc: B0 V01N0001 +arc: B1 H02E0301 +arc: B2 V02N0301 +arc: B3 H02E0101 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C2 V02N0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C6 V02N0001 +arc: C7 V02N0201 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: LSR0 V00T0100 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: M3 W1_H02E0201 +arc: M4 V00T0000 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q7 +word: SLICEA.K0.INIT 0101101001010010 +word: SLICEA.K1.INIT 0011001100000000 +word: SLICEB.K0.INIT 0000000011111101 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 0011110000111100 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 0000111100001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C24:PLC2 +arc: E1_H02E0201 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 V06N0203 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: B1 W1_H02E0301 +arc: C0 F4 +arc: C1 F4 +arc: C4 S1_V02N0201 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V02N0001 +arc: D4 H02E0001 +arc: E1_H01E0001 F4 +arc: E1_H02E0601 F4 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: H01W0000 F4 +arc: LSR0 V00B0100 +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: M5 E1_H02W0001 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: V00T0000 F0 +arc: V01S0000 F4 +arc: W1_H02W0601 F4 +word: SLICEA.K0.INIT 0101010110100101 +word: SLICEA.K1.INIT 0010010001100101 +word: SLICEC.K0.INIT 0000111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C25:PLC2 +arc: H00R0000 H02E0601 +arc: S1_V02S0201 H01E0001 +arc: V00B0100 W1_H02E0501 +arc: W1_H02W0701 V01N0101 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V01N0101 +arc: B0 V02N0301 +arc: B2 V02N0301 +arc: B3 V01N0001 +arc: C0 V02N0401 +arc: C2 V02N0601 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: D0 H02E0201 +arc: D1 V02N0001 +arc: D2 H02E0201 +arc: D3 V02N0001 +arc: D4 V01N0001 +arc: D5 V01N0001 +arc: D6 V01N0001 +arc: D7 V01N0001 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 W1_H02E0201 +arc: M4 V00B0100 +arc: M5 H00R0000 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 0110001001100110 +word: SLICEA.K1.INIT 0000000010101010 +word: SLICEB.K0.INIT 0101010001010101 +word: SLICEB.K1.INIT 0011001100000000 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 0000111111110000 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R2C26:PLC2 +arc: W1_H02W0001 H01E0001 + +.tile R2C30:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 + +.tile R2C36:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 + +.tile R2C3:PLC2 +arc: S3_V06S0303 E3_H06W0303 + +.tile R2C42:PLC2 +arc: E3_H06E0203 W3_H06E0203 +arc: N1_V02N0501 W3_H06E0303 + +.tile R2C48:PLC2 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 W3_H06E0203 + +.tile R2C49:PLC2 +arc: N1_V02N0701 H01E0101 + +.tile R2C50:PLC2 +arc: N1_V02N0701 W1_H02E0701 + +.tile R2C9:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R30C16:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: H00R0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: B0 H02W0101 +arc: B4 V02S0501 +arc: CE0 H00R0000 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D4 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q4 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEC.K0.INIT 1100110000000000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 + +.tile R30C17:PLC2 +arc: H00R0100 V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 N3_V06S0203 +arc: V00B0100 N1_V02S0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0601 N3_V06S0303 +arc: A6 V02S0101 +arc: B6 S1_V02N0701 +arc: C6 S1_V02N0001 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D6 H02W0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: LSR1 H02W0301 +arc: M0 V00B0100 +arc: M1 H02E0001 +arc: M2 V00B0100 +arc: M3 E1_H02W0201 +arc: M4 V00B0100 +arc: M5 H02E0001 +arc: M6 V00B0100 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: S3_V06S0203 Q7 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111011111111 +word: SLICED.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 1111111111111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R30C18:PLC2 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 N1_V02S0601 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 V02N0201 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0301 V01N0101 +arc: A0 H00L0000 +arc: B0 S1_V02N0301 +arc: C0 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: D0 H02W0001 +arc: D2 H02W0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: N1_V02N0101 F1 +word: SLICEA.K0.INIT 1000011100000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000111100000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R30C19:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N3_V06S0003 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 V01N0001 +arc: A0 V02S0501 +arc: C0 N1_V01N0001 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: LSR0 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 0101000010100000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R30C20:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0303 N3_V06S0303 +arc: A1 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 H02W0101 +arc: C0 E1_H01W0000 +arc: C1 N1_V01S0100 +arc: C7 H02W0601 +arc: D0 N1_V01S0000 +arc: D1 H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: M0 V00T0000 +word: SLICEA.K0.INIT 1100000000000000 +word: SLICEA.K1.INIT 1110000000000000 +word: SLICED.K1.INIT 0000111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R30C21:PLC2 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: W1_H02W0501 E1_H01W0100 +arc: A2 V00B0000 +arc: A5 V00B0000 +arc: B0 W1_H02E0301 +arc: B2 H00L0000 +arc: B4 H01E0101 +arc: B5 H00L0000 +arc: C1 V02N0401 +arc: C2 H00L0100 +arc: C5 V00T0100 +arc: CE0 H00R0000 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D4 H02W0001 +arc: D5 H02W0201 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 F5 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q4 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEB.K0.INIT 0011011000111100 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1100100011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R30C22:PLC2 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 H02E0701 +arc: W1_H02W0001 N3_V06S0003 +arc: C0 N1_V01N0001 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0000000011110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R31C16:PLC2 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N1_V01S0000 + +.tile R31C17:PLC2 +arc: N1_V02N0701 N1_V01S0100 + +.tile R31C18:PLC2 +arc: E1_H02E0301 V02N0301 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 E1_H02W0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0201 +arc: A0 E1_H02W0501 +arc: B0 V01N0001 +arc: C0 V02S0401 +arc: C2 V02S0401 +arc: D0 V02S0201 +arc: D2 V00B0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0000 +arc: M1 H02W0001 +arc: M2 V00T0000 +arc: N1_V02N0301 F1 +word: SLICEA.K0.INIT 0100000100000101 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R31C19:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0201 E1_H01W0000 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V06S0003 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 V02S0501 +arc: B0 H02E0301 +arc: C0 V02S0401 +arc: C2 V02S0401 +arc: D0 V02S0001 +arc: D2 V00T0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: N1_V01N0001 F1 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0100000100000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R31C20:PLC2 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0001 N3_V06S0003 +arc: A1 H00L0000 +arc: B1 V02S0301 +arc: C1 V02S0401 +arc: C3 V02S0601 +arc: C7 E1_H01E0101 +arc: D1 N1_V02S0201 +arc: D3 E1_H02W0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00T0100 +arc: V00T0100 F3 +arc: W1_H02W0201 F0 +arc: W1_H02W0501 F7 +word: SLICED.K1.INIT 0000111111110000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEA.K1.INIT 0000100000000000 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R31C21:PLC2 +arc: N1_V02N0401 H01E0001 + +.tile R31C22:PLC2 +arc: W1_H02W0201 N1_V01S0000 + +.tile R31C3:PLC2 +arc: W1_H02W0501 V06S0303 + +.tile R32C17:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0701 N3_V06S0203 + +.tile R32C18:PLC2 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 + +.tile R36C17:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R3C16:PLC2 +arc: N1_V02N0501 S3_V06N0303 + +.tile R3C19:PLC2 +arc: E1_H01E0001 E3_H06W0003 + +.tile R3C20:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06W0203 + +.tile R3C21:PLC2 +arc: E1_H02E0001 V06N0003 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: A0 V02N0701 +arc: A7 Q7 +arc: B0 E1_H01W0100 +arc: C0 V02N0401 +arc: C4 V00B0100 +arc: C5 V00B0100 +arc: C6 V00B0100 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: LSR1 E1_H02W0501 +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M3 E1_H02W0201 +arc: M4 V00B0000 +arc: M5 H00R0000 +arc: M6 V00B0000 +arc: M7 H00L0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0101 F3 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +word: SLICED.K1.INIT 1010101010101010 +word: SLICED.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111111000000001 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C22:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S3_V06N0203 +arc: A3 V00B0000 +arc: B0 V00T0000 +arc: B3 Q3 +arc: C1 S1_V02N0401 +arc: C4 Q4 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 H02E0001 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q3 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0401 Q4 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: W1_H02W0601 Q4 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICEA.K0.INIT 0011001111001100 +word: SLICEB.K1.INIT 1001100111001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R3C23:PLC2 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H01E0101 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 H00L0100 +arc: A1 V02N0701 +arc: A3 H02W0701 +arc: A6 F5 +arc: A7 F5 +arc: B0 V00T0000 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B5 F1 +arc: B6 V02N0501 +arc: B7 E1_H02W0301 +arc: C0 H00L0000 +arc: C2 H00L0100 +arc: C3 E1_H01W0000 +arc: C5 E1_H02W0601 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D1 V01S0100 +arc: D2 V00T0100 +arc: D5 F0 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F6 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q1 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F7 +word: SLICEB.K1.INIT 1100100111001001 +word: SLICEA.K0.INIT 1100100111001100 +word: SLICEA.K1.INIT 0101010110101010 +word: SLICED.K1.INIT 0000000000000010 +word: SLICED.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000000000110000 +word: SLICEB.K0.INIT 1100001111001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R3C24:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H01E0001 +arc: S1_V02S0101 E1_H01W0100 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 V01N0001 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A7 V00T0100 +arc: B1 H02E0101 +arc: B3 H02E0301 +arc: B7 H02E0301 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C3 E1_H01W0000 +arc: C7 V00B0100 +arc: CE0 H00L0000 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D3 V01S0100 +arc: D5 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: LSR1 H02E0501 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F1 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: V01S0000 F7 +arc: V01S0100 Q0 +arc: W1_H02W0301 F1 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K1.INIT 1010101010101001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111000000001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 + +.tile R3C25:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 H01E0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V01N0001 +arc: B0 V00T0000 +arc: B1 Q1 +arc: C0 W1_H02E0401 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0201 +arc: D1 H01E0101 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q0 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 F1 +arc: W3_H06W0003 Q0 +word: SLICEA.K1.INIT 0011001111001100 +word: SLICEA.K0.INIT 1100001111001100 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R3C29:PLC2 +arc: N1_V02N0501 S1_V02N0501 + +.tile R42C17:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R48C17:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R4C21:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: H00L0100 V02S0101 +arc: N1_V02N0601 S1_V02N0301 +arc: V00T0100 E1_H02W0301 +arc: A2 F7 +arc: A3 F7 +arc: A4 V00B0000 +arc: A6 V02S0301 +arc: A7 H00R0000 +arc: B4 V00B0100 +arc: B6 E1_H02W0101 +arc: B7 V02S0701 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 F6 +arc: C5 F6 +arc: C6 V02S0201 +arc: C7 V01N0101 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 V02N0401 +arc: D5 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F1 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H00R0100 Q5 +arc: LSR0 E1_H02W0501 +arc: M0 V00T0100 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q5 +arc: V00B0000 Q4 +arc: V00B0100 Q5 +arc: V01S0000 Q5 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K1.INIT 0001000000000000 +word: SLICEB.K0.INIT 0000000000001010 +word: SLICEC.K1.INIT 0000111111110000 +word: SLICEB.K1.INIT 0000101000000000 +word: SLICED.K0.INIT 0000010000000100 +word: SLICEC.K0.INIT 1001101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C22:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0100 H02W0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: V00T0000 V02S0401 +arc: A0 H02E0701 +arc: B0 V02S0101 +arc: C0 H02E0601 +arc: D0 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: S1_V02S0101 F3 +arc: V01S0000 F3 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R4C23:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0100 V02S0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0501 V02N0501 +arc: A2 V00T0000 +arc: B2 E1_H02W0101 +arc: C2 E1_H01W0000 +arc: D2 N1_V01S0000 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H00R0100 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: N1_V01N0001 F3 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R4C24:PLC2 +arc: E1_H02E0501 W1_H02E0401 +arc: H00L0000 H02W0001 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0201 V01N0001 +arc: A0 F7 +arc: A1 F7 +arc: A2 V00T0000 +arc: A5 V02S0101 +arc: A7 F5 +arc: B1 Q1 +arc: B2 V02S0101 +arc: B5 N1_V01S0000 +arc: B7 H02E0301 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 H00L0000 +arc: C5 V00T0000 +arc: C7 H02E0601 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 N1_V01S0000 +arc: D5 E1_H01W0100 +arc: D7 H02E0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 Q2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F5 +arc: V00T0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0001 F0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1111010100001010 +word: SLICED.K1.INIT 0000000000000010 +word: SLICEA.K1.INIT 1100110011000110 +word: SLICEC.K1.INIT 0000000000000100 +word: SLICEB.K0.INIT 1010100110101010 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R4C25:PLC2 +arc: H00R0100 H02E0501 +arc: N1_V02N0401 H01E0001 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0701 +arc: A4 N1_V01N0101 +arc: B0 V02S0301 +arc: B1 Q1 +arc: B4 H01E0101 +arc: C0 N1_V01S0100 +arc: C4 V00T0000 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D4 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 Q1 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEA.K0.INIT 1111001100001100 +word: SLICEA.K1.INIT 0011001111001100 +word: SLICEC.K0.INIT 0000000000000001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R4C31:PLC2 +arc: N3_V06N0003 S1_V02N0001 + +.tile R4C41:PLC2 +arc: N3_V06N0203 S1_V02N0701 + +.tile R54C17:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R5C20:PLC2 +arc: A3 E1_H01E0001 +arc: B3 Q3 +arc: C2 H00L0000 +arc: CE0 H02W0101 +arc: CE1 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: D3 V01S0100 +arc: E1_H01E0001 Q2 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q3 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 0110011011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R5C21:PLC2 +arc: H00L0000 H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0601 E1_H01W0000 +arc: A0 F5 +arc: A1 E1_H01E0001 +arc: A2 V00T0000 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: B1 H02E0101 +arc: B3 V02N0101 +arc: B4 N1_V01S0000 +arc: B5 H02E0101 +arc: C1 H00L0000 +arc: C2 N1_V01S0100 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C6 V00T0000 +arc: CE0 H00L0100 +arc: CE1 H00R0000 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H02E0001 +arc: D2 N1_V01S0000 +arc: D3 V02N0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00L0100 F3 +arc: LSR1 H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 F6 +arc: N1_V02N0401 F6 +arc: S1_V02S0701 F5 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q0 +arc: W1_H02W0101 F3 +word: SLICEC.K0.INIT 1111110100000010 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICEA.K1.INIT 0110101010101010 +word: SLICEA.K0.INIT 0101010110101010 +word: SLICEB.K1.INIT 0000000011001100 +word: SLICED.K0.INIT 0000000000001111 +word: SLICEB.K0.INIT 1010101001011010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 + +.tile R5C22:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V01N0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H01E0101 +arc: A1 H00L0100 +arc: A3 H00L0100 +arc: A4 V02S0101 +arc: A7 S1_V02N0101 +arc: B3 E1_H02W0101 +arc: B4 H00L0000 +arc: C0 H00L0000 +arc: C1 F4 +arc: C3 H00L0000 +arc: C7 S1_V02N0001 +arc: CE0 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D1 E1_H02W0201 +arc: D3 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0601 F4 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F4 +arc: V00B0100 F7 +arc: W1_H02W0501 F7 +word: SLICEA.K1.INIT 1010101001011010 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0010001000100010 +word: SLICED.K1.INIT 1010101011111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R5C23:PLC2 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 H01E0101 +arc: V00T0000 E1_H02W0001 +arc: A2 H01E0001 +arc: B2 E1_H01W0100 +arc: C2 E1_H01W0000 +arc: D2 H02W0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H02E0001 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M5 H02E0001 +arc: M6 V00T0000 +arc: N3_V06N0003 F3 +word: SLICED.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R5C24:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 W1_H02E0401 +arc: N3_V06N0203 E1_H01W0000 +arc: W1_H02W0201 E1_H01W0000 +arc: A2 F7 +arc: A3 H00L0100 +arc: A7 E1_H01W0000 +arc: B1 Q1 +arc: B2 H02E0101 +arc: B3 E1_H01W0100 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C2 H00L0000 +arc: C3 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D3 H02E0201 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q3 +arc: H01W0000 Q2 +arc: H01W0100 Q3 +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q1 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: V01S0000 Q3 +arc: V01S0100 F7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 Q1 +word: SLICEB.K1.INIT 1010101010011010 +word: SLICEB.K0.INIT 1111110111001100 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0011001111001100 +word: SLICED.K1.INIT 0000000000010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R5C25:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0701 H06E0203 +arc: C0 H02E0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0000111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C29:PLC2 +arc: N1_V02N0501 V01N0101 +arc: S1_V02S0001 E1_H02W0001 +arc: A3 V00B0000 +arc: B3 H00L0000 +arc: C0 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: CE0 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 H00R0000 +arc: D3 E1_H02W0001 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q6 +arc: LSR0 H02W0501 +arc: M2 E1_H02W0601 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR3 LSR0 +arc: S1_V02S0601 Q6 +arc: V00B0000 Q6 +arc: V00T0000 F2 +arc: V01S0000 Q6 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0110101010101010 +word: SLICEA.K0.INIT 0000111111110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C30:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0100 V02N0101 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 F5 +arc: C0 H00L0000 +arc: C5 H01E0001 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D5 V02N0601 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 Q0 +arc: LSR0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0101101011110000 +word: SLICEC.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C31:PLC2 +arc: V00B0100 H02E0701 +arc: W1_H02W0601 V02N0601 +arc: C0 H00L0000 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: F0 F0_SLICE +arc: H00L0000 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: S1_V02S0201 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0000111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R60C17:PLC2 +arc: S3_V06S0303 N3_V06S0203 + +.tile R66C17:PLC2 +arc: S1_V02S0501 N3_V06S0303 + +.tile R68C17:PLC2 +arc: E1_H02E0501 N1_V02S0501 + +.tile R68C18:PLC2 +arc: S1_V02S0501 H02E0501 + +.tile R6C21:PLC2 +arc: E1_H02E0201 V02N0201 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: A0 V02S0701 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D6 E1_H01W0100 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 F0 +arc: N3_V06N0003 F0 +arc: S3_V06S0003 Q0 +arc: V00B0000 F6 +word: SLICED.K0.INIT 1111000011111111 +word: SLICEA.K0.INIT 1010101000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C22:PLC2 +arc: H00L0100 V02N0301 +arc: V00T0000 H02E0201 +arc: B0 H01W0100 +arc: C0 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 0011000011111100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C24:PLC2 +arc: E1_H02E0501 V01N0101 + +.tile R6C25:PLC2 +arc: A0 H00L0100 +arc: A4 V02N0301 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: C0 F4 +arc: C1 F4 +arc: C2 F4 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V01S0100 +arc: D2 Q2 +arc: D4 S1_V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: S1_V02S0001 Q2 +arc: S1_V02S0201 Q2 +arc: V00T0000 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q1 +word: SLICEA.K0.INIT 0111111110000000 +word: SLICEA.K1.INIT 0011111111000000 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICEB.K0.INIT 0000111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C26:PLC2 +arc: H00L0100 S1_V02N0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H01E0101 +arc: V00B0100 V02N0301 +arc: A1 H01E0001 +arc: B1 H02E0101 +arc: C1 V02N0401 +arc: D1 H02E0201 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00B0100 +arc: M1 H00L0100 +arc: M2 V00B0100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R6C27:PLC2 +arc: H00L0000 H02W0201 +arc: H00L0100 H02E0301 +arc: H00R0000 V02N0401 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 V01N0101 +arc: S1_V02S0701 V01N0101 +arc: V00T0000 V02N0601 +arc: A1 H00L0000 +arc: A2 E1_H02W0701 +arc: B1 H02W0101 +arc: B2 H02W0301 +arc: C1 H02W0601 +arc: C2 H02W0401 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00L0100 +arc: M2 V00T0000 +arc: M3 H00R0000 +arc: M4 V00T0000 +arc: M5 H00L0100 +arc: M6 V00T0000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R6C28:PLC2 +arc: H00L0000 E1_H02W0001 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 F7 +arc: B1 W1_H02E0301 +arc: B3 H00R0000 +arc: B4 H00R0000 +arc: B6 W1_H02E0301 +arc: C0 F6 +arc: C1 V02N0401 +arc: C3 H00L0100 +arc: C4 V00T0000 +arc: C7 F6 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02N0001 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D6 V02N0601 +arc: D7 H01W0000 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 Q4 +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 Q3 +arc: S1_V02S0601 Q4 +arc: V00B0100 F7 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0301 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0011001100110000 +word: SLICEB.K0.INIT 0101010110101010 +word: SLICEB.K1.INIT 0111100011110000 +word: SLICEC.K0.INIT 0110110001101100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C29:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N1_V01S0100 +arc: W1_H02W0701 H01E0101 +arc: A0 V01N0101 +arc: A1 V02N0701 +arc: B0 V02N0301 +arc: B1 V01N0001 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR0 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 0000111100001101 +word: SLICEA.K1.INIT 0000111100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C30:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 V02N0501 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A3 V01N0101 +arc: B1 V01N0001 +arc: B2 V02N0101 +arc: C1 N1_V01S0100 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: D1 H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H00L0100 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: S1_V02S0101 F3 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 1010101010101010 +word: SLICEA.K1.INIT 0110101010101010 +word: SLICEB.K0.INIT 1100110011001100 +word: SLICEB.K1.INIT 1010101010101010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R6C31:PLC2 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: A0 V02N0501 +arc: B0 S1_V02N0301 +arc: C0 H02E0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: F0 F0_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0000000011101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C35:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R6C41:PLC2 +arc: N1_V02N0701 W3_H06E0203 + +.tile R7C13:PLC2 +arc: W3_H06W0003 E3_H06W0003 + +.tile R7C15:PLC2 +arc: S3_V06S0203 N3_V06S0203 + +.tile R7C16:PLC2 +arc: S3_V06S0103 N3_V06S0003 + +.tile R7C18:PLC2 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0303 N3_V06S0203 + +.tile R7C19:PLC2 +arc: S3_V06S0003 N3_V06S0003 +arc: W3_H06W0003 E3_H06W0003 + +.tile R7C21:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0103 +arc: W3_H06W0103 N3_V06S0103 + +.tile R7C22:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 + +.tile R7C24:PLC2 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 W1_H02E0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 N3_V06S0103 +arc: B5 W1_H02E0301 +arc: C5 V02N0001 +arc: D5 V02N0401 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 F5 +arc: F5 F5_SLICE +arc: N1_V01N0101 F5 +arc: S1_V02S0501 F5 +word: SLICEC.K1.INIT 1111111100001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R7C25:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: V00T0100 E1_H02W0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 H00L0000 +arc: B1 E1_H02W0301 +arc: C1 N1_V01S0100 +arc: D1 N1_V01S0000 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 E1_H02W0001 +arc: M2 V00T0100 +arc: M3 H00L0100 +arc: M4 V00T0100 +arc: M5 E1_H02W0001 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R7C26:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: H00L0100 V02N0301 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 E1_H01W0000 +arc: V00T0100 H02W0301 +arc: A0 V02S0501 +arc: A1 H02E0701 +arc: A2 V02S0501 +arc: A3 E1_H02W0501 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0101 +arc: B3 H02E0301 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: D0 E1_H02W0001 +arc: D1 H02E0001 +arc: D2 E1_H02W0001 +arc: D3 H02E0201 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M1 H00L0100 +arc: M2 V00T0100 +arc: M3 H02W0201 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00T0100 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R7C27:PLC2 +arc: H00L0100 V02N0301 +arc: N1_V02N0401 H01E0001 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: A1 E1_H01E0001 +arc: A2 V00T0000 +arc: A4 V02S0301 +arc: B0 H01W0100 +arc: B1 V00T0000 +arc: B3 Q3 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V02N0001 +arc: D4 V00B0000 +arc: E1_H01E0001 Q1 +arc: E1_H02E0401 Q4 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR0 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 Q1 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V01S0000 Q2 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0301 Q3 +word: SLICEC.K0.INIT 0101010110101010 +word: SLICEA.K0.INIT 0011110011001100 +word: SLICEB.K0.INIT 0101010110101010 +word: SLICEB.K1.INIT 0011001111001100 +word: SLICEA.K1.INIT 0000111000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C28:PLC2 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02E0601 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: A1 H00L0000 +arc: B1 V02S0301 +arc: C1 V02S0601 +arc: D1 V02S0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0301 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02E0601 +arc: M1 H00L0100 +arc: M2 H02E0601 +arc: M3 W1_H02E0201 +arc: M4 H02E0401 +arc: M5 H00L0100 +arc: M6 H02E0401 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R7C29:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 V02N0101 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0401 H01E0001 +arc: V00B0000 H02W0601 +arc: V00T0000 N1_V02S0601 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H02W0001 +arc: M2 H02W0601 +arc: M3 H00L0100 +arc: M4 V00B0000 +arc: M5 H02W0001 +arc: M6 V00B0000 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R7C30:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 V02N0001 +arc: H00L0100 V02S0101 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 H01E0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 W3_H06E0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: A1 E1_H01E0001 +arc: B1 V00T0000 +arc: B4 H00R0000 +arc: C1 H02E0601 +arc: C4 S1_V02N0201 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 N1_V02S0201 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D4 V01N0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F1 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00B0100 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M3 H00L0100 +arc: M7 H02E0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: V01S0000 Q4 +arc: V01S0100 Q7 +arc: W1_H02W0601 Q4 +word: SLICEC.K0.INIT 0000000011111100 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0110101010101010 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C31:PLC2 +arc: H00R0000 V02N0401 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H01E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: A1 S1_V02N0501 +arc: B0 W1_H02E0101 +arc: B1 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0000111100000011 +word: SLICEA.K1.INIT 0000111100001011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C33:PLC2 +arc: W1_H02W0301 N3_V06S0003 + +.tile R7C37:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile R7C43:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 + +.tile R7C49:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 + +.tile R7C55:PLC2 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0103 + +.tile R7C61:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 + +.tile R7C64:PLC2 +arc: N3_V06N0203 S3_V06N0103 + +.tile R7C67:PLC2 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 + +.tile R7C73:PLC2 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 + +.tile R7C79:PLC2 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 + +.tile R7C7:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R7C85:PLC2 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 + +.tile R7C87:PLC2 +arc: E1_H02E0701 W1_H02E0701 + +.tile R7C88:PLC2 +arc: S3_V06S0103 H06E0103 + +.tile R8C24:PLC2 +arc: N1_V02N0401 N1_V01S0000 +arc: V00B0000 V02S0201 +arc: A0 E1_H01E0001 +arc: B0 V02S0301 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0100010011101110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C25:PLC2 +arc: H00L0100 V02N0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0401 E1_H01W0000 +arc: V00B0000 V02N0201 +arc: A0 V02N0501 +arc: B0 V02N0301 +arc: C0 E1_H02W0601 +arc: D0 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H02W0001 +arc: M2 V00B0000 +arc: M3 H00L0100 +arc: M4 V00B0000 +arc: M5 H02W0001 +arc: M6 V00B0000 +arc: N1_V02N0101 F3 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R8C26:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: W1_H02W0001 V01N0001 +arc: A1 V02S0501 +arc: B1 V02S0101 +arc: C1 V02S0601 +arc: D1 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F3 +arc: M0 E1_H02W0601 +arc: M1 H00R0100 +arc: M2 E1_H02W0601 +arc: M3 H00L0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0100 +arc: M6 E1_H02W0401 +arc: N1_V02N0301 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R8C27:PLC2 +arc: H00L0000 V02S0201 +arc: H00L0100 V02S0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 N1_V02S0701 +arc: A1 H00L0000 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0501 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V02S0101 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V00B0100 +arc: B7 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C1 H00L0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 V02S0001 +arc: C5 V02S0001 +arc: C6 V02S0001 +arc: C7 V02S0201 +arc: D0 V02S0001 +arc: D1 N1_V01S0000 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0000 +arc: M1 H00R0100 +arc: M2 V00T0000 +arc: M3 H02E0201 +arc: M4 V00T0000 +arc: M5 H00R0100 +arc: M6 V00T0000 +arc: N1_V01N0001 F3 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0000000000000001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R8C28:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: H00L0000 E1_H02W0001 +arc: S1_V02S0001 E1_H02W0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: B0 F3 +arc: B3 V01N0001 +arc: C7 V02N0001 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D3 W1_H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F7 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F3 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: W1_H02W0001 Q0 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 0011001111001100 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C29:PLC2 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0201 H01E0001 +arc: V00B0000 V02N0201 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 H02E0001 +arc: M2 H02W0601 +arc: M3 H00L0100 +arc: M4 V00B0000 +arc: M5 H02E0001 +arc: M6 V00B0000 +arc: N1_V02N0101 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R8C30:PLC2 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0501 V02S0501 +arc: H00L0100 V02N0101 +arc: N1_V02N0001 W3_H06E0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V01N0101 +arc: A1 V01N0101 +arc: B1 V02N0301 +arc: C1 E1_H01W0000 +arc: D1 N1_V01S0000 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 W1_H02E0201 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: N1_V01N0001 F3 +arc: N1_V02N0301 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R8C31:PLC2 +arc: H00L0000 H02E0001 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H01E0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 V01N0001 +arc: B0 V00T0000 +arc: C0 V02N0601 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0011110011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C3:PLC2 +arc: S3_V06S0303 N3_V06S0303 + +.tile R9C16:PLC2 +arc: N3_V06N0303 S3_V06N0303 + +.tile R9C20:PLC2 +arc: S1_V02S0401 H06W0203 + +.tile R9C22:PLC2 +arc: N3_V06N0203 S1_V02N0701 + +.tile R9C23:PLC2 +arc: W3_H06W0203 E1_H01W0000 + +.tile R9C24:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 N1_V02S0201 +arc: S1_V02S0201 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0201 +arc: D2 N1_V01S0000 +arc: E1_H02E0001 F0 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V02N0001 F0 +arc: V00T0000 F2 +word: SLICEB.K0.INIT 1111000011111111 +word: SLICEA.K0.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C25:PLC2 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H01W0100 +arc: A0 H00L0100 +arc: A4 E1_H01W0000 +arc: A6 H00L0000 +arc: B0 H01W0100 +arc: B1 Q1 +arc: B4 H00L0000 +arc: B6 V01S0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 F6 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C6 H02W0401 +arc: CE0 H02W0101 +arc: CE1 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 Q2 +arc: D3 V00T0100 +arc: D4 E1_H01W0100 +arc: D6 H02W0201 +arc: E1_H01E0001 F4 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00L0000 Q0 +arc: H00L0100 Q1 +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: LSR1 H02E0501 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 Q2 +arc: V00T0000 Q2 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q2 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEA.K0.INIT 0110110011001100 +word: SLICEA.K1.INIT 0011110011001100 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R9C26:PLC2 +arc: E1_H02E0401 H01E0001 +arc: H00L0000 H02E0001 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0201 H01E0001 +arc: V00T0000 H02E0001 +arc: W1_H02W0401 E1_H01W0000 +arc: A3 V00B0000 +arc: A4 V00B0000 +arc: B3 H02E0101 +arc: B4 H02E0101 +arc: C0 E1_H01W0000 +arc: C1 W1_H02E0601 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 E1_H01E0101 +arc: CE0 H00L0100 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 W1_H02E0001 +arc: D3 H02E0201 +arc: D4 H02E0201 +arc: D5 H00R0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 F1 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 F1 +arc: H00R0100 Q5 +arc: H01W0000 Q4 +arc: H01W0100 Q5 +arc: LSR1 W1_H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V02N0101 F3 +arc: N1_V02N0501 Q5 +arc: V00B0000 Q4 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEC.K0.INIT 1010101010101001 +word: SLICEB.K1.INIT 0000000000000010 +word: SLICEC.K1.INIT 0000111111110000 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C27:PLC2 +arc: N1_V02N0501 E1_H01W0100 +arc: V00T0000 N1_V02S0601 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: LSR0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEA.K0.INIT 0000000011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C28:PLC2 +arc: H00L0000 V02S0001 +arc: N1_V02N0001 E1_H02W0001 +arc: C0 W1_H02E0401 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: H01W0100 Q0 +arc: LSR0 E1_H02W0501 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0000111111110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C29:PLC2 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0701 H06E0203 +arc: V00T0100 H02W0301 +arc: A1 H00L0100 +arc: B1 E1_H01W0100 +arc: C1 E1_H02W0601 +arc: D1 H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: M0 V00T0100 +arc: M1 H00R0000 +arc: M2 V00T0100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R9C30:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0501 N1_V02S0501 +arc: A2 V00B0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: C0 F4 +arc: C2 F4 +arc: C4 E1_H01E0101 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V00B0100 +arc: D2 Q2 +arc: D4 H00L0100 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 Q1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q0 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: V01S0000 Q0 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q1 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEB.K0.INIT 0111111110000000 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0011001111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C31:PLC2 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0601 N1_V01S0000 +arc: A1 E1_H01E0001 +arc: B1 V00T0000 +arc: C1 N1_V01S0100 +arc: CE1 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 H02E0001 +arc: E1_H01E0001 Q3 +arc: F0 F5A_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q3 +arc: LSR0 H02E0501 +arc: M0 H01E0001 +arc: M3 H00L0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 Q3 +arc: V01S0100 Q3 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 0110101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C32:PLC2 +arc: H01W0100 W3_H06E0303 + +.tile TAP_R11C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R11C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R12C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R12C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R13C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R13C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R14C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R14C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R15C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R15C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R16C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R18C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R24C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R25C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R25C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R26C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R26C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R27C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R27C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R28C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R29C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R29C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R2C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R2C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R30C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R30C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R3C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R3C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R4C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R4C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R5C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R5C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R6C13:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R6C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R7C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R8C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R9C31:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: R_HPBX0000 G_VPTX0000 + diff --git a/synth/ecp5/p8/top.json b/synth/ecp5/p8/top.json new file mode 100644 index 0000000..a6033d0 --- /dev/null +++ b/synth/ecp5/p8/top.json @@ -0,0 +1,66138 @@ +{ + "creator": "Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)", + "modules": { + "$__ABC9_DELAY": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000011", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.1-7.10" + }, + "parameter_default_values": { + "DELAY": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + "$specify$296547": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000000000000", + "T_FALL_MIN": "00000000000000000000000000000000", + "T_FALL_TYP": "00000000000000000000000000000000", + "T_RISE_MAX": "00000000000000000000000000000000", + "T_RISE_MIN": "00000000000000000000000000000000", + "T_RISE_TYP": "00000000000000000000000000000000" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:5.5-5.22" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 3 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + } + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.29-2.30" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.39-2.40" + } + } + } + }, + "$__ABC9_SCC_BREAKER": { + "attributes": { + "dynports": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.1-11.10" + }, + "parameter_default_values": { + "WIDTH": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "offset": -1, + "upto": 1, + "bits": [ 2, 3 ] + }, + "O": { + "direction": "output", + "offset": -1, + "upto": 1, + "bits": [ 4, 5 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2, 3 ], + "offset": -1, + "upto": 1, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.47-9.48" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4, 5 ], + "offset": -1, + "upto": 1, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:9.69-9.70" + } + } + } + }, + "$__DFF_N__$abc9_flop": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000010", + "blackbox": "00000000000000000000000000000001", + "abc9_flop": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.1-20.10" + }, + "ports": { + "C": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "input", + "bits": [ 4 ] + }, + "n1": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "C": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.36-14.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.39-14.40" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.42-14.43" + } + }, + "n1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:14.52-14.54" + } + } + } + }, + "$__DFF_P__$abc9_flop": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "abc9_flop": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.1-29.10" + }, + "ports": { + "C": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "input", + "bits": [ 4 ] + }, + "n1": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "C": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.36-23.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.39-23.40" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.42-23.43" + } + }, + "n1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:23.52-23.54" + } + } + } + }, + "\\$__ABC9_LUT5": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000000010", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.1-30.10" + }, + "ports": { + "M0": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "C": { + "direction": "input", + "bits": [ 4 ] + }, + "B": { + "direction": "input", + "bits": [ 5 ] + }, + "A": { + "direction": "input", + "bits": [ 6 ] + }, + "Z": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + "$specify$295858": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000010010111", + "T_FALL_MIN": "00000000000000000000000010010111", + "T_FALL_TYP": "00000000000000000000000010010111", + "T_RISE_MAX": "00000000000000000000000010010111", + "T_RISE_MIN": "00000000000000000000000010010111", + "T_RISE_TYP": "00000000000000000000000010010111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:24.9-24.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + }, + "$specify$295859": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000011101111", + "T_FALL_MIN": "00000000000000000000000011101111", + "T_FALL_TYP": "00000000000000000000000011101111", + "T_RISE_MAX": "00000000000000000000000011101111", + "T_RISE_MIN": "00000000000000000000000011101111", + "T_RISE_TYP": "00000000000000000000000011101111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:25.9-25.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 3 ] + } + }, + "$specify$295860": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000101110101", + "T_FALL_MIN": "00000000000000000000000101110101", + "T_FALL_TYP": "00000000000000000000000101110101", + "T_RISE_MAX": "00000000000000000000000101110101", + "T_RISE_MIN": "00000000000000000000000101110101", + "T_RISE_TYP": "00000000000000000000000101110101" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:26.9-26.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 4 ] + } + }, + "$specify$295861": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000111011101", + "T_FALL_MIN": "00000000000000000000000111011101", + "T_FALL_TYP": "00000000000000000000000111011101", + "T_RISE_MAX": "00000000000000000000000111011101", + "T_RISE_MIN": "00000000000000000000000111011101", + "T_RISE_TYP": "00000000000000000000000111011101" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:27.9-27.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 5 ] + } + }, + "$specify$295862": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000111011101", + "T_FALL_MIN": "00000000000000000000000111011101", + "T_FALL_TYP": "00000000000000000000000111011101", + "T_RISE_MAX": "00000000000000000000000111011101", + "T_RISE_MIN": "00000000000000000000000111011101", + "T_RISE_TYP": "00000000000000000000000111011101" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:28.9-28.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 7 ], + "EN": [ "1" ], + "SRC": [ 6 ] + } + } + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.42-22.43" + } + }, + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.39-22.40" + } + }, + "C": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.36-22.37" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.33-22.34" + } + }, + "M0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.29-22.31" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:22.52-22.53" + } + } + } + }, + "\\$__ABC9_LUT6": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000000100", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.1-45.10" + }, + "ports": { + "M1": { + "direction": "input", + "bits": [ 2 ] + }, + "M0": { + "direction": "input", + "bits": [ 3 ] + }, + "D": { + "direction": "input", + "bits": [ 4 ] + }, + "C": { + "direction": "input", + "bits": [ 5 ] + }, + "B": { + "direction": "input", + "bits": [ 6 ] + }, + "A": { + "direction": "input", + "bits": [ 7 ] + }, + "Z": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + "$specify$295863": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000010010100", + "T_FALL_MIN": "00000000000000000000000010010100", + "T_FALL_TYP": "00000000000000000000000010010100", + "T_RISE_MAX": "00000000000000000000000010010100", + "T_RISE_MIN": "00000000000000000000000010010100", + "T_RISE_TYP": "00000000000000000000000010010100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:38.9-38.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + }, + "$specify$295864": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000100100100", + "T_FALL_MIN": "00000000000000000000000100100100", + "T_FALL_TYP": "00000000000000000000000100100100", + "T_RISE_MAX": "00000000000000000000000100100100", + "T_RISE_MIN": "00000000000000000000000100100100", + "T_RISE_TYP": "00000000000000000000000100100100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:39.9-39.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 3 ] + } + }, + "$specify$295865": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000101111100", + "T_FALL_MIN": "00000000000000000000000101111100", + "T_FALL_TYP": "00000000000000000000000101111100", + "T_RISE_MAX": "00000000000000000000000101111100", + "T_RISE_MIN": "00000000000000000000000101111100", + "T_RISE_TYP": "00000000000000000000000101111100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:40.9-40.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 4 ] + } + }, + "$specify$295866": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001000000010", + "T_FALL_MIN": "00000000000000000000001000000010", + "T_FALL_TYP": "00000000000000000000001000000010", + "T_RISE_MAX": "00000000000000000000001000000010", + "T_RISE_MIN": "00000000000000000000001000000010", + "T_RISE_TYP": "00000000000000000000001000000010" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:41.9-41.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 5 ] + } + }, + "$specify$295867": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001001101010", + "T_FALL_MIN": "00000000000000000000001001101010", + "T_FALL_TYP": "00000000000000000000001001101010", + "T_RISE_MAX": "00000000000000000000001001101010", + "T_RISE_MIN": "00000000000000000000001001101010", + "T_RISE_TYP": "00000000000000000000001001101010" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:42.9-42.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 6 ] + } + }, + "$specify$295868": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001001101010", + "T_FALL_MIN": "00000000000000000000001001101010", + "T_FALL_TYP": "00000000000000000000001001101010", + "T_RISE_MAX": "00000000000000000000001001101010", + "T_RISE_MIN": "00000000000000000000001001101010", + "T_RISE_TYP": "00000000000000000000001001101010" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:43.9-43.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 8 ], + "EN": [ "1" ], + "SRC": [ 7 ] + } + } + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.46-36.47" + } + }, + "B": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.43-36.44" + } + }, + "C": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.40-36.41" + } + }, + "D": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.37-36.38" + } + }, + "M0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.33-36.35" + } + }, + "M1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.29-36.31" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:36.56-36.57" + } + } + } + }, + "\\$__ABC9_LUT7": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000001000", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.1-61.10" + }, + "ports": { + "M2": { + "direction": "input", + "bits": [ 2 ] + }, + "M1": { + "direction": "input", + "bits": [ 3 ] + }, + "M0": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "C": { + "direction": "input", + "bits": [ 6 ] + }, + "B": { + "direction": "input", + "bits": [ 7 ] + }, + "A": { + "direction": "input", + "bits": [ 8 ] + }, + "Z": { + "direction": "output", + "bits": [ 9 ] + } + }, + "cells": { + "$specify$295869": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000010010100", + "T_FALL_MIN": "00000000000000000000000010010100", + "T_FALL_TYP": "00000000000000000000000010010100", + "T_RISE_MAX": "00000000000000000000000010010100", + "T_RISE_MIN": "00000000000000000000000010010100", + "T_RISE_TYP": "00000000000000000000000010010100" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:53.9-53.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 2 ] + } + }, + "$specify$295870": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000100100001", + "T_FALL_MIN": "00000000000000000000000100100001", + "T_FALL_TYP": "00000000000000000000000100100001", + "T_RISE_MAX": "00000000000000000000000100100001", + "T_RISE_MIN": "00000000000000000000000100100001", + "T_RISE_TYP": "00000000000000000000000100100001" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:54.9-54.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 3 ] + } + }, + "$specify$295871": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000000110110001", + "T_FALL_MIN": "00000000000000000000000110110001", + "T_FALL_TYP": "00000000000000000000000110110001", + "T_RISE_MAX": "00000000000000000000000110110001", + "T_RISE_MIN": "00000000000000000000000110110001", + "T_RISE_TYP": "00000000000000000000000110110001" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:55.9-55.25" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 4 ] + } + }, + "$specify$295872": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001000001001", + "T_FALL_MIN": "00000000000000000000001000001001", + "T_FALL_TYP": "00000000000000000000001000001001", + "T_RISE_MAX": "00000000000000000000001000001001", + "T_RISE_MIN": "00000000000000000000001000001001", + "T_RISE_TYP": "00000000000000000000001000001001" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:56.9-56.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 5 ] + } + }, + "$specify$295873": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001010001111", + "T_FALL_MIN": "00000000000000000000001010001111", + "T_FALL_TYP": "00000000000000000000001010001111", + "T_RISE_MAX": "00000000000000000000001010001111", + "T_RISE_MIN": "00000000000000000000001010001111", + "T_RISE_TYP": "00000000000000000000001010001111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:57.9-57.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 6 ] + } + }, + "$specify$295874": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001011110111", + "T_FALL_MIN": "00000000000000000000001011110111", + "T_FALL_TYP": "00000000000000000000001011110111", + "T_RISE_MAX": "00000000000000000000001011110111", + "T_RISE_MIN": "00000000000000000000001011110111", + "T_RISE_TYP": "00000000000000000000001011110111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:58.9-58.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 7 ] + } + }, + "$specify$295875": { + "hide_name": 1, + "type": "$specify2", + "parameters": { + "DST_WIDTH": "00000000000000000000000000000001", + "FULL": "0", + "SRC_DST_PEN": "0", + "SRC_DST_POL": "0", + "SRC_WIDTH": "00000000000000000000000000000001", + "T_FALL_MAX": "00000000000000000000001011110111", + "T_FALL_MIN": "00000000000000000000001011110111", + "T_FALL_TYP": "00000000000000000000001011110111", + "T_RISE_MAX": "00000000000000000000001011110111", + "T_RISE_MIN": "00000000000000000000001011110111", + "T_RISE_TYP": "00000000000000000000001011110111" + }, + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:59.9-59.24" + }, + "port_directions": { + "DST": "input", + "EN": "input", + "SRC": "input" + }, + "connections": { + "DST": [ 9 ], + "EN": [ "1" ], + "SRC": [ 8 ] + } + } + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.50-51.51" + } + }, + "B": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.47-51.48" + } + }, + "C": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.44-51.45" + } + }, + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.41-51.42" + } + }, + "M0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.37-51.39" + } + }, + "M1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.33-51.35" + } + }, + "M2": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.29-51.31" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:51.60-51.61" + } + } + } + }, + "ALU54B": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:489.1-1007.10" + }, + "parameter_default_values": { + "CLK0_DIV": "ENABLED", + "CLK1_DIV": "ENABLED", + "CLK2_DIV": "ENABLED", + "CLK3_DIV": "ENABLED", + "FORCE_ZERO_BARREL_SHIFT": "DISABLED", + "GSR": "ENABLED", + "LEGACY": "DISABLED", + "MASK01": "0x00000000000000 ", + "MASKPAT": "0x00000000000000 ", + "MASKPAT_SOURCE": "STATIC", + "MCPAT": "0x00000000000000 ", + "MCPAT_SOURCE": "STATIC", + "MULT9_MODE": "DISABLED", + "REG_FLAG_CE": "CE0", + "REG_FLAG_CLK": "NONE", + "REG_FLAG_RST": "RST0", + "REG_INPUTC0_CE": "CE0", + "REG_INPUTC0_CLK": "NONE", + "REG_INPUTC0_RST": "RST0", + "REG_INPUTC1_CE": "CE0", + "REG_INPUTC1_CLK": "NONE", + "REG_INPUTC1_RST": "RST0", + "REG_INPUTCFB_CE": "CE0", + "REG_INPUTCFB_CLK": "NONE", + "REG_INPUTCFB_RST": "RST0", + "REG_OPCODEIN_0_CE": "CE0", + "REG_OPCODEIN_0_CLK": "NONE", + "REG_OPCODEIN_0_RST": "RST0", + "REG_OPCODEIN_1_CE": "CE0", + "REG_OPCODEIN_1_CLK": "NONE", + "REG_OPCODEIN_1_RST": "RST0", + "REG_OPCODEOP0_0_CE": "CE0", + "REG_OPCODEOP0_0_CLK": "NONE", + "REG_OPCODEOP0_0_RST": "RST0", + "REG_OPCODEOP0_1_CE": "CE0", + "REG_OPCODEOP0_1_CLK": "NONE", + "REG_OPCODEOP0_1_RST": "RST0", + "REG_OPCODEOP1_0_CLK": "NONE", + "REG_OPCODEOP1_1_CLK": "NONE", + "REG_OUTPUT0_CE": "CE0", + "REG_OUTPUT0_CLK": "NONE", + "REG_OUTPUT0_RST": "RST0", + "REG_OUTPUT1_CE": "CE0", + "REG_OUTPUT1_CLK": "NONE", + "REG_OUTPUT1_RST": "RST0", + "RESETMODE": "SYNC", + "RNDPAT": "0x00000000000000 " + }, + "ports": { + "CE3": { + "direction": "input", + "bits": [ 2 ] + }, + "CE2": { + "direction": "input", + "bits": [ 3 ] + }, + "CE1": { + "direction": "input", + "bits": [ 4 ] + }, + "CE0": { + "direction": "input", + "bits": [ 5 ] + }, + "CLK3": { + "direction": "input", + "bits": [ 6 ] + }, + "CLK2": { + "direction": "input", + "bits": [ 7 ] + }, + "CLK1": { + "direction": "input", + "bits": [ 8 ] + }, + "CLK0": { + "direction": "input", + "bits": [ 9 ] + }, + "RST3": { + "direction": "input", + "bits": [ 10 ] + }, + "RST2": { + "direction": "input", + "bits": [ 11 ] + }, + "RST1": { + "direction": "input", + "bits": [ 12 ] + }, + "RST0": { + "direction": "input", + "bits": [ 13 ] + }, + "SIGNEDIA": { + "direction": "input", + "bits": [ 14 ] + }, + "SIGNEDIB": { + "direction": "input", + "bits": [ 15 ] + }, + "SIGNEDCIN": { + "direction": "input", + "bits": [ 16 ] + }, + "A35": { + "direction": "input", + "bits": [ 17 ] + }, + "A34": { + "direction": "input", + "bits": [ 18 ] + }, + "A33": { + "direction": "input", + "bits": [ 19 ] + }, + "A32": { + "direction": "input", + "bits": [ 20 ] + }, + "A31": { + "direction": "input", + "bits": [ 21 ] + }, + "A30": { + "direction": "input", + "bits": [ 22 ] + }, + "A29": { + "direction": "input", + "bits": [ 23 ] + }, + "A28": { + "direction": "input", + "bits": [ 24 ] + }, + "A27": { + "direction": "input", + "bits": [ 25 ] + }, + "A26": { + "direction": "input", + "bits": [ 26 ] + }, + "A25": { + "direction": "input", + "bits": [ 27 ] + }, + "A24": { + "direction": "input", + "bits": [ 28 ] + }, + "A23": { + "direction": "input", + "bits": [ 29 ] + }, + "A22": { + "direction": "input", + "bits": [ 30 ] + }, + "A21": { + "direction": "input", + "bits": [ 31 ] + }, + "A20": { + "direction": "input", + "bits": [ 32 ] + }, + "A19": { + "direction": "input", + "bits": [ 33 ] + }, + "A18": { + "direction": "input", + "bits": [ 34 ] + }, + "A17": { + "direction": "input", + "bits": [ 35 ] + }, + "A16": { + "direction": "input", + "bits": [ 36 ] + }, + "A15": { + "direction": "input", + "bits": [ 37 ] + }, + "A14": { + "direction": "input", + "bits": [ 38 ] + }, + "A13": { + "direction": "input", + "bits": [ 39 ] + }, + "A12": { + "direction": "input", + "bits": [ 40 ] + }, + "A11": { + "direction": "input", + "bits": [ 41 ] + }, + "A10": { + "direction": "input", + "bits": [ 42 ] + }, + "A9": { + "direction": "input", + "bits": [ 43 ] + }, + "A8": { + "direction": "input", + "bits": [ 44 ] + }, + "A7": { + "direction": "input", + "bits": [ 45 ] + }, + "A6": { + "direction": "input", + "bits": [ 46 ] + }, + "A5": { + "direction": "input", + "bits": [ 47 ] + }, + "A4": { + "direction": "input", + "bits": [ 48 ] + }, + "A3": { + "direction": "input", + "bits": [ 49 ] + }, + "A2": { + "direction": "input", + "bits": [ 50 ] + }, + "A1": { + "direction": "input", + "bits": [ 51 ] + }, + "A0": { + "direction": "input", + "bits": [ 52 ] + }, + "B35": { + "direction": "input", + "bits": [ 53 ] + }, + "B34": { + "direction": "input", + "bits": [ 54 ] + }, + "B33": { + "direction": "input", + "bits": [ 55 ] + }, + "B32": { + "direction": "input", + "bits": [ 56 ] + }, + "B31": { + "direction": "input", + "bits": [ 57 ] + }, + "B30": { + "direction": "input", + "bits": [ 58 ] + }, + "B29": { + "direction": "input", + "bits": [ 59 ] + }, + "B28": { + "direction": "input", + "bits": [ 60 ] + }, + "B27": { + "direction": "input", + "bits": [ 61 ] + }, + "B26": { + "direction": "input", + "bits": [ 62 ] + }, + "B25": { + "direction": "input", + "bits": [ 63 ] + }, + "B24": { + "direction": "input", + "bits": [ 64 ] + }, + "B23": { + "direction": "input", + "bits": [ 65 ] + }, + "B22": { + "direction": "input", + "bits": [ 66 ] + }, + "B21": { + "direction": "input", + "bits": [ 67 ] + }, + "B20": { + "direction": "input", + "bits": [ 68 ] + }, + "B19": { + "direction": "input", + "bits": [ 69 ] + }, + "B18": { + "direction": "input", + "bits": [ 70 ] + }, + "B17": { + "direction": "input", + "bits": [ 71 ] + }, + "B16": { + "direction": "input", + "bits": [ 72 ] + }, + "B15": { + "direction": "input", + "bits": [ 73 ] + }, + "B14": { + "direction": "input", + "bits": [ 74 ] + }, + "B13": { + "direction": "input", + "bits": [ 75 ] + }, + "B12": { + "direction": "input", + "bits": [ 76 ] + }, + "B11": { + "direction": "input", + "bits": [ 77 ] + }, + "B10": { + "direction": "input", + "bits": [ 78 ] + }, + "B9": { + "direction": "input", + "bits": [ 79 ] + }, + "B8": { + "direction": "input", + "bits": [ 80 ] + }, + "B7": { + "direction": "input", + "bits": [ 81 ] + }, + "B6": { + "direction": "input", + "bits": [ 82 ] + }, + "B5": { + "direction": "input", + "bits": [ 83 ] + }, + "B4": { + "direction": "input", + "bits": [ 84 ] + }, + "B3": { + "direction": "input", + "bits": [ 85 ] + }, + "B2": { + "direction": "input", + "bits": [ 86 ] + }, + "B1": { + "direction": "input", + "bits": [ 87 ] + }, + "B0": { + "direction": "input", + "bits": [ 88 ] + }, + "C53": { + "direction": "input", + "bits": [ 89 ] + }, + "C52": { + "direction": "input", + "bits": [ 90 ] + }, + "C51": { + "direction": "input", + "bits": [ 91 ] + }, + "C50": { + "direction": "input", + "bits": [ 92 ] + }, + "C49": { + "direction": "input", + "bits": [ 93 ] + }, + "C48": { + "direction": "input", + "bits": [ 94 ] + }, + "C47": { + "direction": "input", + "bits": [ 95 ] + }, + "C46": { + "direction": "input", + "bits": [ 96 ] + }, + "C45": { + "direction": "input", + "bits": [ 97 ] + }, + "C44": { + "direction": "input", + "bits": [ 98 ] + }, + "C43": { + "direction": "input", + "bits": [ 99 ] + }, + "C42": { + "direction": "input", + "bits": [ 100 ] + }, + "C41": { + "direction": "input", + "bits": [ 101 ] + }, + "C40": { + "direction": "input", + "bits": [ 102 ] + }, + "C39": { + "direction": "input", + "bits": [ 103 ] + }, + "C38": { + "direction": "input", + "bits": [ 104 ] + }, + "C37": { + "direction": "input", + "bits": [ 105 ] + }, + "C36": { + "direction": "input", + "bits": [ 106 ] + }, + "C35": { + "direction": "input", + "bits": [ 107 ] + }, + "C34": { + "direction": "input", + "bits": [ 108 ] + }, + "C33": { + "direction": "input", + "bits": [ 109 ] + }, + "C32": { + "direction": "input", + "bits": [ 110 ] + }, + "C31": { + "direction": "input", + "bits": [ 111 ] + }, + "C30": { + "direction": "input", + "bits": [ 112 ] + }, + "C29": { + "direction": "input", + "bits": [ 113 ] + }, + "C28": { + "direction": "input", + "bits": [ 114 ] + }, + "C27": { + "direction": "input", + "bits": [ 115 ] + }, + "C26": { + "direction": "input", + "bits": [ 116 ] + }, + "C25": { + "direction": "input", + "bits": [ 117 ] + }, + "C24": { + "direction": "input", + "bits": [ 118 ] + }, + "C23": { + "direction": "input", + "bits": [ 119 ] + }, + "C22": { + "direction": "input", + "bits": [ 120 ] + }, + "C21": { + "direction": "input", + "bits": [ 121 ] + }, + "C20": { + "direction": "input", + "bits": [ 122 ] + }, + "C19": { + "direction": "input", + "bits": [ 123 ] + }, + "C18": { + "direction": "input", + "bits": [ 124 ] + }, + "C17": { + "direction": "input", + "bits": [ 125 ] + }, + "C16": { + "direction": "input", + "bits": [ 126 ] + }, + "C15": { + "direction": "input", + "bits": [ 127 ] + }, + "C14": { + "direction": "input", + "bits": [ 128 ] + }, + "C13": { + "direction": "input", + "bits": [ 129 ] + }, + "C12": { + "direction": "input", + "bits": [ 130 ] + }, + "C11": { + "direction": "input", + "bits": [ 131 ] + }, + "C10": { + "direction": "input", + "bits": [ 132 ] + }, + "C9": { + "direction": "input", + "bits": [ 133 ] + }, + "C8": { + "direction": "input", + "bits": [ 134 ] + }, + "C7": { + "direction": "input", + "bits": [ 135 ] + }, + "C6": { + "direction": "input", + "bits": [ 136 ] + }, + "C5": { + "direction": "input", + "bits": [ 137 ] + }, + "C4": { + "direction": "input", + "bits": [ 138 ] + }, + "C3": { + "direction": "input", + "bits": [ 139 ] + }, + "C2": { + "direction": "input", + "bits": [ 140 ] + }, + "C1": { + "direction": "input", + "bits": [ 141 ] + }, + "C0": { + "direction": "input", + "bits": [ 142 ] + }, + "CFB53": { + "direction": "input", + "bits": [ 143 ] + }, + "CFB52": { + "direction": "input", + "bits": [ 144 ] + }, + "CFB51": { + "direction": "input", + "bits": [ 145 ] + }, + "CFB50": { + "direction": "input", + "bits": [ 146 ] + }, + "CFB49": { + "direction": "input", + "bits": [ 147 ] + }, + "CFB48": { + "direction": "input", + "bits": [ 148 ] + }, + "CFB47": { + "direction": "input", + "bits": [ 149 ] + }, + "CFB46": { + "direction": "input", + "bits": [ 150 ] + }, + "CFB45": { + "direction": "input", + "bits": [ 151 ] + }, + "CFB44": { + "direction": "input", + "bits": [ 152 ] + }, + "CFB43": { + "direction": "input", + "bits": [ 153 ] + }, + "CFB42": { + "direction": "input", + "bits": [ 154 ] + }, + "CFB41": { + "direction": "input", + "bits": [ 155 ] + }, + "CFB40": { + "direction": "input", + "bits": [ 156 ] + }, + "CFB39": { + "direction": "input", + "bits": [ 157 ] + }, + "CFB38": { + "direction": "input", + "bits": [ 158 ] + }, + "CFB37": { + "direction": "input", + "bits": [ 159 ] + }, + "CFB36": { + "direction": "input", + "bits": [ 160 ] + }, + "CFB35": { + "direction": "input", + "bits": [ 161 ] + }, + "CFB34": { + "direction": "input", + "bits": [ 162 ] + }, + "CFB33": { + "direction": "input", + "bits": [ 163 ] + }, + "CFB32": { + "direction": "input", + "bits": [ 164 ] + }, + "CFB31": { + "direction": "input", + "bits": [ 165 ] + }, + "CFB30": { + "direction": "input", + "bits": [ 166 ] + }, + "CFB29": { + "direction": "input", + "bits": [ 167 ] + }, + "CFB28": { + "direction": "input", + "bits": [ 168 ] + }, + "CFB27": { + "direction": "input", + "bits": [ 169 ] + }, + "CFB26": { + "direction": "input", + "bits": [ 170 ] + }, + "CFB25": { + "direction": "input", + "bits": [ 171 ] + }, + "CFB24": { + "direction": "input", + "bits": [ 172 ] + }, + "CFB23": { + "direction": "input", + "bits": [ 173 ] + }, + "CFB22": { + "direction": "input", + "bits": [ 174 ] + }, + "CFB21": { + "direction": "input", + "bits": [ 175 ] + }, + "CFB20": { + "direction": "input", + "bits": [ 176 ] + }, + "CFB19": { + "direction": "input", + "bits": [ 177 ] + }, + "CFB18": { + "direction": "input", + "bits": [ 178 ] + }, + "CFB17": { + "direction": "input", + "bits": [ 179 ] + }, + "CFB16": { + "direction": "input", + "bits": [ 180 ] + }, + "CFB15": { + "direction": "input", + "bits": [ 181 ] + }, + "CFB14": { + "direction": "input", + "bits": [ 182 ] + }, + "CFB13": { + "direction": "input", + "bits": [ 183 ] + }, + "CFB12": { + "direction": "input", + "bits": [ 184 ] + }, + "CFB11": { + "direction": "input", + "bits": [ 185 ] + }, + "CFB10": { + "direction": "input", + "bits": [ 186 ] + }, + "CFB9": { + "direction": "input", + "bits": [ 187 ] + }, + "CFB8": { + "direction": "input", + "bits": [ 188 ] + }, + "CFB7": { + "direction": "input", + "bits": [ 189 ] + }, + "CFB6": { + "direction": "input", + "bits": [ 190 ] + }, + "CFB5": { + "direction": "input", + "bits": [ 191 ] + }, + "CFB4": { + "direction": "input", + "bits": [ 192 ] + }, + "CFB3": { + "direction": "input", + "bits": [ 193 ] + }, + "CFB2": { + "direction": "input", + "bits": [ 194 ] + }, + "CFB1": { + "direction": "input", + "bits": [ 195 ] + }, + "CFB0": { + "direction": "input", + "bits": [ 196 ] + }, + "MA35": { + "direction": "input", + "bits": [ 197 ] + }, + "MA34": { + "direction": "input", + "bits": [ 198 ] + }, + "MA33": { + "direction": "input", + "bits": [ 199 ] + }, + "MA32": { + "direction": "input", + "bits": [ 200 ] + }, + "MA31": { + "direction": "input", + "bits": [ 201 ] + }, + "MA30": { + "direction": "input", + "bits": [ 202 ] + }, + "MA29": { + "direction": "input", + "bits": [ 203 ] + }, + "MA28": { + "direction": "input", + "bits": [ 204 ] + }, + "MA27": { + "direction": "input", + "bits": [ 205 ] + }, + "MA26": { + "direction": "input", + "bits": [ 206 ] + }, + "MA25": { + "direction": "input", + "bits": [ 207 ] + }, + "MA24": { + "direction": "input", + "bits": [ 208 ] + }, + "MA23": { + "direction": "input", + "bits": [ 209 ] + }, + "MA22": { + "direction": "input", + "bits": [ 210 ] + }, + "MA21": { + "direction": "input", + "bits": [ 211 ] + }, + "MA20": { + "direction": "input", + "bits": [ 212 ] + }, + "MA19": { + "direction": "input", + "bits": [ 213 ] + }, + "MA18": { + "direction": "input", + "bits": [ 214 ] + }, + "MA17": { + "direction": "input", + "bits": [ 215 ] + }, + "MA16": { + "direction": "input", + "bits": [ 216 ] + }, + "MA15": { + "direction": "input", + "bits": [ 217 ] + }, + "MA14": { + "direction": "input", + "bits": [ 218 ] + }, + "MA13": { + "direction": "input", + "bits": [ 219 ] + }, + "MA12": { + "direction": "input", + "bits": [ 220 ] + }, + "MA11": { + "direction": "input", + "bits": [ 221 ] + }, + "MA10": { + "direction": "input", + "bits": [ 222 ] + }, + "MA9": { + "direction": "input", + "bits": [ 223 ] + }, + "MA8": { + "direction": "input", + "bits": [ 224 ] + }, + "MA7": { + "direction": "input", + "bits": [ 225 ] + }, + "MA6": { + "direction": "input", + "bits": [ 226 ] + }, + "MA5": { + "direction": "input", + "bits": [ 227 ] + }, + "MA4": { + "direction": "input", + "bits": [ 228 ] + }, + "MA3": { + "direction": "input", + "bits": [ 229 ] + }, + "MA2": { + "direction": "input", + "bits": [ 230 ] + }, + "MA1": { + "direction": "input", + "bits": [ 231 ] + }, + "MA0": { + "direction": "input", + "bits": [ 232 ] + }, + "MB35": { + "direction": "input", + "bits": [ 233 ] + }, + "MB34": { + "direction": "input", + "bits": [ 234 ] + }, + "MB33": { + "direction": "input", + "bits": [ 235 ] + }, + "MB32": { + "direction": "input", + "bits": [ 236 ] + }, + "MB31": { + "direction": "input", + "bits": [ 237 ] + }, + "MB30": { + "direction": "input", + "bits": [ 238 ] + }, + "MB29": { + "direction": "input", + "bits": [ 239 ] + }, + "MB28": { + "direction": "input", + "bits": [ 240 ] + }, + "MB27": { + "direction": "input", + "bits": [ 241 ] + }, + "MB26": { + "direction": "input", + "bits": [ 242 ] + }, + "MB25": { + "direction": "input", + "bits": [ 243 ] + }, + "MB24": { + "direction": "input", + "bits": [ 244 ] + }, + "MB23": { + "direction": "input", + "bits": [ 245 ] + }, + "MB22": { + "direction": "input", + "bits": [ 246 ] + }, + "MB21": { + "direction": "input", + "bits": [ 247 ] + }, + "MB20": { + "direction": "input", + "bits": [ 248 ] + }, + "MB19": { + "direction": "input", + "bits": [ 249 ] + }, + "MB18": { + "direction": "input", + "bits": [ 250 ] + }, + "MB17": { + "direction": "input", + "bits": [ 251 ] + }, + "MB16": { + "direction": "input", + "bits": [ 252 ] + }, + "MB15": { + "direction": "input", + "bits": [ 253 ] + }, + "MB14": { + "direction": "input", + "bits": [ 254 ] + }, + "MB13": { + "direction": "input", + "bits": [ 255 ] + }, + "MB12": { + "direction": "input", + "bits": [ 256 ] + }, + "MB11": { + "direction": "input", + "bits": [ 257 ] + }, + "MB10": { + "direction": "input", + "bits": [ 258 ] + }, + "MB9": { + "direction": "input", + "bits": [ 259 ] + }, + "MB8": { + "direction": "input", + "bits": [ 260 ] + }, + "MB7": { + "direction": "input", + "bits": [ 261 ] + }, + "MB6": { + "direction": "input", + "bits": [ 262 ] + }, + "MB5": { + "direction": "input", + "bits": [ 263 ] + }, + "MB4": { + "direction": "input", + "bits": [ 264 ] + }, + "MB3": { + "direction": "input", + "bits": [ 265 ] + }, + "MB2": { + "direction": "input", + "bits": [ 266 ] + }, + "MB1": { + "direction": "input", + "bits": [ 267 ] + }, + "MB0": { + "direction": "input", + "bits": [ 268 ] + }, + "CIN53": { + "direction": "input", + "bits": [ 269 ] + }, + "CIN52": { + "direction": "input", + "bits": [ 270 ] + }, + "CIN51": { + "direction": "input", + "bits": [ 271 ] + }, + "CIN50": { + "direction": "input", + "bits": [ 272 ] + }, + "CIN49": { + "direction": "input", + "bits": [ 273 ] + }, + "CIN48": { + "direction": "input", + "bits": [ 274 ] + }, + "CIN47": { + "direction": "input", + "bits": [ 275 ] + }, + "CIN46": { + "direction": "input", + "bits": [ 276 ] + }, + "CIN45": { + "direction": "input", + "bits": [ 277 ] + }, + "CIN44": { + "direction": "input", + "bits": [ 278 ] + }, + "CIN43": { + "direction": "input", + "bits": [ 279 ] + }, + "CIN42": { + "direction": "input", + "bits": [ 280 ] + }, + "CIN41": { + "direction": "input", + "bits": [ 281 ] + }, + "CIN40": { + "direction": "input", + "bits": [ 282 ] + }, + "CIN39": { + "direction": "input", + "bits": [ 283 ] + }, + "CIN38": { + "direction": "input", + "bits": [ 284 ] + }, + "CIN37": { + "direction": "input", + "bits": [ 285 ] + }, + "CIN36": { + "direction": "input", + "bits": [ 286 ] + }, + "CIN35": { + "direction": "input", + "bits": [ 287 ] + }, + "CIN34": { + "direction": "input", + "bits": [ 288 ] + }, + "CIN33": { + "direction": "input", + "bits": [ 289 ] + }, + "CIN32": { + "direction": "input", + "bits": [ 290 ] + }, + "CIN31": { + "direction": "input", + "bits": [ 291 ] + }, + "CIN30": { + "direction": "input", + "bits": [ 292 ] + }, + "CIN29": { + "direction": "input", + "bits": [ 293 ] + }, + "CIN28": { + "direction": "input", + "bits": [ 294 ] + }, + "CIN27": { + "direction": "input", + "bits": [ 295 ] + }, + "CIN26": { + "direction": "input", + "bits": [ 296 ] + }, + "CIN25": { + "direction": "input", + "bits": [ 297 ] + }, + "CIN24": { + "direction": "input", + "bits": [ 298 ] + }, + "CIN23": { + "direction": "input", + "bits": [ 299 ] + }, + "CIN22": { + "direction": "input", + "bits": [ 300 ] + }, + "CIN21": { + "direction": "input", + "bits": [ 301 ] + }, + "CIN20": { + "direction": "input", + "bits": [ 302 ] + }, + "CIN19": { + "direction": "input", + "bits": [ 303 ] + }, + "CIN18": { + "direction": "input", + "bits": [ 304 ] + }, + "CIN17": { + "direction": "input", + "bits": [ 305 ] + }, + "CIN16": { + "direction": "input", + "bits": [ 306 ] + }, + "CIN15": { + "direction": "input", + "bits": [ 307 ] + }, + "CIN14": { + "direction": "input", + "bits": [ 308 ] + }, + "CIN13": { + "direction": "input", + "bits": [ 309 ] + }, + "CIN12": { + "direction": "input", + "bits": [ 310 ] + }, + "CIN11": { + "direction": "input", + "bits": [ 311 ] + }, + "CIN10": { + "direction": "input", + "bits": [ 312 ] + }, + "CIN9": { + "direction": "input", + "bits": [ 313 ] + }, + "CIN8": { + "direction": "input", + "bits": [ 314 ] + }, + "CIN7": { + "direction": "input", + "bits": [ 315 ] + }, + "CIN6": { + "direction": "input", + "bits": [ 316 ] + }, + "CIN5": { + "direction": "input", + "bits": [ 317 ] + }, + "CIN4": { + "direction": "input", + "bits": [ 318 ] + }, + "CIN3": { + "direction": "input", + "bits": [ 319 ] + }, + "CIN2": { + "direction": "input", + "bits": [ 320 ] + }, + "CIN1": { + "direction": "input", + "bits": [ 321 ] + }, + "CIN0": { + "direction": "input", + "bits": [ 322 ] + }, + "OP10": { + "direction": "input", + "bits": [ 323 ] + }, + "OP9": { + "direction": "input", + "bits": [ 324 ] + }, + "OP8": { + "direction": "input", + "bits": [ 325 ] + }, + "OP7": { + "direction": "input", + "bits": [ 326 ] + }, + "OP6": { + "direction": "input", + "bits": [ 327 ] + }, + "OP5": { + "direction": "input", + "bits": [ 328 ] + }, + "OP4": { + "direction": "input", + "bits": [ 329 ] + }, + "OP3": { + "direction": "input", + "bits": [ 330 ] + }, + "OP2": { + "direction": "input", + "bits": [ 331 ] + }, + "OP1": { + "direction": "input", + "bits": [ 332 ] + }, + "OP0": { + "direction": "input", + "bits": [ 333 ] + }, + "R53": { + "direction": "output", + "bits": [ 334 ] + }, + "R52": { + "direction": "output", + "bits": [ 335 ] + }, + "R51": { + "direction": "output", + "bits": [ 336 ] + }, + "R50": { + "direction": "output", + "bits": [ 337 ] + }, + "R49": { + "direction": "output", + "bits": [ 338 ] + }, + "R48": { + "direction": "output", + "bits": [ 339 ] + }, + "R47": { + "direction": "output", + "bits": [ 340 ] + }, + "R46": { + "direction": "output", + "bits": [ 341 ] + }, + "R45": { + "direction": "output", + "bits": [ 342 ] + }, + "R44": { + "direction": "output", + "bits": [ 343 ] + }, + "R43": { + "direction": "output", + "bits": [ 344 ] + }, + "R42": { + "direction": "output", + "bits": [ 345 ] + }, + "R41": { + "direction": "output", + "bits": [ 346 ] + }, + "R40": { + "direction": "output", + "bits": [ 347 ] + }, + "R39": { + "direction": "output", + "bits": [ 348 ] + }, + "R38": { + "direction": "output", + "bits": [ 349 ] + }, + "R37": { + "direction": "output", + "bits": [ 350 ] + }, + "R36": { + "direction": "output", + "bits": [ 351 ] + }, + "R35": { + "direction": "output", + "bits": [ 352 ] + }, + "R34": { + "direction": "output", + "bits": [ 353 ] + }, + "R33": { + "direction": "output", + "bits": [ 354 ] + }, + "R32": { + "direction": "output", + "bits": [ 355 ] + }, + "R31": { + "direction": "output", + "bits": [ 356 ] + }, + "R30": { + "direction": "output", + "bits": [ 357 ] + }, + "R29": { + "direction": "output", + "bits": [ 358 ] + }, + "R28": { + "direction": "output", + "bits": [ 359 ] + }, + "R27": { + "direction": "output", + "bits": [ 360 ] + }, + "R26": { + "direction": "output", + "bits": [ 361 ] + }, + "R25": { + "direction": "output", + "bits": [ 362 ] + }, + "R24": { + "direction": "output", + "bits": [ 363 ] + }, + "R23": { + "direction": "output", + "bits": [ 364 ] + }, + "R22": { + "direction": "output", + "bits": [ 365 ] + }, + "R21": { + "direction": "output", + "bits": [ 366 ] + }, + "R20": { + "direction": "output", + "bits": [ 367 ] + }, + "R19": { + "direction": "output", + "bits": [ 368 ] + }, + "R18": { + "direction": "output", + "bits": [ 369 ] + }, + "R17": { + "direction": "output", + "bits": [ 370 ] + }, + "R16": { + "direction": "output", + "bits": [ 371 ] + }, + "R15": { + "direction": "output", + "bits": [ 372 ] + }, + "R14": { + "direction": "output", + "bits": [ 373 ] + }, + "R13": { + "direction": "output", + "bits": [ 374 ] + }, + "R12": { + "direction": "output", + "bits": [ 375 ] + }, + "R11": { + "direction": "output", + "bits": [ 376 ] + }, + "R10": { + "direction": "output", + "bits": [ 377 ] + }, + "R9": { + "direction": "output", + "bits": [ 378 ] + }, + "R8": { + "direction": "output", + "bits": [ 379 ] + }, + "R7": { + "direction": "output", + "bits": [ 380 ] + }, + "R6": { + "direction": "output", + "bits": [ 381 ] + }, + "R5": { + "direction": "output", + "bits": [ 382 ] + }, + "R4": { + "direction": "output", + "bits": [ 383 ] + }, + "R3": { + "direction": "output", + "bits": [ 384 ] + }, + "R2": { + "direction": "output", + "bits": [ 385 ] + }, + "R1": { + "direction": "output", + "bits": [ 386 ] + }, + "R0": { + "direction": "output", + "bits": [ 387 ] + }, + "CO53": { + "direction": "output", + "bits": [ 388 ] + }, + "CO52": { + "direction": "output", + "bits": [ 389 ] + }, + "CO51": { + "direction": "output", + "bits": [ 390 ] + }, + "CO50": { + "direction": "output", + "bits": [ 391 ] + }, + "CO49": { + "direction": "output", + "bits": [ 392 ] + }, + "CO48": { + "direction": "output", + "bits": [ 393 ] + }, + "CO47": { + "direction": "output", + "bits": [ 394 ] + }, + "CO46": { + "direction": "output", + "bits": [ 395 ] + }, + "CO45": { + "direction": "output", + "bits": [ 396 ] + }, + "CO44": { + "direction": "output", + "bits": [ 397 ] + }, + "CO43": { + "direction": "output", + "bits": [ 398 ] + }, + "CO42": { + "direction": "output", + "bits": [ 399 ] + }, + "CO41": { + "direction": "output", + "bits": [ 400 ] + }, + "CO40": { + "direction": "output", + "bits": [ 401 ] + }, + "CO39": { + "direction": "output", + "bits": [ 402 ] + }, + "CO38": { + "direction": "output", + "bits": [ 403 ] + }, + "CO37": { + "direction": "output", + "bits": [ 404 ] + }, + "CO36": { + "direction": "output", + "bits": [ 405 ] + }, + "CO35": { + "direction": "output", + "bits": [ 406 ] + }, + "CO34": { + "direction": "output", + "bits": [ 407 ] + }, + "CO33": { + "direction": "output", + "bits": [ 408 ] + }, + "CO32": { + "direction": "output", + "bits": [ 409 ] + }, + "CO31": { + "direction": "output", + "bits": [ 410 ] + }, + "CO30": { + "direction": "output", + "bits": [ 411 ] + }, + "CO29": { + "direction": "output", + "bits": [ 412 ] + }, + "CO28": { + "direction": "output", + "bits": [ 413 ] + }, + "CO27": { + "direction": "output", + "bits": [ 414 ] + }, + "CO26": { + "direction": "output", + "bits": [ 415 ] + }, + "CO25": { + "direction": "output", + "bits": [ 416 ] + }, + "CO24": { + "direction": "output", + "bits": [ 417 ] + }, + "CO23": { + "direction": "output", + "bits": [ 418 ] + }, + "CO22": { + "direction": "output", + "bits": [ 419 ] + }, + "CO21": { + "direction": "output", + "bits": [ 420 ] + }, + "CO20": { + "direction": "output", + "bits": [ 421 ] + }, + "CO19": { + "direction": "output", + "bits": [ 422 ] + }, + "CO18": { + "direction": "output", + "bits": [ 423 ] + }, + "CO17": { + "direction": "output", + "bits": [ 424 ] + }, + "CO16": { + "direction": "output", + "bits": [ 425 ] + }, + "CO15": { + "direction": "output", + "bits": [ 426 ] + }, + "CO14": { + "direction": "output", + "bits": [ 427 ] + }, + "CO13": { + "direction": "output", + "bits": [ 428 ] + }, + "CO12": { + "direction": "output", + "bits": [ 429 ] + }, + "CO11": { + "direction": "output", + "bits": [ 430 ] + }, + "CO10": { + "direction": "output", + "bits": [ 431 ] + }, + "CO9": { + "direction": "output", + "bits": [ 432 ] + }, + "CO8": { + "direction": "output", + "bits": [ 433 ] + }, + "CO7": { + "direction": "output", + "bits": [ 434 ] + }, + "CO6": { + "direction": "output", + "bits": [ 435 ] + }, + "CO5": { + "direction": "output", + "bits": [ 436 ] + }, + "CO4": { + "direction": "output", + "bits": [ 437 ] + }, + "CO3": { + "direction": "output", + "bits": [ 438 ] + }, + "CO2": { + "direction": "output", + "bits": [ 439 ] + }, + "CO1": { + "direction": "output", + "bits": [ 440 ] + }, + "CO0": { + "direction": "output", + "bits": [ 441 ] + }, + "EQZ": { + "direction": "output", + "bits": [ 442 ] + }, + "EQZM": { + "direction": "output", + "bits": [ 443 ] + }, + "EQOM": { + "direction": "output", + "bits": [ 444 ] + }, + "EQPAT": { + "direction": "output", + "bits": [ 445 ] + }, + "EQPATB": { + "direction": "output", + "bits": [ 446 ] + }, + "OVER": { + "direction": "output", + "bits": [ 447 ] + }, + "UNDER": { + "direction": "output", + "bits": [ 448 ] + }, + "OVERUNDER": { + "direction": "output", + "bits": [ 449 ] + }, + "SIGNEDR": { + "direction": "output", + "bits": [ 450 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:608.11-608.13" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:607.11-607.13" + } + }, + "A10": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:598.11-598.14" + } + }, + "A11": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:597.11-597.14" + } + }, + "A12": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:596.11-596.14" + } + }, + "A13": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:595.11-595.14" + } + }, + "A14": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:594.11-594.14" + } + }, + "A15": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:593.11-593.14" + } + }, + "A16": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:592.11-592.14" + } + }, + "A17": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:591.11-591.14" + } + }, + "A18": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:590.11-590.14" + } + }, + "A19": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:589.11-589.14" + } + }, + "A2": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:606.11-606.13" + } + }, + "A20": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:588.11-588.14" + } + }, + "A21": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:587.11-587.14" + } + }, + "A22": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:586.11-586.14" + } + }, + "A23": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:585.11-585.14" + } + }, + "A24": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:584.11-584.14" + } + }, + "A25": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:583.11-583.14" + } + }, + "A26": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:582.11-582.14" + } + }, + "A27": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:581.11-581.14" + } + }, + "A28": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:580.11-580.14" + } + }, + "A29": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:579.11-579.14" + } + }, + "A3": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:605.11-605.13" + } + }, + "A30": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:578.11-578.14" + } + }, + "A31": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:577.11-577.14" + } + }, + "A32": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:576.11-576.14" + } + }, + "A33": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:575.11-575.14" + } + }, + "A34": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:574.11-574.14" + } + }, + "A35": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:573.11-573.14" + } + }, + "A4": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:604.11-604.13" + } + }, + "A5": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:603.11-603.13" + } + }, + "A6": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:602.11-602.13" + } + }, + "A7": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:601.11-601.13" + } + }, + "A8": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:600.11-600.13" + } + }, + "A9": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:599.11-599.13" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:644.11-644.13" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:643.11-643.13" + } + }, + "B10": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:634.11-634.14" + } + }, + "B11": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:633.11-633.14" + } + }, + "B12": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:632.11-632.14" + } + }, + "B13": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:631.11-631.14" + } + }, + "B14": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:630.11-630.14" + } + }, + "B15": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:629.11-629.14" + } + }, + "B16": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:628.11-628.14" + } + }, + "B17": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:627.11-627.14" + } + }, + "B18": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:626.11-626.14" + } + }, + "B19": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:625.11-625.14" + } + }, + "B2": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:642.11-642.13" + } + }, + "B20": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:624.11-624.14" + } + }, + "B21": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:623.11-623.14" + } + }, + "B22": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:622.11-622.14" + } + }, + "B23": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:621.11-621.14" + } + }, + "B24": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:620.11-620.14" + } + }, + "B25": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:619.11-619.14" + } + }, + "B26": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:618.11-618.14" + } + }, + "B27": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:617.11-617.14" + } + }, + "B28": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:616.11-616.14" + } + }, + "B29": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:615.11-615.14" + } + }, + "B3": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:641.11-641.13" + } + }, + "B30": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:614.11-614.14" + } + }, + "B31": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:613.11-613.14" + } + }, + "B32": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:612.11-612.14" + } + }, + "B33": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:611.11-611.14" + } + }, + "B34": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:610.11-610.14" + } + }, + "B35": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:609.11-609.14" + } + }, + "B4": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:640.11-640.13" + } + }, + "B5": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:639.11-639.13" + } + }, + "B6": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:638.11-638.13" + } + }, + "B7": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:637.11-637.13" + } + }, + "B8": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:636.11-636.13" + } + }, + "B9": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:635.11-635.13" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:698.11-698.13" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:697.11-697.13" + } + }, + "C10": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:688.11-688.14" + } + }, + "C11": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:687.11-687.14" + } + }, + "C12": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:686.11-686.14" + } + }, + "C13": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:685.11-685.14" + } + }, + "C14": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:684.11-684.14" + } + }, + "C15": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:683.11-683.14" + } + }, + "C16": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:682.11-682.14" + } + }, + "C17": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:681.11-681.14" + } + }, + "C18": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:680.11-680.14" + } + }, + "C19": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:679.11-679.14" + } + }, + "C2": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:696.11-696.13" + } + }, + "C20": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:678.11-678.14" + } + }, + "C21": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:677.11-677.14" + } + }, + "C22": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:676.11-676.14" + } + }, + "C23": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:675.11-675.14" + } + }, + "C24": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:674.11-674.14" + } + }, + "C25": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:673.11-673.14" + } + }, + "C26": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:672.11-672.14" + } + }, + "C27": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:671.11-671.14" + } + }, + "C28": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:670.11-670.14" + } + }, + "C29": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:669.11-669.14" + } + }, + "C3": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:695.11-695.13" + } + }, + "C30": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:668.11-668.14" + } + }, + "C31": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:667.11-667.14" + } + }, + "C32": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:666.11-666.14" + } + }, + "C33": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:665.11-665.14" + } + }, + "C34": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:664.11-664.14" + } + }, + "C35": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:663.11-663.14" + } + }, + "C36": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:662.11-662.14" + } + }, + "C37": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:661.11-661.14" + } + }, + "C38": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:660.11-660.14" + } + }, + "C39": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:659.11-659.14" + } + }, + "C4": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:694.11-694.13" + } + }, + "C40": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:658.11-658.14" + } + }, + "C41": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:657.11-657.14" + } + }, + "C42": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:656.11-656.14" + } + }, + "C43": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:655.11-655.14" + } + }, + "C44": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:654.11-654.14" + } + }, + "C45": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:653.11-653.14" + } + }, + "C46": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:652.11-652.14" + } + }, + "C47": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:651.11-651.14" + } + }, + "C48": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:650.11-650.14" + } + }, + "C49": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:649.11-649.14" + } + }, + "C5": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:693.11-693.13" + } + }, + "C50": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:648.11-648.14" + } + }, + "C51": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:647.11-647.14" + } + }, + "C52": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:646.11-646.14" + } + }, + "C53": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:645.11-645.14" + } + }, + "C6": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:692.11-692.13" + } + }, + "C7": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:691.11-691.13" + } + }, + "C8": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:690.11-690.13" + } + }, + "C9": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:689.11-689.13" + } + }, + "CE0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:561.11-561.14" + } + }, + "CE1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:560.11-560.14" + } + }, + "CE2": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:559.11-559.14" + } + }, + "CE3": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:558.11-558.14" + } + }, + "CFB0": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:752.11-752.15" + } + }, + "CFB1": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:751.11-751.15" + } + }, + "CFB10": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:742.11-742.16" + } + }, + "CFB11": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:741.11-741.16" + } + }, + "CFB12": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:740.11-740.16" + } + }, + "CFB13": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:739.11-739.16" + } + }, + "CFB14": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:738.11-738.16" + } + }, + "CFB15": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:737.11-737.16" + } + }, + "CFB16": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:736.11-736.16" + } + }, + "CFB17": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:735.11-735.16" + } + }, + "CFB18": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:734.11-734.16" + } + }, + "CFB19": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:733.11-733.16" + } + }, + "CFB2": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:750.11-750.15" + } + }, + "CFB20": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:732.11-732.16" + } + }, + "CFB21": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:731.11-731.16" + } + }, + "CFB22": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:730.11-730.16" + } + }, + "CFB23": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:729.11-729.16" + } + }, + "CFB24": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:728.11-728.16" + } + }, + "CFB25": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:727.11-727.16" + } + }, + "CFB26": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:726.11-726.16" + } + }, + "CFB27": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:725.11-725.16" + } + }, + "CFB28": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:724.11-724.16" + } + }, + "CFB29": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:723.11-723.16" + } + }, + "CFB3": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:749.11-749.15" + } + }, + "CFB30": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:722.11-722.16" + } + }, + "CFB31": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:721.11-721.16" + } + }, + "CFB32": { + "hide_name": 0, + "bits": [ 164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:720.11-720.16" + } + }, + "CFB33": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:719.11-719.16" + } + }, + "CFB34": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:718.11-718.16" + } + }, + "CFB35": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:717.11-717.16" + } + }, + "CFB36": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:716.11-716.16" + } + }, + "CFB37": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:715.11-715.16" + } + }, + "CFB38": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:714.11-714.16" + } + }, + "CFB39": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:713.11-713.16" + } + }, + "CFB4": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:748.11-748.15" + } + }, + "CFB40": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:712.11-712.16" + } + }, + "CFB41": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:711.11-711.16" + } + }, + "CFB42": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:710.11-710.16" + } + }, + "CFB43": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:709.11-709.16" + } + }, + "CFB44": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:708.11-708.16" + } + }, + "CFB45": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:707.11-707.16" + } + }, + "CFB46": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:706.11-706.16" + } + }, + "CFB47": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:705.11-705.16" + } + }, + "CFB48": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:704.11-704.16" + } + }, + "CFB49": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:703.11-703.16" + } + }, + "CFB5": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:747.11-747.15" + } + }, + "CFB50": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:702.11-702.16" + } + }, + "CFB51": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:701.11-701.16" + } + }, + "CFB52": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:700.11-700.16" + } + }, + "CFB53": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:699.11-699.16" + } + }, + "CFB6": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:746.11-746.15" + } + }, + "CFB7": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:745.11-745.15" + } + }, + "CFB8": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:744.11-744.15" + } + }, + "CFB9": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:743.11-743.15" + } + }, + "CIN0": { + "hide_name": 0, + "bits": [ 322 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:878.11-878.15" + } + }, + "CIN1": { + "hide_name": 0, + "bits": [ 321 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:877.11-877.15" + } + }, + "CIN10": { + "hide_name": 0, + "bits": [ 312 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:868.11-868.16" + } + }, + "CIN11": { + "hide_name": 0, + "bits": [ 311 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:867.11-867.16" + } + }, + "CIN12": { + "hide_name": 0, + "bits": [ 310 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:866.11-866.16" + } + }, + "CIN13": { + "hide_name": 0, + "bits": [ 309 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:865.11-865.16" + } + }, + "CIN14": { + "hide_name": 0, + "bits": [ 308 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:864.11-864.16" + } + }, + "CIN15": { + "hide_name": 0, + "bits": [ 307 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:863.11-863.16" + } + }, + "CIN16": { + "hide_name": 0, + "bits": [ 306 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:862.11-862.16" + } + }, + "CIN17": { + "hide_name": 0, + "bits": [ 305 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:861.11-861.16" + } + }, + "CIN18": { + "hide_name": 0, + "bits": [ 304 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:860.11-860.16" + } + }, + "CIN19": { + "hide_name": 0, + "bits": [ 303 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:859.11-859.16" + } + }, + "CIN2": { + "hide_name": 0, + "bits": [ 320 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:876.11-876.15" + } + }, + "CIN20": { + "hide_name": 0, + "bits": [ 302 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:858.11-858.16" + } + }, + "CIN21": { + "hide_name": 0, + "bits": [ 301 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:857.11-857.16" + } + }, + "CIN22": { + "hide_name": 0, + "bits": [ 300 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:856.11-856.16" + } + }, + "CIN23": { + "hide_name": 0, + "bits": [ 299 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:855.11-855.16" + } + }, + "CIN24": { + "hide_name": 0, + "bits": [ 298 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:854.11-854.16" + } + }, + "CIN25": { + "hide_name": 0, + "bits": [ 297 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:853.11-853.16" + } + }, + "CIN26": { + "hide_name": 0, + "bits": [ 296 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:852.11-852.16" + } + }, + "CIN27": { + "hide_name": 0, + "bits": [ 295 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:851.11-851.16" + } + }, + "CIN28": { + "hide_name": 0, + "bits": [ 294 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:850.11-850.16" + } + }, + "CIN29": { + "hide_name": 0, + "bits": [ 293 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:849.11-849.16" + } + }, + "CIN3": { + "hide_name": 0, + "bits": [ 319 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:875.11-875.15" + } + }, + "CIN30": { + "hide_name": 0, + "bits": [ 292 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:848.11-848.16" + } + }, + "CIN31": { + "hide_name": 0, + "bits": [ 291 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:847.11-847.16" + } + }, + "CIN32": { + "hide_name": 0, + "bits": [ 290 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:846.11-846.16" + } + }, + "CIN33": { + "hide_name": 0, + "bits": [ 289 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:845.11-845.16" + } + }, + "CIN34": { + "hide_name": 0, + "bits": [ 288 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:844.11-844.16" + } + }, + "CIN35": { + "hide_name": 0, + "bits": [ 287 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:843.11-843.16" + } + }, + "CIN36": { + "hide_name": 0, + "bits": [ 286 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:842.11-842.16" + } + }, + "CIN37": { + "hide_name": 0, + "bits": [ 285 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:841.11-841.16" + } + }, + "CIN38": { + "hide_name": 0, + "bits": [ 284 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:840.11-840.16" + } + }, + "CIN39": { + "hide_name": 0, + "bits": [ 283 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:839.11-839.16" + } + }, + "CIN4": { + "hide_name": 0, + "bits": [ 318 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:874.11-874.15" + } + }, + "CIN40": { + "hide_name": 0, + "bits": [ 282 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:838.11-838.16" + } + }, + "CIN41": { + "hide_name": 0, + "bits": [ 281 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:837.11-837.16" + } + }, + "CIN42": { + "hide_name": 0, + "bits": [ 280 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:836.11-836.16" + } + }, + "CIN43": { + "hide_name": 0, + "bits": [ 279 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:835.11-835.16" + } + }, + "CIN44": { + "hide_name": 0, + "bits": [ 278 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:834.11-834.16" + } + }, + "CIN45": { + "hide_name": 0, + "bits": [ 277 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:833.11-833.16" + } + }, + "CIN46": { + "hide_name": 0, + "bits": [ 276 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:832.11-832.16" + } + }, + "CIN47": { + "hide_name": 0, + "bits": [ 275 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:831.11-831.16" + } + }, + "CIN48": { + "hide_name": 0, + "bits": [ 274 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:830.11-830.16" + } + }, + "CIN49": { + "hide_name": 0, + "bits": [ 273 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:829.11-829.16" + } + }, + "CIN5": { + "hide_name": 0, + "bits": [ 317 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:873.11-873.15" + } + }, + "CIN50": { + "hide_name": 0, + "bits": [ 272 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:828.11-828.16" + } + }, + "CIN51": { + "hide_name": 0, + "bits": [ 271 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:827.11-827.16" + } + }, + "CIN52": { + "hide_name": 0, + "bits": [ 270 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:826.11-826.16" + } + }, + "CIN53": { + "hide_name": 0, + "bits": [ 269 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:825.11-825.16" + } + }, + "CIN6": { + "hide_name": 0, + "bits": [ 316 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:872.11-872.15" + } + }, + "CIN7": { + "hide_name": 0, + "bits": [ 315 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:871.11-871.15" + } + }, + "CIN8": { + "hide_name": 0, + "bits": [ 314 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:870.11-870.15" + } + }, + "CIN9": { + "hide_name": 0, + "bits": [ 313 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:869.11-869.15" + } + }, + "CLK0": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:565.11-565.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:564.11-564.15" + } + }, + "CLK2": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:563.11-563.15" + } + }, + "CLK3": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:562.11-562.15" + } + }, + "CO0": { + "hide_name": 0, + "bits": [ 441 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:997.12-997.15" + } + }, + "CO1": { + "hide_name": 0, + "bits": [ 440 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:996.12-996.15" + } + }, + "CO10": { + "hide_name": 0, + "bits": [ 431 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:987.12-987.16" + } + }, + "CO11": { + "hide_name": 0, + "bits": [ 430 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:986.12-986.16" + } + }, + "CO12": { + "hide_name": 0, + "bits": [ 429 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:985.12-985.16" + } + }, + "CO13": { + "hide_name": 0, + "bits": [ 428 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:984.12-984.16" + } + }, + "CO14": { + "hide_name": 0, + "bits": [ 427 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:983.12-983.16" + } + }, + "CO15": { + "hide_name": 0, + "bits": [ 426 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:982.12-982.16" + } + }, + "CO16": { + "hide_name": 0, + "bits": [ 425 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:981.12-981.16" + } + }, + "CO17": { + "hide_name": 0, + "bits": [ 424 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:980.12-980.16" + } + }, + "CO18": { + "hide_name": 0, + "bits": [ 423 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:979.12-979.16" + } + }, + "CO19": { + "hide_name": 0, + "bits": [ 422 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:978.12-978.16" + } + }, + "CO2": { + "hide_name": 0, + "bits": [ 439 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:995.12-995.15" + } + }, + "CO20": { + "hide_name": 0, + "bits": [ 421 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:977.12-977.16" + } + }, + "CO21": { + "hide_name": 0, + "bits": [ 420 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:976.12-976.16" + } + }, + "CO22": { + "hide_name": 0, + "bits": [ 419 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:975.12-975.16" + } + }, + "CO23": { + "hide_name": 0, + "bits": [ 418 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:974.12-974.16" + } + }, + "CO24": { + "hide_name": 0, + "bits": [ 417 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:973.12-973.16" + } + }, + "CO25": { + "hide_name": 0, + "bits": [ 416 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:972.12-972.16" + } + }, + "CO26": { + "hide_name": 0, + "bits": [ 415 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:971.12-971.16" + } + }, + "CO27": { + "hide_name": 0, + "bits": [ 414 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:970.12-970.16" + } + }, + "CO28": { + "hide_name": 0, + "bits": [ 413 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:969.12-969.16" + } + }, + "CO29": { + "hide_name": 0, + "bits": [ 412 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:968.12-968.16" + } + }, + "CO3": { + "hide_name": 0, + "bits": [ 438 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:994.12-994.15" + } + }, + "CO30": { + "hide_name": 0, + "bits": [ 411 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:967.12-967.16" + } + }, + "CO31": { + "hide_name": 0, + "bits": [ 410 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:966.12-966.16" + } + }, + "CO32": { + "hide_name": 0, + "bits": [ 409 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:965.12-965.16" + } + }, + "CO33": { + "hide_name": 0, + "bits": [ 408 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:964.12-964.16" + } + }, + "CO34": { + "hide_name": 0, + "bits": [ 407 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:963.12-963.16" + } + }, + "CO35": { + "hide_name": 0, + "bits": [ 406 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:962.12-962.16" + } + }, + "CO36": { + "hide_name": 0, + "bits": [ 405 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:961.12-961.16" + } + }, + "CO37": { + "hide_name": 0, + "bits": [ 404 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:960.12-960.16" + } + }, + "CO38": { + "hide_name": 0, + "bits": [ 403 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:959.12-959.16" + } + }, + "CO39": { + "hide_name": 0, + "bits": [ 402 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:958.12-958.16" + } + }, + "CO4": { + "hide_name": 0, + "bits": [ 437 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:993.12-993.15" + } + }, + "CO40": { + "hide_name": 0, + "bits": [ 401 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:957.12-957.16" + } + }, + "CO41": { + "hide_name": 0, + "bits": [ 400 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:956.12-956.16" + } + }, + "CO42": { + "hide_name": 0, + "bits": [ 399 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:955.12-955.16" + } + }, + "CO43": { + "hide_name": 0, + "bits": [ 398 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:954.12-954.16" + } + }, + "CO44": { + "hide_name": 0, + "bits": [ 397 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:953.12-953.16" + } + }, + "CO45": { + "hide_name": 0, + "bits": [ 396 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:952.12-952.16" + } + }, + "CO46": { + "hide_name": 0, + "bits": [ 395 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:951.12-951.16" + } + }, + "CO47": { + "hide_name": 0, + "bits": [ 394 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:950.12-950.16" + } + }, + "CO48": { + "hide_name": 0, + "bits": [ 393 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:949.12-949.16" + } + }, + "CO49": { + "hide_name": 0, + "bits": [ 392 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:948.12-948.16" + } + }, + "CO5": { + "hide_name": 0, + "bits": [ 436 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:992.12-992.15" + } + }, + "CO50": { + "hide_name": 0, + "bits": [ 391 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:947.12-947.16" + } + }, + "CO51": { + "hide_name": 0, + "bits": [ 390 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:946.12-946.16" + } + }, + "CO52": { + "hide_name": 0, + "bits": [ 389 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:945.12-945.16" + } + }, + "CO53": { + "hide_name": 0, + "bits": [ 388 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:944.12-944.16" + } + }, + "CO6": { + "hide_name": 0, + "bits": [ 435 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:991.12-991.15" + } + }, + "CO7": { + "hide_name": 0, + "bits": [ 434 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:990.12-990.15" + } + }, + "CO8": { + "hide_name": 0, + "bits": [ 433 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:989.12-989.15" + } + }, + "CO9": { + "hide_name": 0, + "bits": [ 432 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:988.12-988.15" + } + }, + "EQOM": { + "hide_name": 0, + "bits": [ 444 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1000.12-1000.16" + } + }, + "EQPAT": { + "hide_name": 0, + "bits": [ 445 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1001.12-1001.17" + } + }, + "EQPATB": { + "hide_name": 0, + "bits": [ 446 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1002.12-1002.18" + } + }, + "EQZ": { + "hide_name": 0, + "bits": [ 442 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:998.12-998.15" + } + }, + "EQZM": { + "hide_name": 0, + "bits": [ 443 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:999.12-999.16" + } + }, + "MA0": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:788.11-788.14" + } + }, + "MA1": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:787.11-787.14" + } + }, + "MA10": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:778.11-778.15" + } + }, + "MA11": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:777.11-777.15" + } + }, + "MA12": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:776.11-776.15" + } + }, + "MA13": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:775.11-775.15" + } + }, + "MA14": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:774.11-774.15" + } + }, + "MA15": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:773.11-773.15" + } + }, + "MA16": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:772.11-772.15" + } + }, + "MA17": { + "hide_name": 0, + "bits": [ 215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:771.11-771.15" + } + }, + "MA18": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:770.11-770.15" + } + }, + "MA19": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:769.11-769.15" + } + }, + "MA2": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:786.11-786.14" + } + }, + "MA20": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:768.11-768.15" + } + }, + "MA21": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:767.11-767.15" + } + }, + "MA22": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:766.11-766.15" + } + }, + "MA23": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:765.11-765.15" + } + }, + "MA24": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:764.11-764.15" + } + }, + "MA25": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:763.11-763.15" + } + }, + "MA26": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:762.11-762.15" + } + }, + "MA27": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:761.11-761.15" + } + }, + "MA28": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:760.11-760.15" + } + }, + "MA29": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:759.11-759.15" + } + }, + "MA3": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:785.11-785.14" + } + }, + "MA30": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:758.11-758.15" + } + }, + "MA31": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:757.11-757.15" + } + }, + "MA32": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:756.11-756.15" + } + }, + "MA33": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:755.11-755.15" + } + }, + "MA34": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:754.11-754.15" + } + }, + "MA35": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:753.11-753.15" + } + }, + "MA4": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:784.11-784.14" + } + }, + "MA5": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:783.11-783.14" + } + }, + "MA6": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:782.11-782.14" + } + }, + "MA7": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:781.11-781.14" + } + }, + "MA8": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:780.11-780.14" + } + }, + "MA9": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:779.11-779.14" + } + }, + "MB0": { + "hide_name": 0, + "bits": [ 268 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:824.11-824.14" + } + }, + "MB1": { + "hide_name": 0, + "bits": [ 267 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:823.11-823.14" + } + }, + "MB10": { + "hide_name": 0, + "bits": [ 258 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:814.11-814.15" + } + }, + "MB11": { + "hide_name": 0, + "bits": [ 257 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:813.11-813.15" + } + }, + "MB12": { + "hide_name": 0, + "bits": [ 256 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:812.11-812.15" + } + }, + "MB13": { + "hide_name": 0, + "bits": [ 255 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:811.11-811.15" + } + }, + "MB14": { + "hide_name": 0, + "bits": [ 254 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:810.11-810.15" + } + }, + "MB15": { + "hide_name": 0, + "bits": [ 253 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:809.11-809.15" + } + }, + "MB16": { + "hide_name": 0, + "bits": [ 252 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:808.11-808.15" + } + }, + "MB17": { + "hide_name": 0, + "bits": [ 251 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:807.11-807.15" + } + }, + "MB18": { + "hide_name": 0, + "bits": [ 250 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:806.11-806.15" + } + }, + "MB19": { + "hide_name": 0, + "bits": [ 249 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:805.11-805.15" + } + }, + "MB2": { + "hide_name": 0, + "bits": [ 266 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:822.11-822.14" + } + }, + "MB20": { + "hide_name": 0, + "bits": [ 248 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:804.11-804.15" + } + }, + "MB21": { + "hide_name": 0, + "bits": [ 247 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:803.11-803.15" + } + }, + "MB22": { + "hide_name": 0, + "bits": [ 246 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:802.11-802.15" + } + }, + "MB23": { + "hide_name": 0, + "bits": [ 245 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:801.11-801.15" + } + }, + "MB24": { + "hide_name": 0, + "bits": [ 244 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:800.11-800.15" + } + }, + "MB25": { + "hide_name": 0, + "bits": [ 243 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:799.11-799.15" + } + }, + "MB26": { + "hide_name": 0, + "bits": [ 242 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:798.11-798.15" + } + }, + "MB27": { + "hide_name": 0, + "bits": [ 241 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:797.11-797.15" + } + }, + "MB28": { + "hide_name": 0, + "bits": [ 240 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:796.11-796.15" + } + }, + "MB29": { + "hide_name": 0, + "bits": [ 239 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:795.11-795.15" + } + }, + "MB3": { + "hide_name": 0, + "bits": [ 265 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:821.11-821.14" + } + }, + "MB30": { + "hide_name": 0, + "bits": [ 238 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:794.11-794.15" + } + }, + "MB31": { + "hide_name": 0, + "bits": [ 237 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:793.11-793.15" + } + }, + "MB32": { + "hide_name": 0, + "bits": [ 236 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:792.11-792.15" + } + }, + "MB33": { + "hide_name": 0, + "bits": [ 235 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:791.11-791.15" + } + }, + "MB34": { + "hide_name": 0, + "bits": [ 234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:790.11-790.15" + } + }, + "MB35": { + "hide_name": 0, + "bits": [ 233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:789.11-789.15" + } + }, + "MB4": { + "hide_name": 0, + "bits": [ 264 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:820.11-820.14" + } + }, + "MB5": { + "hide_name": 0, + "bits": [ 263 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:819.11-819.14" + } + }, + "MB6": { + "hide_name": 0, + "bits": [ 262 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:818.11-818.14" + } + }, + "MB7": { + "hide_name": 0, + "bits": [ 261 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:817.11-817.14" + } + }, + "MB8": { + "hide_name": 0, + "bits": [ 260 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:816.11-816.14" + } + }, + "MB9": { + "hide_name": 0, + "bits": [ 259 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:815.11-815.14" + } + }, + "OP0": { + "hide_name": 0, + "bits": [ 333 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:889.11-889.14" + } + }, + "OP1": { + "hide_name": 0, + "bits": [ 332 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:888.11-888.14" + } + }, + "OP10": { + "hide_name": 0, + "bits": [ 323 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:879.11-879.15" + } + }, + "OP2": { + "hide_name": 0, + "bits": [ 331 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:887.11-887.14" + } + }, + "OP3": { + "hide_name": 0, + "bits": [ 330 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:886.11-886.14" + } + }, + "OP4": { + "hide_name": 0, + "bits": [ 329 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:885.11-885.14" + } + }, + "OP5": { + "hide_name": 0, + "bits": [ 328 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:884.11-884.14" + } + }, + "OP6": { + "hide_name": 0, + "bits": [ 327 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:883.11-883.14" + } + }, + "OP7": { + "hide_name": 0, + "bits": [ 326 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:882.11-882.14" + } + }, + "OP8": { + "hide_name": 0, + "bits": [ 325 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:881.11-881.14" + } + }, + "OP9": { + "hide_name": 0, + "bits": [ 324 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:880.11-880.14" + } + }, + "OVER": { + "hide_name": 0, + "bits": [ 447 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1003.12-1003.16" + } + }, + "OVERUNDER": { + "hide_name": 0, + "bits": [ 449 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1005.12-1005.21" + } + }, + "R0": { + "hide_name": 0, + "bits": [ 387 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:943.12-943.14" + } + }, + "R1": { + "hide_name": 0, + "bits": [ 386 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:942.12-942.14" + } + }, + "R10": { + "hide_name": 0, + "bits": [ 377 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:933.12-933.15" + } + }, + "R11": { + "hide_name": 0, + "bits": [ 376 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:932.12-932.15" + } + }, + "R12": { + "hide_name": 0, + "bits": [ 375 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:931.12-931.15" + } + }, + "R13": { + "hide_name": 0, + "bits": [ 374 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:930.12-930.15" + } + }, + "R14": { + "hide_name": 0, + "bits": [ 373 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:929.12-929.15" + } + }, + "R15": { + "hide_name": 0, + "bits": [ 372 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:928.12-928.15" + } + }, + "R16": { + "hide_name": 0, + "bits": [ 371 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:927.12-927.15" + } + }, + "R17": { + "hide_name": 0, + "bits": [ 370 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:926.12-926.15" + } + }, + "R18": { + "hide_name": 0, + "bits": [ 369 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:925.12-925.15" + } + }, + "R19": { + "hide_name": 0, + "bits": [ 368 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:924.12-924.15" + } + }, + "R2": { + "hide_name": 0, + "bits": [ 385 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:941.12-941.14" + } + }, + "R20": { + "hide_name": 0, + "bits": [ 367 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:923.12-923.15" + } + }, + "R21": { + "hide_name": 0, + "bits": [ 366 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:922.12-922.15" + } + }, + "R22": { + "hide_name": 0, + "bits": [ 365 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:921.12-921.15" + } + }, + "R23": { + "hide_name": 0, + "bits": [ 364 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:920.12-920.15" + } + }, + "R24": { + "hide_name": 0, + "bits": [ 363 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:919.12-919.15" + } + }, + "R25": { + "hide_name": 0, + "bits": [ 362 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:918.12-918.15" + } + }, + "R26": { + "hide_name": 0, + "bits": [ 361 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:917.12-917.15" + } + }, + "R27": { + "hide_name": 0, + "bits": [ 360 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:916.12-916.15" + } + }, + "R28": { + "hide_name": 0, + "bits": [ 359 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:915.12-915.15" + } + }, + "R29": { + "hide_name": 0, + "bits": [ 358 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:914.12-914.15" + } + }, + "R3": { + "hide_name": 0, + "bits": [ 384 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:940.12-940.14" + } + }, + "R30": { + "hide_name": 0, + "bits": [ 357 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:913.12-913.15" + } + }, + "R31": { + "hide_name": 0, + "bits": [ 356 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:912.12-912.15" + } + }, + "R32": { + "hide_name": 0, + "bits": [ 355 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:911.12-911.15" + } + }, + "R33": { + "hide_name": 0, + "bits": [ 354 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:910.12-910.15" + } + }, + "R34": { + "hide_name": 0, + "bits": [ 353 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:909.12-909.15" + } + }, + "R35": { + "hide_name": 0, + "bits": [ 352 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:908.12-908.15" + } + }, + "R36": { + "hide_name": 0, + "bits": [ 351 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:907.12-907.15" + } + }, + "R37": { + "hide_name": 0, + "bits": [ 350 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:906.12-906.15" + } + }, + "R38": { + "hide_name": 0, + "bits": [ 349 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:905.12-905.15" + } + }, + "R39": { + "hide_name": 0, + "bits": [ 348 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:904.12-904.15" + } + }, + "R4": { + "hide_name": 0, + "bits": [ 383 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:939.12-939.14" + } + }, + "R40": { + "hide_name": 0, + "bits": [ 347 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:903.12-903.15" + } + }, + "R41": { + "hide_name": 0, + "bits": [ 346 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:902.12-902.15" + } + }, + "R42": { + "hide_name": 0, + "bits": [ 345 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:901.12-901.15" + } + }, + "R43": { + "hide_name": 0, + "bits": [ 344 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:900.12-900.15" + } + }, + "R44": { + "hide_name": 0, + "bits": [ 343 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:899.12-899.15" + } + }, + "R45": { + "hide_name": 0, + "bits": [ 342 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:898.12-898.15" + } + }, + "R46": { + "hide_name": 0, + "bits": [ 341 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:897.12-897.15" + } + }, + "R47": { + "hide_name": 0, + "bits": [ 340 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:896.12-896.15" + } + }, + "R48": { + "hide_name": 0, + "bits": [ 339 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:895.12-895.15" + } + }, + "R49": { + "hide_name": 0, + "bits": [ 338 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:894.12-894.15" + } + }, + "R5": { + "hide_name": 0, + "bits": [ 382 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:938.12-938.14" + } + }, + "R50": { + "hide_name": 0, + "bits": [ 337 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:893.12-893.15" + } + }, + "R51": { + "hide_name": 0, + "bits": [ 336 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:892.12-892.15" + } + }, + "R52": { + "hide_name": 0, + "bits": [ 335 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:891.12-891.15" + } + }, + "R53": { + "hide_name": 0, + "bits": [ 334 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:890.12-890.15" + } + }, + "R6": { + "hide_name": 0, + "bits": [ 381 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:937.12-937.14" + } + }, + "R7": { + "hide_name": 0, + "bits": [ 380 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:936.12-936.14" + } + }, + "R8": { + "hide_name": 0, + "bits": [ 379 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:935.12-935.14" + } + }, + "R9": { + "hide_name": 0, + "bits": [ 378 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:934.12-934.14" + } + }, + "RST0": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:569.11-569.15" + } + }, + "RST1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:568.11-568.15" + } + }, + "RST2": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:567.11-567.15" + } + }, + "RST3": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:566.11-566.15" + } + }, + "SIGNEDCIN": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:572.11-572.20" + } + }, + "SIGNEDIA": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:570.11-570.19" + } + }, + "SIGNEDIB": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:571.11-571.19" + } + }, + "SIGNEDR": { + "hide_name": 0, + "bits": [ 450 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1006.12-1006.19" + } + }, + "UNDER": { + "hide_name": 0, + "bits": [ 448 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1004.12-1004.17" + } + } + } + }, + "BB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + }, + "B": { + "direction": "inout", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.68-10.69" + } + }, + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.20-10.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.34-10.35" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.23-10.24" + } + } + } + }, + "BBPD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + }, + "B": { + "direction": "inout", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.68-12.69" + } + }, + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.20-12.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.34-12.35" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.23-12.24" + } + } + } + }, + "BBPU": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + }, + "B": { + "direction": "inout", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.68-11.69" + } + }, + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.20-11.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.34-11.35" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.23-11.24" + } + } + } + }, + "CCU2C": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000100", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:3.1-61.10" + }, + "parameter_default_values": { + "INIT0": "0000000000000000", + "INIT1": "0000000000000000", + "INJECT1_0": "YES", + "INJECT1_1": "YES" + }, + "ports": { + "CIN": { + "direction": "input", + "bits": [ 2 ] + }, + "A0": { + "direction": "input", + "bits": [ 3 ] + }, + "B0": { + "direction": "input", + "bits": [ 4 ] + }, + "C0": { + "direction": "input", + "bits": [ 5 ] + }, + "D0": { + "direction": "input", + "bits": [ 6 ] + }, + "A1": { + "direction": "input", + "bits": [ 7 ] + }, + "B1": { + "direction": "input", + "bits": [ 8 ] + }, + "C1": { + "direction": "input", + "bits": [ 9 ] + }, + "D1": { + "direction": "input", + "bits": [ 10 ] + }, + "S0": { + "direction": "output", + "bits": [ 11 ] + }, + "S1": { + "direction": "output", + "bits": [ 12 ] + }, + "COUT": { + "direction": "output", + "bits": [ 13 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.9-6.11" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.25-6.27" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.13-6.15" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.29-6.31" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.17-6.19" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.33-6.35" + } + }, + "CIN": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:5.9-5.12" + } + }, + "COUT": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "abc9_carry": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13" + } + }, + "D0": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.21-6.23" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:6.37-6.39" + } + }, + "S0": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.9-7.11" + } + }, + "S1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:7.13-7.15" + } + } + } + }, + "CLKDIVF": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1010.1-1017.10" + }, + "parameter_default_values": { + "DIV": "2.0", + "GSR": "DISABLED" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "ALIGNWD": { + "direction": "input", + "bits": [ 4 ] + }, + "CDIVX": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "ALIGNWD": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1015.11-1015.18" + } + }, + "CDIVX": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1016.12-1016.17" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1013.11-1013.15" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1014.11-1014.14" + } + } + } + }, + "DCCA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1043.1-1047.10" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "CE": { + "direction": "input", + "bits": [ 3 ] + }, + "CLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "CE": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1045.11-1045.13" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1044.11-1044.15" + } + }, + "CLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1046.12-1046.16" + } + } + } + }, + "DCSC": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1032.1-1040.10" + }, + "parameter_default_values": { + "DCSMODE": "POS" + }, + "ports": { + "CLK1": { + "direction": "input", + "bits": [ 2 ] + }, + "CLK0": { + "direction": "input", + "bits": [ 3 ] + }, + "SEL1": { + "direction": "input", + "bits": [ 4 ] + }, + "SEL0": { + "direction": "input", + "bits": [ 5 ] + }, + "MODESEL": { + "direction": "input", + "bits": [ 6 ] + }, + "DCSOUT": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "CLK0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1035.11-1035.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1034.11-1034.15" + } + }, + "DCSOUT": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1039.12-1039.18" + } + }, + "MODESEL": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1038.11-1038.18" + } + }, + "SEL0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1037.11-1037.15" + } + }, + "SEL1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1036.11-1036.15" + } + } + } + }, + "DCUA": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1456.1-2032.10" + }, + "parameter_default_values": { + "CH0_AUTO_CALIB_EN": "DONTCARE", + "CH0_AUTO_FACQ_EN": "DONTCARE", + "CH0_BAND_THRESHOLD": "DONTCARE", + "CH0_CALIB_CK_MODE": "DONTCARE", + "CH0_CC_MATCH_1": "DONTCARE", + "CH0_CC_MATCH_2": "DONTCARE", + "CH0_CC_MATCH_3": "DONTCARE", + "CH0_CC_MATCH_4": "DONTCARE", + "CH0_CDR_CNT4SEL": "DONTCARE", + "CH0_CDR_CNT8SEL": "DONTCARE", + "CH0_CDR_MAX_RATE": "DONTCARE", + "CH0_CTC_BYPASS": "DONTCARE", + "CH0_DCOATDCFG": "DONTCARE", + "CH0_DCOATDDLY": "DONTCARE", + "CH0_DCOBYPSATD": "DONTCARE", + "CH0_DCOCALDIV": "DONTCARE", + "CH0_DCOCTLGI": "DONTCARE", + "CH0_DCODISBDAVOID": "DONTCARE", + "CH0_DCOFLTDAC": "DONTCARE", + "CH0_DCOFTNRG": "DONTCARE", + "CH0_DCOIOSTUNE": "DONTCARE", + "CH0_DCOITUNE": "DONTCARE", + "CH0_DCOITUNE4LSB": "DONTCARE", + "CH0_DCOIUPDNX2": "DONTCARE", + "CH0_DCONUOFLSB": "DONTCARE", + "CH0_DCOSCALEI": "DONTCARE", + "CH0_DCOSTARTVAL": "DONTCARE", + "CH0_DCOSTEP": "DONTCARE", + "CH0_DEC_BYPASS": "DONTCARE", + "CH0_ENABLE_CG_ALIGN": "DONTCARE", + "CH0_ENC_BYPASS": "DONTCARE", + "CH0_FF_RX_F_CLK_DIS": "DONTCARE", + "CH0_FF_RX_H_CLK_EN": "DONTCARE", + "CH0_FF_TX_F_CLK_DIS": "DONTCARE", + "CH0_FF_TX_H_CLK_EN": "DONTCARE", + "CH0_GE_AN_ENABLE": "DONTCARE", + "CH0_INVERT_RX": "DONTCARE", + "CH0_INVERT_TX": "DONTCARE", + "CH0_LDR_CORE2TX_SEL": "DONTCARE", + "CH0_LDR_RX2CORE_SEL": "DONTCARE", + "CH0_LEQ_OFFSET_SEL": "DONTCARE", + "CH0_LEQ_OFFSET_TRIM": "DONTCARE", + "CH0_LSM_DISABLE": "DONTCARE", + "CH0_MATCH_2_ENABLE": "DONTCARE", + "CH0_MATCH_4_ENABLE": "DONTCARE", + "CH0_MIN_IPG_CNT": "DONTCARE", + "CH0_PCIE_EI_EN": "DONTCARE", + "CH0_PCIE_MODE": "DONTCARE", + "CH0_PCS_DET_TIME_SEL": "DONTCARE", + "CH0_PDEN_SEL": "DONTCARE", + "CH0_PRBS_ENABLE": "DONTCARE", + "CH0_PRBS_LOCK": "DONTCARE", + "CH0_PRBS_SELECTION": "DONTCARE", + "CH0_PROTOCOL": "DONTCARE", + "CH0_RATE_MODE_RX": "DONTCARE", + "CH0_RATE_MODE_TX": "DONTCARE", + "CH0_RCV_DCC_EN": "DONTCARE", + "CH0_REG_BAND_OFFSET": "DONTCARE", + "CH0_REG_BAND_SEL": "DONTCARE", + "CH0_REG_IDAC_EN": "DONTCARE", + "CH0_REG_IDAC_SEL": "DONTCARE", + "CH0_REQ_EN": "DONTCARE", + "CH0_REQ_LVL_SET": "DONTCARE", + "CH0_RIO_MODE": "DONTCARE", + "CH0_RLOS_SEL": "DONTCARE", + "CH0_RPWDNB": "DONTCARE", + "CH0_RTERM_RX": "DONTCARE", + "CH0_RTERM_TX": "DONTCARE", + "CH0_RXIN_CM": "DONTCARE", + "CH0_RXTERM_CM": "DONTCARE", + "CH0_RX_DCO_CK_DIV": "DONTCARE", + "CH0_RX_DIV11_SEL": "DONTCARE", + "CH0_RX_GEAR_BYPASS": "DONTCARE", + "CH0_RX_GEAR_MODE": "DONTCARE", + "CH0_RX_LOS_CEQ": "DONTCARE", + "CH0_RX_LOS_EN": "DONTCARE", + "CH0_RX_LOS_HYST_EN": "DONTCARE", + "CH0_RX_LOS_LVL": "DONTCARE", + "CH0_RX_RATE_SEL": "DONTCARE", + "CH0_RX_SB_BYPASS": "DONTCARE", + "CH0_SB_BYPASS": "DONTCARE", + "CH0_SEL_SD_RX_CLK": "DONTCARE", + "CH0_TDRV_DAT_SEL": "DONTCARE", + "CH0_TDRV_POST_EN": "DONTCARE", + "CH0_TDRV_PRE_EN": "DONTCARE", + "CH0_TDRV_SLICE0_CUR": "DONTCARE", + "CH0_TDRV_SLICE0_SEL": "DONTCARE", + "CH0_TDRV_SLICE1_CUR": "DONTCARE", + "CH0_TDRV_SLICE1_SEL": "DONTCARE", + "CH0_TDRV_SLICE2_CUR": "DONTCARE", + "CH0_TDRV_SLICE2_SEL": "DONTCARE", + "CH0_TDRV_SLICE3_CUR": "DONTCARE", + "CH0_TDRV_SLICE3_SEL": "DONTCARE", + "CH0_TDRV_SLICE4_CUR": "DONTCARE", + "CH0_TDRV_SLICE4_SEL": "DONTCARE", + "CH0_TDRV_SLICE5_CUR": "DONTCARE", + "CH0_TDRV_SLICE5_SEL": "DONTCARE", + "CH0_TPWDNB": "DONTCARE", + "CH0_TXAMPLITUDE": "DONTCARE", + "CH0_TXDEPOST": "DONTCARE", + "CH0_TXDEPRE": "DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 138 ] + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 139 ] + }, + "D_SCAN_ENABLE": { + "direction": "input", + "bits": [ 140 ] + }, + "D_SCAN_IN_0": { + "direction": "input", + "bits": [ 141 ] + }, + "D_SCAN_IN_1": { + "direction": "input", + "bits": [ 142 ] + }, + "D_SCAN_IN_2": { + "direction": "input", + "bits": [ 143 ] + }, + "D_SCAN_IN_3": { + "direction": "input", + "bits": [ 144 ] + }, + "D_SCAN_IN_4": { + "direction": "input", + "bits": [ 145 ] + }, + "D_SCAN_IN_5": { + "direction": "input", + "bits": [ 146 ] + }, + "D_SCAN_IN_6": { + "direction": "input", + "bits": [ 147 ] + }, + "D_SCAN_IN_7": { + "direction": "input", + "bits": [ 148 ] + }, + "D_SCAN_MODE": { + "direction": "input", + "bits": [ 149 ] + }, + "D_SCAN_RESET": { + "direction": "input", + "bits": [ 150 ] + }, + "D_CIN0": { + "direction": "input", + "bits": [ 151 ] + }, + "D_CIN1": { + "direction": "input", + "bits": [ 152 ] + }, + "D_CIN2": { + "direction": "input", + "bits": [ 153 ] + }, + "D_CIN3": { + "direction": "input", + "bits": [ 154 ] + }, + "D_CIN4": { + "direction": "input", + "bits": [ 155 ] + }, + "D_CIN5": { + "direction": "input", + "bits": [ 156 ] + }, + "D_CIN6": { + "direction": "input", + "bits": [ 157 ] + }, + "D_CIN7": { + "direction": "input", + "bits": [ 158 ] + }, + "D_CIN8": { + "direction": "input", + "bits": [ 159 ] + }, + "D_CIN9": { + "direction": "input", + "bits": [ 160 ] + }, + "D_CIN10": { + "direction": "input", + "bits": [ 161 ] + }, + "D_CIN11": { + "direction": "input", + "bits": [ 162 ] + }, + "CH0_HDOUTP": { + "direction": "output", + "bits": [ 163 ] + }, + "CH1_HDOUTP": { + "direction": "output", + "bits": [ 164 ] + }, + "CH0_HDOUTN": { + "direction": "output", + "bits": [ 165 ] + }, + "CH1_HDOUTN": { + "direction": "output", + "bits": [ 166 ] + }, + "D_TXBIT_CLKP_TO_ND": { + "direction": "output", + "bits": [ 167 ] + }, + "D_TXBIT_CLKN_TO_ND": { + "direction": "output", + "bits": [ 168 ] + }, + "D_SYNC_PULSE2ND": { + "direction": "output", + "bits": [ 169 ] + }, + "D_TXPLL_LOL_TO_ND": { + "direction": "output", + "bits": [ 170 ] + }, + "CH0_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 171 ] + }, + "CH1_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 172 ] + }, + "CH0_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 173 ] + }, + "CH1_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 174 ] + }, + "CH0_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 175 ] + }, + "CH1_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 176 ] + }, + "CH0_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 177 ] + }, + "CH1_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 178 ] + }, + "CH0_FF_RX_PCLK": { + "direction": "output", + "bits": [ 179 ] + }, + "CH1_FF_RX_PCLK": { + "direction": "output", + "bits": [ 180 ] + }, + "CH0_FF_TX_PCLK": { + "direction": "output", + "bits": [ 181 ] + }, + "CH1_FF_TX_PCLK": { + "direction": "output", + "bits": [ 182 ] + }, + "CH0_FF_RX_D_0": { + "direction": "output", + "bits": [ 183 ] + }, + "CH1_FF_RX_D_0": { + "direction": "output", + "bits": [ 184 ] + }, + "CH0_FF_RX_D_1": { + "direction": "output", + "bits": [ 185 ] + }, + "CH1_FF_RX_D_1": { + "direction": "output", + "bits": [ 186 ] + }, + "CH0_FF_RX_D_2": { + "direction": "output", + "bits": [ 187 ] + }, + "CH1_FF_RX_D_2": { + "direction": "output", + "bits": [ 188 ] + }, + "CH0_FF_RX_D_3": { + "direction": "output", + "bits": [ 189 ] + }, + "CH1_FF_RX_D_3": { + "direction": "output", + "bits": [ 190 ] + }, + "CH0_FF_RX_D_4": { + "direction": "output", + "bits": [ 191 ] + }, + "CH1_FF_RX_D_4": { + "direction": "output", + "bits": [ 192 ] + }, + "CH0_FF_RX_D_5": { + "direction": "output", + "bits": [ 193 ] + }, + "CH1_FF_RX_D_5": { + "direction": "output", + "bits": [ 194 ] + }, + "CH0_FF_RX_D_6": { + "direction": "output", + "bits": [ 195 ] + }, + "CH1_FF_RX_D_6": { + "direction": "output", + "bits": [ 196 ] + }, + "CH0_FF_RX_D_7": { + "direction": "output", + "bits": [ 197 ] + }, + "CH1_FF_RX_D_7": { + "direction": "output", + "bits": [ 198 ] + }, + "CH0_FF_RX_D_8": { + "direction": "output", + "bits": [ 199 ] + }, + "CH1_FF_RX_D_8": { + "direction": "output", + "bits": [ 200 ] + }, + "CH0_FF_RX_D_9": { + "direction": "output", + "bits": [ 201 ] + }, + "CH1_FF_RX_D_9": { + "direction": "output", + "bits": [ 202 ] + }, + "CH0_FF_RX_D_10": { + "direction": "output", + "bits": [ 203 ] + }, + "CH1_FF_RX_D_10": { + "direction": "output", + "bits": [ 204 ] + }, + "CH0_FF_RX_D_11": { + "direction": "output", + "bits": [ 205 ] + }, + "CH1_FF_RX_D_11": { + "direction": "output", + "bits": [ 206 ] + }, + "CH0_FF_RX_D_12": { + "direction": "output", + "bits": [ 207 ] + }, + "CH1_FF_RX_D_12": { + "direction": "output", + "bits": [ 208 ] + }, + "CH0_FF_RX_D_13": { + "direction": "output", + "bits": [ 209 ] + }, + "CH1_FF_RX_D_13": { + "direction": "output", + "bits": [ 210 ] + }, + "CH0_FF_RX_D_14": { + "direction": "output", + "bits": [ 211 ] + }, + "CH1_FF_RX_D_14": { + "direction": "output", + "bits": [ 212 ] + }, + "CH0_FF_RX_D_15": { + "direction": "output", + "bits": [ 213 ] + }, + "CH1_FF_RX_D_15": { + "direction": "output", + "bits": [ 214 ] + }, + "CH0_FF_RX_D_16": { + "direction": "output", + "bits": [ 215 ] + }, + "CH1_FF_RX_D_16": { + "direction": "output", + "bits": [ 216 ] + }, + "CH0_FF_RX_D_17": { + "direction": "output", + "bits": [ 217 ] + }, + "CH1_FF_RX_D_17": { + "direction": "output", + "bits": [ 218 ] + }, + "CH0_FF_RX_D_18": { + "direction": "output", + "bits": [ 219 ] + }, + "CH1_FF_RX_D_18": { + "direction": "output", + "bits": [ 220 ] + }, + "CH0_FF_RX_D_19": { + "direction": "output", + "bits": [ 221 ] + }, + "CH1_FF_RX_D_19": { + "direction": "output", + "bits": [ 222 ] + }, + "CH0_FF_RX_D_20": { + "direction": "output", + "bits": [ 223 ] + }, + "CH1_FF_RX_D_20": { + "direction": "output", + "bits": [ 224 ] + }, + "CH0_FF_RX_D_21": { + "direction": "output", + "bits": [ 225 ] + }, + "CH1_FF_RX_D_21": { + "direction": "output", + "bits": [ 226 ] + }, + "CH0_FF_RX_D_22": { + "direction": "output", + "bits": [ 227 ] + }, + "CH1_FF_RX_D_22": { + "direction": "output", + "bits": [ 228 ] + }, + "CH0_FF_RX_D_23": { + "direction": "output", + "bits": [ 229 ] + }, + "CH1_FF_RX_D_23": { + "direction": "output", + "bits": [ 230 ] + }, + "CH0_FFS_PCIE_DONE": { + "direction": "output", + "bits": [ 231 ] + }, + "CH1_FFS_PCIE_DONE": { + "direction": "output", + "bits": [ 232 ] + }, + "CH0_FFS_PCIE_CON": { + "direction": "output", + "bits": [ 233 ] + }, + "CH1_FFS_PCIE_CON": { + "direction": "output", + "bits": [ 234 ] + }, + "CH0_FFS_RLOS": { + "direction": "output", + "bits": [ 235 ] + }, + "CH1_FFS_RLOS": { + "direction": "output", + "bits": [ 236 ] + }, + "CH0_FFS_LS_SYNC_STATUS": { + "direction": "output", + "bits": [ 237 ] + }, + "CH1_FFS_LS_SYNC_STATUS": { + "direction": "output", + "bits": [ 238 ] + }, + "CH0_FFS_CC_UNDERRUN": { + "direction": "output", + "bits": [ 239 ] + }, + "CH1_FFS_CC_UNDERRUN": { + "direction": "output", + "bits": [ 240 ] + }, + "CH0_FFS_CC_OVERRUN": { + "direction": "output", + "bits": [ 241 ] + }, + "CH1_FFS_CC_OVERRUN": { + "direction": "output", + "bits": [ 242 ] + }, + "CH0_FFS_RXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 243 ] + }, + "CH1_FFS_RXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 244 ] + }, + "CH0_FFS_TXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 245 ] + }, + "CH1_FFS_TXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 246 ] + }, + "CH0_FFS_RLOL": { + "direction": "output", + "bits": [ 247 ] + }, + "CH1_FFS_RLOL": { + "direction": "output", + "bits": [ 248 ] + }, + "CH0_FFS_SKP_ADDED": { + "direction": "output", + "bits": [ 249 ] + }, + "CH1_FFS_SKP_ADDED": { + "direction": "output", + "bits": [ 250 ] + }, + "CH0_FFS_SKP_DELETED": { + "direction": "output", + "bits": [ 251 ] + }, + "CH1_FFS_SKP_DELETED": { + "direction": "output", + "bits": [ 252 ] + }, + "CH0_LDR_RX2CORE": { + "direction": "output", + "bits": [ 253 ] + }, + "CH1_LDR_RX2CORE": { + "direction": "output", + "bits": [ 254 ] + }, + "D_SCIRDATA0": { + "direction": "output", + "bits": [ 255 ] + }, + "D_SCIRDATA1": { + "direction": "output", + "bits": [ 256 ] + }, + "D_SCIRDATA2": { + "direction": "output", + "bits": [ 257 ] + }, + "D_SCIRDATA3": { + "direction": "output", + "bits": [ 258 ] + }, + "D_SCIRDATA4": { + "direction": "output", + "bits": [ 259 ] + }, + "D_SCIRDATA5": { + "direction": "output", + "bits": [ 260 ] + }, + "D_SCIRDATA6": { + "direction": "output", + "bits": [ 261 ] + }, + "D_SCIRDATA7": { + "direction": "output", + "bits": [ 262 ] + }, + "D_SCIINT": { + "direction": "output", + "bits": [ 263 ] + }, + "D_SCAN_OUT_0": { + "direction": "output", + "bits": [ 264 ] + }, + "D_SCAN_OUT_1": { + "direction": "output", + "bits": [ 265 ] + }, + "D_SCAN_OUT_2": { + "direction": "output", + "bits": [ 266 ] + }, + "D_SCAN_OUT_3": { + "direction": "output", + "bits": [ 267 ] + }, + "D_SCAN_OUT_4": { + "direction": "output", + "bits": [ 268 ] + }, + "D_SCAN_OUT_5": { + "direction": "output", + "bits": [ 269 ] + }, + "D_SCAN_OUT_6": { + "direction": "output", + "bits": [ 270 ] + }, + "D_SCAN_OUT_7": { + "direction": "output", + "bits": [ 271 ] + }, + "D_COUT0": { + "direction": "output", + "bits": [ 272 ] + }, + "D_COUT1": { + "direction": "output", + "bits": [ 273 ] + }, + "D_COUT2": { + "direction": "output", + "bits": [ 274 ] + }, + "D_COUT3": { + "direction": "output", + "bits": [ 275 ] + }, + "D_COUT4": { + "direction": "output", + "bits": [ 276 ] + }, + "D_COUT5": { + "direction": "output", + "bits": [ 277 ] + }, + "D_COUT6": { + "direction": "output", + "bits": [ 278 ] + }, + "D_COUT7": { + "direction": "output", + "bits": [ 279 ] + }, + "D_COUT8": { + "direction": "output", + "bits": [ 280 ] + }, + "D_COUT9": { + "direction": "output", + "bits": [ 281 ] + }, + "D_COUT10": { + "direction": "output", + "bits": [ 282 ] + }, + "D_COUT11": { + "direction": "output", + "bits": [ 283 ] + }, + "D_COUT12": { + "direction": "output", + "bits": [ 284 ] + }, + "D_COUT13": { + "direction": "output", + "bits": [ 285 ] + }, + "D_COUT14": { + "direction": "output", + "bits": [ 286 ] + }, + "D_COUT15": { + "direction": "output", + "bits": [ 287 ] + }, + "D_COUT16": { + "direction": "output", + "bits": [ 288 ] + }, + "D_COUT17": { + "direction": "output", + "bits": [ 289 ] + }, + "D_COUT18": { + "direction": "output", + "bits": [ 290 ] + }, + "D_COUT19": { + "direction": "output", + "bits": [ 291 ] + }, + "D_REFCLKI": { + "direction": "input", + "bits": [ 292 ] + }, + "D_FFS_PLOL": { + "direction": "output", + "bits": [ 293 ] + } + }, + "cells": { + }, + "netnames": { + "CH0_FFC_CDR_EN_BITSLIP": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1876.11-1876.33" + } + }, + "CH0_FFC_DIV11_MODE_RX": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1826.11-1826.32" + } + }, + "CH0_FFC_DIV11_MODE_TX": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1832.11-1832.32" + } + }, + "CH0_FFC_EI_EN": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1804.11-1804.24" + } + }, + "CH0_FFC_ENABLE_CGALIGN": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1812.11-1812.33" + } + }, + "CH0_FFC_FB_LOOPBACK": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1816.11-1816.30" + } + }, + "CH0_FFC_LANE_RX_RST": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1838.11-1838.30" + } + }, + "CH0_FFC_LANE_TX_RST": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1836.11-1836.30" + } + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1834.11-1834.33" + } + }, + "CH0_FFC_PCIE_CT": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1808.11-1808.26" + } + }, + "CH0_FFC_PCIE_DET_EN": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1806.11-1806.30" + } + }, + "CH0_FFC_PFIFO_CLR": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1820.11-1820.28" + } + }, + "CH0_FFC_RATE_MODE_RX": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1822.11-1822.31" + } + }, + "CH0_FFC_RATE_MODE_TX": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1824.11-1824.31" + } + }, + "CH0_FFC_RRST": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1840.11-1840.23" + } + }, + "CH0_FFC_RXPWDNB": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1844.11-1844.26" + } + }, + "CH0_FFC_RX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1828.11-1828.31" + } + }, + "CH0_FFC_SB_INV_RX": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1810.11-1810.28" + } + }, + "CH0_FFC_SB_PFIFO_LP": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1818.11-1818.30" + } + }, + "CH0_FFC_SIGNAL_DETECT": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1814.11-1814.32" + } + }, + "CH0_FFC_TXPWDNB": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1842.11-1842.26" + } + }, + "CH0_FFC_TX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1830.11-1830.31" + } + }, + "CH0_FFS_CC_OVERRUN": { + "hide_name": 0, + "bits": [ 241 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1979.12-1979.30" + } + }, + "CH0_FFS_CC_UNDERRUN": { + "hide_name": 0, + "bits": [ 239 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1977.12-1977.31" + } + }, + "CH0_FFS_LS_SYNC_STATUS": { + "hide_name": 0, + "bits": [ 237 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1975.12-1975.34" + } + }, + "CH0_FFS_PCIE_CON": { + "hide_name": 0, + "bits": [ 233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1971.12-1971.28" + } + }, + "CH0_FFS_PCIE_DONE": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1969.12-1969.29" + } + }, + "CH0_FFS_RLOL": { + "hide_name": 0, + "bits": [ 247 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1985.12-1985.24" + } + }, + "CH0_FFS_RLOS": { + "hide_name": 0, + "bits": [ 235 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1973.12-1973.24" + } + }, + "CH0_FFS_RXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 243 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1981.12-1981.34" + } + }, + "CH0_FFS_SKP_ADDED": { + "hide_name": 0, + "bits": [ 249 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1987.12-1987.29" + } + }, + "CH0_FFS_SKP_DELETED": { + "hide_name": 0, + "bits": [ 251 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1989.12-1989.31" + } + }, + "CH0_FFS_TXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 245 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1983.12-1983.34" + } + }, + "CH0_FF_EBRD_CLK": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1754.11-1754.26" + } + }, + "CH0_FF_RXI_CLK": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1750.11-1750.25" + } + }, + "CH0_FF_RX_D_0": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1921.12-1921.25" + } + }, + "CH0_FF_RX_D_1": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1923.12-1923.25" + } + }, + "CH0_FF_RX_D_10": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1941.12-1941.26" + } + }, + "CH0_FF_RX_D_11": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1943.12-1943.26" + } + }, + "CH0_FF_RX_D_12": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1945.12-1945.26" + } + }, + "CH0_FF_RX_D_13": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1947.12-1947.26" + } + }, + "CH0_FF_RX_D_14": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1949.12-1949.26" + } + }, + "CH0_FF_RX_D_15": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1951.12-1951.26" + } + }, + "CH0_FF_RX_D_16": { + "hide_name": 0, + "bits": [ 215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1953.12-1953.26" + } + }, + "CH0_FF_RX_D_17": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1955.12-1955.26" + } + }, + "CH0_FF_RX_D_18": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1957.12-1957.26" + } + }, + "CH0_FF_RX_D_19": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1959.12-1959.26" + } + }, + "CH0_FF_RX_D_2": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1925.12-1925.25" + } + }, + "CH0_FF_RX_D_20": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1961.12-1961.26" + } + }, + "CH0_FF_RX_D_21": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1963.12-1963.26" + } + }, + "CH0_FF_RX_D_22": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1965.12-1965.26" + } + }, + "CH0_FF_RX_D_23": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1967.12-1967.26" + } + }, + "CH0_FF_RX_D_3": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1927.12-1927.25" + } + }, + "CH0_FF_RX_D_4": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1929.12-1929.25" + } + }, + "CH0_FF_RX_D_5": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1931.12-1931.25" + } + }, + "CH0_FF_RX_D_6": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1933.12-1933.25" + } + }, + "CH0_FF_RX_D_7": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1935.12-1935.25" + } + }, + "CH0_FF_RX_D_8": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1937.12-1937.25" + } + }, + "CH0_FF_RX_D_9": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1939.12-1939.25" + } + }, + "CH0_FF_RX_F_CLK": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1909.12-1909.27" + } + }, + "CH0_FF_RX_H_CLK": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1911.12-1911.27" + } + }, + "CH0_FF_RX_PCLK": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1917.12-1917.26" + } + }, + "CH0_FF_TXI_CLK": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1752.11-1752.25" + } + }, + "CH0_FF_TX_D_0": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1756.11-1756.24" + } + }, + "CH0_FF_TX_D_1": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1758.11-1758.24" + } + }, + "CH0_FF_TX_D_10": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1776.11-1776.25" + } + }, + "CH0_FF_TX_D_11": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1778.11-1778.25" + } + }, + "CH0_FF_TX_D_12": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1780.11-1780.25" + } + }, + "CH0_FF_TX_D_13": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1782.11-1782.25" + } + }, + "CH0_FF_TX_D_14": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1784.11-1784.25" + } + }, + "CH0_FF_TX_D_15": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1786.11-1786.25" + } + }, + "CH0_FF_TX_D_16": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1788.11-1788.25" + } + }, + "CH0_FF_TX_D_17": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1790.11-1790.25" + } + }, + "CH0_FF_TX_D_18": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1792.11-1792.25" + } + }, + "CH0_FF_TX_D_19": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1794.11-1794.25" + } + }, + "CH0_FF_TX_D_2": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1760.11-1760.24" + } + }, + "CH0_FF_TX_D_20": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1796.11-1796.25" + } + }, + "CH0_FF_TX_D_21": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1798.11-1798.25" + } + }, + "CH0_FF_TX_D_22": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1800.11-1800.25" + } + }, + "CH0_FF_TX_D_23": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1802.11-1802.25" + } + }, + "CH0_FF_TX_D_3": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1762.11-1762.24" + } + }, + "CH0_FF_TX_D_4": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1764.11-1764.24" + } + }, + "CH0_FF_TX_D_5": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1766.11-1766.24" + } + }, + "CH0_FF_TX_D_6": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1768.11-1768.24" + } + }, + "CH0_FF_TX_D_7": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1770.11-1770.24" + } + }, + "CH0_FF_TX_D_8": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1772.11-1772.24" + } + }, + "CH0_FF_TX_D_9": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1774.11-1774.24" + } + }, + "CH0_FF_TX_F_CLK": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1913.12-1913.27" + } + }, + "CH0_FF_TX_H_CLK": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1915.12-1915.27" + } + }, + "CH0_FF_TX_PCLK": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1919.12-1919.26" + } + }, + "CH0_HDINN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1741.11-1741.20" + } + }, + "CH0_HDINP": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1737.11-1737.20" + } + }, + "CH0_HDOUTN": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1903.12-1903.22" + } + }, + "CH0_HDOUTP": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1901.12-1901.22" + } + }, + "CH0_LDR_CORE2TX": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1846.11-1846.26" + } + }, + "CH0_LDR_RX2CORE": { + "hide_name": 0, + "bits": [ 253 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1991.12-1991.27" + } + }, + "CH0_RX_REFCLK": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1748.11-1748.24" + } + }, + "CH0_SCIEN": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1864.11-1864.20" + } + }, + "CH0_SCISEL": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1866.11-1866.21" + } + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1877.11-1877.33" + } + }, + "CH1_FFC_DIV11_MODE_RX": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1827.11-1827.32" + } + }, + "CH1_FFC_DIV11_MODE_TX": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1833.11-1833.32" + } + }, + "CH1_FFC_EI_EN": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1805.11-1805.24" + } + }, + "CH1_FFC_ENABLE_CGALIGN": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1813.11-1813.33" + } + }, + "CH1_FFC_FB_LOOPBACK": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1817.11-1817.30" + } + }, + "CH1_FFC_LANE_RX_RST": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1839.11-1839.30" + } + }, + "CH1_FFC_LANE_TX_RST": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1837.11-1837.30" + } + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1835.11-1835.33" + } + }, + "CH1_FFC_PCIE_CT": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1809.11-1809.26" + } + }, + "CH1_FFC_PCIE_DET_EN": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1807.11-1807.30" + } + }, + "CH1_FFC_PFIFO_CLR": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1821.11-1821.28" + } + }, + "CH1_FFC_RATE_MODE_RX": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1823.11-1823.31" + } + }, + "CH1_FFC_RATE_MODE_TX": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1825.11-1825.31" + } + }, + "CH1_FFC_RRST": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1841.11-1841.23" + } + }, + "CH1_FFC_RXPWDNB": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1845.11-1845.26" + } + }, + "CH1_FFC_RX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1829.11-1829.31" + } + }, + "CH1_FFC_SB_INV_RX": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1811.11-1811.28" + } + }, + "CH1_FFC_SB_PFIFO_LP": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1819.11-1819.30" + } + }, + "CH1_FFC_SIGNAL_DETECT": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1815.11-1815.32" + } + }, + "CH1_FFC_TXPWDNB": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1843.11-1843.26" + } + }, + "CH1_FFC_TX_GEAR_MODE": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1831.11-1831.31" + } + }, + "CH1_FFS_CC_OVERRUN": { + "hide_name": 0, + "bits": [ 242 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1980.12-1980.30" + } + }, + "CH1_FFS_CC_UNDERRUN": { + "hide_name": 0, + "bits": [ 240 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1978.12-1978.31" + } + }, + "CH1_FFS_LS_SYNC_STATUS": { + "hide_name": 0, + "bits": [ 238 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1976.12-1976.34" + } + }, + "CH1_FFS_PCIE_CON": { + "hide_name": 0, + "bits": [ 234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1972.12-1972.28" + } + }, + "CH1_FFS_PCIE_DONE": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1970.12-1970.29" + } + }, + "CH1_FFS_RLOL": { + "hide_name": 0, + "bits": [ 248 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1986.12-1986.24" + } + }, + "CH1_FFS_RLOS": { + "hide_name": 0, + "bits": [ 236 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1974.12-1974.24" + } + }, + "CH1_FFS_RXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 244 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1982.12-1982.34" + } + }, + "CH1_FFS_SKP_ADDED": { + "hide_name": 0, + "bits": [ 250 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1988.12-1988.29" + } + }, + "CH1_FFS_SKP_DELETED": { + "hide_name": 0, + "bits": [ 252 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1990.12-1990.31" + } + }, + "CH1_FFS_TXFBFIFO_ERROR": { + "hide_name": 0, + "bits": [ 246 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1984.12-1984.34" + } + }, + "CH1_FF_EBRD_CLK": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1755.11-1755.26" + } + }, + "CH1_FF_RXI_CLK": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1751.11-1751.25" + } + }, + "CH1_FF_RX_D_0": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1922.12-1922.25" + } + }, + "CH1_FF_RX_D_1": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1924.12-1924.25" + } + }, + "CH1_FF_RX_D_10": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1942.12-1942.26" + } + }, + "CH1_FF_RX_D_11": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1944.12-1944.26" + } + }, + "CH1_FF_RX_D_12": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1946.12-1946.26" + } + }, + "CH1_FF_RX_D_13": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1948.12-1948.26" + } + }, + "CH1_FF_RX_D_14": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1950.12-1950.26" + } + }, + "CH1_FF_RX_D_15": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1952.12-1952.26" + } + }, + "CH1_FF_RX_D_16": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1954.12-1954.26" + } + }, + "CH1_FF_RX_D_17": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1956.12-1956.26" + } + }, + "CH1_FF_RX_D_18": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1958.12-1958.26" + } + }, + "CH1_FF_RX_D_19": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1960.12-1960.26" + } + }, + "CH1_FF_RX_D_2": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1926.12-1926.25" + } + }, + "CH1_FF_RX_D_20": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1962.12-1962.26" + } + }, + "CH1_FF_RX_D_21": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1964.12-1964.26" + } + }, + "CH1_FF_RX_D_22": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1966.12-1966.26" + } + }, + "CH1_FF_RX_D_23": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1968.12-1968.26" + } + }, + "CH1_FF_RX_D_3": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1928.12-1928.25" + } + }, + "CH1_FF_RX_D_4": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1930.12-1930.25" + } + }, + "CH1_FF_RX_D_5": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1932.12-1932.25" + } + }, + "CH1_FF_RX_D_6": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1934.12-1934.25" + } + }, + "CH1_FF_RX_D_7": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1936.12-1936.25" + } + }, + "CH1_FF_RX_D_8": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1938.12-1938.25" + } + }, + "CH1_FF_RX_D_9": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1940.12-1940.25" + } + }, + "CH1_FF_RX_F_CLK": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1910.12-1910.27" + } + }, + "CH1_FF_RX_H_CLK": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1912.12-1912.27" + } + }, + "CH1_FF_RX_PCLK": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1918.12-1918.26" + } + }, + "CH1_FF_TXI_CLK": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1753.11-1753.25" + } + }, + "CH1_FF_TX_D_0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1757.11-1757.24" + } + }, + "CH1_FF_TX_D_1": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1759.11-1759.24" + } + }, + "CH1_FF_TX_D_10": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1777.11-1777.25" + } + }, + "CH1_FF_TX_D_11": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1779.11-1779.25" + } + }, + "CH1_FF_TX_D_12": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1781.11-1781.25" + } + }, + "CH1_FF_TX_D_13": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1783.11-1783.25" + } + }, + "CH1_FF_TX_D_14": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1785.11-1785.25" + } + }, + "CH1_FF_TX_D_15": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1787.11-1787.25" + } + }, + "CH1_FF_TX_D_16": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1789.11-1789.25" + } + }, + "CH1_FF_TX_D_17": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1791.11-1791.25" + } + }, + "CH1_FF_TX_D_18": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1793.11-1793.25" + } + }, + "CH1_FF_TX_D_19": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1795.11-1795.25" + } + }, + "CH1_FF_TX_D_2": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1761.11-1761.24" + } + }, + "CH1_FF_TX_D_20": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1797.11-1797.25" + } + }, + "CH1_FF_TX_D_21": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1799.11-1799.25" + } + }, + "CH1_FF_TX_D_22": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1801.11-1801.25" + } + }, + "CH1_FF_TX_D_23": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1803.11-1803.25" + } + }, + "CH1_FF_TX_D_3": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1763.11-1763.24" + } + }, + "CH1_FF_TX_D_4": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1765.11-1765.24" + } + }, + "CH1_FF_TX_D_5": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1767.11-1767.24" + } + }, + "CH1_FF_TX_D_6": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1769.11-1769.24" + } + }, + "CH1_FF_TX_D_7": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1771.11-1771.24" + } + }, + "CH1_FF_TX_D_8": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1773.11-1773.24" + } + }, + "CH1_FF_TX_D_9": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1775.11-1775.24" + } + }, + "CH1_FF_TX_F_CLK": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1914.12-1914.27" + } + }, + "CH1_FF_TX_H_CLK": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1916.12-1916.27" + } + }, + "CH1_FF_TX_PCLK": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1920.12-1920.26" + } + }, + "CH1_HDINN": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1743.11-1743.20" + } + }, + "CH1_HDINP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1739.11-1739.20" + } + }, + "CH1_HDOUTN": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1904.12-1904.22" + } + }, + "CH1_HDOUTP": { + "hide_name": 0, + "bits": [ 164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1902.12-1902.22" + } + }, + "CH1_LDR_CORE2TX": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1847.11-1847.26" + } + }, + "CH1_LDR_RX2CORE": { + "hide_name": 0, + "bits": [ 254 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1992.12-1992.27" + } + }, + "CH1_RX_REFCLK": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1749.11-1749.24" + } + }, + "CH1_SCIEN": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1865.11-1865.20" + } + }, + "CH1_SCISEL": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1867.11-1867.21" + } + }, + "D_CIN0": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1889.11-1889.17" + } + }, + "D_CIN1": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1890.11-1890.17" + } + }, + "D_CIN10": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1899.11-1899.18" + } + }, + "D_CIN11": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1900.11-1900.18" + } + }, + "D_CIN2": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1891.11-1891.17" + } + }, + "D_CIN3": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1892.11-1892.17" + } + }, + "D_CIN4": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1893.11-1893.17" + } + }, + "D_CIN5": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1894.11-1894.17" + } + }, + "D_CIN6": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1895.11-1895.17" + } + }, + "D_CIN7": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1896.11-1896.17" + } + }, + "D_CIN8": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1897.11-1897.17" + } + }, + "D_CIN9": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1898.11-1898.17" + } + }, + "D_COUT0": { + "hide_name": 0, + "bits": [ 272 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2010.12-2010.19" + } + }, + "D_COUT1": { + "hide_name": 0, + "bits": [ 273 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2011.12-2011.19" + } + }, + "D_COUT10": { + "hide_name": 0, + "bits": [ 282 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2020.12-2020.20" + } + }, + "D_COUT11": { + "hide_name": 0, + "bits": [ 283 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2021.12-2021.20" + } + }, + "D_COUT12": { + "hide_name": 0, + "bits": [ 284 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2022.12-2022.20" + } + }, + "D_COUT13": { + "hide_name": 0, + "bits": [ 285 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2023.12-2023.20" + } + }, + "D_COUT14": { + "hide_name": 0, + "bits": [ 286 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2024.12-2024.20" + } + }, + "D_COUT15": { + "hide_name": 0, + "bits": [ 287 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2025.12-2025.20" + } + }, + "D_COUT16": { + "hide_name": 0, + "bits": [ 288 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2026.12-2026.20" + } + }, + "D_COUT17": { + "hide_name": 0, + "bits": [ 289 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2027.12-2027.20" + } + }, + "D_COUT18": { + "hide_name": 0, + "bits": [ 290 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2028.12-2028.20" + } + }, + "D_COUT19": { + "hide_name": 0, + "bits": [ 291 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2029.12-2029.20" + } + }, + "D_COUT2": { + "hide_name": 0, + "bits": [ 274 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2012.12-2012.19" + } + }, + "D_COUT3": { + "hide_name": 0, + "bits": [ 275 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2013.12-2013.19" + } + }, + "D_COUT4": { + "hide_name": 0, + "bits": [ 276 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2014.12-2014.19" + } + }, + "D_COUT5": { + "hide_name": 0, + "bits": [ 277 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2015.12-2015.19" + } + }, + "D_COUT6": { + "hide_name": 0, + "bits": [ 278 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2016.12-2016.19" + } + }, + "D_COUT7": { + "hide_name": 0, + "bits": [ 279 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2017.12-2017.19" + } + }, + "D_COUT8": { + "hide_name": 0, + "bits": [ 280 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2018.12-2018.19" + } + }, + "D_COUT9": { + "hide_name": 0, + "bits": [ 281 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2019.12-2019.19" + } + }, + "D_CYAWSTN": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1870.11-1870.20" + } + }, + "D_FFC_DUAL_RST": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1872.11-1872.25" + } + }, + "D_FFC_MACROPDB": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1874.11-1874.25" + } + }, + "D_FFC_MACRO_RST": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1873.11-1873.26" + } + }, + "D_FFC_SYNC_TOGGLE": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1871.11-1871.28" + } + }, + "D_FFC_TRST": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1875.11-1875.21" + } + }, + "D_FFS_PLOL": { + "hide_name": 0, + "bits": [ 293 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2031.12-2031.22" + } + }, + "D_REFCLKI": { + "hide_name": 0, + "bits": [ 292 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2030.11-2030.20" + } + }, + "D_SCAN_ENABLE": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1878.11-1878.24" + } + }, + "D_SCAN_IN_0": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1879.11-1879.22" + } + }, + "D_SCAN_IN_1": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1880.11-1880.22" + } + }, + "D_SCAN_IN_2": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1881.11-1881.22" + } + }, + "D_SCAN_IN_3": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1882.11-1882.22" + } + }, + "D_SCAN_IN_4": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1883.11-1883.22" + } + }, + "D_SCAN_IN_5": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1884.11-1884.22" + } + }, + "D_SCAN_IN_6": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1885.11-1885.22" + } + }, + "D_SCAN_IN_7": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1886.11-1886.22" + } + }, + "D_SCAN_MODE": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1887.11-1887.22" + } + }, + "D_SCAN_OUT_0": { + "hide_name": 0, + "bits": [ 264 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2002.12-2002.24" + } + }, + "D_SCAN_OUT_1": { + "hide_name": 0, + "bits": [ 265 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2003.12-2003.24" + } + }, + "D_SCAN_OUT_2": { + "hide_name": 0, + "bits": [ 266 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2004.12-2004.24" + } + }, + "D_SCAN_OUT_3": { + "hide_name": 0, + "bits": [ 267 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2005.12-2005.24" + } + }, + "D_SCAN_OUT_4": { + "hide_name": 0, + "bits": [ 268 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2006.12-2006.24" + } + }, + "D_SCAN_OUT_5": { + "hide_name": 0, + "bits": [ 269 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2007.12-2007.24" + } + }, + "D_SCAN_OUT_6": { + "hide_name": 0, + "bits": [ 270 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2008.12-2008.24" + } + }, + "D_SCAN_OUT_7": { + "hide_name": 0, + "bits": [ 271 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2009.12-2009.24" + } + }, + "D_SCAN_RESET": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1888.11-1888.23" + } + }, + "D_SCIADDR0": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1856.11-1856.21" + } + }, + "D_SCIADDR1": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1857.11-1857.21" + } + }, + "D_SCIADDR2": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1858.11-1858.21" + } + }, + "D_SCIADDR3": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1859.11-1859.21" + } + }, + "D_SCIADDR4": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1860.11-1860.21" + } + }, + "D_SCIADDR5": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1861.11-1861.21" + } + }, + "D_SCIENAUX": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1862.11-1862.21" + } + }, + "D_SCIINT": { + "hide_name": 0, + "bits": [ 263 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2001.12-2001.20" + } + }, + "D_SCIRD": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1868.11-1868.18" + } + }, + "D_SCIRDATA0": { + "hide_name": 0, + "bits": [ 255 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1993.12-1993.23" + } + }, + "D_SCIRDATA1": { + "hide_name": 0, + "bits": [ 256 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1994.12-1994.23" + } + }, + "D_SCIRDATA2": { + "hide_name": 0, + "bits": [ 257 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1995.12-1995.23" + } + }, + "D_SCIRDATA3": { + "hide_name": 0, + "bits": [ 258 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1996.12-1996.23" + } + }, + "D_SCIRDATA4": { + "hide_name": 0, + "bits": [ 259 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1997.12-1997.23" + } + }, + "D_SCIRDATA5": { + "hide_name": 0, + "bits": [ 260 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1998.12-1998.23" + } + }, + "D_SCIRDATA6": { + "hide_name": 0, + "bits": [ 261 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1999.12-1999.23" + } + }, + "D_SCIRDATA7": { + "hide_name": 0, + "bits": [ 262 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:2000.12-2000.23" + } + }, + "D_SCISELAUX": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1863.11-1863.22" + } + }, + "D_SCIWDATA0": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1848.11-1848.22" + } + }, + "D_SCIWDATA1": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1849.11-1849.22" + } + }, + "D_SCIWDATA2": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1850.11-1850.22" + } + }, + "D_SCIWDATA3": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1851.11-1851.22" + } + }, + "D_SCIWDATA4": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1852.11-1852.22" + } + }, + "D_SCIWDATA5": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1853.11-1853.22" + } + }, + "D_SCIWDATA6": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1854.11-1854.22" + } + }, + "D_SCIWDATA7": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1855.11-1855.22" + } + }, + "D_SCIWSTN": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1869.11-1869.20" + } + }, + "D_SYNC_ND": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1746.11-1746.20" + } + }, + "D_SYNC_PULSE2ND": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1907.12-1907.27" + } + }, + "D_TXBIT_CLKN_FROM_ND": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1745.11-1745.31" + } + }, + "D_TXBIT_CLKN_TO_ND": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1906.12-1906.30" + } + }, + "D_TXBIT_CLKP_FROM_ND": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1744.11-1744.31" + } + }, + "D_TXBIT_CLKP_TO_ND": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1905.12-1905.30" + } + }, + "D_TXPLL_LOL_FROM_ND": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1747.11-1747.30" + } + }, + "D_TXPLL_LOL_TO_ND": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1908.12-1908.29" + } + } + } + }, + "DDRDLLA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1139.1-1156.10" + }, + "parameter_default_values": { + "FORCE_MAX_DELAY": "NO", + "GSR": "ENABLED" + }, + "ports": { + "CLK": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "UDDCNTLN": { + "direction": "input", + "bits": [ 4 ] + }, + "FREEZE": { + "direction": "input", + "bits": [ 5 ] + }, + "DDRDEL": { + "direction": "output", + "bits": [ 6 ] + }, + "LOCK": { + "direction": "output", + "bits": [ 7 ] + }, + "DCNTL7": { + "direction": "output", + "bits": [ 8 ] + }, + "DCNTL6": { + "direction": "output", + "bits": [ 9 ] + }, + "DCNTL5": { + "direction": "output", + "bits": [ 10 ] + }, + "DCNTL4": { + "direction": "output", + "bits": [ 11 ] + }, + "DCNTL3": { + "direction": "output", + "bits": [ 12 ] + }, + "DCNTL2": { + "direction": "output", + "bits": [ 13 ] + }, + "DCNTL1": { + "direction": "output", + "bits": [ 14 ] + }, + "DCNTL0": { + "direction": "output", + "bits": [ 15 ] + } + }, + "cells": { + }, + "netnames": { + "CLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1142.11-1142.14" + } + }, + "DCNTL0": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1155.12-1155.18" + } + }, + "DCNTL1": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1154.12-1154.18" + } + }, + "DCNTL2": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1153.12-1153.18" + } + }, + "DCNTL3": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1152.12-1152.18" + } + }, + "DCNTL4": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1151.12-1151.18" + } + }, + "DCNTL5": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1150.12-1150.18" + } + }, + "DCNTL6": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1149.12-1149.18" + } + }, + "DCNTL7": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1148.12-1148.18" + } + }, + "DDRDEL": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1146.12-1146.18" + } + }, + "FREEZE": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1145.11-1145.17" + } + }, + "LOCK": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1147.12-1147.16" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1143.11-1143.14" + } + }, + "UDDCNTLN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1144.11-1144.19" + } + } + } + }, + "DELAYF": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1065.1-1074.10" + }, + "parameter_default_values": { + "DEL_MODE": "USER_DEFINED", + "DEL_VALUE": "00000000000000000000000000000000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "LOADN": { + "direction": "input", + "bits": [ 3 ] + }, + "MOVE": { + "direction": "input", + "bits": [ 4 ] + }, + "DIRECTION": { + "direction": "input", + "bits": [ 5 ] + }, + "Z": { + "direction": "output", + "bits": [ 6 ] + }, + "CFLAG": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1068.11-1068.12" + } + }, + "CFLAG": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1073.12-1073.17" + } + }, + "DIRECTION": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1071.11-1071.20" + } + }, + "LOADN": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1069.11-1069.16" + } + }, + "MOVE": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1070.11-1070.15" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1072.12-1072.13" + } + } + } + }, + "DELAYG": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1077.1-1082.10" + }, + "parameter_default_values": { + "DEL_MODE": "USER_DEFINED", + "DEL_VALUE": "00000000000000000000000000000000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "Z": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1080.11-1080.12" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1081.12-1081.13" + } + } + } + }, + "DLLDELD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1159.1-1167.10" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "DDRDEL": { + "direction": "input", + "bits": [ 3 ] + }, + "LOADN": { + "direction": "input", + "bits": [ 4 ] + }, + "MOVE": { + "direction": "input", + "bits": [ 5 ] + }, + "DIRECTION": { + "direction": "input", + "bits": [ 6 ] + }, + "Z": { + "direction": "output", + "bits": [ 7 ] + }, + "CFLAG": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1160.11-1160.12" + } + }, + "CFLAG": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1166.12-1166.17" + } + }, + "DDRDEL": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1161.11-1161.17" + } + }, + "DIRECTION": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1164.11-1164.20" + } + }, + "LOADN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1162.11-1162.16" + } + }, + "MOVE": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1163.11-1163.15" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1165.12-1165.13" + } + } + } + }, + "DP16KD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:5.1-219.10" + }, + "parameter_default_values": { + "ADA0MUX": "ADA0", + "ADA10MUX": "ADA10", + "ADA11MUX": "ADA11", + "ADA12MUX": "ADA12", + "ADA13MUX": "ADA13", + "ADA1MUX": "ADA1", + "ADA2MUX": "ADA2", + "ADA3MUX": "ADA3", + "ADA4MUX": "ADA4", + "ADA5MUX": "ADA5", + "ADA6MUX": "ADA6", + "ADA7MUX": "ADA7", + "ADA8MUX": "ADA8", + "ADA9MUX": "ADA9", + "ADB0MUX": "ADB0", + "ADB10MUX": "ADB10", + "ADB11MUX": "ADB11", + "ADB12MUX": "ADB12", + "ADB13MUX": "ADB13", + "ADB1MUX": "ADB1", + "ADB2MUX": "ADB2", + "ADB3MUX": "ADB3", + "ADB4MUX": "ADB4", + "ADB5MUX": "ADB5", + "ADB6MUX": "ADB6", + "ADB7MUX": "ADB7", + "ADB8MUX": "ADB8", + "ADB9MUX": "ADB9", + "ASYNC_RESET_RELEASE": "SYNC", + "CEAMUX": "CEA", + "CEBMUX": "CEB", + "CLKAMUX": "CLKA", + "CLKBMUX": "CLKB", + "CSA0MUX": "CSA0", + "CSA1MUX": "CSA1", + "CSA2MUX": "CSA2", + "CSB0MUX": "CSB0", + "CSB1MUX": "CSB1", + "CSB2MUX": "CSB2", + "CSDECODE_A": "0b000", + "CSDECODE_B": "0b000", + "DATA_WIDTH_A": "00000000000000000000000000010010", + "DATA_WIDTH_B": "00000000000000000000000000010010", + "DIA0MUX": "DIA0", + "DIA10MUX": "DIA10", + "DIA11MUX": "DIA11", + "DIA12MUX": "DIA12", + "DIA13MUX": "DIA13", + "DIA14MUX": "DIA14", + "DIA15MUX": "DIA15", + "DIA16MUX": "DIA16", + "DIA17MUX": "DIA17", + "DIA1MUX": "DIA1", + "DIA2MUX": "DIA2", + "DIA3MUX": "DIA3", + "DIA4MUX": "DIA4", + "DIA5MUX": "DIA5", + "DIA6MUX": "DIA6", + "DIA7MUX": "DIA7", + "DIA8MUX": "DIA8", + "DIA9MUX": "DIA9", + "DIB0MUX": "DIB0", + "DIB10MUX": "DIB10", + "DIB11MUX": "DIB11", + "DIB12MUX": "DIB12", + "DIB13MUX": "DIB13", + "DIB14MUX": "DIB14", + "DIB15MUX": "DIB15", + "DIB16MUX": "DIB16", + "DIB17MUX": "DIB17", + "DIB1MUX": "DIB1", + "DIB2MUX": "DIB2", + "DIB3MUX": "DIB3", + "DIB4MUX": "DIB4", + "DIB5MUX": "DIB5", + "DIB6MUX": "DIB6", + "DIB7MUX": "DIB7", + "DIB8MUX": "DIB8", + "DIB9MUX": "DIB9", + "DOA0MUX": "DOA0", + "DOA10MUX": "DOA10", + "DOA11MUX": "DOA11", + "DOA12MUX": "DOA12", + "DOA13MUX": "DOA13", + "DOA14MUX": "DOA14", + "DOA15MUX": "DOA15", + "DOA16MUX": "DOA16", + "DOA17MUX": "DOA17", + "DOA1MUX": "DOA1", + "DOA2MUX": "DOA2", + "DOA3MUX": "DOA3", + "DOA4MUX": "DOA4", + "DOA5MUX": "DOA5", + "DOA6MUX": "DOA6", + "DOA7MUX": "DOA7", + "DOA8MUX": "DOA8", + "DOA9MUX": "DOA9", + "DOB0MUX": "DOB0", + "DOB10MUX": "DOB10", + "DOB11MUX": "DOB11", + "DOB12MUX": "DOB12", + "DOB13MUX": "DOB13", + "DOB14MUX": "DOB14", + "DOB15MUX": "DOB15", + "DOB16MUX": "DOB16", + "DOB17MUX": "DOB17", + "DOB1MUX": "DOB1", + "DOB2MUX": "DOB2", + "DOB3MUX": "DOB3", + "DOB4MUX": "DOB4", + "DOB5MUX": "DOB5", + "DOB6MUX": "DOB6", + "DOB7MUX": "DOB7", + "DOB8MUX": "DOB8", + "DOB9MUX": "DOB9", + "GSR": "ENABLED", + "INITVAL_00": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_01": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_02": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_03": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_04": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_05": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_06": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_07": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_08": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_09": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_10": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_11": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_12": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_13": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_14": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_15": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_16": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_17": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_18": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_19": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_20": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_21": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_22": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_23": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_24": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_25": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_26": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_27": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_28": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_29": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_30": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_31": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_32": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_33": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_34": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_35": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_36": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_37": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_38": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_39": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INIT_DATA": "STATIC", + "OCEAMUX": "OCEA", + "OCEBMUX": "OCEB", + "REGMODE_A": "NOREG", + "REGMODE_B": "NOREG", + "RESETMODE": "SYNC", + "RSTAMUX": "RSTA", + "RSTBMUX": "RSTB", + "WEAMUX": "WEA", + "WEBMUX": "WEB", + "WID": "00000000000000000000000000000000", + "WRITEMODE_A": "NORMAL", + "WRITEMODE_B": "NORMAL" + }, + "ports": { + "DIA17": { + "direction": "input", + "bits": [ 2 ] + }, + "DIA16": { + "direction": "input", + "bits": [ 3 ] + }, + "DIA15": { + "direction": "input", + "bits": [ 4 ] + }, + "DIA14": { + "direction": "input", + "bits": [ 5 ] + }, + "DIA13": { + "direction": "input", + "bits": [ 6 ] + }, + "DIA12": { + "direction": "input", + "bits": [ 7 ] + }, + "DIA11": { + "direction": "input", + "bits": [ 8 ] + }, + "DIA10": { + "direction": "input", + "bits": [ 9 ] + }, + "DIA9": { + "direction": "input", + "bits": [ 10 ] + }, + "DIA8": { + "direction": "input", + "bits": [ 11 ] + }, + "DIA7": { + "direction": "input", + "bits": [ 12 ] + }, + "DIA6": { + "direction": "input", + "bits": [ 13 ] + }, + "DIA5": { + "direction": "input", + "bits": [ 14 ] + }, + "DIA4": { + "direction": "input", + "bits": [ 15 ] + }, + "DIA3": { + "direction": "input", + "bits": [ 16 ] + }, + "DIA2": { + "direction": "input", + "bits": [ 17 ] + }, + "DIA1": { + "direction": "input", + "bits": [ 18 ] + }, + "DIA0": { + "direction": "input", + "bits": [ 19 ] + }, + "ADA13": { + "direction": "input", + "bits": [ 20 ] + }, + "ADA12": { + "direction": "input", + "bits": [ 21 ] + }, + "ADA11": { + "direction": "input", + "bits": [ 22 ] + }, + "ADA10": { + "direction": "input", + "bits": [ 23 ] + }, + "ADA9": { + "direction": "input", + "bits": [ 24 ] + }, + "ADA8": { + "direction": "input", + "bits": [ 25 ] + }, + "ADA7": { + "direction": "input", + "bits": [ 26 ] + }, + "ADA6": { + "direction": "input", + "bits": [ 27 ] + }, + "ADA5": { + "direction": "input", + "bits": [ 28 ] + }, + "ADA4": { + "direction": "input", + "bits": [ 29 ] + }, + "ADA3": { + "direction": "input", + "bits": [ 30 ] + }, + "ADA2": { + "direction": "input", + "bits": [ 31 ] + }, + "ADA1": { + "direction": "input", + "bits": [ 32 ] + }, + "ADA0": { + "direction": "input", + "bits": [ 33 ] + }, + "CEA": { + "direction": "input", + "bits": [ 34 ] + }, + "OCEA": { + "direction": "input", + "bits": [ 35 ] + }, + "CLKA": { + "direction": "input", + "bits": [ 36 ] + }, + "WEA": { + "direction": "input", + "bits": [ 37 ] + }, + "RSTA": { + "direction": "input", + "bits": [ 38 ] + }, + "CSA2": { + "direction": "input", + "bits": [ 39 ] + }, + "CSA1": { + "direction": "input", + "bits": [ 40 ] + }, + "CSA0": { + "direction": "input", + "bits": [ 41 ] + }, + "DOA17": { + "direction": "output", + "bits": [ 42 ] + }, + "DOA16": { + "direction": "output", + "bits": [ 43 ] + }, + "DOA15": { + "direction": "output", + "bits": [ 44 ] + }, + "DOA14": { + "direction": "output", + "bits": [ 45 ] + }, + "DOA13": { + "direction": "output", + "bits": [ 46 ] + }, + "DOA12": { + "direction": "output", + "bits": [ 47 ] + }, + "DOA11": { + "direction": "output", + "bits": [ 48 ] + }, + "DOA10": { + "direction": "output", + "bits": [ 49 ] + }, + "DOA9": { + "direction": "output", + "bits": [ 50 ] + }, + "DOA8": { + "direction": "output", + "bits": [ 51 ] + }, + "DOA7": { + "direction": "output", + "bits": [ 52 ] + }, + "DOA6": { + "direction": "output", + "bits": [ 53 ] + }, + "DOA5": { + "direction": "output", + "bits": [ 54 ] + }, + "DOA4": { + "direction": "output", + "bits": [ 55 ] + }, + "DOA3": { + "direction": "output", + "bits": [ 56 ] + }, + "DOA2": { + "direction": "output", + "bits": [ 57 ] + }, + "DOA1": { + "direction": "output", + "bits": [ 58 ] + }, + "DOA0": { + "direction": "output", + "bits": [ 59 ] + }, + "DIB17": { + "direction": "input", + "bits": [ 60 ] + }, + "DIB16": { + "direction": "input", + "bits": [ 61 ] + }, + "DIB15": { + "direction": "input", + "bits": [ 62 ] + }, + "DIB14": { + "direction": "input", + "bits": [ 63 ] + }, + "DIB13": { + "direction": "input", + "bits": [ 64 ] + }, + "DIB12": { + "direction": "input", + "bits": [ 65 ] + }, + "DIB11": { + "direction": "input", + "bits": [ 66 ] + }, + "DIB10": { + "direction": "input", + "bits": [ 67 ] + }, + "DIB9": { + "direction": "input", + "bits": [ 68 ] + }, + "DIB8": { + "direction": "input", + "bits": [ 69 ] + }, + "DIB7": { + "direction": "input", + "bits": [ 70 ] + }, + "DIB6": { + "direction": "input", + "bits": [ 71 ] + }, + "DIB5": { + "direction": "input", + "bits": [ 72 ] + }, + "DIB4": { + "direction": "input", + "bits": [ 73 ] + }, + "DIB3": { + "direction": "input", + "bits": [ 74 ] + }, + "DIB2": { + "direction": "input", + "bits": [ 75 ] + }, + "DIB1": { + "direction": "input", + "bits": [ 76 ] + }, + "DIB0": { + "direction": "input", + "bits": [ 77 ] + }, + "ADB13": { + "direction": "input", + "bits": [ 78 ] + }, + "ADB12": { + "direction": "input", + "bits": [ 79 ] + }, + "ADB11": { + "direction": "input", + "bits": [ 80 ] + }, + "ADB10": { + "direction": "input", + "bits": [ 81 ] + }, + "ADB9": { + "direction": "input", + "bits": [ 82 ] + }, + "ADB8": { + "direction": "input", + "bits": [ 83 ] + }, + "ADB7": { + "direction": "input", + "bits": [ 84 ] + }, + "ADB6": { + "direction": "input", + "bits": [ 85 ] + }, + "ADB5": { + "direction": "input", + "bits": [ 86 ] + }, + "ADB4": { + "direction": "input", + "bits": [ 87 ] + }, + "ADB3": { + "direction": "input", + "bits": [ 88 ] + }, + "ADB2": { + "direction": "input", + "bits": [ 89 ] + }, + "ADB1": { + "direction": "input", + "bits": [ 90 ] + }, + "ADB0": { + "direction": "input", + "bits": [ 91 ] + }, + "CEB": { + "direction": "input", + "bits": [ 92 ] + }, + "OCEB": { + "direction": "input", + "bits": [ 93 ] + }, + "CLKB": { + "direction": "input", + "bits": [ 94 ] + }, + "WEB": { + "direction": "input", + "bits": [ 95 ] + }, + "RSTB": { + "direction": "input", + "bits": [ 96 ] + }, + "CSB2": { + "direction": "input", + "bits": [ 97 ] + }, + "CSB1": { + "direction": "input", + "bits": [ 98 ] + }, + "CSB0": { + "direction": "input", + "bits": [ 99 ] + }, + "DOB17": { + "direction": "output", + "bits": [ 100 ] + }, + "DOB16": { + "direction": "output", + "bits": [ 101 ] + }, + "DOB15": { + "direction": "output", + "bits": [ 102 ] + }, + "DOB14": { + "direction": "output", + "bits": [ 103 ] + }, + "DOB13": { + "direction": "output", + "bits": [ 104 ] + }, + "DOB12": { + "direction": "output", + "bits": [ 105 ] + }, + "DOB11": { + "direction": "output", + "bits": [ 106 ] + }, + "DOB10": { + "direction": "output", + "bits": [ 107 ] + }, + "DOB9": { + "direction": "output", + "bits": [ 108 ] + }, + "DOB8": { + "direction": "output", + "bits": [ 109 ] + }, + "DOB7": { + "direction": "output", + "bits": [ 110 ] + }, + "DOB6": { + "direction": "output", + "bits": [ 111 ] + }, + "DOB5": { + "direction": "output", + "bits": [ 112 ] + }, + "DOB4": { + "direction": "output", + "bits": [ 113 ] + }, + "DOB3": { + "direction": "output", + "bits": [ 114 ] + }, + "DOB2": { + "direction": "output", + "bits": [ 115 ] + }, + "DOB1": { + "direction": "output", + "bits": [ 116 ] + }, + "DOB0": { + "direction": "output", + "bits": [ 117 ] + } + }, + "cells": { + }, + "netnames": { + "ADA0": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.91-7.95" + } + }, + "ADA1": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.85-7.89" + } + }, + "ADA10": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.30-7.35" + } + }, + "ADA11": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.23-7.28" + } + }, + "ADA12": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.16-7.21" + } + }, + "ADA13": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.9-7.14" + } + }, + "ADA2": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.79-7.83" + } + }, + "ADA3": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.73-7.77" + } + }, + "ADA4": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.67-7.71" + } + }, + "ADA5": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.61-7.65" + } + }, + "ADA6": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.55-7.59" + } + }, + "ADA7": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.49-7.53" + } + }, + "ADA8": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.43-7.47" + } + }, + "ADA9": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:7.37-7.41" + } + }, + "ADB0": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.91-13.95" + } + }, + "ADB1": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.85-13.89" + } + }, + "ADB10": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.30-13.35" + } + }, + "ADB11": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.23-13.28" + } + }, + "ADB12": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.16-13.21" + } + }, + "ADB13": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.9-13.14" + } + }, + "ADB2": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.79-13.83" + } + }, + "ADB3": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.73-13.77" + } + }, + "ADB4": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.67-13.71" + } + }, + "ADB5": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.61-13.65" + } + }, + "ADB6": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.55-13.59" + } + }, + "ADB7": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.49-13.53" + } + }, + "ADB8": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.43-13.47" + } + }, + "ADB9": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:13.37-13.41" + } + }, + "CEA": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.9-8.12" + } + }, + "CEB": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.9-14.12" + } + }, + "CLKA": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.20-8.24" + } + }, + "CLKB": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.20-14.24" + } + }, + "CSA0": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:9.21-9.25" + } + }, + "CSA1": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:9.15-9.19" + } + }, + "CSA2": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:9.9-9.13" + } + }, + "CSB0": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:15.21-15.25" + } + }, + "CSB1": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:15.15-15.19" + } + }, + "CSB2": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:15.9-15.13" + } + }, + "DIA0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.119-6.123" + } + }, + "DIA1": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.113-6.117" + } + }, + "DIA10": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.58-6.63" + } + }, + "DIA11": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.51-6.56" + } + }, + "DIA12": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.44-6.49" + } + }, + "DIA13": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.37-6.42" + } + }, + "DIA14": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.30-6.35" + } + }, + "DIA15": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.23-6.28" + } + }, + "DIA16": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.16-6.21" + } + }, + "DIA17": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.9-6.14" + } + }, + "DIA2": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.107-6.111" + } + }, + "DIA3": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.101-6.105" + } + }, + "DIA4": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.95-6.99" + } + }, + "DIA5": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.89-6.93" + } + }, + "DIA6": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.83-6.87" + } + }, + "DIA7": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.77-6.81" + } + }, + "DIA8": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.71-6.75" + } + }, + "DIA9": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:6.65-6.69" + } + }, + "DIB0": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.119-12.123" + } + }, + "DIB1": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.113-12.117" + } + }, + "DIB10": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.58-12.63" + } + }, + "DIB11": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.51-12.56" + } + }, + "DIB12": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.44-12.49" + } + }, + "DIB13": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.37-12.42" + } + }, + "DIB14": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.30-12.35" + } + }, + "DIB15": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.23-12.28" + } + }, + "DIB16": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.16-12.21" + } + }, + "DIB17": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.9-12.14" + } + }, + "DIB2": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.107-12.111" + } + }, + "DIB3": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.101-12.105" + } + }, + "DIB4": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.95-12.99" + } + }, + "DIB5": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.89-12.93" + } + }, + "DIB6": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.83-12.87" + } + }, + "DIB7": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.77-12.81" + } + }, + "DIB8": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.71-12.75" + } + }, + "DIB9": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:12.65-12.69" + } + }, + "DOA0": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.120-10.124" + } + }, + "DOA1": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.114-10.118" + } + }, + "DOA10": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.59-10.64" + } + }, + "DOA11": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.52-10.57" + } + }, + "DOA12": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.45-10.50" + } + }, + "DOA13": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.38-10.43" + } + }, + "DOA14": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.31-10.36" + } + }, + "DOA15": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.24-10.29" + } + }, + "DOA16": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.17-10.22" + } + }, + "DOA17": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.10-10.15" + } + }, + "DOA2": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.108-10.112" + } + }, + "DOA3": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.102-10.106" + } + }, + "DOA4": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.96-10.100" + } + }, + "DOA5": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.90-10.94" + } + }, + "DOA6": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.84-10.88" + } + }, + "DOA7": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.78-10.82" + } + }, + "DOA8": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.72-10.76" + } + }, + "DOA9": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:10.66-10.70" + } + }, + "DOB0": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.120-16.124" + } + }, + "DOB1": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.114-16.118" + } + }, + "DOB10": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.59-16.64" + } + }, + "DOB11": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.52-16.57" + } + }, + "DOB12": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.45-16.50" + } + }, + "DOB13": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.38-16.43" + } + }, + "DOB14": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.31-16.36" + } + }, + "DOB15": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.24-16.29" + } + }, + "DOB16": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.17-16.22" + } + }, + "DOB17": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.10-16.15" + } + }, + "DOB2": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.108-16.112" + } + }, + "DOB3": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.102-16.106" + } + }, + "DOB4": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.96-16.100" + } + }, + "DOB5": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.90-16.94" + } + }, + "DOB6": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.84-16.88" + } + }, + "DOB7": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.78-16.82" + } + }, + "DOB8": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.72-16.76" + } + }, + "DOB9": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:16.66-16.70" + } + }, + "OCEA": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.14-8.18" + } + }, + "OCEB": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.14-14.18" + } + }, + "RSTA": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.31-8.35" + } + }, + "RSTB": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.31-14.35" + } + }, + "WEA": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:8.26-8.29" + } + }, + "WEB": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v:14.26-14.29" + } + } + } + }, + "DPR16X4C": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000101", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:174.1-233.10" + }, + "parameter_default_values": { + "INITVAL": "0x0000000000000000 " + }, + "ports": { + "DI": { + "direction": "input", + "bits": [ 2, 3, 4, 5 ] + }, + "WCK": { + "direction": "input", + "bits": [ 6 ] + }, + "WRE": { + "direction": "input", + "bits": [ 7 ] + }, + "RAD": { + "direction": "input", + "bits": [ 8, 9, 10, 11 ] + }, + "WAD": { + "direction": "input", + "bits": [ 12, 13, 14, 15 ] + }, + "DO": { + "direction": "output", + "bits": [ 16, 17, 18, 19 ] + } + }, + "cells": { + }, + "netnames": { + "DI": { + "hide_name": 0, + "bits": [ 2, 3, 4, 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:175.15-175.17" + } + }, + "DO": { + "hide_name": 0, + "bits": [ 16, 17, 18, 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:179.16-179.18" + } + }, + "RAD": { + "hide_name": 0, + "bits": [ 8, 9, 10, 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:177.15-177.18" + } + }, + "WAD": { + "hide_name": 0, + "bits": [ 12, 13, 14, 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:178.15-178.18" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:176.9-176.12" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:176.14-176.17" + } + } + } + }, + "DQSBUFM": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1091.1-1136.10" + }, + "parameter_default_values": { + "DQS_LI_DEL_ADJ": "FACTORYONLY", + "DQS_LI_DEL_VAL": "00000000000000000000000000000100", + "DQS_LO_DEL_ADJ": "FACTORYONLY", + "DQS_LO_DEL_VAL": "00000000000000000000000000000000", + "GSR": "ENABLED" + }, + "ports": { + "DQSI": { + "direction": "input", + "bits": [ 2 ] + }, + "READ1": { + "direction": "input", + "bits": [ 3 ] + }, + "READ0": { + "direction": "input", + "bits": [ 4 ] + }, + "READCLKSEL2": { + "direction": "input", + "bits": [ 5 ] + }, + "READCLKSEL1": { + "direction": "input", + "bits": [ 6 ] + }, + "READCLKSEL0": { + "direction": "input", + "bits": [ 7 ] + }, + "DDRDEL": { + "direction": "input", + "bits": [ 8 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 9 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "RST": { + "direction": "input", + "bits": [ 11 ] + }, + "DYNDELAY7": { + "direction": "input", + "bits": [ 12 ] + }, + "DYNDELAY6": { + "direction": "input", + "bits": [ 13 ] + }, + "DYNDELAY5": { + "direction": "input", + "bits": [ 14 ] + }, + "DYNDELAY4": { + "direction": "input", + "bits": [ 15 ] + }, + "DYNDELAY3": { + "direction": "input", + "bits": [ 16 ] + }, + "DYNDELAY2": { + "direction": "input", + "bits": [ 17 ] + }, + "DYNDELAY1": { + "direction": "input", + "bits": [ 18 ] + }, + "DYNDELAY0": { + "direction": "input", + "bits": [ 19 ] + }, + "PAUSE": { + "direction": "input", + "bits": [ 20 ] + }, + "RDLOADN": { + "direction": "input", + "bits": [ 21 ] + }, + "RDMOVE": { + "direction": "input", + "bits": [ 22 ] + }, + "RDDIRECTION": { + "direction": "input", + "bits": [ 23 ] + }, + "WRLOADN": { + "direction": "input", + "bits": [ 24 ] + }, + "WRMOVE": { + "direction": "input", + "bits": [ 25 ] + }, + "WRDIRECTION": { + "direction": "input", + "bits": [ 26 ] + }, + "DQSR90": { + "direction": "output", + "bits": [ 27 ] + }, + "DQSW": { + "direction": "output", + "bits": [ 28 ] + }, + "DQSW270": { + "direction": "output", + "bits": [ 29 ] + }, + "RDPNTR2": { + "direction": "output", + "bits": [ 30 ] + }, + "RDPNTR1": { + "direction": "output", + "bits": [ 31 ] + }, + "RDPNTR0": { + "direction": "output", + "bits": [ 32 ] + }, + "WRPNTR2": { + "direction": "output", + "bits": [ 33 ] + }, + "WRPNTR1": { + "direction": "output", + "bits": [ 34 ] + }, + "WRPNTR0": { + "direction": "output", + "bits": [ 35 ] + }, + "DATAVALID": { + "direction": "output", + "bits": [ 36 ] + }, + "BURSTDET": { + "direction": "output", + "bits": [ 37 ] + }, + "RDCFLAG": { + "direction": "output", + "bits": [ 38 ] + }, + "WRCFLAG": { + "direction": "output", + "bits": [ 39 ] + } + }, + "cells": { + }, + "netnames": { + "BURSTDET": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1133.12-1133.20" + } + }, + "DATAVALID": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1132.12-1132.21" + } + }, + "DDRDEL": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1104.11-1104.17" + } + }, + "DQSI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1098.11-1098.15" + } + }, + "DQSR90": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1123.12-1123.18" + } + }, + "DQSW": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1124.12-1124.16" + } + }, + "DQSW270": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1125.12-1125.19" + } + }, + "DYNDELAY0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1115.11-1115.20" + } + }, + "DYNDELAY1": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1114.11-1114.20" + } + }, + "DYNDELAY2": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1113.11-1113.20" + } + }, + "DYNDELAY3": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1112.11-1112.20" + } + }, + "DYNDELAY4": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1111.11-1111.20" + } + }, + "DYNDELAY5": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1110.11-1110.20" + } + }, + "DYNDELAY6": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1109.11-1109.20" + } + }, + "DYNDELAY7": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1108.11-1108.20" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1105.11-1105.15" + } + }, + "PAUSE": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1116.11-1116.16" + } + }, + "RDCFLAG": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1134.12-1134.19" + } + }, + "RDDIRECTION": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1119.11-1119.22" + } + }, + "RDLOADN": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1117.11-1117.18" + } + }, + "RDMOVE": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1118.11-1118.17" + } + }, + "RDPNTR0": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1128.12-1128.19" + } + }, + "RDPNTR1": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1127.12-1127.19" + } + }, + "RDPNTR2": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1126.12-1126.19" + } + }, + "READ0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1100.11-1100.16" + } + }, + "READ1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1099.11-1099.16" + } + }, + "READCLKSEL0": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1103.11-1103.22" + } + }, + "READCLKSEL1": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1102.11-1102.22" + } + }, + "READCLKSEL2": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1101.11-1101.22" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1107.11-1107.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1106.11-1106.15" + } + }, + "WRCFLAG": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1135.12-1135.19" + } + }, + "WRDIRECTION": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1122.11-1122.22" + } + }, + "WRLOADN": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1120.11-1120.18" + } + }, + "WRMOVE": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1121.11-1121.17" + } + }, + "WRPNTR0": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1131.12-1131.19" + } + }, + "WRPNTR1": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1130.12-1130.19" + } + }, + "WRPNTR2": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1129.12-1129.19" + } + } + } + }, + "DTR": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1399.1-1410.10" + }, + "parameter_default_values": { + "DTR_TEMP": "00000000000000000000000000011001" + }, + "ports": { + "STARTPULSE": { + "direction": "input", + "bits": [ 2 ] + }, + "DTROUT7": { + "direction": "output", + "bits": [ 3 ] + }, + "DTROUT6": { + "direction": "output", + "bits": [ 4 ] + }, + "DTROUT5": { + "direction": "output", + "bits": [ 5 ] + }, + "DTROUT4": { + "direction": "output", + "bits": [ 6 ] + }, + "DTROUT3": { + "direction": "output", + "bits": [ 7 ] + }, + "DTROUT2": { + "direction": "output", + "bits": [ 8 ] + }, + "DTROUT1": { + "direction": "output", + "bits": [ 9 ] + }, + "DTROUT0": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "DTROUT0": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1409.12-1409.19" + } + }, + "DTROUT1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1408.12-1408.19" + } + }, + "DTROUT2": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1407.12-1407.19" + } + }, + "DTROUT3": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1406.12-1406.19" + } + }, + "DTROUT4": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1405.12-1405.19" + } + }, + "DTROUT5": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1404.12-1404.19" + } + }, + "DTROUT6": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1403.12-1403.19" + } + }, + "DTROUT7": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1402.12-1402.19" + } + }, + "STARTPULSE": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1401.11-1401.21" + } + } + } + }, + "ECLKBRIDGECS": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1057.1-1062.10" + }, + "ports": { + "CLK0": { + "direction": "input", + "bits": [ 2 ] + }, + "CLK1": { + "direction": "input", + "bits": [ 3 ] + }, + "SEL": { + "direction": "input", + "bits": [ 4 ] + }, + "ECSOUT": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CLK0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1058.11-1058.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1059.11-1059.15" + } + }, + "ECSOUT": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1061.12-1061.18" + } + }, + "SEL": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1060.11-1060.14" + } + } + } + }, + "ECLKSYNCB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1050.1-1054.10" + }, + "ports": { + "ECLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "STOP": { + "direction": "input", + "bits": [ 3 ] + }, + "ECLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "ECLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1051.11-1051.16" + } + }, + "ECLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1053.12-1053.17" + } + }, + "STOP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1052.11-1052.15" + } + } + } + }, + "EHXPLLL": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1336.1-1396.10" + }, + "parameter_default_values": { + "CLKFB_DIV": "00000000000000000000000000000001", + "CLKI_DIV": "00000000000000000000000000000001", + "CLKOP_CPHASE": "00000000000000000000000000000000", + "CLKOP_DIV": "00000000000000000000000000001000", + "CLKOP_ENABLE": "ENABLED", + "CLKOP_FPHASE": "00000000000000000000000000000000", + "CLKOP_TRIM_DELAY": "00000000000000000000000000000000", + "CLKOP_TRIM_POL": "RISING", + "CLKOS2_CPHASE": "00000000000000000000000000000000", + "CLKOS2_DIV": "00000000000000000000000000001000", + "CLKOS2_ENABLE": "DISABLED", + "CLKOS2_FPHASE": "00000000000000000000000000000000", + "CLKOS3_CPHASE": "00000000000000000000000000000000", + "CLKOS3_DIV": "00000000000000000000000000001000", + "CLKOS3_ENABLE": "DISABLED", + "CLKOS3_FPHASE": "00000000000000000000000000000000", + "CLKOS_CPHASE": "00000000000000000000000000000000", + "CLKOS_DIV": "00000000000000000000000000001000", + "CLKOS_ENABLE": "DISABLED", + "CLKOS_FPHASE": "00000000000000000000000000000000", + "CLKOS_TRIM_DELAY": "00000000000000000000000000000000", + "CLKOS_TRIM_POL": "RISING", + "DPHASE_SOURCE": "DISABLED", + "FEEDBK_PATH": "CLKOP", + "INTFB_WAKE": "DISABLED", + "INT_LOCK_STICKY": "ENABLED", + "OUTDIVIDER_MUXA": "DIVA", + "OUTDIVIDER_MUXB": "DIVB", + "OUTDIVIDER_MUXC": "DIVC", + "OUTDIVIDER_MUXD": "DIVD", + "PLLRST_ENA": "DISABLED", + "PLL_LOCK_DELAY": "00000000000000000000000011001000", + "PLL_LOCK_MODE": "00000000000000000000000000000000", + "REFIN_RESET": "DISABLED", + "STDBY_ENABLE": "DISABLED", + "SYNC_ENABLE": "DISABLED" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "CLKFB": { + "direction": "input", + "bits": [ 3 ] + }, + "PHASESEL1": { + "direction": "input", + "bits": [ 4 ] + }, + "PHASESEL0": { + "direction": "input", + "bits": [ 5 ] + }, + "PHASEDIR": { + "direction": "input", + "bits": [ 6 ] + }, + "PHASESTEP": { + "direction": "input", + "bits": [ 7 ] + }, + "PHASELOADREG": { + "direction": "input", + "bits": [ 8 ] + }, + "STDBY": { + "direction": "input", + "bits": [ 9 ] + }, + "PLLWAKESYNC": { + "direction": "input", + "bits": [ 10 ] + }, + "RST": { + "direction": "input", + "bits": [ 11 ] + }, + "ENCLKOP": { + "direction": "input", + "bits": [ 12 ] + }, + "ENCLKOS": { + "direction": "input", + "bits": [ 13 ] + }, + "ENCLKOS2": { + "direction": "input", + "bits": [ 14 ] + }, + "ENCLKOS3": { + "direction": "input", + "bits": [ 15 ] + }, + "CLKOP": { + "direction": "output", + "bits": [ 16 ] + }, + "CLKOS": { + "direction": "output", + "bits": [ 17 ] + }, + "CLKOS2": { + "direction": "output", + "bits": [ 18 ] + }, + "CLKOS3": { + "direction": "output", + "bits": [ 19 ] + }, + "LOCK": { + "direction": "output", + "bits": [ 20 ] + }, + "INTLOCK": { + "direction": "output", + "bits": [ 21 ] + }, + "REFCLK": { + "direction": "output", + "bits": [ 22 ] + }, + "CLKINTFB": { + "direction": "output", + "bits": [ 23 ] + } + }, + "cells": { + }, + "netnames": { + "CLKFB": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1375.11-1375.16" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1374.11-1374.15" + } + }, + "CLKINTFB": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1395.12-1395.20" + } + }, + "CLKOP": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1388.12-1388.17" + } + }, + "CLKOS": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1389.12-1389.17" + } + }, + "CLKOS2": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1390.12-1390.18" + } + }, + "CLKOS3": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1391.12-1391.18" + } + }, + "ENCLKOP": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1384.11-1384.18" + } + }, + "ENCLKOS": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1385.11-1385.18" + } + }, + "ENCLKOS2": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1386.11-1386.19" + } + }, + "ENCLKOS3": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1387.11-1387.19" + } + }, + "INTLOCK": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1393.12-1393.19" + } + }, + "LOCK": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1392.12-1392.16" + } + }, + "PHASEDIR": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1378.11-1378.19" + } + }, + "PHASELOADREG": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1380.11-1380.23" + } + }, + "PHASESEL0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1377.11-1377.20" + } + }, + "PHASESEL1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1376.11-1376.20" + } + }, + "PHASESTEP": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1379.11-1379.20" + } + }, + "PLLWAKESYNC": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1382.11-1382.22" + } + }, + "REFCLK": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1394.12-1394.18" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1383.11-1383.14" + } + }, + "STDBY": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1381.11-1381.16" + } + } + } + }, + "EXTREFB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1419.1-1428.10" + }, + "parameter_default_values": { + "REFCK_DCBIAS_EN": "DONTCARE", + "REFCK_PWDNB": "DONTCARE", + "REFCK_RTERM": "DONTCARE" + }, + "ports": { + "REFCLKP": { + "direction": "input", + "bits": [ 2 ] + }, + "REFCLKN": { + "direction": "input", + "bits": [ 3 ] + }, + "REFCLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "REFCLKN": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1426.11-1426.18" + } + }, + "REFCLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1427.12-1427.19" + } + }, + "REFCLKP": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1424.11-1424.18" + } + } + } + }, + "FD1P3AX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SP": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.33-2.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.26-2.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.44-2.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.29-2.31" + } + } + } + }, + "FD1P3AY": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SP": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.33-3.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.26-3.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.44-3.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.29-3.31" + } + } + } + }, + "FD1P3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.33-4.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.26-4.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.22-4.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.44-4.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.29-4.31" + } + } + } + }, + "FD1P3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.22-5.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.33-5.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.26-5.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.44-5.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.29-5.31" + } + } + } + }, + "FD1P3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.22-6.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.33-6.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.26-6.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.44-6.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.29-6.31" + } + } + } + }, + "FD1P3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "CK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.33-7.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.26-7.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.22-7.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.44-7.45" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.29-7.31" + } + } + } + }, + "FD1S3AX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "CK": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.33-8.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.26-8.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.44-8.45" + } + } + } + }, + "FD1S3AY": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "CK": { + "direction": "input", + "bits": [ 3 ] + }, + "Q": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.33-9.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.26-9.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.44-9.45" + } + } + } + }, + "FD1S3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.33-10.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.26-10.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.22-10.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.44-10.45" + } + } + } + }, + "FD1S3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.22-11.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.33-11.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.26-11.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.44-11.45" + } + } + } + }, + "FD1S3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.22-12.24" + } + }, + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.33-12.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.26-12.27" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.44-12.45" + } + } + } + }, + "FD1S3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "CK": { + "direction": "input", + "bits": [ 4 ] + }, + "Q": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "CK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.33-13.35" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.26-13.27" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.22-13.24" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.44-13.45" + } + } + } + }, + "GSR": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:4.1-6.10" + }, + "ports": { + "GSR": { + "direction": "input", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "GSR": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:5.11-5.14" + } + } + } + }, + "IB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.45-2.46" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.59-2.60" + } + } + } + }, + "IBPD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.45-4.46" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.59-4.60" + } + } + } + }, + "IBPU": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.45-3.46" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.59-3.60" + } + } + } + }, + "IDDR71B": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1194.1-1208.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 3 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 4 ] + }, + "RST": { + "direction": "input", + "bits": [ 5 ] + }, + "ALIGNWD": { + "direction": "input", + "bits": [ 6 ] + }, + "Q6": { + "direction": "output", + "bits": [ 7 ] + }, + "Q5": { + "direction": "output", + "bits": [ 8 ] + }, + "Q4": { + "direction": "output", + "bits": [ 9 ] + }, + "Q3": { + "direction": "output", + "bits": [ 10 ] + }, + "Q2": { + "direction": "output", + "bits": [ 11 ] + }, + "Q1": { + "direction": "output", + "bits": [ 12 ] + }, + "Q0": { + "direction": "output", + "bits": [ 13 ] + } + }, + "cells": { + }, + "netnames": { + "ALIGNWD": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1200.11-1200.18" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1196.11-1196.12" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1198.11-1198.15" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1207.12-1207.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1206.12-1206.14" + } + }, + "Q2": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1205.12-1205.14" + } + }, + "Q3": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1204.12-1204.14" + } + }, + "Q4": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1203.12-1203.14" + } + }, + "Q5": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1202.12-1202.14" + } + }, + "Q6": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1201.12-1201.14" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1199.11-1199.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1197.11-1197.15" + } + } + } + }, + "IDDRX1F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1170.1-1177.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 3 ] + }, + "RST": { + "direction": "input", + "bits": [ 4 ] + }, + "Q0": { + "direction": "output", + "bits": [ 5 ] + }, + "Q1": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1172.11-1172.12" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1175.12-1175.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1176.12-1176.14" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1174.11-1174.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1173.11-1173.15" + } + } + } + }, + "IDDRX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1211.1-1229.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 3 ] + }, + "DQSR90": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "RST": { + "direction": "input", + "bits": [ 6 ] + }, + "RDPNTR2": { + "direction": "input", + "bits": [ 7 ] + }, + "RDPNTR1": { + "direction": "input", + "bits": [ 8 ] + }, + "RDPNTR0": { + "direction": "input", + "bits": [ 9 ] + }, + "WRPNTR2": { + "direction": "input", + "bits": [ 10 ] + }, + "WRPNTR1": { + "direction": "input", + "bits": [ 11 ] + }, + "WRPNTR0": { + "direction": "input", + "bits": [ 12 ] + }, + "Q3": { + "direction": "output", + "bits": [ 13 ] + }, + "Q2": { + "direction": "output", + "bits": [ 14 ] + }, + "Q1": { + "direction": "output", + "bits": [ 15 ] + }, + "Q0": { + "direction": "output", + "bits": [ 16 ] + }, + "QWL": { + "direction": "output", + "bits": [ 17 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1216.11-1216.12" + } + }, + "DQSR90": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1215.11-1215.17" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1214.11-1214.15" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1227.12-1227.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1226.12-1226.14" + } + }, + "Q2": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1225.12-1225.14" + } + }, + "Q3": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1224.12-1224.14" + } + }, + "QWL": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1228.12-1228.15" + } + }, + "RDPNTR0": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1220.11-1220.18" + } + }, + "RDPNTR1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1219.11-1219.18" + } + }, + "RDPNTR2": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1218.11-1218.18" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1217.11-1217.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1213.11-1213.15" + } + }, + "WRPNTR0": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1223.11-1223.18" + } + }, + "WRPNTR1": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1222.11-1222.18" + } + }, + "WRPNTR2": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1221.11-1221.18" + } + } + } + }, + "IDDRX2F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1180.1-1191.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D": { + "direction": "input", + "bits": [ 2 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 3 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 4 ] + }, + "RST": { + "direction": "input", + "bits": [ 5 ] + }, + "ALIGNWD": { + "direction": "input", + "bits": [ 6 ] + }, + "Q3": { + "direction": "output", + "bits": [ 7 ] + }, + "Q2": { + "direction": "output", + "bits": [ 8 ] + }, + "Q1": { + "direction": "output", + "bits": [ 9 ] + }, + "Q0": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "ALIGNWD": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1186.11-1186.18" + } + }, + "D": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1182.11-1182.12" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1184.11-1184.15" + } + }, + "Q0": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1190.12-1190.14" + } + }, + "Q1": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1189.12-1189.14" + } + }, + "Q2": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1188.12-1188.14" + } + }, + "Q3": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1187.12-1187.14" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1185.11-1185.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1183.11-1183.15" + } + } + } + }, + "IFS1P3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.27-26.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.23-26.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.47-26.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.34-26.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.30-26.32" + } + } + } + }, + "IFS1P3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.23-27.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.27-27.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.47-27.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.34-27.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.30-27.32" + } + } + } + }, + "IFS1P3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.23-28.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.27-28.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.47-28.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.34-28.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.30-28.32" + } + } + } + }, + "IFS1P3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.27-29.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.23-29.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.47-29.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.34-29.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.30-29.32" + } + } + } + }, + "ILVDS": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "AN": { + "direction": "input", + "bits": [ 3 ] + }, + "Z": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.20-13.21" + } + }, + "AN": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.23-13.25" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.59-13.60" + } + } + } + }, + "INV": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:348.1-350.10" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "Z": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:348.18-348.19" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:348.28-348.29" + } + } + } + }, + "JTAGG": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1431.1-1453.10" + }, + "parameter_default_values": { + "ER1": "ENABLED", + "ER2": "ENABLED" + }, + "ports": { + "TCK": { + "direction": "input", + "bits": [ 2 ] + }, + "TMS": { + "direction": "input", + "bits": [ 3 ] + }, + "TDI": { + "direction": "input", + "bits": [ 4 ] + }, + "JTDO2": { + "direction": "input", + "bits": [ 5 ] + }, + "JTDO1": { + "direction": "input", + "bits": [ 6 ] + }, + "TDO": { + "direction": "output", + "bits": [ 7 ] + }, + "JTDI": { + "direction": "output", + "bits": [ 8 ] + }, + "JTCK": { + "direction": "output", + "bits": [ 9 ] + }, + "JRTI2": { + "direction": "output", + "bits": [ 10 ] + }, + "JRTI1": { + "direction": "output", + "bits": [ 11 ] + }, + "JSHIFT": { + "direction": "output", + "bits": [ 12 ] + }, + "JUPDATE": { + "direction": "output", + "bits": [ 13 ] + }, + "JRSTN": { + "direction": "output", + "bits": [ 14 ] + }, + "JCE2": { + "direction": "output", + "bits": [ 15 ] + }, + "JCE1": { + "direction": "output", + "bits": [ 16 ] + } + }, + "cells": { + }, + "netnames": { + "JCE1": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1452.12-1452.16" + } + }, + "JCE2": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1451.12-1451.16" + } + }, + "JRSTN": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1450.12-1450.17" + } + }, + "JRTI1": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1447.12-1447.17" + } + }, + "JRTI2": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1446.12-1446.17" + } + }, + "JSHIFT": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1448.12-1448.18" + } + }, + "JTCK": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1445.12-1445.16" + } + }, + "JTDI": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1444.12-1444.16" + } + }, + "JTDO1": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1441.11-1441.16" + } + }, + "JTDO2": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1440.11-1440.16" + } + }, + "JUPDATE": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1449.12-1449.19" + } + }, + "TCK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1435.11-1435.14" + } + }, + "TDI": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1439.11-1439.14" + } + }, + "TDO": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1443.12-1443.15" + } + }, + "TMS": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1437.11-1437.14" + } + } + } + }, + "L6MUX21": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "abc9_box_id": "00000000000000000000000000001000", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.1-72.10" + }, + "ports": { + "D0": { + "direction": "input", + "bits": [ 2 ] + }, + "D1": { + "direction": "input", + "bits": [ 3 ] + }, + "SD": { + "direction": "input", + "bits": [ 4 ] + }, + "Z": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.23-65.25" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.27-65.29" + } + }, + "SD": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.31-65.33" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:65.42-65.43" + } + } + } + }, + "LUT2": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.1-242.10" + }, + "parameter_default_values": { + "INIT": "0000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "B": { + "direction": "input", + "bits": [ 3 ] + }, + "Z": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.19-238.20" + } + }, + "B": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.22-238.23" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:238.32-238.33" + } + } + } + }, + "LUT4": { + "attributes": { + "abc9_lut": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.1-16.10" + }, + "parameter_default_values": { + "INIT": "0000000000000000" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "B": { + "direction": "input", + "bits": [ 3 ] + }, + "C": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "Z": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.19-4.20" + } + }, + "B": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.22-4.23" + } + }, + "C": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.25-4.26" + } + }, + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.28-4.29" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:4.38-4.39" + } + } + } + }, + "MULT18X18D": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:216.1-486.10" + }, + "parameter_default_values": { + "CAS_MATCH_REG": "FALSE", + "CLK0_DIV": "ENABLED", + "CLK1_DIV": "ENABLED", + "CLK2_DIV": "ENABLED", + "CLK3_DIV": "ENABLED", + "GSR": "ENABLED", + "HIGHSPEED_CLK": "NONE", + "MULT_BYPASS": "DISABLED", + "REG_INPUTA_CE": "CE0", + "REG_INPUTA_CLK": "NONE", + "REG_INPUTA_RST": "RST0", + "REG_INPUTB_CE": "CE0", + "REG_INPUTB_CLK": "NONE", + "REG_INPUTB_RST": "RST0", + "REG_INPUTC_CE": "CE0", + "REG_INPUTC_CLK": "NONE", + "REG_INPUTC_RST": "RST0", + "REG_OUTPUT_CE": "CE0", + "REG_OUTPUT_CLK": "NONE", + "REG_OUTPUT_RST": "RST0", + "REG_PIPELINE_CE": "CE0", + "REG_PIPELINE_CLK": "NONE", + "REG_PIPELINE_RST": "RST0", + "RESETMODE": "SYNC", + "SOURCEB_MODE": "B_SHIFT" + }, + "ports": { + "A17": { + "direction": "input", + "bits": [ 2 ] + }, + "A16": { + "direction": "input", + "bits": [ 3 ] + }, + "A15": { + "direction": "input", + "bits": [ 4 ] + }, + "A14": { + "direction": "input", + "bits": [ 5 ] + }, + "A13": { + "direction": "input", + "bits": [ 6 ] + }, + "A12": { + "direction": "input", + "bits": [ 7 ] + }, + "A11": { + "direction": "input", + "bits": [ 8 ] + }, + "A10": { + "direction": "input", + "bits": [ 9 ] + }, + "A9": { + "direction": "input", + "bits": [ 10 ] + }, + "A8": { + "direction": "input", + "bits": [ 11 ] + }, + "A7": { + "direction": "input", + "bits": [ 12 ] + }, + "A6": { + "direction": "input", + "bits": [ 13 ] + }, + "A5": { + "direction": "input", + "bits": [ 14 ] + }, + "A4": { + "direction": "input", + "bits": [ 15 ] + }, + "A3": { + "direction": "input", + "bits": [ 16 ] + }, + "A2": { + "direction": "input", + "bits": [ 17 ] + }, + "A1": { + "direction": "input", + "bits": [ 18 ] + }, + "A0": { + "direction": "input", + "bits": [ 19 ] + }, + "B17": { + "direction": "input", + "bits": [ 20 ] + }, + "B16": { + "direction": "input", + "bits": [ 21 ] + }, + "B15": { + "direction": "input", + "bits": [ 22 ] + }, + "B14": { + "direction": "input", + "bits": [ 23 ] + }, + "B13": { + "direction": "input", + "bits": [ 24 ] + }, + "B12": { + "direction": "input", + "bits": [ 25 ] + }, + "B11": { + "direction": "input", + "bits": [ 26 ] + }, + "B10": { + "direction": "input", + "bits": [ 27 ] + }, + "B9": { + "direction": "input", + "bits": [ 28 ] + }, + "B8": { + "direction": "input", + "bits": [ 29 ] + }, + "B7": { + "direction": "input", + "bits": [ 30 ] + }, + "B6": { + "direction": "input", + "bits": [ 31 ] + }, + "B5": { + "direction": "input", + "bits": [ 32 ] + }, + "B4": { + "direction": "input", + "bits": [ 33 ] + }, + "B3": { + "direction": "input", + "bits": [ 34 ] + }, + "B2": { + "direction": "input", + "bits": [ 35 ] + }, + "B1": { + "direction": "input", + "bits": [ 36 ] + }, + "B0": { + "direction": "input", + "bits": [ 37 ] + }, + "C17": { + "direction": "input", + "bits": [ 38 ] + }, + "C16": { + "direction": "input", + "bits": [ 39 ] + }, + "C15": { + "direction": "input", + "bits": [ 40 ] + }, + "C14": { + "direction": "input", + "bits": [ 41 ] + }, + "C13": { + "direction": "input", + "bits": [ 42 ] + }, + "C12": { + "direction": "input", + "bits": [ 43 ] + }, + "C11": { + "direction": "input", + "bits": [ 44 ] + }, + "C10": { + "direction": "input", + "bits": [ 45 ] + }, + "C9": { + "direction": "input", + "bits": [ 46 ] + }, + "C8": { + "direction": "input", + "bits": [ 47 ] + }, + "C7": { + "direction": "input", + "bits": [ 48 ] + }, + "C6": { + "direction": "input", + "bits": [ 49 ] + }, + "C5": { + "direction": "input", + "bits": [ 50 ] + }, + "C4": { + "direction": "input", + "bits": [ 51 ] + }, + "C3": { + "direction": "input", + "bits": [ 52 ] + }, + "C2": { + "direction": "input", + "bits": [ 53 ] + }, + "C1": { + "direction": "input", + "bits": [ 54 ] + }, + "C0": { + "direction": "input", + "bits": [ 55 ] + }, + "SIGNEDA": { + "direction": "input", + "bits": [ 56 ] + }, + "SIGNEDB": { + "direction": "input", + "bits": [ 57 ] + }, + "SOURCEA": { + "direction": "input", + "bits": [ 58 ] + }, + "SOURCEB": { + "direction": "input", + "bits": [ 59 ] + }, + "CLK3": { + "direction": "input", + "bits": [ 60 ] + }, + "CLK2": { + "direction": "input", + "bits": [ 61 ] + }, + "CLK1": { + "direction": "input", + "bits": [ 62 ] + }, + "CLK0": { + "direction": "input", + "bits": [ 63 ] + }, + "CE3": { + "direction": "input", + "bits": [ 64 ] + }, + "CE2": { + "direction": "input", + "bits": [ 65 ] + }, + "CE1": { + "direction": "input", + "bits": [ 66 ] + }, + "CE0": { + "direction": "input", + "bits": [ 67 ] + }, + "RST3": { + "direction": "input", + "bits": [ 68 ] + }, + "RST2": { + "direction": "input", + "bits": [ 69 ] + }, + "RST1": { + "direction": "input", + "bits": [ 70 ] + }, + "RST0": { + "direction": "input", + "bits": [ 71 ] + }, + "SRIA17": { + "direction": "input", + "bits": [ 72 ] + }, + "SRIA16": { + "direction": "input", + "bits": [ 73 ] + }, + "SRIA15": { + "direction": "input", + "bits": [ 74 ] + }, + "SRIA14": { + "direction": "input", + "bits": [ 75 ] + }, + "SRIA13": { + "direction": "input", + "bits": [ 76 ] + }, + "SRIA12": { + "direction": "input", + "bits": [ 77 ] + }, + "SRIA11": { + "direction": "input", + "bits": [ 78 ] + }, + "SRIA10": { + "direction": "input", + "bits": [ 79 ] + }, + "SRIA9": { + "direction": "input", + "bits": [ 80 ] + }, + "SRIA8": { + "direction": "input", + "bits": [ 81 ] + }, + "SRIA7": { + "direction": "input", + "bits": [ 82 ] + }, + "SRIA6": { + "direction": "input", + "bits": [ 83 ] + }, + "SRIA5": { + "direction": "input", + "bits": [ 84 ] + }, + "SRIA4": { + "direction": "input", + "bits": [ 85 ] + }, + "SRIA3": { + "direction": "input", + "bits": [ 86 ] + }, + "SRIA2": { + "direction": "input", + "bits": [ 87 ] + }, + "SRIA1": { + "direction": "input", + "bits": [ 88 ] + }, + "SRIA0": { + "direction": "input", + "bits": [ 89 ] + }, + "SRIB17": { + "direction": "input", + "bits": [ 90 ] + }, + "SRIB16": { + "direction": "input", + "bits": [ 91 ] + }, + "SRIB15": { + "direction": "input", + "bits": [ 92 ] + }, + "SRIB14": { + "direction": "input", + "bits": [ 93 ] + }, + "SRIB13": { + "direction": "input", + "bits": [ 94 ] + }, + "SRIB12": { + "direction": "input", + "bits": [ 95 ] + }, + "SRIB11": { + "direction": "input", + "bits": [ 96 ] + }, + "SRIB10": { + "direction": "input", + "bits": [ 97 ] + }, + "SRIB9": { + "direction": "input", + "bits": [ 98 ] + }, + "SRIB8": { + "direction": "input", + "bits": [ 99 ] + }, + "SRIB7": { + "direction": "input", + "bits": [ 100 ] + }, + "SRIB6": { + "direction": "input", + "bits": [ 101 ] + }, + "SRIB5": { + "direction": "input", + "bits": [ 102 ] + }, + "SRIB4": { + "direction": "input", + "bits": [ 103 ] + }, + "SRIB3": { + "direction": "input", + "bits": [ 104 ] + }, + "SRIB2": { + "direction": "input", + "bits": [ 105 ] + }, + "SRIB1": { + "direction": "input", + "bits": [ 106 ] + }, + "SRIB0": { + "direction": "input", + "bits": [ 107 ] + }, + "SROA17": { + "direction": "output", + "bits": [ 108 ] + }, + "SROA16": { + "direction": "output", + "bits": [ 109 ] + }, + "SROA15": { + "direction": "output", + "bits": [ 110 ] + }, + "SROA14": { + "direction": "output", + "bits": [ 111 ] + }, + "SROA13": { + "direction": "output", + "bits": [ 112 ] + }, + "SROA12": { + "direction": "output", + "bits": [ 113 ] + }, + "SROA11": { + "direction": "output", + "bits": [ 114 ] + }, + "SROA10": { + "direction": "output", + "bits": [ 115 ] + }, + "SROA9": { + "direction": "output", + "bits": [ 116 ] + }, + "SROA8": { + "direction": "output", + "bits": [ 117 ] + }, + "SROA7": { + "direction": "output", + "bits": [ 118 ] + }, + "SROA6": { + "direction": "output", + "bits": [ 119 ] + }, + "SROA5": { + "direction": "output", + "bits": [ 120 ] + }, + "SROA4": { + "direction": "output", + "bits": [ 121 ] + }, + "SROA3": { + "direction": "output", + "bits": [ 122 ] + }, + "SROA2": { + "direction": "output", + "bits": [ 123 ] + }, + "SROA1": { + "direction": "output", + "bits": [ 124 ] + }, + "SROA0": { + "direction": "output", + "bits": [ 125 ] + }, + "SROB17": { + "direction": "output", + "bits": [ 126 ] + }, + "SROB16": { + "direction": "output", + "bits": [ 127 ] + }, + "SROB15": { + "direction": "output", + "bits": [ 128 ] + }, + "SROB14": { + "direction": "output", + "bits": [ 129 ] + }, + "SROB13": { + "direction": "output", + "bits": [ 130 ] + }, + "SROB12": { + "direction": "output", + "bits": [ 131 ] + }, + "SROB11": { + "direction": "output", + "bits": [ 132 ] + }, + "SROB10": { + "direction": "output", + "bits": [ 133 ] + }, + "SROB9": { + "direction": "output", + "bits": [ 134 ] + }, + "SROB8": { + "direction": "output", + "bits": [ 135 ] + }, + "SROB7": { + "direction": "output", + "bits": [ 136 ] + }, + "SROB6": { + "direction": "output", + "bits": [ 137 ] + }, + "SROB5": { + "direction": "output", + "bits": [ 138 ] + }, + "SROB4": { + "direction": "output", + "bits": [ 139 ] + }, + "SROB3": { + "direction": "output", + "bits": [ 140 ] + }, + "SROB2": { + "direction": "output", + "bits": [ 141 ] + }, + "SROB1": { + "direction": "output", + "bits": [ 142 ] + }, + "SROB0": { + "direction": "output", + "bits": [ 143 ] + }, + "ROA17": { + "direction": "output", + "bits": [ 144 ] + }, + "ROA16": { + "direction": "output", + "bits": [ 145 ] + }, + "ROA15": { + "direction": "output", + "bits": [ 146 ] + }, + "ROA14": { + "direction": "output", + "bits": [ 147 ] + }, + "ROA13": { + "direction": "output", + "bits": [ 148 ] + }, + "ROA12": { + "direction": "output", + "bits": [ 149 ] + }, + "ROA11": { + "direction": "output", + "bits": [ 150 ] + }, + "ROA10": { + "direction": "output", + "bits": [ 151 ] + }, + "ROA9": { + "direction": "output", + "bits": [ 152 ] + }, + "ROA8": { + "direction": "output", + "bits": [ 153 ] + }, + "ROA7": { + "direction": "output", + "bits": [ 154 ] + }, + "ROA6": { + "direction": "output", + "bits": [ 155 ] + }, + "ROA5": { + "direction": "output", + "bits": [ 156 ] + }, + "ROA4": { + "direction": "output", + "bits": [ 157 ] + }, + "ROA3": { + "direction": "output", + "bits": [ 158 ] + }, + "ROA2": { + "direction": "output", + "bits": [ 159 ] + }, + "ROA1": { + "direction": "output", + "bits": [ 160 ] + }, + "ROA0": { + "direction": "output", + "bits": [ 161 ] + }, + "ROB17": { + "direction": "output", + "bits": [ 162 ] + }, + "ROB16": { + "direction": "output", + "bits": [ 163 ] + }, + "ROB15": { + "direction": "output", + "bits": [ 164 ] + }, + "ROB14": { + "direction": "output", + "bits": [ 165 ] + }, + "ROB13": { + "direction": "output", + "bits": [ 166 ] + }, + "ROB12": { + "direction": "output", + "bits": [ 167 ] + }, + "ROB11": { + "direction": "output", + "bits": [ 168 ] + }, + "ROB10": { + "direction": "output", + "bits": [ 169 ] + }, + "ROB9": { + "direction": "output", + "bits": [ 170 ] + }, + "ROB8": { + "direction": "output", + "bits": [ 171 ] + }, + "ROB7": { + "direction": "output", + "bits": [ 172 ] + }, + "ROB6": { + "direction": "output", + "bits": [ 173 ] + }, + "ROB5": { + "direction": "output", + "bits": [ 174 ] + }, + "ROB4": { + "direction": "output", + "bits": [ 175 ] + }, + "ROB3": { + "direction": "output", + "bits": [ 176 ] + }, + "ROB2": { + "direction": "output", + "bits": [ 177 ] + }, + "ROB1": { + "direction": "output", + "bits": [ 178 ] + }, + "ROB0": { + "direction": "output", + "bits": [ 179 ] + }, + "ROC17": { + "direction": "output", + "bits": [ 180 ] + }, + "ROC16": { + "direction": "output", + "bits": [ 181 ] + }, + "ROC15": { + "direction": "output", + "bits": [ 182 ] + }, + "ROC14": { + "direction": "output", + "bits": [ 183 ] + }, + "ROC13": { + "direction": "output", + "bits": [ 184 ] + }, + "ROC12": { + "direction": "output", + "bits": [ 185 ] + }, + "ROC11": { + "direction": "output", + "bits": [ 186 ] + }, + "ROC10": { + "direction": "output", + "bits": [ 187 ] + }, + "ROC9": { + "direction": "output", + "bits": [ 188 ] + }, + "ROC8": { + "direction": "output", + "bits": [ 189 ] + }, + "ROC7": { + "direction": "output", + "bits": [ 190 ] + }, + "ROC6": { + "direction": "output", + "bits": [ 191 ] + }, + "ROC5": { + "direction": "output", + "bits": [ 192 ] + }, + "ROC4": { + "direction": "output", + "bits": [ 193 ] + }, + "ROC3": { + "direction": "output", + "bits": [ 194 ] + }, + "ROC2": { + "direction": "output", + "bits": [ 195 ] + }, + "ROC1": { + "direction": "output", + "bits": [ 196 ] + }, + "ROC0": { + "direction": "output", + "bits": [ 197 ] + }, + "P35": { + "direction": "output", + "bits": [ 198 ] + }, + "P34": { + "direction": "output", + "bits": [ 199 ] + }, + "P33": { + "direction": "output", + "bits": [ 200 ] + }, + "P32": { + "direction": "output", + "bits": [ 201 ] + }, + "P31": { + "direction": "output", + "bits": [ 202 ] + }, + "P30": { + "direction": "output", + "bits": [ 203 ] + }, + "P29": { + "direction": "output", + "bits": [ 204 ] + }, + "P28": { + "direction": "output", + "bits": [ 205 ] + }, + "P27": { + "direction": "output", + "bits": [ 206 ] + }, + "P26": { + "direction": "output", + "bits": [ 207 ] + }, + "P25": { + "direction": "output", + "bits": [ 208 ] + }, + "P24": { + "direction": "output", + "bits": [ 209 ] + }, + "P23": { + "direction": "output", + "bits": [ 210 ] + }, + "P22": { + "direction": "output", + "bits": [ 211 ] + }, + "P21": { + "direction": "output", + "bits": [ 212 ] + }, + "P20": { + "direction": "output", + "bits": [ 213 ] + }, + "P19": { + "direction": "output", + "bits": [ 214 ] + }, + "P18": { + "direction": "output", + "bits": [ 215 ] + }, + "P17": { + "direction": "output", + "bits": [ 216 ] + }, + "P16": { + "direction": "output", + "bits": [ 217 ] + }, + "P15": { + "direction": "output", + "bits": [ 218 ] + }, + "P14": { + "direction": "output", + "bits": [ 219 ] + }, + "P13": { + "direction": "output", + "bits": [ 220 ] + }, + "P12": { + "direction": "output", + "bits": [ 221 ] + }, + "P11": { + "direction": "output", + "bits": [ 222 ] + }, + "P10": { + "direction": "output", + "bits": [ 223 ] + }, + "P9": { + "direction": "output", + "bits": [ 224 ] + }, + "P8": { + "direction": "output", + "bits": [ 225 ] + }, + "P7": { + "direction": "output", + "bits": [ 226 ] + }, + "P6": { + "direction": "output", + "bits": [ 227 ] + }, + "P5": { + "direction": "output", + "bits": [ 228 ] + }, + "P4": { + "direction": "output", + "bits": [ 229 ] + }, + "P3": { + "direction": "output", + "bits": [ 230 ] + }, + "P2": { + "direction": "output", + "bits": [ 231 ] + }, + "P1": { + "direction": "output", + "bits": [ 232 ] + }, + "P0": { + "direction": "output", + "bits": [ 233 ] + }, + "SIGNEDP": { + "direction": "output", + "bits": [ 234 ] + } + }, + "cells": { + }, + "netnames": { + "A0": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:270.11-270.13" + } + }, + "A1": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:269.11-269.13" + } + }, + "A10": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:260.11-260.14" + } + }, + "A11": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:259.11-259.14" + } + }, + "A12": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:258.11-258.14" + } + }, + "A13": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:257.11-257.14" + } + }, + "A14": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:256.11-256.14" + } + }, + "A15": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:255.11-255.14" + } + }, + "A16": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:254.11-254.14" + } + }, + "A17": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:253.11-253.14" + } + }, + "A2": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:268.11-268.13" + } + }, + "A3": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:267.11-267.13" + } + }, + "A4": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:266.11-266.13" + } + }, + "A5": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:265.11-265.13" + } + }, + "A6": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:264.11-264.13" + } + }, + "A7": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:263.11-263.13" + } + }, + "A8": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:262.11-262.13" + } + }, + "A9": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:261.11-261.13" + } + }, + "B0": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:288.11-288.13" + } + }, + "B1": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:287.11-287.13" + } + }, + "B10": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:278.11-278.14" + } + }, + "B11": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:277.11-277.14" + } + }, + "B12": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:276.11-276.14" + } + }, + "B13": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:275.11-275.14" + } + }, + "B14": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:274.11-274.14" + } + }, + "B15": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:273.11-273.14" + } + }, + "B16": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:272.11-272.14" + } + }, + "B17": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:271.11-271.14" + } + }, + "B2": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:286.11-286.13" + } + }, + "B3": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:285.11-285.13" + } + }, + "B4": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:284.11-284.13" + } + }, + "B5": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:283.11-283.13" + } + }, + "B6": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:282.11-282.13" + } + }, + "B7": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:281.11-281.13" + } + }, + "B8": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:280.11-280.13" + } + }, + "B9": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:279.11-279.13" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:306.11-306.13" + } + }, + "C1": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:305.11-305.13" + } + }, + "C10": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:296.11-296.14" + } + }, + "C11": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:295.11-295.14" + } + }, + "C12": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:294.11-294.14" + } + }, + "C13": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:293.11-293.14" + } + }, + "C14": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:292.11-292.14" + } + }, + "C15": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:291.11-291.14" + } + }, + "C16": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:290.11-290.14" + } + }, + "C17": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:289.11-289.14" + } + }, + "C2": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:304.11-304.13" + } + }, + "C3": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:303.11-303.13" + } + }, + "C4": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:302.11-302.13" + } + }, + "C5": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:301.11-301.13" + } + }, + "C6": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:300.11-300.13" + } + }, + "C7": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:299.11-299.13" + } + }, + "C8": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:298.11-298.13" + } + }, + "C9": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:297.11-297.13" + } + }, + "CE0": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:318.11-318.14" + } + }, + "CE1": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:317.11-317.14" + } + }, + "CE2": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:316.11-316.14" + } + }, + "CE3": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:315.11-315.14" + } + }, + "CLK0": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:314.11-314.15" + } + }, + "CLK1": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:313.11-313.15" + } + }, + "CLK2": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:312.11-312.15" + } + }, + "CLK3": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:311.11-311.15" + } + }, + "P0": { + "hide_name": 0, + "bits": [ 233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:484.12-484.14" + } + }, + "P1": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:483.12-483.14" + } + }, + "P10": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:474.12-474.15" + } + }, + "P11": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:473.12-473.15" + } + }, + "P12": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:472.12-472.15" + } + }, + "P13": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:471.12-471.15" + } + }, + "P14": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:470.12-470.15" + } + }, + "P15": { + "hide_name": 0, + "bits": [ 218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:469.12-469.15" + } + }, + "P16": { + "hide_name": 0, + "bits": [ 217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:468.12-468.15" + } + }, + "P17": { + "hide_name": 0, + "bits": [ 216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:467.12-467.15" + } + }, + "P18": { + "hide_name": 0, + "bits": [ 215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:466.12-466.15" + } + }, + "P19": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:465.12-465.15" + } + }, + "P2": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:482.12-482.14" + } + }, + "P20": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:464.12-464.15" + } + }, + "P21": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:463.12-463.15" + } + }, + "P22": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:462.12-462.15" + } + }, + "P23": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:461.12-461.15" + } + }, + "P24": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:460.12-460.15" + } + }, + "P25": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:459.12-459.15" + } + }, + "P26": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:458.12-458.15" + } + }, + "P27": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:457.12-457.15" + } + }, + "P28": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:456.12-456.15" + } + }, + "P29": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:455.12-455.15" + } + }, + "P3": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:481.12-481.14" + } + }, + "P30": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:454.12-454.15" + } + }, + "P31": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:453.12-453.15" + } + }, + "P32": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:452.12-452.15" + } + }, + "P33": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:451.12-451.15" + } + }, + "P34": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:450.12-450.15" + } + }, + "P35": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:449.12-449.15" + } + }, + "P4": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:480.12-480.14" + } + }, + "P5": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:479.12-479.14" + } + }, + "P6": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:478.12-478.14" + } + }, + "P7": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:477.12-477.14" + } + }, + "P8": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:476.12-476.14" + } + }, + "P9": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:475.12-475.14" + } + }, + "ROA0": { + "hide_name": 0, + "bits": [ 161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:412.12-412.16" + } + }, + "ROA1": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:411.12-411.16" + } + }, + "ROA10": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:402.12-402.17" + } + }, + "ROA11": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:401.12-401.17" + } + }, + "ROA12": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:400.12-400.17" + } + }, + "ROA13": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:399.12-399.17" + } + }, + "ROA14": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:398.12-398.17" + } + }, + "ROA15": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:397.12-397.17" + } + }, + "ROA16": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:396.12-396.17" + } + }, + "ROA17": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:395.12-395.17" + } + }, + "ROA2": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:410.12-410.16" + } + }, + "ROA3": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:409.12-409.16" + } + }, + "ROA4": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:408.12-408.16" + } + }, + "ROA5": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:407.12-407.16" + } + }, + "ROA6": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:406.12-406.16" + } + }, + "ROA7": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:405.12-405.16" + } + }, + "ROA8": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:404.12-404.16" + } + }, + "ROA9": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:403.12-403.16" + } + }, + "ROB0": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:430.12-430.16" + } + }, + "ROB1": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:429.12-429.16" + } + }, + "ROB10": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:420.12-420.17" + } + }, + "ROB11": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:419.12-419.17" + } + }, + "ROB12": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:418.12-418.17" + } + }, + "ROB13": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:417.12-417.17" + } + }, + "ROB14": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:416.12-416.17" + } + }, + "ROB15": { + "hide_name": 0, + "bits": [ 164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:415.12-415.17" + } + }, + "ROB16": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:414.12-414.17" + } + }, + "ROB17": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:413.12-413.17" + } + }, + "ROB2": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:428.12-428.16" + } + }, + "ROB3": { + "hide_name": 0, + "bits": [ 176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:427.12-427.16" + } + }, + "ROB4": { + "hide_name": 0, + "bits": [ 175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:426.12-426.16" + } + }, + "ROB5": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:425.12-425.16" + } + }, + "ROB6": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:424.12-424.16" + } + }, + "ROB7": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:423.12-423.16" + } + }, + "ROB8": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:422.12-422.16" + } + }, + "ROB9": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:421.12-421.16" + } + }, + "ROC0": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:448.12-448.16" + } + }, + "ROC1": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:447.12-447.16" + } + }, + "ROC10": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:438.12-438.17" + } + }, + "ROC11": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:437.12-437.17" + } + }, + "ROC12": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:436.12-436.17" + } + }, + "ROC13": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:435.12-435.17" + } + }, + "ROC14": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:434.12-434.17" + } + }, + "ROC15": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:433.12-433.17" + } + }, + "ROC16": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:432.12-432.17" + } + }, + "ROC17": { + "hide_name": 0, + "bits": [ 180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:431.12-431.17" + } + }, + "ROC2": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:446.12-446.16" + } + }, + "ROC3": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:445.12-445.16" + } + }, + "ROC4": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:444.12-444.16" + } + }, + "ROC5": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:443.12-443.16" + } + }, + "ROC6": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:442.12-442.16" + } + }, + "ROC7": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:441.12-441.16" + } + }, + "ROC8": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:440.12-440.16" + } + }, + "ROC9": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:439.12-439.16" + } + }, + "RST0": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:322.11-322.15" + } + }, + "RST1": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:321.11-321.15" + } + }, + "RST2": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:320.11-320.15" + } + }, + "RST3": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:319.11-319.15" + } + }, + "SIGNEDA": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:307.11-307.18" + } + }, + "SIGNEDB": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:308.11-308.18" + } + }, + "SIGNEDP": { + "hide_name": 0, + "bits": [ 234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:485.12-485.19" + } + }, + "SOURCEA": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:309.11-309.18" + } + }, + "SOURCEB": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:310.11-310.18" + } + }, + "SRIA0": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:340.11-340.16" + } + }, + "SRIA1": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:339.11-339.16" + } + }, + "SRIA10": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:330.11-330.17" + } + }, + "SRIA11": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:329.11-329.17" + } + }, + "SRIA12": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:328.11-328.17" + } + }, + "SRIA13": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:327.11-327.17" + } + }, + "SRIA14": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:326.11-326.17" + } + }, + "SRIA15": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:325.11-325.17" + } + }, + "SRIA16": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:324.11-324.17" + } + }, + "SRIA17": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:323.11-323.17" + } + }, + "SRIA2": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:338.11-338.16" + } + }, + "SRIA3": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:337.11-337.16" + } + }, + "SRIA4": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:336.11-336.16" + } + }, + "SRIA5": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:335.11-335.16" + } + }, + "SRIA6": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:334.11-334.16" + } + }, + "SRIA7": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:333.11-333.16" + } + }, + "SRIA8": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:332.11-332.16" + } + }, + "SRIA9": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:331.11-331.16" + } + }, + "SRIB0": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:358.11-358.16" + } + }, + "SRIB1": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:357.11-357.16" + } + }, + "SRIB10": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:348.11-348.17" + } + }, + "SRIB11": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:347.11-347.17" + } + }, + "SRIB12": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:346.11-346.17" + } + }, + "SRIB13": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:345.11-345.17" + } + }, + "SRIB14": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:344.11-344.17" + } + }, + "SRIB15": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:343.11-343.17" + } + }, + "SRIB16": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:342.11-342.17" + } + }, + "SRIB17": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:341.11-341.17" + } + }, + "SRIB2": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:356.11-356.16" + } + }, + "SRIB3": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:355.11-355.16" + } + }, + "SRIB4": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:354.11-354.16" + } + }, + "SRIB5": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:353.11-353.16" + } + }, + "SRIB6": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:352.11-352.16" + } + }, + "SRIB7": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:351.11-351.16" + } + }, + "SRIB8": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:350.11-350.16" + } + }, + "SRIB9": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:349.11-349.16" + } + }, + "SROA0": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:376.12-376.17" + } + }, + "SROA1": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:375.12-375.17" + } + }, + "SROA10": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:366.12-366.18" + } + }, + "SROA11": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:365.12-365.18" + } + }, + "SROA12": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:364.12-364.18" + } + }, + "SROA13": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:363.12-363.18" + } + }, + "SROA14": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:362.12-362.18" + } + }, + "SROA15": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:361.12-361.18" + } + }, + "SROA16": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:360.12-360.18" + } + }, + "SROA17": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:359.12-359.18" + } + }, + "SROA2": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:374.12-374.17" + } + }, + "SROA3": { + "hide_name": 0, + "bits": [ 122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:373.12-373.17" + } + }, + "SROA4": { + "hide_name": 0, + "bits": [ 121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:372.12-372.17" + } + }, + "SROA5": { + "hide_name": 0, + "bits": [ 120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:371.12-371.17" + } + }, + "SROA6": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:370.12-370.17" + } + }, + "SROA7": { + "hide_name": 0, + "bits": [ 118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:369.12-369.17" + } + }, + "SROA8": { + "hide_name": 0, + "bits": [ 117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:368.12-368.17" + } + }, + "SROA9": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:367.12-367.17" + } + }, + "SROB0": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:394.12-394.17" + } + }, + "SROB1": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:393.12-393.17" + } + }, + "SROB10": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:384.12-384.18" + } + }, + "SROB11": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:383.12-383.18" + } + }, + "SROB12": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:382.12-382.18" + } + }, + "SROB13": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:381.12-381.18" + } + }, + "SROB14": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:380.12-380.18" + } + }, + "SROB15": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:379.12-379.18" + } + }, + "SROB16": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:378.12-378.18" + } + }, + "SROB17": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:377.12-377.18" + } + }, + "SROB2": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:392.12-392.17" + } + }, + "SROB3": { + "hide_name": 0, + "bits": [ 140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:391.12-391.17" + } + }, + "SROB4": { + "hide_name": 0, + "bits": [ 139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:390.12-390.17" + } + }, + "SROB5": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:389.12-389.17" + } + }, + "SROB6": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:388.12-388.17" + } + }, + "SROB7": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:387.12-387.17" + } + }, + "SROB8": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:386.12-386.17" + } + }, + "SROB9": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:385.12-385.17" + } + } + } + }, + "OB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.20-5.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.59-5.60" + } + } + } + }, + "OBCO": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "OT": { + "direction": "output", + "bits": [ 3 ] + }, + "OC": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.20-9.21" + } + }, + "OC": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.38-9.40" + } + }, + "OT": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.34-9.36" + } + } + } + }, + "OBZ": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.20-6.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.59-6.60" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.23-6.24" + } + } + } + }, + "OBZPD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.20-8.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.59-8.60" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.23-8.24" + } + } + } + }, + "OBZPU": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "T": { + "direction": "input", + "bits": [ 3 ] + }, + "O": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "I": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.20-7.21" + } + }, + "O": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.59-7.60" + } + }, + "T": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.23-7.24" + } + } + } + }, + "ODDR71B": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1255.1-1268.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 3 ] + }, + "RST": { + "direction": "input", + "bits": [ 4 ] + }, + "D6": { + "direction": "input", + "bits": [ 5 ] + }, + "D5": { + "direction": "input", + "bits": [ 6 ] + }, + "D4": { + "direction": "input", + "bits": [ 7 ] + }, + "D3": { + "direction": "input", + "bits": [ 8 ] + }, + "D2": { + "direction": "input", + "bits": [ 9 ] + }, + "D1": { + "direction": "input", + "bits": [ 10 ] + }, + "D0": { + "direction": "input", + "bits": [ 11 ] + }, + "Q": { + "direction": "output", + "bits": [ 12 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1266.11-1266.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1265.11-1265.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1264.11-1264.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1263.11-1263.13" + } + }, + "D4": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1262.11-1262.13" + } + }, + "D5": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1261.11-1261.13" + } + }, + "D6": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1260.11-1260.13" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1258.11-1258.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1267.12-1267.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1259.11-1259.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1257.11-1257.15" + } + } + } + }, + "ODDRX1F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1232.1-1239.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "D0": { + "direction": "input", + "bits": [ 4 ] + }, + "D1": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1236.11-1236.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1237.11-1237.13" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1238.12-1238.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1235.11-1235.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1234.11-1234.15" + } + } + } + }, + "ODDRX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1308.1-1319.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D3": { + "direction": "input", + "bits": [ 2 ] + }, + "D2": { + "direction": "input", + "bits": [ 3 ] + }, + "D1": { + "direction": "input", + "bits": [ 4 ] + }, + "D0": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW270": { + "direction": "input", + "bits": [ 6 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 7 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 8 ] + }, + "RST": { + "direction": "input", + "bits": [ 9 ] + }, + "Q": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1313.11-1313.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1312.11-1312.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1311.11-1311.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1310.11-1310.13" + } + }, + "DQSW270": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1314.11-1314.18" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1316.11-1316.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1318.12-1318.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1317.11-1317.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1315.11-1315.15" + } + } + } + }, + "ODDRX2DQSB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1322.1-1333.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D3": { + "direction": "input", + "bits": [ 2 ] + }, + "D2": { + "direction": "input", + "bits": [ 3 ] + }, + "D1": { + "direction": "input", + "bits": [ 4 ] + }, + "D0": { + "direction": "input", + "bits": [ 5 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 6 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 7 ] + }, + "DQSW": { + "direction": "input", + "bits": [ 8 ] + }, + "RST": { + "direction": "input", + "bits": [ 9 ] + }, + "Q": { + "direction": "output", + "bits": [ 10 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1327.11-1327.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1326.11-1326.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1325.11-1325.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1324.11-1324.13" + } + }, + "DQSW": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1330.11-1330.15" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1329.11-1329.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1332.12-1332.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1331.11-1331.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1328.11-1328.15" + } + } + } + }, + "ODDRX2F": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1242.1-1252.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "SCLK": { + "direction": "input", + "bits": [ 2 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 3 ] + }, + "RST": { + "direction": "input", + "bits": [ 4 ] + }, + "D3": { + "direction": "input", + "bits": [ 5 ] + }, + "D2": { + "direction": "input", + "bits": [ 6 ] + }, + "D1": { + "direction": "input", + "bits": [ 7 ] + }, + "D0": { + "direction": "input", + "bits": [ 8 ] + }, + "Q": { + "direction": "output", + "bits": [ 9 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1250.11-1250.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1249.11-1249.13" + } + }, + "D2": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1248.11-1248.13" + } + }, + "D3": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1247.11-1247.13" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1245.11-1245.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1251.12-1251.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1246.11-1246.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1244.11-1244.15" + } + } + } + }, + "OFS1P3BX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.27-31.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.23-31.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.47-31.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.34-31.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.30-31.32" + } + } + } + }, + "OFS1P3DX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.23-32.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.27-32.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.47-32.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.34-32.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.30-32.32" + } + } + } + }, + "OFS1P3IX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "CD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "CD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.23-33.25" + } + }, + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.27-33.28" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.47-33.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.34-33.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.30-33.32" + } + } + } + }, + "OFS1P3JX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "PD": { + "direction": "input", + "bits": [ 2 ] + }, + "D": { + "direction": "input", + "bits": [ 3 ] + }, + "SP": { + "direction": "input", + "bits": [ 4 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 5 ] + }, + "Q": { + "direction": "output", + "bits": [ 6 ] + } + }, + "cells": { + }, + "netnames": { + "D": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.27-34.28" + } + }, + "PD": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.23-34.25" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.47-34.48" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.34-34.38" + } + }, + "SP": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.30-34.32" + } + } + } + }, + "OLVDS": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "Z": { + "direction": "output", + "bits": [ 3 ] + }, + "ZN": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.20-14.21" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.59-14.60" + } + }, + "ZN": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.69-14.71" + } + } + } + }, + "OSCG": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1413.1-1416.10" + }, + "parameter_default_values": { + "DIV": "00000000000000000000000010000000" + }, + "ports": { + "OSC": { + "direction": "output", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "OSC": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1415.12-1415.15" + } + } + } + }, + "OSHX2A": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1271.1-1279.10" + }, + "parameter_default_values": { + "GSR": "ENABLED" + }, + "ports": { + "D1": { + "direction": "input", + "bits": [ 2 ] + }, + "D0": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "RST": { + "direction": "input", + "bits": [ 6 ] + }, + "Q": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "D0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1274.11-1274.13" + } + }, + "D1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1273.11-1273.13" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1276.11-1276.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1278.12-1278.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1277.11-1277.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1275.11-1275.15" + } + } + } + }, + "PCSCLKDIV": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1020.1-1029.10" + }, + "parameter_default_values": { + "GSR": "DISABLED" + }, + "ports": { + "CLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "RST": { + "direction": "input", + "bits": [ 3 ] + }, + "SEL2": { + "direction": "input", + "bits": [ 4 ] + }, + "SEL1": { + "direction": "input", + "bits": [ 5 ] + }, + "SEL0": { + "direction": "input", + "bits": [ 6 ] + }, + "CDIV1": { + "direction": "output", + "bits": [ 7 ] + }, + "CDIVX": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "CDIV1": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1027.12-1027.17" + } + }, + "CDIVX": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1028.12-1028.17" + } + }, + "CLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1022.11-1022.15" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1023.11-1023.14" + } + }, + "SEL0": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1026.11-1026.15" + } + }, + "SEL1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1025.11-1025.15" + } + }, + "SEL2": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1024.11-1024.15" + } + } + } + }, + "PDPW16KD": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:21.1-213.10" + }, + "parameter_default_values": { + "ASYNC_RESET_RELEASE": "SYNC", + "CLKRMUX": "CLKR", + "CLKWMUX": "CLKW", + "CSDECODE_R": "0b000", + "CSDECODE_W": "0b000", + "DATA_WIDTH_R": "00000000000000000000000000100100", + "DATA_WIDTH_W": "00000000000000000000000000100100", + "GSR": "ENABLED", + "INITVAL_00": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_01": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_02": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_03": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_04": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_05": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_06": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_07": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_08": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_09": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_0F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_10": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_11": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_12": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_13": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_14": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_15": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_16": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_17": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_18": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_19": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_1F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_20": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_21": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_22": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_23": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_24": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_25": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_26": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_27": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_28": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_29": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_2F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_30": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_31": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_32": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_33": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_34": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_35": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_36": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_37": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_38": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_39": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3A": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3B": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3C": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3D": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3E": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INITVAL_3F": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "INIT_DATA": "STATIC", + "REGMODE": "NOREG", + "RESETMODE": "SYNC" + }, + "ports": { + "DI35": { + "direction": "input", + "bits": [ 2 ] + }, + "DI34": { + "direction": "input", + "bits": [ 3 ] + }, + "DI33": { + "direction": "input", + "bits": [ 4 ] + }, + "DI32": { + "direction": "input", + "bits": [ 5 ] + }, + "DI31": { + "direction": "input", + "bits": [ 6 ] + }, + "DI30": { + "direction": "input", + "bits": [ 7 ] + }, + "DI29": { + "direction": "input", + "bits": [ 8 ] + }, + "DI28": { + "direction": "input", + "bits": [ 9 ] + }, + "DI27": { + "direction": "input", + "bits": [ 10 ] + }, + "DI26": { + "direction": "input", + "bits": [ 11 ] + }, + "DI25": { + "direction": "input", + "bits": [ 12 ] + }, + "DI24": { + "direction": "input", + "bits": [ 13 ] + }, + "DI23": { + "direction": "input", + "bits": [ 14 ] + }, + "DI22": { + "direction": "input", + "bits": [ 15 ] + }, + "DI21": { + "direction": "input", + "bits": [ 16 ] + }, + "DI20": { + "direction": "input", + "bits": [ 17 ] + }, + "DI19": { + "direction": "input", + "bits": [ 18 ] + }, + "DI18": { + "direction": "input", + "bits": [ 19 ] + }, + "DI17": { + "direction": "input", + "bits": [ 20 ] + }, + "DI16": { + "direction": "input", + "bits": [ 21 ] + }, + "DI15": { + "direction": "input", + "bits": [ 22 ] + }, + "DI14": { + "direction": "input", + "bits": [ 23 ] + }, + "DI13": { + "direction": "input", + "bits": [ 24 ] + }, + "DI12": { + "direction": "input", + "bits": [ 25 ] + }, + "DI11": { + "direction": "input", + "bits": [ 26 ] + }, + "DI10": { + "direction": "input", + "bits": [ 27 ] + }, + "DI9": { + "direction": "input", + "bits": [ 28 ] + }, + "DI8": { + "direction": "input", + "bits": [ 29 ] + }, + "DI7": { + "direction": "input", + "bits": [ 30 ] + }, + "DI6": { + "direction": "input", + "bits": [ 31 ] + }, + "DI5": { + "direction": "input", + "bits": [ 32 ] + }, + "DI4": { + "direction": "input", + "bits": [ 33 ] + }, + "DI3": { + "direction": "input", + "bits": [ 34 ] + }, + "DI2": { + "direction": "input", + "bits": [ 35 ] + }, + "DI1": { + "direction": "input", + "bits": [ 36 ] + }, + "DI0": { + "direction": "input", + "bits": [ 37 ] + }, + "ADW8": { + "direction": "input", + "bits": [ 38 ] + }, + "ADW7": { + "direction": "input", + "bits": [ 39 ] + }, + "ADW6": { + "direction": "input", + "bits": [ 40 ] + }, + "ADW5": { + "direction": "input", + "bits": [ 41 ] + }, + "ADW4": { + "direction": "input", + "bits": [ 42 ] + }, + "ADW3": { + "direction": "input", + "bits": [ 43 ] + }, + "ADW2": { + "direction": "input", + "bits": [ 44 ] + }, + "ADW1": { + "direction": "input", + "bits": [ 45 ] + }, + "ADW0": { + "direction": "input", + "bits": [ 46 ] + }, + "BE3": { + "direction": "input", + "bits": [ 47 ] + }, + "BE2": { + "direction": "input", + "bits": [ 48 ] + }, + "BE1": { + "direction": "input", + "bits": [ 49 ] + }, + "BE0": { + "direction": "input", + "bits": [ 50 ] + }, + "CEW": { + "direction": "input", + "bits": [ 51 ] + }, + "CLKW": { + "direction": "input", + "bits": [ 52 ] + }, + "CSW2": { + "direction": "input", + "bits": [ 53 ] + }, + "CSW1": { + "direction": "input", + "bits": [ 54 ] + }, + "CSW0": { + "direction": "input", + "bits": [ 55 ] + }, + "ADR13": { + "direction": "input", + "bits": [ 56 ] + }, + "ADR12": { + "direction": "input", + "bits": [ 57 ] + }, + "ADR11": { + "direction": "input", + "bits": [ 58 ] + }, + "ADR10": { + "direction": "input", + "bits": [ 59 ] + }, + "ADR9": { + "direction": "input", + "bits": [ 60 ] + }, + "ADR8": { + "direction": "input", + "bits": [ 61 ] + }, + "ADR7": { + "direction": "input", + "bits": [ 62 ] + }, + "ADR6": { + "direction": "input", + "bits": [ 63 ] + }, + "ADR5": { + "direction": "input", + "bits": [ 64 ] + }, + "ADR4": { + "direction": "input", + "bits": [ 65 ] + }, + "ADR3": { + "direction": "input", + "bits": [ 66 ] + }, + "ADR2": { + "direction": "input", + "bits": [ 67 ] + }, + "ADR1": { + "direction": "input", + "bits": [ 68 ] + }, + "ADR0": { + "direction": "input", + "bits": [ 69 ] + }, + "CER": { + "direction": "input", + "bits": [ 70 ] + }, + "OCER": { + "direction": "input", + "bits": [ 71 ] + }, + "CLKR": { + "direction": "input", + "bits": [ 72 ] + }, + "CSR2": { + "direction": "input", + "bits": [ 73 ] + }, + "CSR1": { + "direction": "input", + "bits": [ 74 ] + }, + "CSR0": { + "direction": "input", + "bits": [ 75 ] + }, + "RST": { + "direction": "input", + "bits": [ 76 ] + }, + "DO35": { + "direction": "output", + "bits": [ 77 ] + }, + "DO34": { + "direction": "output", + "bits": [ 78 ] + }, + "DO33": { + "direction": "output", + "bits": [ 79 ] + }, + "DO32": { + "direction": "output", + "bits": [ 80 ] + }, + "DO31": { + "direction": "output", + "bits": [ 81 ] + }, + "DO30": { + "direction": "output", + "bits": [ 82 ] + }, + "DO29": { + "direction": "output", + "bits": [ 83 ] + }, + "DO28": { + "direction": "output", + "bits": [ 84 ] + }, + "DO27": { + "direction": "output", + "bits": [ 85 ] + }, + "DO26": { + "direction": "output", + "bits": [ 86 ] + }, + "DO25": { + "direction": "output", + "bits": [ 87 ] + }, + "DO24": { + "direction": "output", + "bits": [ 88 ] + }, + "DO23": { + "direction": "output", + "bits": [ 89 ] + }, + "DO22": { + "direction": "output", + "bits": [ 90 ] + }, + "DO21": { + "direction": "output", + "bits": [ 91 ] + }, + "DO20": { + "direction": "output", + "bits": [ 92 ] + }, + "DO19": { + "direction": "output", + "bits": [ 93 ] + }, + "DO18": { + "direction": "output", + "bits": [ 94 ] + }, + "DO17": { + "direction": "output", + "bits": [ 95 ] + }, + "DO16": { + "direction": "output", + "bits": [ 96 ] + }, + "DO15": { + "direction": "output", + "bits": [ 97 ] + }, + "DO14": { + "direction": "output", + "bits": [ 98 ] + }, + "DO13": { + "direction": "output", + "bits": [ 99 ] + }, + "DO12": { + "direction": "output", + "bits": [ 100 ] + }, + "DO11": { + "direction": "output", + "bits": [ 101 ] + }, + "DO10": { + "direction": "output", + "bits": [ 102 ] + }, + "DO9": { + "direction": "output", + "bits": [ 103 ] + }, + "DO8": { + "direction": "output", + "bits": [ 104 ] + }, + "DO7": { + "direction": "output", + "bits": [ 105 ] + }, + "DO6": { + "direction": "output", + "bits": [ 106 ] + }, + "DO5": { + "direction": "output", + "bits": [ 107 ] + }, + "DO4": { + "direction": "output", + "bits": [ 108 ] + }, + "DO3": { + "direction": "output", + "bits": [ 109 ] + }, + "DO2": { + "direction": "output", + "bits": [ 110 ] + }, + "DO1": { + "direction": "output", + "bits": [ 111 ] + }, + "DO0": { + "direction": "output", + "bits": [ 112 ] + } + }, + "cells": { + }, + "netnames": { + "ADR0": { + "hide_name": 0, + "bits": [ 69 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:169.11-169.15" + } + }, + "ADR1": { + "hide_name": 0, + "bits": [ 68 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:168.11-168.15" + } + }, + "ADR10": { + "hide_name": 0, + "bits": [ 59 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:159.11-159.16" + } + }, + "ADR11": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:158.11-158.16" + } + }, + "ADR12": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:157.11-157.16" + } + }, + "ADR13": { + "hide_name": 0, + "bits": [ 56 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:156.11-156.16" + } + }, + "ADR2": { + "hide_name": 0, + "bits": [ 67 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:167.11-167.15" + } + }, + "ADR3": { + "hide_name": 0, + "bits": [ 66 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:166.11-166.15" + } + }, + "ADR4": { + "hide_name": 0, + "bits": [ 65 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:165.11-165.15" + } + }, + "ADR5": { + "hide_name": 0, + "bits": [ 64 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:164.11-164.15" + } + }, + "ADR6": { + "hide_name": 0, + "bits": [ 63 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:163.11-163.15" + } + }, + "ADR7": { + "hide_name": 0, + "bits": [ 62 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:162.11-162.15" + } + }, + "ADR8": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:161.11-161.15" + } + }, + "ADR9": { + "hide_name": 0, + "bits": [ 60 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:160.11-160.15" + } + }, + "ADW0": { + "hide_name": 0, + "bits": [ 46 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:146.11-146.15" + } + }, + "ADW1": { + "hide_name": 0, + "bits": [ 45 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:145.11-145.15" + } + }, + "ADW2": { + "hide_name": 0, + "bits": [ 44 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:144.11-144.15" + } + }, + "ADW3": { + "hide_name": 0, + "bits": [ 43 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:143.11-143.15" + } + }, + "ADW4": { + "hide_name": 0, + "bits": [ 42 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:142.11-142.15" + } + }, + "ADW5": { + "hide_name": 0, + "bits": [ 41 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:141.11-141.15" + } + }, + "ADW6": { + "hide_name": 0, + "bits": [ 40 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:140.11-140.15" + } + }, + "ADW7": { + "hide_name": 0, + "bits": [ 39 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:139.11-139.15" + } + }, + "ADW8": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:138.11-138.15" + } + }, + "BE0": { + "hide_name": 0, + "bits": [ 50 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:150.11-150.14" + } + }, + "BE1": { + "hide_name": 0, + "bits": [ 49 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:149.11-149.14" + } + }, + "BE2": { + "hide_name": 0, + "bits": [ 48 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:148.11-148.14" + } + }, + "BE3": { + "hide_name": 0, + "bits": [ 47 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:147.11-147.14" + } + }, + "CER": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:170.11-170.14" + } + }, + "CEW": { + "hide_name": 0, + "bits": [ 51 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:151.11-151.14" + } + }, + "CLKR": { + "hide_name": 0, + "bits": [ 72 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:172.11-172.15" + } + }, + "CLKW": { + "hide_name": 0, + "bits": [ 52 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:152.11-152.15" + } + }, + "CSR0": { + "hide_name": 0, + "bits": [ 75 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:175.11-175.15" + } + }, + "CSR1": { + "hide_name": 0, + "bits": [ 74 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:174.11-174.15" + } + }, + "CSR2": { + "hide_name": 0, + "bits": [ 73 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:173.11-173.15" + } + }, + "CSW0": { + "hide_name": 0, + "bits": [ 55 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:155.11-155.15" + } + }, + "CSW1": { + "hide_name": 0, + "bits": [ 54 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:154.11-154.15" + } + }, + "CSW2": { + "hide_name": 0, + "bits": [ 53 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:153.11-153.15" + } + }, + "DI0": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:137.11-137.14" + } + }, + "DI1": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:136.11-136.14" + } + }, + "DI10": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:127.11-127.15" + } + }, + "DI11": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:126.11-126.15" + } + }, + "DI12": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:125.11-125.15" + } + }, + "DI13": { + "hide_name": 0, + "bits": [ 24 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:124.11-124.15" + } + }, + "DI14": { + "hide_name": 0, + "bits": [ 23 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:123.11-123.15" + } + }, + "DI15": { + "hide_name": 0, + "bits": [ 22 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:122.11-122.15" + } + }, + "DI16": { + "hide_name": 0, + "bits": [ 21 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:121.11-121.15" + } + }, + "DI17": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:120.11-120.15" + } + }, + "DI18": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:119.11-119.15" + } + }, + "DI19": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:118.11-118.15" + } + }, + "DI2": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:135.11-135.14" + } + }, + "DI20": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:117.11-117.15" + } + }, + "DI21": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:116.11-116.15" + } + }, + "DI22": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:115.11-115.15" + } + }, + "DI23": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:114.11-114.15" + } + }, + "DI24": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:113.11-113.15" + } + }, + "DI25": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:112.11-112.15" + } + }, + "DI26": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:111.11-111.15" + } + }, + "DI27": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:110.11-110.15" + } + }, + "DI28": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:109.11-109.15" + } + }, + "DI29": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:108.11-108.15" + } + }, + "DI3": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:134.11-134.14" + } + }, + "DI30": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:107.11-107.15" + } + }, + "DI31": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:106.11-106.15" + } + }, + "DI32": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:105.11-105.15" + } + }, + "DI33": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:104.11-104.15" + } + }, + "DI34": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:103.11-103.15" + } + }, + "DI35": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:102.11-102.15" + } + }, + "DI4": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:133.11-133.14" + } + }, + "DI5": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:132.11-132.14" + } + }, + "DI6": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:131.11-131.14" + } + }, + "DI7": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:130.11-130.14" + } + }, + "DI8": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:129.11-129.14" + } + }, + "DI9": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:128.11-128.14" + } + }, + "DO0": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:212.12-212.15" + } + }, + "DO1": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:211.12-211.15" + } + }, + "DO10": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:202.12-202.16" + } + }, + "DO11": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:201.12-201.16" + } + }, + "DO12": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:200.12-200.16" + } + }, + "DO13": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:199.12-199.16" + } + }, + "DO14": { + "hide_name": 0, + "bits": [ 98 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:198.12-198.16" + } + }, + "DO15": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:197.12-197.16" + } + }, + "DO16": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:196.12-196.16" + } + }, + "DO17": { + "hide_name": 0, + "bits": [ 95 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:195.12-195.16" + } + }, + "DO18": { + "hide_name": 0, + "bits": [ 94 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:194.12-194.16" + } + }, + "DO19": { + "hide_name": 0, + "bits": [ 93 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:193.12-193.16" + } + }, + "DO2": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:210.12-210.15" + } + }, + "DO20": { + "hide_name": 0, + "bits": [ 92 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:192.12-192.16" + } + }, + "DO21": { + "hide_name": 0, + "bits": [ 91 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:191.12-191.16" + } + }, + "DO22": { + "hide_name": 0, + "bits": [ 90 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:190.12-190.16" + } + }, + "DO23": { + "hide_name": 0, + "bits": [ 89 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:189.12-189.16" + } + }, + "DO24": { + "hide_name": 0, + "bits": [ 88 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:188.12-188.16" + } + }, + "DO25": { + "hide_name": 0, + "bits": [ 87 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:187.12-187.16" + } + }, + "DO26": { + "hide_name": 0, + "bits": [ 86 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:186.12-186.16" + } + }, + "DO27": { + "hide_name": 0, + "bits": [ 85 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:185.12-185.16" + } + }, + "DO28": { + "hide_name": 0, + "bits": [ 84 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:184.12-184.16" + } + }, + "DO29": { + "hide_name": 0, + "bits": [ 83 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:183.12-183.16" + } + }, + "DO3": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:209.12-209.15" + } + }, + "DO30": { + "hide_name": 0, + "bits": [ 82 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:182.12-182.16" + } + }, + "DO31": { + "hide_name": 0, + "bits": [ 81 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:181.12-181.16" + } + }, + "DO32": { + "hide_name": 0, + "bits": [ 80 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:180.12-180.16" + } + }, + "DO33": { + "hide_name": 0, + "bits": [ 79 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:179.12-179.16" + } + }, + "DO34": { + "hide_name": 0, + "bits": [ 78 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:178.12-178.16" + } + }, + "DO35": { + "hide_name": 0, + "bits": [ 77 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:177.12-177.16" + } + }, + "DO4": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:208.12-208.15" + } + }, + "DO5": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:207.12-207.15" + } + }, + "DO6": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:206.12-206.15" + } + }, + "DO7": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:205.12-205.15" + } + }, + "DO8": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:204.12-204.15" + } + }, + "DO9": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:203.12-203.15" + } + }, + "OCER": { + "hide_name": 0, + "bits": [ 71 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:171.11-171.15" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 76 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:176.11-176.14" + } + } + } + }, + "PFUMX": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "abc9_box_id": "00000000000000000000000000000111", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.1-124.10" + }, + "ports": { + "ALUT": { + "direction": "input", + "bits": [ 2 ] + }, + "BLUT": { + "direction": "input", + "bits": [ 3 ] + }, + "C0": { + "direction": "input", + "bits": [ 4 ] + }, + "Z": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "ALUT": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.21-117.25" + } + }, + "BLUT": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.27-117.31" + } + }, + "C0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.33-117.35" + } + }, + "Z": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:117.44-117.45" + } + } + } + }, + "PUR": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:9.1-12.10" + }, + "parameter_default_values": { + "RST_PULSE": "00000000000000000000000000000001" + }, + "ports": { + "PUR": { + "direction": "input", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "PUR": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:11.11-11.14" + } + } + } + }, + "SGSR": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:15.1-18.10" + }, + "ports": { + "GSR": { + "direction": "input", + "bits": [ 2 ] + }, + "CLK": { + "direction": "input", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "CLK": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:17.11-17.14" + } + }, + "GSR": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:16.11-16.14" + } + } + } + }, + "TRELLIS_COMB": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:354.1-395.10" + }, + "parameter_default_values": { + "CCU2_INJECT1": "NO", + "INITVAL": "0000000000000000", + "IS_Z1": "0", + "MODE": "LOGIC", + "WREMUX": "WRE" + }, + "ports": { + "A": { + "direction": "input", + "bits": [ 2 ] + }, + "B": { + "direction": "input", + "bits": [ 3 ] + }, + "C": { + "direction": "input", + "bits": [ 4 ] + }, + "D": { + "direction": "input", + "bits": [ 5 ] + }, + "M": { + "direction": "input", + "bits": [ 6 ] + }, + "FCI": { + "direction": "input", + "bits": [ 7 ] + }, + "F1": { + "direction": "input", + "bits": [ 8 ] + }, + "FXA": { + "direction": "input", + "bits": [ 9 ] + }, + "FXB": { + "direction": "input", + "bits": [ 10 ] + }, + "WD": { + "direction": "input", + "bits": [ 11 ] + }, + "WAD0": { + "direction": "input", + "bits": [ 12 ] + }, + "WAD1": { + "direction": "input", + "bits": [ 13 ] + }, + "WAD2": { + "direction": "input", + "bits": [ 14 ] + }, + "WAD3": { + "direction": "input", + "bits": [ 15 ] + }, + "WRE": { + "direction": "input", + "bits": [ 16 ] + }, + "WCK": { + "direction": "input", + "bits": [ 17 ] + }, + "F": { + "direction": "output", + "bits": [ 18 ] + }, + "FCO": { + "direction": "output", + "bits": [ 19 ] + }, + "OFX": { + "direction": "output", + "bits": [ 20 ] + } + }, + "cells": { + }, + "netnames": { + "A": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.8-355.9" + } + }, + "B": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.11-355.12" + } + }, + "C": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.14-355.15" + } + }, + "D": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.17-355.18" + } + }, + "F": { + "hide_name": 0, + "bits": [ 18 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:360.9-360.10" + } + }, + "F1": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.13-356.15" + } + }, + "FCI": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.8-356.11" + } + }, + "FCO": { + "hide_name": 0, + "bits": [ 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:360.12-360.15" + } + }, + "FXA": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.17-356.20" + } + }, + "FXB": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:356.22-356.25" + } + }, + "M": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:355.20-355.21" + } + }, + "OFX": { + "hide_name": 0, + "bits": [ 20 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:360.17-360.20" + } + }, + "WAD0": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.8-358.12" + } + }, + "WAD1": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.14-358.18" + } + }, + "WAD2": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.20-358.24" + } + }, + "WAD3": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:358.26-358.30" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 17 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:359.13-359.16" + } + }, + "WD": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:357.8-357.10" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 16 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:359.8-359.11" + } + } + } + }, + "TRELLIS_DPR16X4": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000110", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:128.1-169.10" + }, + "parameter_default_values": { + "INITVAL": "0000000000000000000000000000000000000000000000000000000000000000", + "WCKMUX": "WCK", + "WREMUX": "WRE" + }, + "ports": { + "DI": { + "direction": "input", + "bits": [ 2, 3, 4, 5 ] + }, + "WAD": { + "direction": "input", + "bits": [ 6, 7, 8, 9 ] + }, + "WRE": { + "direction": "input", + "bits": [ 10 ] + }, + "WCK": { + "direction": "input", + "bits": [ 11 ] + }, + "RAD": { + "direction": "input", + "bits": [ 12, 13, 14, 15 ] + }, + "DO": { + "direction": "output", + "bits": [ 16, 17, 18, 19 ] + } + }, + "cells": { + }, + "netnames": { + "DI": { + "hide_name": 0, + "bits": [ 2, 3, 4, 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:129.15-129.17" + } + }, + "DO": { + "hide_name": 0, + "bits": [ 16, 17, 18, 19 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:134.15-134.17" + } + }, + "RAD": { + "hide_name": 0, + "bits": [ 12, 13, 14, 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:133.15-133.18" + } + }, + "WAD": { + "hide_name": 0, + "bits": [ 6, 7, 8, 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:130.15-130.18" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:132.15-132.18" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:131.15-131.18" + } + } + } + }, + "TRELLIS_FF": { + "attributes": { + "abc9_flop": "1", + "abc9_box": "0", + "blackbox": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.1-314.10" + }, + "parameter_default_values": { + "CEMUX": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110001", + "CLKMUX": "CLK", + "GSR": "ENABLED", + "LSRMODE": "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000101001101010010", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "ports": { + "CLK": { + "direction": "input", + "bits": [ 2 ] + }, + "LSR": { + "direction": "input", + "bits": [ 3 ] + }, + "CE": { + "direction": "input", + "bits": [ 4 ] + }, + "DI": { + "direction": "input", + "bits": [ 5 ] + }, + "M": { + "direction": "input", + "bits": [ 6 ] + }, + "Q": { + "direction": "output", + "bits": [ 7 ] + } + }, + "cells": { + }, + "netnames": { + "CE": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.35-249.37" + } + }, + "CLK": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.25-249.28" + } + }, + "DI": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.39-249.41" + } + }, + "LSR": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.30-249.33" + } + }, + "M": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.43-249.44" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:249.57-249.58" + } + } + } + }, + "TRELLIS_IO": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:318.1-344.10" + }, + "parameter_default_values": { + "DIR": "INPUT" + }, + "ports": { + "B": { + "direction": "inout", + "bits": [ 2 ] + }, + "I": { + "direction": "input", + "bits": [ 3 ] + }, + "T": { + "direction": "input", + "bits": [ 4 ] + }, + "O": { + "direction": "output", + "bits": [ 5 ] + } + }, + "cells": { + }, + "netnames": { + "B": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "iopad_external_pin": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:320.8-320.9" + } + }, + "I": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:321.8-321.9" + } + }, + "O": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:323.9-323.10" + } + }, + "T": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:322.8-322.9" + } + } + } + }, + "TRELLIS_RAM16X2": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:76.1-113.10" + }, + "parameter_default_values": { + "INITVAL_0": "0000000000000000", + "INITVAL_1": "0000000000000000", + "WCKMUX": "WCK", + "WREMUX": "WRE" + }, + "ports": { + "DI0": { + "direction": "input", + "bits": [ 2 ] + }, + "DI1": { + "direction": "input", + "bits": [ 3 ] + }, + "WAD0": { + "direction": "input", + "bits": [ 4 ] + }, + "WAD1": { + "direction": "input", + "bits": [ 5 ] + }, + "WAD2": { + "direction": "input", + "bits": [ 6 ] + }, + "WAD3": { + "direction": "input", + "bits": [ 7 ] + }, + "WRE": { + "direction": "input", + "bits": [ 8 ] + }, + "WCK": { + "direction": "input", + "bits": [ 9 ] + }, + "RAD0": { + "direction": "input", + "bits": [ 10 ] + }, + "RAD1": { + "direction": "input", + "bits": [ 11 ] + }, + "RAD2": { + "direction": "input", + "bits": [ 12 ] + }, + "RAD3": { + "direction": "input", + "bits": [ 13 ] + }, + "DO0": { + "direction": "output", + "bits": [ 14 ] + }, + "DO1": { + "direction": "output", + "bits": [ 15 ] + } + }, + "cells": { + }, + "netnames": { + "DI0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:77.8-77.11" + } + }, + "DI1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:77.13-77.16" + } + }, + "DO0": { + "hide_name": 0, + "bits": [ 14 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:81.9-81.12" + } + }, + "DO1": { + "hide_name": 0, + "bits": [ 15 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:81.14-81.17" + } + }, + "RAD0": { + "hide_name": 0, + "bits": [ 10 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.8-80.12" + } + }, + "RAD1": { + "hide_name": 0, + "bits": [ 11 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.14-80.18" + } + }, + "RAD2": { + "hide_name": 0, + "bits": [ 12 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.20-80.24" + } + }, + "RAD3": { + "hide_name": 0, + "bits": [ 13 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:80.26-80.30" + } + }, + "WAD0": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.8-78.12" + } + }, + "WAD1": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.14-78.18" + } + }, + "WAD2": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.20-78.24" + } + }, + "WAD3": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:78.26-78.30" + } + }, + "WCK": { + "hide_name": 0, + "bits": [ 9 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:79.13-79.16" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:79.8-79.11" + } + } + } + }, + "TSHX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1282.1-1292.10" + }, + "parameter_default_values": { + "GSR": "ENABLED", + "REGSET": "SET" + }, + "ports": { + "T1": { + "direction": "input", + "bits": [ 2 ] + }, + "T0": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW270": { + "direction": "input", + "bits": [ 6 ] + }, + "RST": { + "direction": "input", + "bits": [ 7 ] + }, + "Q": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "DQSW270": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1289.11-1289.18" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1288.11-1288.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1291.12-1291.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1290.11-1290.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1287.11-1287.15" + } + }, + "T0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1286.11-1286.13" + } + }, + "T1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1285.11-1285.13" + } + } + } + }, + "TSHX2DQSA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1295.1-1305.10" + }, + "parameter_default_values": { + "GSR": "ENABLED", + "REGSET": "SET" + }, + "ports": { + "T1": { + "direction": "input", + "bits": [ 2 ] + }, + "T0": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW": { + "direction": "input", + "bits": [ 6 ] + }, + "RST": { + "direction": "input", + "bits": [ 7 ] + }, + "Q": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "DQSW": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1302.11-1302.15" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1301.11-1301.15" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1304.12-1304.13" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1303.11-1303.14" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1300.11-1300.15" + } + }, + "T0": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1299.11-1299.13" + } + }, + "T1": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1298.11-1298.13" + } + } + } + }, + "USRMCLK": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1085.1-1088.10" + }, + "ports": { + "USRMCLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "USRMCLKTS": { + "direction": "input", + "bits": [ 3 ] + } + }, + "cells": { + }, + "netnames": { + "USRMCLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1086.11-1086.19" + } + }, + "USRMCLKTS": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1087.11-1087.20" + } + } + } + }, + "VHI": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:402.1-404.10" + }, + "ports": { + "Z": { + "direction": "output", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "Z": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:402.19-402.20" + } + } + } + }, + "VLO": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:398.1-400.10" + }, + "ports": { + "Z": { + "direction": "output", + "bits": [ 2 ] + } + }, + "cells": { + }, + "netnames": { + "Z": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:398.19-398.20" + } + } + } + }, + "top": { + "attributes": { + "dynports": "00000000000000000000000000000001", + "top": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:1.1-78.10" + }, + "ports": { + "clk": { + "direction": "input", + "bits": [ 2 ] + }, + "rst": { + "direction": "input", + "bits": [ 3 ] + }, + "start": { + "direction": "input", + "bits": [ 4 ] + }, + "y_bus": { + "direction": "output", + "signed": 1, + "bits": [ 5, 5, 5, 6, 7, 8, 9, "0", 10, 11, 12, 13, 14, 15, 16, "0", 17, 17, 17, 18, 19, 20, 21, "0", 22, 22, 22, 22, 22, 23, 24, "0" ] + }, + "busy": { + "direction": "output", + "bits": [ 25 ] + }, + "done": { + "direction": "output", + "bits": [ 26 ] + } + }, + "cells": { + "busy_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 27 ], + "B": [ 28 ], + "C": [ 29 ], + "D": [ 30 ], + "Z": [ 25 ] + } + }, + "done_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 31 ], + "B": [ 32 ], + "C": [ 33 ], + "D": [ 34 ], + "Z": [ 26 ] + } + }, + "start_LUT4_B": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 29 ], + "Z": [ 35 ] + } + }, + "start_LUT4_B_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 27 ], + "Z": [ 36 ] + } + }, + "start_LUT4_B_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 30 ], + "Z": [ 37 ] + } + }, + "u_layer": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:66.7-76.6", + "module": "$paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\\layer", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "layer", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:1.1-81.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron", + "module": "$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 38 ], + "LSR": [ 37 ], + "Q": [ 39 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 40 ], + "LSR": [ 37 ], + "Q": [ 41 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 42 ], + "LSR": [ 37 ], + "Q": [ 43 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 44 ], + "LSR": [ 37 ], + "Q": [ 45 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 46 ], + "LSR": [ 37 ], + "Q": [ 47 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 48 ], + "LSR": [ 37 ], + "Q": [ 49 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 50 ], + "LSR": [ 37 ], + "Q": [ 51 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 52 ], + "LSR": [ 37 ], + "Q": [ 53 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 54 ], + "LSR": [ 37 ], + "Q": [ 55 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 56 ], + "LSR": [ 37 ], + "Q": [ 57 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 58 ], + "LSR": [ 37 ], + "Q": [ 59 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 60 ], + "LSR": [ 37 ], + "Q": [ 61 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 62 ], + "LSR": [ 37 ], + "Q": [ 63 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 64 ], + "LSR": [ 37 ], + "Q": [ 65 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 66 ], + "LSR": [ 37 ], + "Q": [ 67 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 68 ], + "LSR": [ 37 ], + "Q": [ 69 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 70 ], + "LSR": [ 37 ], + "Q": [ 71 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 72 ], + "LSR": [ 37 ], + "Q": [ 73 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 74 ], + "LSR": [ 37 ], + "Q": [ 75 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 76 ], + "LSR": [ 37 ], + "Q": [ 77 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 78 ], + "LSR": [ 37 ], + "Q": [ 79 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 80 ], + "LSR": [ 37 ], + "Q": [ 81 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 82 ], + "LSR": [ 37 ], + "Q": [ 83 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 84 ], + "LSR": [ 37 ], + "Q": [ 85 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 86 ], + "LSR": [ 37 ], + "Q": [ 87 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 88 ], + "LSR": [ 37 ], + "Q": [ 89 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 90 ], + "LSR": [ 37 ], + "Q": [ 91 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 92 ], + "LSR": [ 37 ], + "Q": [ 93 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 30 ], + "CLK": [ 2 ], + "DI": [ 94 ], + "LSR": [ 37 ], + "Q": [ 95 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 96 ], + "D1": [ 97 ], + "SD": [ 98 ], + "Z": [ 78 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 99 ], + "D1": [ 100 ], + "SD": [ 98 ], + "Z": [ 76 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 101 ], + "BLUT": [ 102 ], + "C0": [ 69 ], + "Z": [ 99 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 77 ], + "Z": [ 101 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 77 ], + "Z": [ 102 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 103 ], + "BLUT": [ 104 ], + "C0": [ 69 ], + "Z": [ 100 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 77 ], + "B": [ 75 ], + "C": [ 73 ], + "D": [ 71 ], + "Z": [ 103 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 77 ], + "Z": [ 104 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 105 ], + "D1": [ 106 ], + "SD": [ 69 ], + "Z": [ 96 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 107 ], + "BLUT": [ 108 ], + "C0": [ 71 ], + "Z": [ 105 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 79 ], + "Z": [ 107 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 79 ], + "Z": [ 108 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 109 ], + "BLUT": [ 110 ], + "C0": [ 71 ], + "Z": [ 106 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 79 ], + "Z": [ 109 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 79 ], + "Z": [ 110 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 111 ], + "D1": [ 112 ], + "SD": [ 69 ], + "Z": [ 97 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 113 ], + "BLUT": [ 114 ], + "C0": [ 71 ], + "Z": [ 111 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 79 ], + "Z": [ 113 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 79 ], + "Z": [ 114 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 115 ], + "BLUT": [ 116 ], + "C0": [ 71 ], + "Z": [ 112 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 79 ], + "B": [ 77 ], + "C": [ 75 ], + "D": [ 73 ], + "Z": [ 115 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 79 ], + "Z": [ 116 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 87 ], + "B": [ 85 ], + "C": [ 117 ], + "D": [ 118 ], + "Z": [ 86 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 89 ], + "D": [ 118 ], + "Z": [ 88 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_10": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 51 ], + "C": [ 49 ], + "D": [ 119 ], + "Z": [ 50 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_11": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 53 ], + "B": [ 51 ], + "C": [ 49 ], + "D": [ 119 ], + "Z": [ 52 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_12": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 55 ], + "D": [ 120 ], + "Z": [ 54 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_13": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 57 ], + "D": [ 121 ], + "Z": [ 56 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_14": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 59 ], + "C": [ 57 ], + "D": [ 121 ], + "Z": [ 58 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 67 ], + "C": [ 98 ], + "D": [ 122 ], + "Z": [ 66 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 123 ], + "D1": [ 124 ], + "SD": [ 120 ], + "Z": [ 98 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 125 ], + "D1": [ 126 ], + "SD": [ 55 ], + "Z": [ 123 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 127 ], + "BLUT": [ 128 ], + "C0": [ 57 ], + "Z": [ 125 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 127 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 128 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 129 ], + "BLUT": [ 130 ], + "C0": [ 57 ], + "Z": [ 126 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 129 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 130 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 131 ], + "D1": [ 132 ], + "SD": [ 55 ], + "Z": [ 124 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 133 ], + "BLUT": [ 134 ], + "C0": [ 57 ], + "Z": [ 131 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 133 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 134 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 135 ], + "BLUT": [ 136 ], + "C0": [ 57 ], + "Z": [ 132 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 67 ], + "B": [ 65 ], + "C": [ 61 ], + "D": [ 59 ], + "Z": [ 135 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 136 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 137 ], + "D1": [ 138 ], + "SD": [ 139 ], + "Z": [ 140 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 141 ], + "D1": [ 142 ], + "SD": [ 120 ], + "Z": [ 122 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 143 ], + "BLUT": [ 144 ], + "C0": [ 55 ], + "Z": [ 141 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 143 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 144 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 145 ], + "BLUT": [ 146 ], + "C0": [ 55 ], + "Z": [ 142 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 65 ], + "B": [ 61 ], + "C": [ 59 ], + "D": [ 57 ], + "Z": [ 145 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 146 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 147 ], + "D1": [ 148 ], + "SD": [ 120 ], + "Z": [ 137 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 149 ], + "BLUT": [ 150 ], + "C0": [ 55 ], + "Z": [ 147 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 149 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 150 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 151 ], + "BLUT": [ 152 ], + "C0": [ 55 ], + "Z": [ 148 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 151 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 152 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 153 ], + "D1": [ 154 ], + "SD": [ 120 ], + "Z": [ 138 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 155 ], + "BLUT": [ 156 ], + "C0": [ 55 ], + "Z": [ 153 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 155 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 65 ], + "B": [ 61 ], + "C": [ 59 ], + "D": [ 57 ], + "Z": [ 156 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 157 ], + "BLUT": [ 158 ], + "C0": [ 55 ], + "Z": [ 154 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 65 ], + "B": [ 61 ], + "C": [ 59 ], + "D": [ 57 ], + "Z": [ 157 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 158 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 159 ], + "D1": [ 160 ], + "SD": [ 161 ], + "Z": [ 139 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 162 ], + "D1": [ 163 ], + "SD": [ 164 ], + "Z": [ 159 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 165 ], + "BLUT": [ 166 ], + "C0": [ 45 ], + "Z": [ 162 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 165 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 166 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 167 ], + "BLUT": [ 168 ], + "C0": [ 45 ], + "Z": [ 163 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 167 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 168 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 169 ], + "D1": [ 170 ], + "SD": [ 164 ], + "Z": [ 160 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 171 ], + "BLUT": [ 172 ], + "C0": [ 45 ], + "Z": [ 169 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 171 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 53 ], + "B": [ 51 ], + "C": [ 49 ], + "D": [ 47 ], + "Z": [ 172 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 173 ], + "BLUT": [ 174 ], + "C0": [ 45 ], + "Z": [ 170 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 53 ], + "B": [ 51 ], + "C": [ 49 ], + "D": [ 47 ], + "Z": [ 173 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 174 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_16": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 63 ], + "D": [ 175 ], + "Z": [ 62 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_16_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 41 ], + "D": [ 176 ], + "Z": [ 175 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_17": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 71 ], + "D": [ 177 ], + "Z": [ 70 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_17_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 69 ], + "D": [ 98 ], + "Z": [ 177 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 41 ], + "D": [ 176 ], + "Z": [ 40 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 178 ], + "D1": [ 179 ], + "SD": [ 176 ], + "Z": [ 180 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 181 ], + "D1": [ 182 ], + "SD": [ 41 ], + "Z": [ 178 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 183 ], + "BLUT": [ 184 ], + "C0": [ 63 ], + "Z": [ 181 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 89 ], + "B": [ 87 ], + "C": [ 85 ], + "D": [ 83 ], + "Z": [ 183 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 89 ], + "B": [ 87 ], + "C": [ 85 ], + "D": [ 83 ], + "Z": [ 184 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 185 ], + "BLUT": [ 186 ], + "C0": [ 63 ], + "Z": [ 182 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 89 ], + "B": [ 87 ], + "C": [ 85 ], + "D": [ 83 ], + "Z": [ 185 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 89 ], + "B": [ 87 ], + "C": [ 85 ], + "D": [ 83 ], + "Z": [ 186 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 187 ], + "D1": [ 188 ], + "SD": [ 41 ], + "Z": [ 179 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 189 ], + "BLUT": [ 190 ], + "C0": [ 63 ], + "Z": [ 187 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 89 ], + "B": [ 87 ], + "C": [ 85 ], + "D": [ 83 ], + "Z": [ 189 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 89 ], + "B": [ 87 ], + "C": [ 85 ], + "D": [ 83 ], + "Z": [ 190 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 191 ], + "BLUT": [ 192 ], + "C0": [ 63 ], + "Z": [ 188 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 89 ], + "B": [ 87 ], + "C": [ 85 ], + "D": [ 83 ], + "Z": [ 191 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 89 ], + "B": [ 87 ], + "C": [ 85 ], + "D": [ 83 ], + "Z": [ 192 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 193 ], + "D1": [ 194 ], + "SD": [ 180 ], + "Z": [ 161 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 195 ], + "D1": [ 196 ], + "SD": [ 118 ], + "Z": [ 193 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 197 ], + "BLUT": [ 198 ], + "C0": [ 89 ], + "Z": [ 195 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 197 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 198 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 199 ], + "BLUT": [ 200 ], + "C0": [ 89 ], + "Z": [ 196 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 199 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 200 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 201 ], + "D1": [ 202 ], + "SD": [ 118 ], + "Z": [ 194 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 203 ], + "BLUT": [ 204 ], + "C0": [ 89 ], + "Z": [ 201 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 43 ], + "B": [ 95 ], + "C": [ 93 ], + "D": [ 91 ], + "Z": [ 203 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 43 ], + "B": [ 95 ], + "C": [ 93 ], + "D": [ 91 ], + "Z": [ 204 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 205 ], + "BLUT": [ 206 ], + "C0": [ 89 ], + "Z": [ 202 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 43 ], + "B": [ 95 ], + "C": [ 93 ], + "D": [ 91 ], + "Z": [ 205 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 43 ], + "B": [ 95 ], + "C": [ 93 ], + "D": [ 91 ], + "Z": [ 206 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 207 ], + "D1": [ 208 ], + "SD": [ 118 ], + "Z": [ 164 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 209 ], + "BLUT": [ 210 ], + "C0": [ 89 ], + "Z": [ 207 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 209 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 210 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 211 ], + "BLUT": [ 212 ], + "C0": [ 89 ], + "Z": [ 208 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 43 ], + "B": [ 95 ], + "C": [ 93 ], + "D": [ 91 ], + "Z": [ 211 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 212 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 213 ], + "BLUT": [ 214 ], + "C0": [ 215 ], + "Z": [ 176 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 213 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000001000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 39 ], + "B": [ 216 ], + "C": [ 217 ], + "D": [ 81 ], + "Z": [ 214 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 39 ], + "D": [ 218 ], + "Z": [ 38 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 219 ], + "D1": [ 220 ], + "SD": [ 218 ], + "Z": [ 118 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 221 ], + "D1": [ 222 ], + "SD": [ 39 ], + "Z": [ 219 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 223 ], + "BLUT": [ 224 ], + "C0": [ 41 ], + "Z": [ 221 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 223 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 224 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 225 ], + "BLUT": [ 226 ], + "C0": [ 41 ], + "Z": [ 222 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 225 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 226 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 227 ], + "D1": [ 228 ], + "SD": [ 39 ], + "Z": [ 220 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 229 ], + "BLUT": [ 230 ], + "C0": [ 41 ], + "Z": [ 227 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 229 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 230 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 231 ], + "BLUT": [ 232 ], + "C0": [ 41 ], + "Z": [ 228 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 87 ], + "B": [ 85 ], + "C": [ 83 ], + "D": [ 63 ], + "Z": [ 231 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 232 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000010000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 216 ], + "B": [ 217 ], + "C": [ 81 ], + "D": [ 215 ], + "Z": [ 218 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 91 ], + "D": [ 233 ], + "Z": [ 90 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_20": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 73 ], + "C": [ 71 ], + "D": [ 177 ], + "Z": [ 72 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_21": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 85 ], + "D": [ 117 ], + "Z": [ 84 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_22": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 69 ], + "D": [ 98 ], + "Z": [ 68 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_23": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 83 ], + "C": [ 63 ], + "D": [ 175 ], + "Z": [ 82 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_24": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 49 ], + "D": [ 119 ], + "Z": [ 48 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_2_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 89 ], + "D": [ 118 ], + "Z": [ 233 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 93 ], + "C": [ 91 ], + "D": [ 233 ], + "Z": [ 92 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 95 ], + "B": [ 93 ], + "C": [ 91 ], + "D": [ 233 ], + "Z": [ 94 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 43 ], + "C": [ 234 ], + "D": [ 164 ], + "Z": [ 42 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 235 ], + "D1": [ 236 ], + "SD": [ 234 ], + "Z": [ 120 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 237 ], + "D1": [ 238 ], + "SD": [ 43 ], + "Z": [ 235 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 239 ], + "BLUT": [ 240 ], + "C0": [ 45 ], + "Z": [ 237 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 239 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 240 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 241 ], + "BLUT": [ 242 ], + "C0": [ 45 ], + "Z": [ 238 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 241 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 242 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 243 ], + "D1": [ 244 ], + "SD": [ 43 ], + "Z": [ 236 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 245 ], + "BLUT": [ 246 ], + "C0": [ 45 ], + "Z": [ 243 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 245 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 246 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 247 ], + "BLUT": [ 248 ], + "C0": [ 45 ], + "Z": [ 244 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 53 ], + "B": [ 51 ], + "C": [ 49 ], + "D": [ 47 ], + "Z": [ 247 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 248 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 249 ], + "D1": [ 250 ], + "SD": [ 117 ], + "Z": [ 234 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 251 ], + "D1": [ 252 ], + "SD": [ 85 ], + "Z": [ 249 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 253 ], + "BLUT": [ 254 ], + "C0": [ 87 ], + "Z": [ 251 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 253 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 254 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 255 ], + "BLUT": [ 256 ], + "C0": [ 87 ], + "Z": [ 252 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 255 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 256 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 257 ], + "D1": [ 258 ], + "SD": [ 85 ], + "Z": [ 250 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 259 ], + "BLUT": [ 260 ], + "C0": [ 87 ], + "Z": [ 257 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 259 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 260 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 261 ], + "BLUT": [ 262 ], + "C0": [ 87 ], + "Z": [ 258 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 95 ], + "B": [ 93 ], + "C": [ 91 ], + "D": [ 89 ], + "Z": [ 261 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 262 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 45 ], + "D": [ 164 ], + "Z": [ 44 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_7": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 47 ], + "D": [ 263 ], + "Z": [ 46 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_7_D_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 47 ], + "D": [ 263 ], + "Z": [ 119 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_7_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 45 ], + "D": [ 164 ], + "Z": [ 263 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_8": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 61 ], + "B": [ 59 ], + "C": [ 57 ], + "D": [ 121 ], + "Z": [ 60 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_8_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 55 ], + "D": [ 120 ], + "Z": [ 121 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_9": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011100001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 216 ], + "B": [ 217 ], + "C": [ 81 ], + "D": [ 215 ], + "Z": [ 80 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 264 ], + "D1": [ 265 ], + "SD": [ 266 ], + "Z": [ 117 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 267 ], + "D1": [ 268 ], + "SD": [ 81 ], + "Z": [ 264 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 269 ], + "BLUT": [ 270 ], + "C0": [ 216 ], + "Z": [ 267 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 269 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 270 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 271 ], + "BLUT": [ 272 ], + "C0": [ 216 ], + "Z": [ 268 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 271 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 272 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 273 ], + "D1": [ 274 ], + "SD": [ 81 ], + "Z": [ 265 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 275 ], + "BLUT": [ 276 ], + "C0": [ 216 ], + "Z": [ 273 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 275 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 276 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 277 ], + "BLUT": [ 278 ], + "C0": [ 216 ], + "Z": [ 274 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 277 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 83 ], + "B": [ 63 ], + "C": [ 41 ], + "D": [ 39 ], + "Z": [ 278 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_SD_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 217 ], + "D": [ 215 ], + "Z": [ 266 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 279 ], + "BLUT": [ 280 ], + "C0": [ 98 ], + "Z": [ 74 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z_1": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 281 ], + "BLUT": [ 282 ], + "C0": [ 121 ], + "Z": [ 64 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z_1_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 65 ], + "B": [ 61 ], + "C": [ 59 ], + "D": [ 57 ], + "Z": [ 281 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z_1_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 65 ], + "Z": [ 282 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 75 ], + "B": [ 73 ], + "C": [ 71 ], + "D": [ 69 ], + "Z": [ 279 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 75 ], + "Z": [ 280 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 283 ], + "LSR": [ 3 ], + "Q": [ 30 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 30 ], + "D": [ 284 ], + "Z": [ 283 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 284 ], + "LSR": [ 285 ], + "Q": [ 34 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 30 ], + "D": [ 284 ], + "Z": [ 286 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 30 ], + "D": [ 284 ], + "Z": [ 287 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 216 ], + "D": [ 288 ], + "Z": [ 284 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 216 ], + "D": [ 288 ], + "Z": [ 289 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 215 ], + "C": [ 290 ], + "D": [ 291 ], + "Z": [ 292 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 290 ], + "D": [ 291 ], + "Z": [ 293 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 217 ], + "B": [ 215 ], + "C": [ 290 ], + "D": [ 291 ], + "Z": [ 294 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 217 ], + "B": [ 215 ], + "C": [ 290 ], + "D": [ 291 ], + "Z": [ 288 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 30 ], + "Z": [ 285 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 287 ], + "CLK": [ 2 ], + "DI": [ 295 ], + "LSR": [ 37 ], + "Q": [ 291 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 287 ], + "CLK": [ 2 ], + "DI": [ 293 ], + "LSR": [ 37 ], + "Q": [ 290 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 287 ], + "CLK": [ 2 ], + "DI": [ 292 ], + "LSR": [ 37 ], + "Q": [ 215 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 287 ], + "CLK": [ 2 ], + "DI": [ 294 ], + "LSR": [ 37 ], + "Q": [ 217 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 287 ], + "CLK": [ 2 ], + "DI": [ 289 ], + "LSR": [ 37 ], + "Q": [ 216 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 291 ], + "Z": [ 295 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8", + "module": "$paramod$24a3a7236073cb7c12a30999f26614228c51a089\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[4].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[4].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[5].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[5].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[6].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[6].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[7].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[7].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 286 ], + "CLK": [ 2 ], + "DI": [ 296 ], + "LSR": [ 3 ], + "Q": [ 5 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 286 ], + "CLK": [ 2 ], + "DI": [ 297 ], + "LSR": [ 3 ], + "Q": [ 6 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_1_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011001000110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 80 ], + "B": [ 78 ], + "C": [ 76 ], + "D": [ 298 ], + "Z": [ 297 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 286 ], + "CLK": [ 2 ], + "DI": [ 299 ], + "LSR": [ 3 ], + "Q": [ 7 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_2_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011001000110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 38 ], + "B": [ 78 ], + "C": [ 76 ], + "D": [ 298 ], + "Z": [ 299 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 286 ], + "CLK": [ 2 ], + "DI": [ 300 ], + "LSR": [ 3 ], + "Q": [ 8 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011001000110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 40 ], + "B": [ 78 ], + "C": [ 76 ], + "D": [ 298 ], + "Z": [ 300 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 301 ], + "D1": [ 302 ], + "SD": [ 140 ], + "Z": [ 298 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 303 ], + "D1": [ 304 ], + "SD": [ 122 ], + "Z": [ 301 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 305 ], + "BLUT": [ 306 ], + "C0": [ 67 ], + "Z": [ 303 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 305 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 306 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 307 ], + "BLUT": [ 308 ], + "C0": [ 67 ], + "Z": [ 304 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 307 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 308 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 309 ], + "D1": [ 310 ], + "SD": [ 122 ], + "Z": [ 302 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 311 ], + "BLUT": [ 312 ], + "C0": [ 67 ], + "Z": [ 309 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 311 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 75 ], + "B": [ 73 ], + "C": [ 71 ], + "D": [ 69 ], + "Z": [ 312 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 313 ], + "BLUT": [ 314 ], + "C0": [ 67 ], + "Z": [ 310 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 75 ], + "B": [ 73 ], + "C": [ 71 ], + "D": [ 69 ], + "Z": [ 313 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 314 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 286 ], + "CLK": [ 2 ], + "DI": [ 315 ], + "LSR": [ 3 ], + "Q": [ 9 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_4_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011001000110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 62 ], + "B": [ 78 ], + "C": [ 76 ], + "D": [ 298 ], + "Z": [ 315 ] + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000000110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 78 ], + "C": [ 76 ], + "D": [ 298 ], + "Z": [ 296 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron", + "module": "$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 317 ], + "LSR": [ 318 ], + "Q": [ 319 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 320 ], + "LSR": [ 318 ], + "Q": [ 321 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 322 ], + "LSR": [ 318 ], + "Q": [ 323 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_10_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 323 ], + "B": [ 324 ], + "C": [ 325 ], + "D": [ 326 ], + "Z": [ 322 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 327 ], + "LSR": [ 318 ], + "Q": [ 328 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 328 ], + "C": [ 324 ], + "D": [ 326 ], + "Z": [ 327 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 329 ], + "D1": [ 330 ], + "SD": [ 331 ], + "Z": [ 326 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 332 ], + "D1": [ 333 ], + "SD": [ 334 ], + "Z": [ 329 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 335 ], + "BLUT": [ 336 ], + "C0": [ 337 ], + "Z": [ 332 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 335 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 336 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 338 ], + "BLUT": [ 339 ], + "C0": [ 337 ], + "Z": [ 333 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 338 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 339 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 340 ], + "D1": [ 341 ], + "SD": [ 334 ], + "Z": [ 330 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 342 ], + "BLUT": [ 343 ], + "C0": [ 337 ], + "Z": [ 340 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 342 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 343 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 344 ], + "BLUT": [ 345 ], + "C0": [ 337 ], + "Z": [ 341 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 323 ], + "B": [ 346 ], + "C": [ 347 ], + "D": [ 348 ], + "Z": [ 344 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 345 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 349 ], + "LSR": [ 318 ], + "Q": [ 350 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_12_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 350 ], + "C": [ 324 ], + "D": [ 351 ], + "Z": [ 349 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_12_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 328 ], + "D": [ 326 ], + "Z": [ 351 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 352 ], + "LSR": [ 318 ], + "Q": [ 353 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_13_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 353 ], + "C": [ 324 ], + "D": [ 354 ], + "Z": [ 352 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_13_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 350 ], + "D": [ 351 ], + "Z": [ 354 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 355 ], + "LSR": [ 318 ], + "Q": [ 356 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_14_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 356 ], + "C": [ 324 ], + "D": [ 357 ], + "Z": [ 355 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_14_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 353 ], + "D": [ 354 ], + "Z": [ 357 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 358 ], + "LSR": [ 318 ], + "Q": [ 359 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_15_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110000010100000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 359 ], + "B": [ 356 ], + "C": [ 324 ], + "D": [ 357 ], + "Z": [ 358 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 360 ], + "LSR": [ 318 ], + "Q": [ 361 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 361 ], + "B": [ 324 ], + "C": [ 362 ], + "D": [ 363 ], + "Z": [ 360 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 364 ], + "D1": [ 365 ], + "SD": [ 362 ], + "Z": [ 366 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 367 ], + "D1": [ 368 ], + "SD": [ 361 ], + "Z": [ 364 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 369 ], + "BLUT": [ 370 ], + "C0": [ 371 ], + "Z": [ 367 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 369 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 370 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 372 ], + "BLUT": [ 373 ], + "C0": [ 371 ], + "Z": [ 368 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 372 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 373 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 374 ], + "D1": [ 375 ], + "SD": [ 361 ], + "Z": [ 365 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 376 ], + "BLUT": [ 377 ], + "C0": [ 371 ], + "Z": [ 374 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 376 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 377 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 378 ], + "BLUT": [ 379 ], + "C0": [ 371 ], + "Z": [ 375 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 380 ], + "B": [ 381 ], + "C": [ 382 ], + "D": [ 383 ], + "Z": [ 378 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 379 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 384 ], + "D1": [ 385 ], + "SD": [ 366 ], + "Z": [ 386 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 387 ], + "D1": [ 388 ], + "SD": [ 389 ], + "Z": [ 384 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 390 ], + "BLUT": [ 391 ], + "C0": [ 392 ], + "Z": [ 387 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 393 ], + "Z": [ 390 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 393 ], + "Z": [ 391 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 394 ], + "BLUT": [ 395 ], + "C0": [ 392 ], + "Z": [ 388 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 393 ], + "Z": [ 394 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 393 ], + "Z": [ 395 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 396 ], + "D1": [ 397 ], + "SD": [ 389 ], + "Z": [ 385 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 398 ], + "BLUT": [ 399 ], + "C0": [ 392 ], + "Z": [ 396 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 393 ], + "Z": [ 398 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 393 ], + "Z": [ 399 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 400 ], + "BLUT": [ 401 ], + "C0": [ 392 ], + "Z": [ 397 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 393 ], + "B": [ 402 ], + "C": [ 403 ], + "D": [ 404 ], + "Z": [ 400 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 393 ], + "Z": [ 401 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 405 ], + "D1": [ 406 ], + "SD": [ 407 ], + "Z": [ 408 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 409 ], + "D1": [ 410 ], + "SD": [ 411 ], + "Z": [ 412 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 413 ], + "D1": [ 414 ], + "SD": [ 392 ], + "Z": [ 409 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 415 ], + "BLUT": [ 416 ], + "C0": [ 404 ], + "Z": [ 413 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 417 ], + "Z": [ 415 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 417 ], + "Z": [ 416 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 418 ], + "BLUT": [ 419 ], + "C0": [ 404 ], + "Z": [ 414 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 417 ], + "Z": [ 418 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 417 ], + "Z": [ 419 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 420 ], + "D1": [ 421 ], + "SD": [ 392 ], + "Z": [ 410 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 422 ], + "BLUT": [ 423 ], + "C0": [ 404 ], + "Z": [ 420 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 417 ], + "Z": [ 422 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 417 ], + "Z": [ 423 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 424 ], + "BLUT": [ 425 ], + "C0": [ 404 ], + "Z": [ 421 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 417 ], + "B": [ 393 ], + "C": [ 402 ], + "D": [ 403 ], + "Z": [ 424 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 417 ], + "Z": [ 425 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 426 ], + "D1": [ 427 ], + "SD": [ 428 ], + "Z": [ 429 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 430 ], + "D1": [ 431 ], + "SD": [ 380 ], + "Z": [ 426 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 432 ], + "BLUT": [ 433 ], + "C0": [ 389 ], + "Z": [ 430 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 402 ], + "Z": [ 432 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 402 ], + "Z": [ 433 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 434 ], + "BLUT": [ 435 ], + "C0": [ 389 ], + "Z": [ 431 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 402 ], + "Z": [ 434 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 402 ], + "Z": [ 435 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 436 ], + "D1": [ 437 ], + "SD": [ 380 ], + "Z": [ 427 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 438 ], + "BLUT": [ 439 ], + "C0": [ 389 ], + "Z": [ 436 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 402 ], + "Z": [ 438 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 402 ], + "Z": [ 439 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 440 ], + "BLUT": [ 441 ], + "C0": [ 389 ], + "Z": [ 437 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 402 ], + "B": [ 403 ], + "C": [ 404 ], + "D": [ 392 ], + "Z": [ 440 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 402 ], + "Z": [ 441 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 442 ], + "D1": [ 443 ], + "SD": [ 428 ], + "Z": [ 444 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 445 ], + "BLUT": [ 446 ], + "C0": [ 380 ], + "Z": [ 442 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 403 ], + "Z": [ 445 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 403 ], + "Z": [ 446 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 447 ], + "BLUT": [ 448 ], + "C0": [ 380 ], + "Z": [ 443 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 403 ], + "B": [ 404 ], + "C": [ 392 ], + "D": [ 389 ], + "Z": [ 447 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 403 ], + "Z": [ 448 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 449 ], + "D1": [ 450 ], + "SD": [ 451 ], + "Z": [ 405 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 452 ], + "BLUT": [ 453 ], + "C0": [ 381 ], + "Z": [ 449 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 452 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 453 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 454 ], + "BLUT": [ 455 ], + "C0": [ 381 ], + "Z": [ 450 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 454 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 455 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 456 ], + "D1": [ 457 ], + "SD": [ 451 ], + "Z": [ 406 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 458 ], + "BLUT": [ 459 ], + "C0": [ 381 ], + "Z": [ 456 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 458 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 404 ], + "B": [ 392 ], + "C": [ 389 ], + "D": [ 380 ], + "Z": [ 459 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 460 ], + "BLUT": [ 461 ], + "C0": [ 381 ], + "Z": [ 457 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 404 ], + "B": [ 392 ], + "C": [ 389 ], + "D": [ 380 ], + "Z": [ 460 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 461 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 462 ], + "B": [ 417 ], + "C": [ 393 ], + "D": [ 463 ], + "Z": [ 464 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 465 ], + "D1": [ 466 ], + "SD": [ 325 ], + "Z": [ 362 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 467 ], + "D1": [ 468 ], + "SD": [ 323 ], + "Z": [ 465 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 469 ], + "BLUT": [ 470 ], + "C0": [ 328 ], + "Z": [ 467 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 469 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 470 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 471 ], + "BLUT": [ 472 ], + "C0": [ 328 ], + "Z": [ 468 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 471 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 472 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 473 ], + "D1": [ 474 ], + "SD": [ 323 ], + "Z": [ 466 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 475 ], + "BLUT": [ 476 ], + "C0": [ 328 ], + "Z": [ 473 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 475 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 476 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 477 ], + "BLUT": [ 478 ], + "C0": [ 328 ], + "Z": [ 474 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 359 ], + "B": [ 356 ], + "C": [ 353 ], + "D": [ 350 ], + "Z": [ 477 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 478 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 479 ], + "D1": [ 480 ], + "SD": [ 326 ], + "Z": [ 363 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 481 ], + "D1": [ 482 ], + "SD": [ 328 ], + "Z": [ 479 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 483 ], + "BLUT": [ 484 ], + "C0": [ 350 ], + "Z": [ 481 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 483 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 484 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 485 ], + "BLUT": [ 486 ], + "C0": [ 350 ], + "Z": [ 482 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 485 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 486 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 487 ], + "D1": [ 488 ], + "SD": [ 328 ], + "Z": [ 480 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 489 ], + "BLUT": [ 490 ], + "C0": [ 350 ], + "Z": [ 487 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 489 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 490 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 491 ], + "BLUT": [ 492 ], + "C0": [ 350 ], + "Z": [ 488 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 361 ], + "B": [ 359 ], + "C": [ 356 ], + "D": [ 353 ], + "Z": [ 491 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 492 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 493 ], + "LSR": [ 318 ], + "Q": [ 371 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_17_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 371 ], + "C": [ 324 ], + "D": [ 363 ], + "Z": [ 493 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 494 ], + "LSR": [ 318 ], + "Q": [ 383 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_18_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 383 ], + "C": [ 324 ], + "D": [ 495 ], + "Z": [ 494 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_18_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 371 ], + "D": [ 363 ], + "Z": [ 495 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 496 ], + "LSR": [ 318 ], + "Q": [ 382 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_19_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 382 ], + "C": [ 324 ], + "D": [ 497 ], + "Z": [ 496 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 498 ], + "D": [ 324 ], + "Z": [ 320 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 321 ], + "D": [ 499 ], + "Z": [ 498 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 319 ], + "D": [ 500 ], + "Z": [ 499 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 501 ], + "BLUT": [ 502 ], + "C0": [ 499 ], + "Z": [ 503 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000010000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 504 ], + "B": [ 505 ], + "C": [ 506 ], + "D": [ 321 ], + "Z": [ 501 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 502 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 507 ], + "D1": [ 508 ], + "SD": [ 428 ], + "Z": [ 463 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 509 ], + "D1": [ 510 ], + "SD": [ 380 ], + "Z": [ 507 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 511 ], + "BLUT": [ 512 ], + "C0": [ 389 ], + "Z": [ 509 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 511 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 512 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 513 ], + "BLUT": [ 514 ], + "C0": [ 389 ], + "Z": [ 510 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 513 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 514 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 515 ], + "D1": [ 516 ], + "SD": [ 380 ], + "Z": [ 508 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 517 ], + "BLUT": [ 518 ], + "C0": [ 389 ], + "Z": [ 515 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 517 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 518 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 519 ], + "BLUT": [ 520 ], + "C0": [ 389 ], + "Z": [ 516 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 402 ], + "B": [ 403 ], + "C": [ 404 ], + "D": [ 392 ], + "Z": [ 519 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 520 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 505 ], + "C": [ 521 ], + "D": [ 522 ], + "Z": [ 523 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 524 ], + "D1": [ 525 ], + "SD": [ 522 ], + "Z": [ 325 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 526 ], + "D1": [ 527 ], + "SD": [ 504 ], + "Z": [ 524 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 528 ], + "BLUT": [ 529 ], + "C0": [ 334 ], + "Z": [ 526 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 528 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 529 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 530 ], + "BLUT": [ 531 ], + "C0": [ 334 ], + "Z": [ 527 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 530 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 531 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 532 ], + "D1": [ 533 ], + "SD": [ 504 ], + "Z": [ 525 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 534 ], + "BLUT": [ 535 ], + "C0": [ 334 ], + "Z": [ 532 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 534 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 535 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 536 ], + "BLUT": [ 537 ], + "C0": [ 334 ], + "Z": [ 533 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 346 ], + "B": [ 347 ], + "C": [ 348 ], + "D": [ 337 ], + "Z": [ 536 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 537 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 538 ], + "BLUT": [ 539 ], + "C0": [ 500 ], + "Z": [ 522 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000100010000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 505 ], + "B": [ 506 ], + "C": [ 321 ], + "D": [ 319 ], + "Z": [ 538 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 505 ], + "C": [ 506 ], + "D": [ 321 ], + "Z": [ 539 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 540 ], + "LSR": [ 318 ], + "Q": [ 506 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 541 ], + "LSR": [ 318 ], + "Q": [ 381 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_20_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110000010100000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 381 ], + "B": [ 382 ], + "C": [ 324 ], + "D": [ 497 ], + "Z": [ 541 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_20_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 383 ], + "D": [ 495 ], + "Z": [ 497 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 542 ], + "LSR": [ 318 ], + "Q": [ 380 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 380 ], + "B": [ 324 ], + "C": [ 428 ], + "D": [ 366 ], + "Z": [ 542 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 543 ], + "D1": [ 544 ], + "SD": [ 545 ], + "Z": [ 428 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 546 ], + "D1": [ 547 ], + "SD": [ 359 ], + "Z": [ 543 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 548 ], + "BLUT": [ 549 ], + "C0": [ 361 ], + "Z": [ 546 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 548 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 549 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 550 ], + "BLUT": [ 551 ], + "C0": [ 361 ], + "Z": [ 547 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 550 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 551 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 552 ], + "D1": [ 553 ], + "SD": [ 359 ], + "Z": [ 544 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 554 ], + "BLUT": [ 555 ], + "C0": [ 361 ], + "Z": [ 552 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 554 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 555 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 556 ], + "BLUT": [ 557 ], + "C0": [ 361 ], + "Z": [ 553 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 381 ], + "B": [ 382 ], + "C": [ 383 ], + "D": [ 371 ], + "Z": [ 556 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 557 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 558 ], + "LSR": [ 318 ], + "Q": [ 389 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_22_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011001000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 389 ], + "B": [ 324 ], + "C": [ 366 ], + "D": [ 411 ], + "Z": [ 558 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 559 ], + "LSR": [ 318 ], + "Q": [ 392 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 392 ], + "C": [ 324 ], + "D": [ 411 ], + "Z": [ 559 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 560 ], + "D1": [ 561 ], + "SD": [ 363 ], + "Z": [ 411 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 562 ], + "D1": [ 563 ], + "SD": [ 371 ], + "Z": [ 560 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 564 ], + "BLUT": [ 565 ], + "C0": [ 383 ], + "Z": [ 562 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 564 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 565 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 566 ], + "BLUT": [ 567 ], + "C0": [ 383 ], + "Z": [ 563 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 566 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 567 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 568 ], + "D1": [ 569 ], + "SD": [ 371 ], + "Z": [ 561 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 570 ], + "BLUT": [ 571 ], + "C0": [ 383 ], + "Z": [ 568 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 570 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 571 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 572 ], + "BLUT": [ 573 ], + "C0": [ 383 ], + "Z": [ 569 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 389 ], + "B": [ 380 ], + "C": [ 381 ], + "D": [ 382 ], + "Z": [ 572 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 573 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 574 ], + "LSR": [ 318 ], + "Q": [ 404 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_24_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 404 ], + "C": [ 324 ], + "D": [ 575 ], + "Z": [ 574 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_24_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 392 ], + "D": [ 411 ], + "Z": [ 575 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 576 ], + "LSR": [ 318 ], + "Q": [ 403 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_25_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 324 ], + "D": [ 444 ], + "Z": [ 576 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 577 ], + "LSR": [ 318 ], + "Q": [ 402 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_26_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 324 ], + "D": [ 429 ], + "Z": [ 577 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 578 ], + "LSR": [ 318 ], + "Q": [ 393 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_27_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 324 ], + "D": [ 386 ], + "Z": [ 578 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 579 ], + "LSR": [ 318 ], + "Q": [ 417 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_28_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 324 ], + "D": [ 412 ], + "Z": [ 579 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_29": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 580 ], + "LSR": [ 318 ], + "Q": [ 462 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_29_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 324 ], + "D": [ 464 ], + "Z": [ 580 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_2_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 581 ], + "D": [ 324 ], + "Z": [ 540 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_2_DI_LUT4_Z_C_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0101011001100110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 506 ], + "B": [ 321 ], + "C": [ 319 ], + "D": [ 500 ], + "Z": [ 581 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 582 ], + "LSR": [ 318 ], + "Q": [ 505 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_30": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 583 ], + "LSR": [ 318 ], + "Q": [ 500 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_30_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 500 ], + "D": [ 324 ], + "Z": [ 583 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_3_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 324 ], + "D": [ 523 ], + "Z": [ 582 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 584 ], + "LSR": [ 318 ], + "Q": [ 504 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 585 ], + "D": [ 324 ], + "Z": [ 584 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 504 ], + "C": [ 505 ], + "D": [ 521 ], + "Z": [ 585 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 586 ], + "D1": [ 587 ], + "SD": [ 521 ], + "Z": [ 588 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 589 ], + "D1": [ 590 ], + "SD": [ 505 ], + "Z": [ 586 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 591 ], + "BLUT": [ 592 ], + "C0": [ 504 ], + "Z": [ 589 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 591 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 592 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 593 ], + "BLUT": [ 594 ], + "C0": [ 504 ], + "Z": [ 590 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 593 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 594 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 595 ], + "D1": [ 596 ], + "SD": [ 505 ], + "Z": [ 587 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 597 ], + "BLUT": [ 598 ], + "C0": [ 504 ], + "Z": [ 595 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 597 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 598 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 599 ], + "BLUT": [ 600 ], + "C0": [ 504 ], + "Z": [ 596 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 347 ], + "B": [ 348 ], + "C": [ 337 ], + "D": [ 334 ], + "Z": [ 599 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 600 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 601 ], + "D1": [ 602 ], + "SD": [ 588 ], + "Z": [ 545 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 603 ], + "D1": [ 604 ], + "SD": [ 346 ], + "Z": [ 601 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 605 ], + "BLUT": [ 606 ], + "C0": [ 323 ], + "Z": [ 603 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 605 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 606 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 607 ], + "BLUT": [ 608 ], + "C0": [ 323 ], + "Z": [ 604 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 607 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 608 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 609 ], + "D1": [ 610 ], + "SD": [ 346 ], + "Z": [ 602 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 611 ], + "BLUT": [ 612 ], + "C0": [ 323 ], + "Z": [ 609 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 611 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 612 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 613 ], + "BLUT": [ 614 ], + "C0": [ 323 ], + "Z": [ 610 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 356 ], + "B": [ 353 ], + "C": [ 350 ], + "D": [ 328 ], + "Z": [ 613 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 614 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1010100010001000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 506 ], + "B": [ 321 ], + "C": [ 319 ], + "D": [ 500 ], + "Z": [ 521 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 615 ], + "LSR": [ 318 ], + "Q": [ 334 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 334 ], + "C": [ 331 ], + "D": [ 324 ], + "Z": [ 615 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 616 ], + "D1": [ 617 ], + "SD": [ 331 ], + "Z": [ 618 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 619 ], + "D1": [ 620 ], + "SD": [ 334 ], + "Z": [ 616 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 621 ], + "BLUT": [ 622 ], + "C0": [ 337 ], + "Z": [ 619 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 621 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 323 ], + "B": [ 346 ], + "C": [ 347 ], + "D": [ 348 ], + "Z": [ 622 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 623 ], + "BLUT": [ 624 ], + "C0": [ 337 ], + "Z": [ 620 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 623 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 624 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 625 ], + "D1": [ 626 ], + "SD": [ 334 ], + "Z": [ 617 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 627 ], + "BLUT": [ 628 ], + "C0": [ 337 ], + "Z": [ 625 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 627 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 628 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 629 ], + "BLUT": [ 630 ], + "C0": [ 337 ], + "Z": [ 626 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 323 ], + "B": [ 346 ], + "C": [ 347 ], + "D": [ 348 ], + "Z": [ 629 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 630 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 631 ], + "D1": [ 632 ], + "SD": [ 618 ], + "Z": [ 633 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 634 ], + "D1": [ 635 ], + "SD": [ 325 ], + "Z": [ 631 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 636 ], + "BLUT": [ 637 ], + "C0": [ 323 ], + "Z": [ 634 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 636 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 637 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 638 ], + "BLUT": [ 639 ], + "C0": [ 323 ], + "Z": [ 635 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 638 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 639 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 640 ], + "D1": [ 641 ], + "SD": [ 325 ], + "Z": [ 632 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 642 ], + "BLUT": [ 643 ], + "C0": [ 323 ], + "Z": [ 640 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 356 ], + "B": [ 353 ], + "C": [ 350 ], + "D": [ 328 ], + "Z": [ 642 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 356 ], + "B": [ 353 ], + "C": [ 350 ], + "D": [ 328 ], + "Z": [ 643 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 644 ], + "BLUT": [ 645 ], + "C0": [ 323 ], + "Z": [ 641 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 356 ], + "B": [ 353 ], + "C": [ 350 ], + "D": [ 328 ], + "Z": [ 644 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 356 ], + "B": [ 353 ], + "C": [ 350 ], + "D": [ 328 ], + "Z": [ 645 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 646 ], + "D1": [ 647 ], + "SD": [ 633 ], + "Z": [ 407 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 648 ], + "D1": [ 649 ], + "SD": [ 545 ], + "Z": [ 646 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 650 ], + "BLUT": [ 651 ], + "C0": [ 359 ], + "Z": [ 648 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 650 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 651 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 652 ], + "BLUT": [ 653 ], + "C0": [ 359 ], + "Z": [ 649 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 652 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 653 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 654 ], + "D1": [ 655 ], + "SD": [ 545 ], + "Z": [ 647 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 656 ], + "BLUT": [ 657 ], + "C0": [ 359 ], + "Z": [ 654 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 656 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 382 ], + "B": [ 383 ], + "C": [ 371 ], + "D": [ 361 ], + "Z": [ 657 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 658 ], + "BLUT": [ 659 ], + "C0": [ 359 ], + "Z": [ 655 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 382 ], + "B": [ 383 ], + "C": [ 371 ], + "D": [ 361 ], + "Z": [ 658 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 659 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 660 ], + "D1": [ 661 ], + "SD": [ 545 ], + "Z": [ 451 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 662 ], + "BLUT": [ 663 ], + "C0": [ 359 ], + "Z": [ 660 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 662 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 663 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 664 ], + "BLUT": [ 665 ], + "C0": [ 359 ], + "Z": [ 661 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 382 ], + "B": [ 383 ], + "C": [ 371 ], + "D": [ 361 ], + "Z": [ 664 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 665 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 666 ], + "D1": [ 667 ], + "SD": [ 500 ], + "Z": [ 331 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 668 ], + "BLUT": [ 669 ], + "C0": [ 319 ], + "Z": [ 666 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 504 ], + "B": [ 505 ], + "C": [ 506 ], + "D": [ 321 ], + "Z": [ 668 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 504 ], + "B": [ 505 ], + "C": [ 506 ], + "D": [ 321 ], + "Z": [ 669 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 670 ], + "BLUT": [ 671 ], + "C0": [ 319 ], + "Z": [ 667 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 504 ], + "C": [ 505 ], + "D": [ 506 ], + "Z": [ 670 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 504 ], + "B": [ 505 ], + "C": [ 506 ], + "D": [ 321 ], + "Z": [ 671 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 672 ], + "LSR": [ 318 ], + "Q": [ 337 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_6_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 337 ], + "C": [ 324 ], + "D": [ 673 ], + "Z": [ 672 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 674 ], + "LSR": [ 318 ], + "Q": [ 348 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_7_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110000010100000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 348 ], + "B": [ 337 ], + "C": [ 324 ], + "D": [ 673 ], + "Z": [ 674 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_7_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 334 ], + "D": [ 331 ], + "Z": [ 673 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 675 ], + "LSR": [ 318 ], + "Q": [ 347 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_8_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000011000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 347 ], + "C": [ 324 ], + "D": [ 676 ], + "Z": [ 675 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 677 ], + "LSR": [ 318 ], + "Q": [ 346 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_9_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110000010100000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 346 ], + "B": [ 347 ], + "C": [ 324 ], + "D": [ 676 ], + "Z": [ 677 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_9_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 348 ], + "C": [ 337 ], + "D": [ 673 ], + "Z": [ 676 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 678 ], + "D": [ 324 ], + "Z": [ 317 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 319 ], + "D": [ 500 ], + "Z": [ 678 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_C": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 28 ], + "D": [ 324 ], + "Z": [ 316 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 3 ], + "D": [ 28 ], + "Z": [ 318 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 679 ], + "LSR": [ 3 ], + "Q": [ 28 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 28 ], + "D": [ 324 ], + "Z": [ 679 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 324 ], + "LSR": [ 680 ], + "Q": [ 32 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 28 ], + "Z": [ 680 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 681 ], + "CLK": [ 2 ], + "DI": [ 682 ], + "LSR": [ 318 ], + "Q": [ 683 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 681 ], + "CLK": [ 2 ], + "DI": [ 684 ], + "LSR": [ 318 ], + "Q": [ 685 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 686 ], + "C": [ 685 ], + "D": [ 683 ], + "Z": [ 687 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1_DI_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 688 ], + "B": [ 686 ], + "C": [ 685 ], + "D": [ 683 ], + "Z": [ 689 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1_DI_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 690 ], + "D": [ 691 ], + "Z": [ 692 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1_DI_LUT4_Z_2_D_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 690 ], + "D": [ 691 ], + "Z": [ 324 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1_DI_LUT4_Z_2_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 688 ], + "B": [ 686 ], + "C": [ 685 ], + "D": [ 683 ], + "Z": [ 691 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1_DI_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 685 ], + "D": [ 683 ], + "Z": [ 684 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 681 ], + "CLK": [ 2 ], + "DI": [ 687 ], + "LSR": [ 318 ], + "Q": [ 686 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 681 ], + "CLK": [ 2 ], + "DI": [ 689 ], + "LSR": [ 318 ], + "Q": [ 688 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 681 ], + "CLK": [ 2 ], + "DI": [ 692 ], + "LSR": [ 318 ], + "Q": [ 690 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_CE_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 28 ], + "D": [ 324 ], + "Z": [ 681 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 683 ], + "Z": [ 682 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8", + "module": "$paramod$24a3a7236073cb7c12a30999f26614228c51a089\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[4].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[4].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[5].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[5].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[6].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[6].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[7].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[7].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 693 ], + "LSR": [ 3 ], + "Q": [ 11 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 694 ], + "LSR": [ 3 ], + "Q": [ 12 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 695 ], + "D1": [ 696 ], + "SD": [ 697 ], + "Z": [ 694 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 698 ], + "D1": [ 699 ], + "SD": [ 464 ], + "Z": [ 695 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 700 ], + "BLUT": [ 701 ], + "C0": [ 412 ], + "Z": [ 698 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 700 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 444 ], + "B": [ 429 ], + "C": [ 386 ], + "D": [ 408 ], + "Z": [ 701 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 702 ], + "BLUT": [ 703 ], + "C0": [ 412 ], + "Z": [ 699 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 702 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 703 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 704 ], + "D1": [ 705 ], + "SD": [ 464 ], + "Z": [ 696 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 706 ], + "BLUT": [ 707 ], + "C0": [ 412 ], + "Z": [ 704 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 706 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 707 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 708 ], + "BLUT": [ 709 ], + "C0": [ 412 ], + "Z": [ 705 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 708 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 709 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 710 ], + "D1": [ 711 ], + "SD": [ 463 ], + "Z": [ 697 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 712 ], + "BLUT": [ 713 ], + "C0": [ 503 ], + "Z": [ 710 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 712 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 462 ], + "D": [ 678 ], + "Z": [ 713 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 714 ], + "BLUT": [ 715 ], + "C0": [ 503 ], + "Z": [ 711 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 714 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1001010100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 462 ], + "B": [ 417 ], + "C": [ 393 ], + "D": [ 678 ], + "Z": [ 715 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 716 ], + "LSR": [ 3 ], + "Q": [ 13 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 717 ], + "D1": [ 718 ], + "SD": [ 719 ], + "Z": [ 716 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 720 ], + "D1": [ 721 ], + "SD": [ 464 ], + "Z": [ 717 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 722 ], + "BLUT": [ 723 ], + "C0": [ 412 ], + "Z": [ 720 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 722 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 444 ], + "B": [ 429 ], + "C": [ 386 ], + "D": [ 408 ], + "Z": [ 723 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 724 ], + "BLUT": [ 725 ], + "C0": [ 412 ], + "Z": [ 721 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 724 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 725 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 726 ], + "D1": [ 727 ], + "SD": [ 464 ], + "Z": [ 718 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 728 ], + "BLUT": [ 729 ], + "C0": [ 412 ], + "Z": [ 726 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 728 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 729 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 730 ], + "BLUT": [ 731 ], + "C0": [ 412 ], + "Z": [ 727 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 730 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 731 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 732 ], + "D1": [ 733 ], + "SD": [ 463 ], + "Z": [ 719 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 734 ], + "BLUT": [ 735 ], + "C0": [ 503 ], + "Z": [ 732 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 734 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 462 ], + "D": [ 498 ], + "Z": [ 735 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 736 ], + "BLUT": [ 737 ], + "C0": [ 503 ], + "Z": [ 733 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 736 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000010010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 462 ], + "B": [ 417 ], + "C": [ 393 ], + "D": [ 498 ], + "Z": [ 737 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 738 ], + "LSR": [ 3 ], + "Q": [ 14 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 739 ], + "D1": [ 740 ], + "SD": [ 741 ], + "Z": [ 738 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 742 ], + "D1": [ 743 ], + "SD": [ 464 ], + "Z": [ 739 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 744 ], + "BLUT": [ 745 ], + "C0": [ 412 ], + "Z": [ 742 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 744 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 444 ], + "B": [ 429 ], + "C": [ 386 ], + "D": [ 408 ], + "Z": [ 745 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 746 ], + "BLUT": [ 747 ], + "C0": [ 412 ], + "Z": [ 743 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 746 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 747 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 748 ], + "D1": [ 749 ], + "SD": [ 464 ], + "Z": [ 740 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 750 ], + "BLUT": [ 751 ], + "C0": [ 412 ], + "Z": [ 748 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 750 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 751 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 752 ], + "BLUT": [ 753 ], + "C0": [ 412 ], + "Z": [ 749 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 752 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 753 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 754 ], + "D1": [ 755 ], + "SD": [ 463 ], + "Z": [ 741 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 756 ], + "BLUT": [ 757 ], + "C0": [ 503 ], + "Z": [ 754 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 756 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 462 ], + "D": [ 581 ], + "Z": [ 757 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 758 ], + "BLUT": [ 759 ], + "C0": [ 503 ], + "Z": [ 755 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 758 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1001010100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 462 ], + "B": [ 417 ], + "C": [ 393 ], + "D": [ 581 ], + "Z": [ 759 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 760 ], + "LSR": [ 3 ], + "Q": [ 15 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 761 ], + "D1": [ 762 ], + "SD": [ 763 ], + "Z": [ 760 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 764 ], + "D1": [ 765 ], + "SD": [ 464 ], + "Z": [ 761 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 766 ], + "BLUT": [ 767 ], + "C0": [ 412 ], + "Z": [ 764 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 766 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 444 ], + "B": [ 429 ], + "C": [ 386 ], + "D": [ 408 ], + "Z": [ 767 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 768 ], + "BLUT": [ 769 ], + "C0": [ 412 ], + "Z": [ 765 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 768 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 769 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 770 ], + "D1": [ 771 ], + "SD": [ 464 ], + "Z": [ 762 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 772 ], + "BLUT": [ 773 ], + "C0": [ 412 ], + "Z": [ 770 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 772 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 773 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 774 ], + "BLUT": [ 775 ], + "C0": [ 412 ], + "Z": [ 771 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 774 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 775 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 776 ], + "D1": [ 777 ], + "SD": [ 463 ], + "Z": [ 763 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 778 ], + "BLUT": [ 779 ], + "C0": [ 523 ], + "Z": [ 776 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 462 ], + "D": [ 503 ], + "Z": [ 778 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 779 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 780 ], + "BLUT": [ 781 ], + "C0": [ 523 ], + "Z": [ 777 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000010010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 462 ], + "B": [ 417 ], + "C": [ 393 ], + "D": [ 503 ], + "Z": [ 780 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 781 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 782 ], + "LSR": [ 3 ], + "Q": [ 16 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 783 ], + "D1": [ 784 ], + "SD": [ 464 ], + "Z": [ 782 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 785 ], + "D1": [ 786 ], + "SD": [ 412 ], + "Z": [ 783 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 787 ], + "BLUT": [ 788 ], + "C0": [ 408 ], + "Z": [ 785 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 585 ], + "B": [ 444 ], + "C": [ 429 ], + "D": [ 386 ], + "Z": [ 787 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 788 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 789 ], + "BLUT": [ 790 ], + "C0": [ 408 ], + "Z": [ 786 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 789 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 790 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 791 ], + "D1": [ 792 ], + "SD": [ 412 ], + "Z": [ 784 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 793 ], + "BLUT": [ 794 ], + "C0": [ 408 ], + "Z": [ 791 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 793 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 794 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 795 ], + "BLUT": [ 796 ], + "C0": [ 408 ], + "Z": [ 792 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 795 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 796 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 316 ], + "CLK": [ 2 ], + "DI": [ 797 ], + "LSR": [ 3 ], + "Q": [ 10 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 798 ], + "D1": [ 799 ], + "SD": [ 464 ], + "Z": [ 797 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 800 ], + "BLUT": [ 801 ], + "C0": [ 412 ], + "Z": [ 798 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 800 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 444 ], + "B": [ 429 ], + "C": [ 386 ], + "D": [ 408 ], + "Z": [ 801 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 802 ], + "BLUT": [ 803 ], + "C0": [ 412 ], + "Z": [ 799 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 802 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 803 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 804 ], + "D1": [ 805 ], + "SD": [ 806 ], + "Z": [ 693 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 807 ], + "D1": [ 808 ], + "SD": [ 464 ], + "Z": [ 804 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 809 ], + "BLUT": [ 810 ], + "C0": [ 412 ], + "Z": [ 807 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 809 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 444 ], + "B": [ 429 ], + "C": [ 386 ], + "D": [ 408 ], + "Z": [ 810 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 811 ], + "BLUT": [ 812 ], + "C0": [ 412 ], + "Z": [ 808 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 811 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 812 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 813 ], + "D1": [ 814 ], + "SD": [ 464 ], + "Z": [ 805 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 815 ], + "BLUT": [ 816 ], + "C0": [ 412 ], + "Z": [ 813 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 815 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 816 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 817 ], + "BLUT": [ 818 ], + "C0": [ 412 ], + "Z": [ 814 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 817 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 818 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 819 ], + "D1": [ 820 ], + "SD": [ 463 ], + "Z": [ 806 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 821 ], + "BLUT": [ 822 ], + "C0": [ 503 ], + "Z": [ 819 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 821 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 462 ], + "D": [ 500 ], + "Z": [ 822 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 823 ], + "BLUT": [ 824 ], + "C0": [ 503 ], + "Z": [ 820 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 823 ] + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000010010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 462 ], + "B": [ 417 ], + "C": [ 393 ], + "D": [ 500 ], + "Z": [ 824 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron", + "module": "$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 825 ], + "LSR": [ 36 ], + "Q": [ 826 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 827 ], + "LSR": [ 36 ], + "Q": [ 828 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 829 ], + "LSR": [ 36 ], + "Q": [ 830 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 831 ], + "LSR": [ 36 ], + "Q": [ 832 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 833 ], + "LSR": [ 36 ], + "Q": [ 834 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 835 ], + "LSR": [ 36 ], + "Q": [ 836 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 837 ], + "LSR": [ 36 ], + "Q": [ 838 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 839 ], + "LSR": [ 36 ], + "Q": [ 840 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 841 ], + "LSR": [ 36 ], + "Q": [ 842 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 843 ], + "LSR": [ 36 ], + "Q": [ 844 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 845 ], + "LSR": [ 36 ], + "Q": [ 846 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 847 ], + "LSR": [ 36 ], + "Q": [ 848 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 849 ], + "LSR": [ 36 ], + "Q": [ 850 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 851 ], + "LSR": [ 36 ], + "Q": [ 852 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 853 ], + "LSR": [ 36 ], + "Q": [ 854 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 855 ], + "LSR": [ 36 ], + "Q": [ 856 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 857 ], + "LSR": [ 36 ], + "Q": [ 858 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 859 ], + "LSR": [ 36 ], + "Q": [ 860 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 861 ], + "LSR": [ 36 ], + "Q": [ 862 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 863 ], + "LSR": [ 36 ], + "Q": [ 864 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_27": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 865 ], + "LSR": [ 36 ], + "Q": [ 866 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_28": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 867 ], + "LSR": [ 36 ], + "Q": [ 868 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 869 ], + "LSR": [ 36 ], + "Q": [ 870 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 871 ], + "LSR": [ 36 ], + "Q": [ 872 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 873 ], + "LSR": [ 36 ], + "Q": [ 874 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 875 ], + "LSR": [ 36 ], + "Q": [ 876 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 877 ], + "LSR": [ 36 ], + "Q": [ 878 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 879 ], + "LSR": [ 36 ], + "Q": [ 880 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 27 ], + "CLK": [ 2 ], + "DI": [ 881 ], + "LSR": [ 36 ], + "Q": [ 882 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 883 ], + "D1": [ 884 ], + "SD": [ 885 ], + "Z": [ 847 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 886 ], + "D1": [ 887 ], + "SD": [ 888 ], + "Z": [ 883 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 889 ], + "BLUT": [ 890 ], + "C0": [ 836 ], + "Z": [ 886 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 848 ], + "Z": [ 889 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 848 ], + "Z": [ 890 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 891 ], + "BLUT": [ 892 ], + "C0": [ 836 ], + "Z": [ 887 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 848 ], + "Z": [ 891 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 848 ], + "Z": [ 892 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 893 ], + "D1": [ 894 ], + "SD": [ 888 ], + "Z": [ 884 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 895 ], + "BLUT": [ 896 ], + "C0": [ 836 ], + "Z": [ 893 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 848 ], + "Z": [ 895 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 848 ], + "Z": [ 896 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 897 ], + "BLUT": [ 898 ], + "C0": [ 836 ], + "Z": [ 894 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 848 ], + "Z": [ 897 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1010101010101001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 848 ], + "B": [ 846 ], + "C": [ 840 ], + "D": [ 838 ], + "Z": [ 898 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100110011000011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 850 ], + "C": [ 828 ], + "D": [ 826 ], + "Z": [ 849 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1010101010101001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 870 ], + "B": [ 850 ], + "C": [ 828 ], + "D": [ 826 ], + "Z": [ 869 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_10": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001111001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 856 ], + "C": [ 854 ], + "D": [ 899 ], + "Z": [ 855 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_11": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 840 ], + "D": [ 900 ], + "Z": [ 839 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_11_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000001100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 838 ], + "C": [ 836 ], + "D": [ 885 ], + "Z": [ 900 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 852 ], + "D": [ 901 ], + "Z": [ 851 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 902 ], + "D1": [ 903 ], + "SD": [ 885 ], + "Z": [ 901 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 904 ], + "D1": [ 905 ], + "SD": [ 888 ], + "Z": [ 902 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 906 ], + "BLUT": [ 907 ], + "C0": [ 836 ], + "Z": [ 904 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 906 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 907 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 908 ], + "BLUT": [ 909 ], + "C0": [ 836 ], + "Z": [ 905 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 908 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 909 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 910 ], + "D1": [ 911 ], + "SD": [ 888 ], + "Z": [ 903 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 912 ], + "BLUT": [ 913 ], + "C0": [ 836 ], + "Z": [ 910 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 912 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 913 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 914 ], + "BLUT": [ 915 ], + "C0": [ 836 ], + "Z": [ 911 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 914 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 848 ], + "B": [ 846 ], + "C": [ 840 ], + "D": [ 838 ], + "Z": [ 915 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 852 ], + "D": [ 901 ], + "Z": [ 899 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 916 ], + "D1": [ 917 ], + "SD": [ 847 ], + "Z": [ 918 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 919 ], + "BLUT": [ 920 ], + "C0": [ 885 ], + "Z": [ 916 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 840 ], + "C": [ 836 ], + "D": [ 921 ], + "Z": [ 919 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000001100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 840 ], + "C": [ 836 ], + "D": [ 921 ], + "Z": [ 920 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0001000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 846 ], + "B": [ 838 ], + "C": [ 888 ], + "D": [ 922 ], + "Z": [ 921 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 864 ], + "B": [ 860 ], + "C": [ 856 ], + "D": [ 852 ], + "Z": [ 922 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 923 ], + "BLUT": [ 924 ], + "C0": [ 885 ], + "Z": [ 917 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 923 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 924 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_13": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1010100110101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 844 ], + "B": [ 842 ], + "C": [ 840 ], + "D": [ 900 ], + "Z": [ 843 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_14": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1010100110101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 858 ], + "B": [ 856 ], + "C": [ 854 ], + "D": [ 899 ], + "Z": [ 857 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111100011111010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 862 ], + "B": [ 860 ], + "C": [ 925 ], + "D": [ 926 ], + "Z": [ 861 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 927 ], + "D1": [ 928 ], + "SD": [ 901 ], + "Z": [ 925 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 929 ], + "D1": [ 930 ], + "SD": [ 852 ], + "Z": [ 927 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 931 ], + "BLUT": [ 932 ], + "C0": [ 854 ], + "Z": [ 929 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 931 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 932 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 933 ], + "BLUT": [ 934 ], + "C0": [ 854 ], + "Z": [ 930 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 933 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 934 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 935 ], + "D1": [ 936 ], + "SD": [ 852 ], + "Z": [ 928 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 937 ], + "BLUT": [ 938 ], + "C0": [ 854 ], + "Z": [ 935 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 937 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 862 ], + "B": [ 860 ], + "C": [ 858 ], + "D": [ 856 ], + "Z": [ 938 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 939 ], + "BLUT": [ 940 ], + "C0": [ 854 ], + "Z": [ 936 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 939 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 940 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 864 ], + "D": [ 925 ], + "Z": [ 941 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 942 ], + "D1": [ 943 ], + "SD": [ 918 ], + "Z": [ 944 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 945 ], + "D1": [ 946 ], + "SD": [ 899 ], + "Z": [ 942 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 947 ], + "BLUT": [ 948 ], + "C0": [ 854 ], + "Z": [ 945 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 947 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 948 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 949 ], + "BLUT": [ 950 ], + "C0": [ 854 ], + "Z": [ 946 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 949 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 950 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 951 ], + "D1": [ 952 ], + "SD": [ 899 ], + "Z": [ 943 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 953 ], + "BLUT": [ 954 ], + "C0": [ 854 ], + "Z": [ 951 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 953 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 862 ], + "D": [ 858 ], + "Z": [ 954 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 955 ], + "BLUT": [ 956 ], + "C0": [ 854 ], + "Z": [ 952 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 862 ], + "D": [ 858 ], + "Z": [ 955 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 956 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 871 ], + "B": [ 833 ], + "C": [ 831 ], + "D": [ 957 ], + "Z": [ 958 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000001000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 959 ], + "B": [ 833 ], + "C": [ 831 ], + "D": [ 957 ], + "Z": [ 960 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 961 ], + "C": [ 877 ], + "D": [ 881 ], + "Z": [ 957 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_D_LUT4_Z_B_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 830 ], + "B": [ 880 ], + "C": [ 876 ], + "D": [ 873 ], + "Z": [ 961 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_D_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 962 ], + "BLUT": [ 963 ], + "C0": [ 826 ], + "Z": [ 959 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_D_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 872 ], + "B": [ 870 ], + "C": [ 850 ], + "D": [ 828 ], + "Z": [ 962 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 963 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 858 ], + "B": [ 856 ], + "C": [ 854 ], + "D": [ 899 ], + "Z": [ 926 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_16": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001111001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 838 ], + "C": [ 836 ], + "D": [ 885 ], + "Z": [ 837 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_17": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 866 ], + "D": [ 941 ], + "Z": [ 865 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_18": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001111001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 868 ], + "C": [ 866 ], + "D": [ 941 ], + "Z": [ 867 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_19": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001111001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 880 ], + "C": [ 878 ], + "D": [ 964 ], + "Z": [ 879 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 828 ], + "D": [ 826 ], + "Z": [ 827 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_20": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1010100110101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 876 ], + "B": [ 874 ], + "C": [ 872 ], + "D": [ 965 ], + "Z": [ 875 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_21": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 864 ], + "D": [ 925 ], + "Z": [ 863 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_22": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001111001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 842 ], + "C": [ 840 ], + "D": [ 900 ], + "Z": [ 841 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_23": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 826 ], + "Z": [ 825 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_24": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 830 ], + "D": [ 966 ], + "Z": [ 829 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_25": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1001101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 846 ], + "B": [ 840 ], + "C": [ 888 ], + "D": [ 900 ], + "Z": [ 845 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_26": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 860 ], + "D": [ 926 ], + "Z": [ 859 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_27": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 854 ], + "D": [ 899 ], + "Z": [ 853 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 872 ], + "D": [ 965 ], + "Z": [ 871 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 876 ], + "B": [ 874 ], + "C": [ 872 ], + "D": [ 965 ], + "Z": [ 964 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 967 ], + "D1": [ 968 ], + "SD": [ 964 ], + "Z": [ 885 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 969 ], + "D1": [ 970 ], + "SD": [ 878 ], + "Z": [ 967 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 971 ], + "BLUT": [ 972 ], + "C0": [ 880 ], + "Z": [ 969 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 971 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 972 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 973 ], + "BLUT": [ 974 ], + "C0": [ 880 ], + "Z": [ 970 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 973 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 974 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 975 ], + "D1": [ 976 ], + "SD": [ 878 ], + "Z": [ 968 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 977 ], + "BLUT": [ 978 ], + "C0": [ 880 ], + "Z": [ 975 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 977 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 834 ], + "B": [ 832 ], + "C": [ 830 ], + "D": [ 882 ], + "Z": [ 978 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 979 ], + "BLUT": [ 980 ], + "C0": [ 880 ], + "Z": [ 976 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 979 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 980 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 844 ], + "D": [ 842 ], + "Z": [ 888 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 870 ], + "B": [ 850 ], + "C": [ 828 ], + "D": [ 826 ], + "Z": [ 965 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1010100110101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 834 ], + "B": [ 832 ], + "C": [ 830 ], + "D": [ 966 ], + "Z": [ 833 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_4_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 882 ], + "B": [ 880 ], + "C": [ 878 ], + "D": [ 964 ], + "Z": [ 966 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001111001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 874 ], + "C": [ 872 ], + "D": [ 965 ], + "Z": [ 873 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 878 ], + "D": [ 964 ], + "Z": [ 877 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_7": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1010100110101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 882 ], + "B": [ 880 ], + "C": [ 878 ], + "D": [ 964 ], + "Z": [ 881 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_8": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001111001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 832 ], + "C": [ 830 ], + "D": [ 966 ], + "Z": [ 831 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_9": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 836 ], + "D": [ 885 ], + "Z": [ 835 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 981 ], + "LSR": [ 3 ], + "Q": [ 27 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 27 ], + "D": [ 982 ], + "Z": [ 981 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 982 ], + "LSR": [ 983 ], + "Q": [ 31 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 27 ], + "D": [ 982 ], + "Z": [ 984 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 27 ], + "D": [ 982 ], + "Z": [ 985 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 986 ], + "D": [ 987 ], + "Z": [ 982 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 986 ], + "D": [ 987 ], + "Z": [ 988 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 989 ], + "C": [ 990 ], + "D": [ 991 ], + "Z": [ 992 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 990 ], + "D": [ 991 ], + "Z": [ 993 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 994 ], + "B": [ 989 ], + "C": [ 990 ], + "D": [ 991 ], + "Z": [ 995 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 994 ], + "B": [ 989 ], + "C": [ 990 ], + "D": [ 991 ], + "Z": [ 987 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 27 ], + "Z": [ 983 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 985 ], + "CLK": [ 2 ], + "DI": [ 996 ], + "LSR": [ 36 ], + "Q": [ 991 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 985 ], + "CLK": [ 2 ], + "DI": [ 993 ], + "LSR": [ 36 ], + "Q": [ 990 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 985 ], + "CLK": [ 2 ], + "DI": [ 992 ], + "LSR": [ 36 ], + "Q": [ 989 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 985 ], + "CLK": [ 2 ], + "DI": [ 995 ], + "LSR": [ 36 ], + "Q": [ 994 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 985 ], + "CLK": [ 2 ], + "DI": [ 988 ], + "LSR": [ 36 ], + "Q": [ 986 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 991 ], + "Z": [ 996 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8", + "module": "$paramod$24a3a7236073cb7c12a30999f26614228c51a089\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[4].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[4].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[5].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[5].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[6].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[6].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[7].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[7].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 984 ], + "CLK": [ 2 ], + "DI": [ 997 ], + "LSR": [ 3 ], + "Q": [ 17 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 984 ], + "CLK": [ 2 ], + "DI": [ 998 ], + "LSR": [ 3 ], + "Q": [ 18 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 999 ], + "D1": [ 1000 ], + "SD": [ 944 ], + "Z": [ 998 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1001 ], + "D1": [ 1002 ], + "SD": [ 941 ], + "Z": [ 999 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1003 ], + "BLUT": [ 1004 ], + "C0": [ 960 ], + "Z": [ 1001 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 868 ], + "Z": [ 1003 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 868 ], + "Z": [ 1004 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1005 ], + "BLUT": [ 1006 ], + "C0": [ 960 ], + "Z": [ 1002 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1005 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1006 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1007 ], + "D1": [ 1008 ], + "SD": [ 941 ], + "Z": [ 1000 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1009 ], + "BLUT": [ 1010 ], + "C0": [ 960 ], + "Z": [ 1007 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1009 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0100010101010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 868 ], + "B": [ 866 ], + "C": [ 826 ], + "D": [ 958 ], + "Z": [ 1010 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1011 ], + "BLUT": [ 1012 ], + "C0": [ 960 ], + "Z": [ 1008 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1011 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0010011001100110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 868 ], + "B": [ 866 ], + "C": [ 826 ], + "D": [ 958 ], + "Z": [ 1012 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 984 ], + "CLK": [ 2 ], + "DI": [ 1013 ], + "LSR": [ 3 ], + "Q": [ 19 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1014 ], + "D1": [ 1015 ], + "SD": [ 944 ], + "Z": [ 1013 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1016 ], + "D1": [ 1017 ], + "SD": [ 941 ], + "Z": [ 1014 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1018 ], + "BLUT": [ 1019 ], + "C0": [ 960 ], + "Z": [ 1016 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 868 ], + "Z": [ 1018 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 868 ], + "Z": [ 1019 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1020 ], + "BLUT": [ 1021 ], + "C0": [ 960 ], + "Z": [ 1017 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1020 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1021 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1022 ], + "D1": [ 1023 ], + "SD": [ 941 ], + "Z": [ 1015 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1024 ], + "BLUT": [ 1025 ], + "C0": [ 960 ], + "Z": [ 1022 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1024 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0101010001010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 868 ], + "B": [ 866 ], + "C": [ 827 ], + "D": [ 958 ], + "Z": [ 1025 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1026 ], + "BLUT": [ 1027 ], + "C0": [ 960 ], + "Z": [ 1023 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1026 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110001001100110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 868 ], + "B": [ 866 ], + "C": [ 827 ], + "D": [ 958 ], + "Z": [ 1027 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 984 ], + "CLK": [ 2 ], + "DI": [ 1028 ], + "LSR": [ 3 ], + "Q": [ 20 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1029 ], + "D1": [ 1030 ], + "SD": [ 944 ], + "Z": [ 1028 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1031 ], + "D1": [ 1032 ], + "SD": [ 941 ], + "Z": [ 1029 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1033 ], + "BLUT": [ 1034 ], + "C0": [ 960 ], + "Z": [ 1031 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 868 ], + "Z": [ 1033 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 868 ], + "Z": [ 1034 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1035 ], + "BLUT": [ 1036 ], + "C0": [ 960 ], + "Z": [ 1032 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1035 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1036 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1037 ], + "D1": [ 1038 ], + "SD": [ 941 ], + "Z": [ 1030 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1039 ], + "BLUT": [ 1040 ], + "C0": [ 960 ], + "Z": [ 1037 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1039 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0101010001010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 868 ], + "B": [ 866 ], + "C": [ 849 ], + "D": [ 958 ], + "Z": [ 1040 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1041 ], + "BLUT": [ 1042 ], + "C0": [ 960 ], + "Z": [ 1038 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1041 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110001001100110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 868 ], + "B": [ 866 ], + "C": [ 849 ], + "D": [ 958 ], + "Z": [ 1042 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 984 ], + "CLK": [ 2 ], + "DI": [ 1043 ], + "LSR": [ 3 ], + "Q": [ 21 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1044 ], + "D1": [ 1045 ], + "SD": [ 944 ], + "Z": [ 1043 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1046 ], + "D1": [ 1047 ], + "SD": [ 941 ], + "Z": [ 1044 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1048 ], + "BLUT": [ 1049 ], + "C0": [ 960 ], + "Z": [ 1046 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 868 ], + "Z": [ 1048 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 868 ], + "Z": [ 1049 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1050 ], + "BLUT": [ 1051 ], + "C0": [ 960 ], + "Z": [ 1047 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1050 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1051 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1052 ], + "D1": [ 1053 ], + "SD": [ 941 ], + "Z": [ 1045 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1054 ], + "BLUT": [ 1055 ], + "C0": [ 960 ], + "Z": [ 1052 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1054 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0101010001010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 868 ], + "B": [ 866 ], + "C": [ 869 ], + "D": [ 958 ], + "Z": [ 1055 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1056 ], + "BLUT": [ 1057 ], + "C0": [ 960 ], + "Z": [ 1053 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 868 ], + "D": [ 866 ], + "Z": [ 1056 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110001001100110" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 868 ], + "B": [ 866 ], + "C": [ 869 ], + "D": [ 958 ], + "Z": [ 1057 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1058 ], + "BLUT": [ 1059 ], + "C0": [ 944 ], + "Z": [ 997 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0010011001000101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 868 ], + "B": [ 866 ], + "C": [ 958 ], + "D": [ 941 ], + "Z": [ 1058 ] + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110000110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 868 ], + "C": [ 866 ], + "D": [ 941 ], + "Z": [ 1059 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:41.15-72.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron", + "module": "$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\\neuron_parallel", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "neuron_parallel", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:1.1-148.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1060 ], + "LSR": [ 35 ], + "Q": [ 1061 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1062 ], + "LSR": [ 35 ], + "Q": [ 1063 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_10": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1064 ], + "LSR": [ 35 ], + "Q": [ 1065 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_11": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1066 ], + "LSR": [ 35 ], + "Q": [ 1067 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_12": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1068 ], + "LSR": [ 35 ], + "Q": [ 1069 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_13": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1070 ], + "LSR": [ 35 ], + "Q": [ 1071 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_14": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1072 ], + "LSR": [ 35 ], + "Q": [ 1073 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_15": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1074 ], + "LSR": [ 35 ], + "Q": [ 1075 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_16": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1076 ], + "LSR": [ 35 ], + "Q": [ 1077 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_17": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1078 ], + "LSR": [ 35 ], + "Q": [ 1079 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_18": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1080 ], + "LSR": [ 35 ], + "Q": [ 1081 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_19": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1082 ], + "LSR": [ 35 ], + "Q": [ 1083 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1084 ], + "LSR": [ 35 ], + "Q": [ 1085 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_20": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1086 ], + "LSR": [ 35 ], + "Q": [ 1087 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_21": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1088 ], + "LSR": [ 35 ], + "Q": [ 1089 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_22": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1090 ], + "LSR": [ 35 ], + "Q": [ 1091 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_23": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1092 ], + "LSR": [ 35 ], + "Q": [ 1093 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_24": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1094 ], + "LSR": [ 35 ], + "Q": [ 1095 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_25": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1096 ], + "LSR": [ 35 ], + "Q": [ 1097 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_26": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1098 ], + "LSR": [ 35 ], + "Q": [ 1099 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1100 ], + "LSR": [ 35 ], + "Q": [ 1101 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1102 ], + "LSR": [ 35 ], + "Q": [ 1103 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_5": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1104 ], + "LSR": [ 35 ], + "Q": [ 1105 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_6": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1106 ], + "LSR": [ 35 ], + "Q": [ 1107 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_7": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1108 ], + "LSR": [ 35 ], + "Q": [ 1109 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_8": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1110 ], + "LSR": [ 35 ], + "Q": [ 1111 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_TRELLIS_FF_Q_9": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 29 ], + "CLK": [ 2 ], + "DI": [ 1112 ], + "LSR": [ 35 ], + "Q": [ 1113 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1114 ], + "D1": [ 1115 ], + "SD": [ 1116 ], + "Z": [ 1082 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1117 ], + "D1": [ 1118 ], + "SD": [ 1073 ], + "Z": [ 1114 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1119 ], + "BLUT": [ 1120 ], + "C0": [ 1075 ], + "Z": [ 1117 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1119 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1120 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1121 ], + "BLUT": [ 1122 ], + "C0": [ 1075 ], + "Z": [ 1118 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1121 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1122 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1123 ], + "D1": [ 1124 ], + "SD": [ 1073 ], + "Z": [ 1115 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1125 ], + "BLUT": [ 1126 ], + "C0": [ 1075 ], + "Z": [ 1123 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1125 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1126 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1127 ], + "BLUT": [ 1128 ], + "C0": [ 1075 ], + "Z": [ 1124 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1083 ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1077 ], + "Z": [ 1127 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1128 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1095 ], + "D": [ 1129 ], + "Z": [ 1094 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1077 ], + "B": [ 1075 ], + "C": [ 1073 ], + "D": [ 1116 ], + "Z": [ 1076 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_10": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1063 ], + "B": [ 1061 ], + "C": [ 1069 ], + "D": [ 1130 ], + "Z": [ 1062 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_11": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1085 ], + "D": [ 1131 ], + "Z": [ 1084 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_12": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1079 ], + "D": [ 1132 ], + "Z": [ 1078 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_13": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1101 ], + "D": [ 1133 ], + "Z": [ 1100 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_13_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1085 ], + "D": [ 1131 ], + "Z": [ 1133 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_14": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1075 ], + "C": [ 1073 ], + "D": [ 1116 ], + "Z": [ 1074 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_15": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1103 ], + "C": [ 1101 ], + "D": [ 1133 ], + "Z": [ 1102 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_16": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1111 ], + "D": [ 1134 ], + "Z": [ 1110 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_16_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1109 ], + "C": [ 1105 ], + "D": [ 1135 ], + "Z": [ 1134 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1109 ], + "C": [ 1105 ], + "D": [ 1135 ], + "Z": [ 1108 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1136 ], + "D1": [ 1137 ], + "SD": [ 1130 ], + "Z": [ 1135 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1138 ], + "D1": [ 1139 ], + "SD": [ 1069 ], + "Z": [ 1136 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1140 ], + "BLUT": [ 1141 ], + "C0": [ 1061 ], + "Z": [ 1138 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1140 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1141 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1142 ], + "BLUT": [ 1143 ], + "C0": [ 1061 ], + "Z": [ 1139 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1142 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1143 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1144 ], + "D1": [ 1145 ], + "SD": [ 1069 ], + "Z": [ 1137 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1146 ], + "BLUT": [ 1147 ], + "C0": [ 1061 ], + "Z": [ 1144 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1146 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1147 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1148 ], + "BLUT": [ 1149 ], + "C0": [ 1061 ], + "Z": [ 1145 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1103 ], + "B": [ 1101 ], + "C": [ 1085 ], + "D": [ 1063 ], + "Z": [ 1148 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1149 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1150 ], + "BLUT": [ 1151 ], + "C0": [ 1135 ], + "Z": [ 1152 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000100010001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1113 ], + "B": [ 1111 ], + "C": [ 1109 ], + "D": [ 1105 ], + "Z": [ 1150 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1113 ], + "D": [ 1111 ], + "Z": [ 1151 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1153 ], + "D1": [ 1154 ], + "SD": [ 1155 ], + "Z": [ 1156 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1157 ], + "D1": [ 1158 ], + "SD": [ 1159 ], + "Z": [ 1160 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1161 ], + "BLUT": [ 1162 ], + "C0": [ 1067 ], + "Z": [ 1157 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1077 ], + "D": [ 1075 ], + "Z": [ 1161 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1077 ], + "D": [ 1075 ], + "Z": [ 1162 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1163 ], + "BLUT": [ 1164 ], + "C0": [ 1067 ], + "Z": [ 1158 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000100010001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1077 ], + "B": [ 1075 ], + "C": [ 1073 ], + "D": [ 1071 ], + "Z": [ 1163 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1077 ], + "D": [ 1075 ], + "Z": [ 1164 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1165 ], + "D1": [ 1166 ], + "SD": [ 1135 ], + "Z": [ 1167 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1168 ], + "D1": [ 1169 ], + "SD": [ 1105 ], + "Z": [ 1165 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1170 ], + "BLUT": [ 1171 ], + "C0": [ 1109 ], + "Z": [ 1168 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1067 ], + "D": [ 1065 ], + "Z": [ 1170 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1067 ], + "D": [ 1065 ], + "Z": [ 1171 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1172 ], + "BLUT": [ 1173 ], + "C0": [ 1109 ], + "Z": [ 1169 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1067 ], + "D": [ 1065 ], + "Z": [ 1172 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1067 ], + "D": [ 1065 ], + "Z": [ 1173 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1174 ], + "D1": [ 1175 ], + "SD": [ 1105 ], + "Z": [ 1166 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1176 ], + "BLUT": [ 1177 ], + "C0": [ 1109 ], + "Z": [ 1174 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1067 ], + "D": [ 1065 ], + "Z": [ 1176 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1067 ], + "D": [ 1065 ], + "Z": [ 1177 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1178 ], + "BLUT": [ 1179 ], + "C0": [ 1109 ], + "Z": [ 1175 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000100010001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1067 ], + "B": [ 1065 ], + "C": [ 1113 ], + "D": [ 1111 ], + "Z": [ 1178 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1067 ], + "D": [ 1065 ], + "Z": [ 1179 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1180 ], + "D1": [ 1181 ], + "SD": [ 1116 ], + "Z": [ 1182 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1183 ], + "BLUT": [ 1184 ], + "C0": [ 1073 ], + "Z": [ 1180 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1081 ], + "D": [ 1079 ], + "Z": [ 1183 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1081 ], + "D": [ 1079 ], + "Z": [ 1184 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1185 ], + "BLUT": [ 1186 ], + "C0": [ 1073 ], + "Z": [ 1181 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000100010001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1081 ], + "B": [ 1079 ], + "C": [ 1077 ], + "D": [ 1075 ], + "Z": [ 1185 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1081 ], + "D": [ 1079 ], + "Z": [ 1186 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1187 ], + "D1": [ 1188 ], + "SD": [ 1131 ], + "Z": [ 1153 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1189 ], + "BLUT": [ 1190 ], + "C0": [ 1085 ], + "Z": [ 1187 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1189 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1190 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1191 ], + "BLUT": [ 1192 ], + "C0": [ 1085 ], + "Z": [ 1188 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1191 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1192 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1193 ], + "D1": [ 1194 ], + "SD": [ 1131 ], + "Z": [ 1154 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1195 ], + "BLUT": [ 1196 ], + "C0": [ 1085 ], + "Z": [ 1193 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1109 ], + "B": [ 1105 ], + "C": [ 1103 ], + "D": [ 1101 ], + "Z": [ 1195 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1109 ], + "B": [ 1105 ], + "C": [ 1103 ], + "D": [ 1101 ], + "Z": [ 1196 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1197 ], + "BLUT": [ 1198 ], + "C0": [ 1085 ], + "Z": [ 1194 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1109 ], + "B": [ 1105 ], + "C": [ 1103 ], + "D": [ 1101 ], + "Z": [ 1197 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1109 ], + "B": [ 1105 ], + "C": [ 1103 ], + "D": [ 1101 ], + "Z": [ 1198 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000100010001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1073 ], + "B": [ 1071 ], + "C": [ 1067 ], + "D": [ 1159 ], + "Z": [ 1199 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_18": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1113 ], + "D": [ 1200 ], + "Z": [ 1112 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_19": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1073 ], + "D": [ 1116 ], + "Z": [ 1072 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1077 ], + "B": [ 1075 ], + "C": [ 1073 ], + "D": [ 1116 ], + "Z": [ 1132 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1087 ], + "B": [ 1201 ], + "C": [ 1202 ], + "D": [ 1203 ], + "Z": [ 1204 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D_LUT4_D_Z_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1205 ], + "BLUT": [ 1206 ], + "C0": [ 1160 ], + "Z": [ 1207 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D_LUT4_D_Z_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1167 ], + "B": [ 1152 ], + "C": [ 1156 ], + "D": [ 1199 ], + "Z": [ 1205 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1206 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1071 ], + "C": [ 1067 ], + "D": [ 1159 ], + "Z": [ 1116 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1132 ], + "Z": [ 1080 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1091 ], + "D": [ 1208 ], + "Z": [ 1090 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1209 ], + "D1": [ 1210 ], + "SD": [ 1208 ], + "Z": [ 1130 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1211 ], + "D1": [ 1212 ], + "SD": [ 1208 ], + "Z": [ 1213 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1214 ], + "D1": [ 1215 ], + "SD": [ 1091 ], + "Z": [ 1211 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1216 ], + "BLUT": [ 1217 ], + "C0": [ 1093 ], + "Z": [ 1214 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1216 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1107 ], + "B": [ 1099 ], + "C": [ 1097 ], + "D": [ 1095 ], + "Z": [ 1217 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1218 ], + "BLUT": [ 1219 ], + "C0": [ 1093 ], + "Z": [ 1215 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1218 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1219 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1220 ], + "D1": [ 1221 ], + "SD": [ 1091 ], + "Z": [ 1212 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1222 ], + "BLUT": [ 1223 ], + "C0": [ 1093 ], + "Z": [ 1220 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1222 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1223 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1224 ], + "BLUT": [ 1225 ], + "C0": [ 1093 ], + "Z": [ 1221 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1107 ], + "B": [ 1099 ], + "C": [ 1097 ], + "D": [ 1095 ], + "Z": [ 1224 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1225 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:153.19-153.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1226 ], + "BLUT": [ 1227 ], + "C0": [ 1213 ], + "Z": [ 1228 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:149.39-150.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1085 ], + "B": [ 1063 ], + "C": [ 1061 ], + "D": [ 1069 ], + "Z": [ 1226 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:147.39-148.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1227 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_D1": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:154.21-154.62" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1229 ], + "D1": [ 1228 ], + "SD": [ 1130 ], + "Z": [ 1155 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_D1_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:152.19-152.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1230 ], + "BLUT": [ 1231 ], + "C0": [ 1213 ], + "Z": [ 1229 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000001" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:144.39-145.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1085 ], + "B": [ 1063 ], + "C": [ 1061 ], + "D": [ 1069 ], + "Z": [ 1230 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:142.39-143.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1231 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_D1_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1063 ], + "B": [ 1061 ], + "C": [ 1069 ], + "D": [ 1130 ], + "Z": [ 1131 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1232 ], + "D1": [ 1233 ], + "SD": [ 1091 ], + "Z": [ 1209 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1234 ], + "BLUT": [ 1235 ], + "C0": [ 1093 ], + "Z": [ 1232 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1234 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1235 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1236 ], + "BLUT": [ 1237 ], + "C0": [ 1093 ], + "Z": [ 1233 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1236 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1237 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1238 ], + "D1": [ 1239 ], + "SD": [ 1091 ], + "Z": [ 1210 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1240 ], + "BLUT": [ 1241 ], + "C0": [ 1093 ], + "Z": [ 1238 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1240 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1241 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1242 ], + "BLUT": [ 1243 ], + "C0": [ 1093 ], + "Z": [ 1239 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1107 ], + "B": [ 1099 ], + "C": [ 1097 ], + "D": [ 1095 ], + "Z": [ 1242 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1243 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:138.19-138.63" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1244 ], + "BLUT": [ 1245 ], + "C0": [ 1203 ], + "Z": [ 1208 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:136.39-137.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1244 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000001000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:134.39-135.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1089 ], + "B": [ 1087 ], + "C": [ 1201 ], + "D": [ 1202 ], + "Z": [ 1245 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_21": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1067 ], + "D": [ 1159 ], + "Z": [ 1066 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_22": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1105 ], + "D": [ 1135 ], + "Z": [ 1104 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_23": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1093 ], + "C": [ 1091 ], + "D": [ 1208 ], + "Z": [ 1092 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_24": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1061 ], + "C": [ 1069 ], + "D": [ 1130 ], + "Z": [ 1060 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_25": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1069 ], + "D": [ 1130 ], + "Z": [ 1068 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_3": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1097 ], + "C": [ 1095 ], + "D": [ 1129 ], + "Z": [ 1096 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_4": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1071 ], + "C": [ 1067 ], + "D": [ 1159 ], + "Z": [ 1070 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_5": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1099 ], + "B": [ 1097 ], + "C": [ 1095 ], + "D": [ 1129 ], + "Z": [ 1098 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_6": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111100001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1087 ], + "C": [ 1204 ], + "D": [ 1246 ], + "Z": [ 1086 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_6_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1201 ], + "C": [ 1202 ], + "D": [ 1203 ], + "Z": [ 1246 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1107 ], + "C": [ 1247 ], + "D": [ 1130 ], + "Z": [ 1106 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1248 ], + "D1": [ 1249 ], + "SD": [ 1247 ], + "Z": [ 1250 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1251 ], + "D1": [ 1252 ], + "SD": [ 1107 ], + "Z": [ 1248 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1253 ], + "BLUT": [ 1254 ], + "C0": [ 1069 ], + "Z": [ 1251 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1253 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1254 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1255 ], + "BLUT": [ 1256 ], + "C0": [ 1069 ], + "Z": [ 1252 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1255 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1256 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1257 ], + "D1": [ 1258 ], + "SD": [ 1107 ], + "Z": [ 1249 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1259 ], + "BLUT": [ 1260 ], + "C0": [ 1069 ], + "Z": [ 1257 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1259 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1260 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1261 ], + "BLUT": [ 1262 ], + "C0": [ 1069 ], + "Z": [ 1258 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1101 ], + "B": [ 1085 ], + "C": [ 1063 ], + "D": [ 1061 ], + "Z": [ 1261 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1262 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1263 ], + "D1": [ 1264 ], + "SD": [ 1250 ], + "Z": [ 1159 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1265 ], + "D1": [ 1266 ], + "SD": [ 1103 ], + "Z": [ 1263 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1267 ], + "BLUT": [ 1268 ], + "C0": [ 1105 ], + "Z": [ 1265 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1267 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1268 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1269 ], + "BLUT": [ 1270 ], + "C0": [ 1105 ], + "Z": [ 1266 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1269 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1270 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1271 ], + "D1": [ 1272 ], + "SD": [ 1103 ], + "Z": [ 1264 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1273 ], + "BLUT": [ 1274 ], + "C0": [ 1105 ], + "Z": [ 1271 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1273 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1274 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1275 ], + "BLUT": [ 1276 ], + "C0": [ 1105 ], + "Z": [ 1272 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1065 ], + "B": [ 1113 ], + "C": [ 1111 ], + "D": [ 1109 ], + "Z": [ 1275 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1276 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1277 ], + "D1": [ 1278 ], + "SD": [ 1204 ], + "Z": [ 1247 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1279 ], + "D1": [ 1280 ], + "SD": [ 1089 ], + "Z": [ 1277 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1281 ], + "BLUT": [ 1282 ], + "C0": [ 1091 ], + "Z": [ 1279 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1281 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1282 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1283 ], + "BLUT": [ 1284 ], + "C0": [ 1091 ], + "Z": [ 1280 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1283 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1284 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1285 ], + "D1": [ 1286 ], + "SD": [ 1089 ], + "Z": [ 1278 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1287 ], + "BLUT": [ 1288 ], + "C0": [ 1091 ], + "Z": [ 1285 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1287 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1288 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1289 ], + "BLUT": [ 1290 ], + "C0": [ 1091 ], + "Z": [ 1286 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1099 ], + "B": [ 1097 ], + "C": [ 1095 ], + "D": [ 1093 ], + "Z": [ 1289 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1290 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_8": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1089 ], + "D": [ 1204 ], + "Z": [ 1088 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_9": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111000001010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1065 ], + "B": [ 1113 ], + "C": [ 1159 ], + "D": [ 1200 ], + "Z": [ 1064 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_9_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1111 ], + "D": [ 1134 ], + "Z": [ 1200 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1093 ], + "C": [ 1091 ], + "D": [ 1208 ], + "Z": [ 1129 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1291 ], + "LSR": [ 3 ], + "Q": [ 29 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000110011111100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 4 ], + "C": [ 29 ], + "D": [ 1292 ], + "Z": [ 1291 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "1 ", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:68.164-68.215" + }, + "port_directions": { + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CLK": [ 2 ], + "DI": [ 1292 ], + "LSR": [ 1293 ], + "Q": [ 33 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 29 ], + "D": [ 1292 ], + "Z": [ 1294 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1201 ], + "D": [ 1295 ], + "Z": [ 1292 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1201 ], + "D": [ 1295 ], + "Z": [ 1296 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 1297 ], + "D": [ 1298 ], + "Z": [ 1299 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0110101010101010" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1202 ], + "B": [ 1203 ], + "C": [ 1297 ], + "D": [ 1298 ], + "Z": [ 1300 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_2": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0011110011001100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:124.33-125.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1203 ], + "C": [ 1297 ], + "D": [ 1298 ], + "Z": [ 1301 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:128.32-129.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1202 ], + "B": [ 1203 ], + "C": [ 1297 ], + "D": [ 1298 ], + "Z": [ 1295 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_LSR_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 3 ], + "D": [ 29 ], + "Z": [ 1293 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1294 ], + "CLK": [ 2 ], + "DI": [ 1302 ], + "LSR": [ 35 ], + "Q": [ 1298 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1294 ], + "CLK": [ 2 ], + "DI": [ 1299 ], + "LSR": [ 35 ], + "Q": [ 1297 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1294 ], + "CLK": [ 2 ], + "DI": [ 1301 ], + "LSR": [ 35 ], + "Q": [ 1203 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_3": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1294 ], + "CLK": [ 2 ], + "DI": [ 1300 ], + "LSR": [ 35 ], + "Q": [ 1202 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_4": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1294 ], + "CLK": [ 2 ], + "DI": [ 1296 ], + "LSR": [ 35 ], + "Q": [ 1201 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:114.33-115.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1298 ], + "Z": [ 1302 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:81.7-86.6", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8", + "module": "$paramod$24a3a7236073cb7c12a30999f26614228c51a089\\mac8", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac8", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:1.1-117.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[4].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[4].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[5].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[5].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[6].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[6].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[7].u_mac": { + "hide_name": 0, + "type": "$scopeinfo", + "parameters": { + "TYPE": "module" + }, + "attributes": { + "cell_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:25.15-42.14", + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[7].u_mac", + "module": "$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\\mac_unit", + "module_dynports": "00000000000000000000000000000001", + "module_hdlname": "mac_unit", + "module_src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:1.1-23.10" + }, + "port_directions": { + }, + "connections": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1303 ], + "CLK": [ 2 ], + "DI": [ 1304 ], + "LSR": [ 3 ], + "Q": [ 22 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1303 ], + "CLK": [ 2 ], + "DI": [ 1305 ], + "LSR": [ 3 ], + "Q": [ 23 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1306 ], + "D1": [ 1307 ], + "SD": [ 1207 ], + "Z": [ 1305 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1308 ], + "D1": [ 1309 ], + "SD": [ 1132 ], + "Z": [ 1306 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1310 ], + "BLUT": [ 1311 ], + "C0": [ 1246 ], + "Z": [ 1308 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1310 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1311 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1312 ], + "BLUT": [ 1313 ], + "C0": [ 1246 ], + "Z": [ 1309 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1083 ], + "C": [ 1081 ], + "D": [ 1079 ], + "Z": [ 1312 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1083 ], + "C": [ 1081 ], + "D": [ 1079 ], + "Z": [ 1313 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1314 ], + "D1": [ 1315 ], + "SD": [ 1132 ], + "Z": [ 1307 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1316 ], + "BLUT": [ 1317 ], + "C0": [ 1246 ], + "Z": [ 1314 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0101010001010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1083 ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1087 ], + "Z": [ 1316 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0101010101010100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1083 ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1087 ], + "Z": [ 1317 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1318 ], + "BLUT": [ 1319 ], + "C0": [ 1246 ], + "Z": [ 1315 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0001010110010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1083 ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1087 ], + "Z": [ 1318 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1001010100010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1083 ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1087 ], + "Z": [ 1319 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2": { + "hide_name": 0, + "type": "TRELLIS_FF", + "parameters": { + "CEMUX": "CE", + "CLKMUX": "CLK", + "GSR": "DISABLED", + "LSRMUX": "LSR", + "REGSET": "RESET", + "SRMODE": "LSR_OVER_CE" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95.5-146.8|/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:83.170-83.229" + }, + "port_directions": { + "CE": "input", + "CLK": "input", + "DI": "input", + "LSR": "input", + "Q": "output" + }, + "connections": { + "CE": [ 1303 ], + "CLK": [ 2 ], + "DI": [ 1320 ], + "LSR": [ 3 ], + "Q": [ 24 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1321 ], + "D1": [ 1322 ], + "SD": [ 1207 ], + "Z": [ 1320 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1323 ], + "D1": [ 1324 ], + "SD": [ 1132 ], + "Z": [ 1321 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1325 ], + "BLUT": [ 1326 ], + "C0": [ 1204 ], + "Z": [ 1323 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1325 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ 1083 ], + "Z": [ 1326 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1327 ], + "BLUT": [ 1328 ], + "C0": [ 1204 ], + "Z": [ 1324 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1083 ], + "C": [ 1081 ], + "D": [ 1079 ], + "Z": [ 1327 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1100001100110011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ 1083 ], + "C": [ 1081 ], + "D": [ 1079 ], + "Z": [ 1328 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1329 ], + "D1": [ 1330 ], + "SD": [ 1132 ], + "Z": [ 1322 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1331 ], + "BLUT": [ 1332 ], + "C0": [ 1204 ], + "Z": [ 1329 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0101010001010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1083 ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1089 ], + "Z": [ 1331 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0101010101010100" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1083 ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1089 ], + "Z": [ 1332 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1333 ], + "BLUT": [ 1334 ], + "C0": [ 1204 ], + "Z": [ 1330 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0001010110010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1083 ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1089 ], + "Z": [ 1333 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1001010100010101" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1083 ], + "B": [ 1081 ], + "C": [ 1079 ], + "D": [ 1089 ], + "Z": [ 1334 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_CE_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:119.33-120.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ 29 ], + "D": [ 1292 ], + "Z": [ 1303 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:184.21-184.63" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1335 ], + "D1": [ 1336 ], + "SD": [ 1182 ], + "Z": [ 1304 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:182.21-182.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1337 ], + "D1": [ 1338 ], + "SD": [ 1082 ], + "Z": [ 1335 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:178.19-178.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1339 ], + "BLUT": [ 1340 ], + "C0": [ 1160 ], + "Z": [ 1337 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:160.39-161.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1339 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:158.39-159.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1340 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:179.19-179.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1341 ], + "BLUT": [ 1342 ], + "C0": [ 1160 ], + "Z": [ 1338 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:165.39-166.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1341 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:163.39-164.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1342 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z": { + "hide_name": 0, + "type": "L6MUX21", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:183.21-183.64" + }, + "port_directions": { + "D0": "input", + "D1": "input", + "SD": "input", + "Z": "output" + }, + "connections": { + "D0": [ 1343 ], + "D1": [ 1344 ], + "SD": [ 1082 ], + "Z": [ 1336 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:180.19-180.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1345 ], + "BLUT": [ 1346 ], + "C0": [ 1160 ], + "Z": [ 1343 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:170.39-171.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ 1167 ], + "B": [ 1152 ], + "C": [ 1156 ], + "D": [ 1199 ], + "Z": [ 1345 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "1111111111111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:168.39-169.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1346 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z": { + "hide_name": 0, + "type": "PFUMX", + "parameters": { + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:181.19-181.65" + }, + "port_directions": { + "ALUT": "input", + "BLUT": "input", + "C0": "input", + "Z": "output" + }, + "connections": { + "ALUT": [ 1347 ], + "BLUT": [ 1348 ], + "C0": [ 1160 ], + "Z": [ 1344 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:175.41-176.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1347 ] + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z": { + "hide_name": 0, + "type": "LUT4", + "parameters": { + "INIT": "0000000000000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:173.41-174.56" + }, + "port_directions": { + "A": "input", + "B": "input", + "C": "input", + "D": "input", + "Z": "output" + }, + "connections": { + "A": [ "0" ], + "B": [ "0" ], + "C": [ "0" ], + "D": [ "0" ], + "Z": [ 1348 ] + } + } + }, + "netnames": { + "bias_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:19.43-19.51" + } + }, + "busy": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:7.12-7.16" + } + }, + "clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:2.11-2.14" + } + }, + "done": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:8.12-8.16" + } + }, + "i": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:21.13-21.14" + } + }, + "rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:3.11-3.14" + } + }, + "start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:4.11-4.16" + } + }, + "start_LUT4_B_1_Z": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + } + }, + "start_LUT4_B_2_Z": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + } + }, + "start_LUT4_B_Z": { + "hide_name": 0, + "bits": [ 35 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc": { + "hide_name": 0, + "bits": [ "0", "0", "0", 81, 39, 41, 63, 83, 85, 87, 89, 91, 93, 95, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 65, 67, 69, 71, 73, 75, 77, 79 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ "0", "0", "0", 80, 38, 40, 62, 82, 84, 86, 88, 90, 92, 94, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 64, 66, 68, 70, 72, 74, 76, 78 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D0": { + "hide_name": 0, + "bits": [ 99 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 101 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 102 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D1": { + "hide_name": 0, + "bits": [ 100 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 103 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_1_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 104 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 96 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 105 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 107 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 108 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 106 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 109 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 110 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 111 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 113 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 112 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 116 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C": { + "hide_name": 0, + "bits": [ 75, 73, 71, 69, 98 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 129 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 130 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 131 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 133 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 134 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 132 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 135 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D": { + "hide_name": 0, + "bits": [ 75, 73, 71, 69, 67, 122, 140 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D0": { + "hide_name": 0, + "bits": [ 141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D1": { + "hide_name": 0, + "bits": [ 142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_1_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 152 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 155 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 156 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD": { + "hide_name": 0, + "bits": [ 65, 61, 59, 57, 55, 120, 139 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 159 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 160 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_15_D_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_16_D": { + "hide_name": 0, + "bits": [ 63, 175 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_17_D": { + "hide_name": 0, + "bits": [ 73, 71, 177 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D": { + "hide_name": 0, + "bits": [ 89, 87, 85, 83, 63, 41, 176 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 182 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 43, 95, 93, 91, 89, 118, 180 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 199 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 200 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 201 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 203 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 204 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 202 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 53, 51, 49, 47, 45, 164, 161 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 207 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 208 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 213 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_18_D_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D": { + "hide_name": 0, + "bits": [ 87, 85, 83, 63, 41, 39, 218 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_19_D_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 43, 95, 93, 91, 89, 118 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_2_D": { + "hide_name": 0, + "bits": [ 95, 93, 91, 233 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C": { + "hide_name": 0, + "bits": [ 53, 51, 49, 47, 45, 43, 234 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 235 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 237 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 239 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 240 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 238 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 241 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 242 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 236 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 243 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 245 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 246 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 244 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 247 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 248 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 65, 61, 59, 57, 55, 120 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 249 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 251 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 253 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 254 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 252 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 255 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 256 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 250 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 257 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 259 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 260 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 258 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 261 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_5_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 262 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_7_D": { + "hide_name": 0, + "bits": [ 47, 263 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_7_D_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 53, 51, 49, 119 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_8_D": { + "hide_name": 0, + "bits": [ 65, 61, 59, 57, 121 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 95, 93, 91, 89, 87, 85, 117 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 264 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 267 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 269 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 270 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 268 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 271 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 272 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 265 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 273 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 275 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 276 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 274 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 277 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 278 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_C_L6MUX21_Z_SD": { + "hide_name": 0, + "bits": [ 83, 63, 41, 39, 216, 81, 266 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z_1_ALUT": { + "hide_name": 0, + "bits": [ 281 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z_1_BLUT": { + "hide_name": 0, + "bits": [ 282 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 279 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.acc_next_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 280 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy": { + "hide_name": 0, + "bits": [ 30 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 283 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done": { + "hide_name": 0, + "bits": [ 34 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 4, 30, 284 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z": { + "hide_name": 0, + "bits": [ 287 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 286 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 216, 288 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 295, 293, 292, 294, 289 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/techmap.v:270.26-270.27" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 285 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ "0", "0", "0", 80, 38, 40, 62, 82, 84, 86, 88, 90, 92, 94, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 64, 66, 68, 70, 72, 74, 76, 78 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 291, 290, 215, 217, 216 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.group_index_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 295, 290, 215, 217, 216 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/techmap.v:287.21-287.22" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.product": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.w": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[2].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[2].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.product": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.w": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[3].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[3].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[4].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[4].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[4].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[4].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[4].u_mac.product": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[4].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[4].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[4].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[4].u_mac.w": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[4].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[4].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[4].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[5].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[5].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[5].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[5].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[5].u_mac.product": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[5].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[5].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[5].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[5].u_mac.w": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[5].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[5].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[5].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[6].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[6].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[6].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[6].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[6].u_mac.product": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[6].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[6].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[6].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[6].u_mac.w": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[6].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[6].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[6].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[7].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[7].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[7].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[7].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[7].u_mac.product": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[7].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[7].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[7].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[7].u_mac.w": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[7].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[7].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 GEN_MAC[7].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", 81, 39, 41, 63, 83, 85, 87, 89, 91, 93, 95, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 65, 67, 69, 71, 73, 75, 77, 79 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", 80, 38, 40, 62, 82, 84, 86, 88, 90, 92, 94, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 64, 66, 68, 70, 72, 74, 76, 78 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[2]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[3]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[4]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[5]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[6]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[6]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[7]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 products[7]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[10]": { + "hide_name": 0, + "bits": [ "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[10]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[11]": { + "hide_name": 0, + "bits": [ "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[11]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[16]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[16]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[17]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[17]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[24]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[24]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[3]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[4]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[5]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[6]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[6]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[7]": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[7]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[8]": { + "hide_name": 0, + "bits": [ "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[8]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.tree[9]": { + "hide_name": 0, + "bits": [ "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 tree[9]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y": { + "hide_name": 0, + "bits": [ 5, 5, 5, 6, 7, 8, 9, "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[0].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_1_DI": { + "hide_name": 0, + "bits": [ 297 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_2_DI": { + "hide_name": 0, + "bits": [ 299 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI": { + "hide_name": 0, + "bits": [ 300 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 80, 78, 76, 298 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 301 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 303 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 305 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 306 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 304 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 307 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 308 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 302 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 309 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 311 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 312 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 310 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 313 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_3_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 314 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_4_DI": { + "hide_name": 0, + "bits": [ 315 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 296 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc": { + "hide_name": 0, + "bits": [ "0", 500, 319, 321, 506, 505, 504, 334, 337, 348, 347, 346, 323, 328, 350, 353, 356, 359, 361, 371, 383, 382, 381, 380, 389, 392, 404, 403, 402, 393, 417, 462 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_10_DI": { + "hide_name": 0, + "bits": [ 322 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI": { + "hide_name": 0, + "bits": [ 327 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 361, 359, 356, 353, 350, 328, 326 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 329 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 332 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 335 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 336 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 333 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 338 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 339 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 330 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 340 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 342 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 343 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 341 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 344 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_11_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 345 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_12_DI": { + "hide_name": 0, + "bits": [ 349 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_12_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 350, 351 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_13_DI": { + "hide_name": 0, + "bits": [ 352 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_13_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 353, 354 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_14_DI": { + "hide_name": 0, + "bits": [ 355 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_14_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 356, 324, 357 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_15_DI": { + "hide_name": 0, + "bits": [ 358 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI": { + "hide_name": 0, + "bits": [ 360 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 380, 381, 382, 383, 371, 361, 362 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 364 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 367 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 369 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 370 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 368 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 372 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 373 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 365 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 374 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 376 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 377 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 375 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 378 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 379 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 393, 402, 403, 404, 392, 389, 366 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 384 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 387 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 390 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 391 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 388 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 394 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 395 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 385 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 396 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 398 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 399 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 397 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 400 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 401 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 444, 429, 386, 408, 412, 464 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0": { + "hide_name": 0, + "bits": [ 409 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 413 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 415 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 416 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 414 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 418 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 419 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1": { + "hide_name": 0, + "bits": [ 410 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 420 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 422 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 423 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 421 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 424 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 425 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0": { + "hide_name": 0, + "bits": [ 426 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 430 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 432 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 433 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 431 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 434 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 435 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1": { + "hide_name": 0, + "bits": [ 427 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 436 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 438 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 439 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 437 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 440 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 441 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D0": { + "hide_name": 0, + "bits": [ 442 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 445 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 446 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D1": { + "hide_name": 0, + "bits": [ 443 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 447 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_3_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 448 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 405 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 449 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 452 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 453 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 450 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 454 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 455 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 406 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 456 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 458 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 459 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 457 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 460 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 461 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 465 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 467 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 469 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 470 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 468 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 471 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 472 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 466 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 473 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 475 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 476 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 474 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 477 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 478 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 389, 380, 381, 382, 383, 371, 363 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 479 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 481 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 483 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 484 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 482 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 485 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 486 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 480 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 487 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 489 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 490 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 488 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 491 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 492 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_17_DI": { + "hide_name": 0, + "bits": [ 493 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_18_DI": { + "hide_name": 0, + "bits": [ 494 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_18_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 383, 495 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_19_DI": { + "hide_name": 0, + "bits": [ 496 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI": { + "hide_name": 0, + "bits": [ 320 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 462, 417, 393, 498, 503, 463 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 504, 505, 506, 321, 499 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_ALUT": { + "hide_name": 0, + "bits": [ 501 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_BLUT": { + "hide_name": 0, + "bits": [ 502 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z": { + "hide_name": 0, + "bits": [ 462, 417, 393, 503, 523, 463 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 507 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 509 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 511 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 512 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 510 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 513 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 514 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 508 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 515 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 517 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 518 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 516 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 519 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 520 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 346, 347, 348, 337, 334, 504, 522 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 524 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 526 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 528 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 529 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 527 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 530 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 531 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 525 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 532 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 534 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 535 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 533 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 536 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 537 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 359, 356, 353, 350, 328, 323, 325 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 538 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 539 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_20_DI": { + "hide_name": 0, + "bits": [ 541 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_20_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 382, 324, 497 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI": { + "hide_name": 0, + "bits": [ 542 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 402, 403, 404, 392, 389, 380, 428 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 543 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 546 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 548 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 549 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 547 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 550 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 551 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 544 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 552 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 554 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 555 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 553 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 556 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_21_DI_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 557 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_22_DI": { + "hide_name": 0, + "bits": [ 558 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI": { + "hide_name": 0, + "bits": [ 559 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 417, 393, 402, 403, 404, 392, 411 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 560 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 562 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 564 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 565 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 563 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 566 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 567 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 561 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 568 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 570 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 571 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 569 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 572 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_23_DI_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 573 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_24_DI": { + "hide_name": 0, + "bits": [ 574 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_24_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 404, 324, 575 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_25_DI": { + "hide_name": 0, + "bits": [ 576 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_26_DI": { + "hide_name": 0, + "bits": [ 577 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_27_DI": { + "hide_name": 0, + "bits": [ 578 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_28_DI": { + "hide_name": 0, + "bits": [ 579 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_29_DI": { + "hide_name": 0, + "bits": [ 580 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_2_DI": { + "hide_name": 0, + "bits": [ 540 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_2_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 462, 417, 393, 581, 503, 463 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_30_DI": { + "hide_name": 0, + "bits": [ 583 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_3_DI": { + "hide_name": 0, + "bits": [ 582 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI": { + "hide_name": 0, + "bits": [ 584 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 585, 444, 429, 386, 408, 412, 464 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 347, 348, 337, 334, 504, 505, 521 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 586 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 589 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 591 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 592 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 590 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 593 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 594 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 587 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 595 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 597 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 598 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 596 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 599 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 600 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 356, 353, 350, 328, 323, 346, 588 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 601 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 603 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 605 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 606 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 604 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 607 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 608 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 602 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 609 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 611 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 612 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 610 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 613 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 614 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_4_DI_LUT4_Z_C_LUT4_Z_D_L6MUX21_SD_Z_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 382, 383, 371, 361, 359, 545 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI": { + "hide_name": 0, + "bits": [ 615 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 323, 346, 347, 348, 337, 334, 331 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 616 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 619 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 621 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 622 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 620 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 623 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 624 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 617 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 625 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 627 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 628 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 626 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 629 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 630 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 356, 353, 350, 328, 323, 325, 618 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 631 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 634 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 636 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 637 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 635 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 638 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 639 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 632 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 640 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 642 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 643 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 641 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 644 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 645 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 382, 383, 371, 361, 359, 545, 633 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 646 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 648 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 650 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 651 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 649 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 652 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 653 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 647 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 654 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 656 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 657 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 655 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 658 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 659 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 404, 392, 389, 380, 381, 451, 407 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 660 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 662 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 663 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 661 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 664 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 665 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 666 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 668 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 669 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 667 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 670 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 671 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_6_DI": { + "hide_name": 0, + "bits": [ 672 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_7_DI": { + "hide_name": 0, + "bits": [ 674 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_7_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 348, 337, 673 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_8_DI": { + "hide_name": 0, + "bits": [ 675 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_9_DI": { + "hide_name": 0, + "bits": [ 677 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_9_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 347, 324, 676 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 317 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_DI_LUT4_Z_C": { + "hide_name": 0, + "bits": [ 462, 417, 393, 678, 503, 463 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ "0", 500, 319, 321, 506, 505, 504, 334, 337, 348, 347, 346, 323, 328, 350, 353, 356, 359, 361, 371, 383, 382, 381, 380, 389, 392, 404, 403, 402, 393, 417, 462 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "1", "0", "1", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy": { + "hide_name": 0, + "bits": [ 28 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_C_Z": { + "hide_name": 0, + "bits": [ 316 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 318 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 679 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done": { + "hide_name": 0, + "bits": [ 32 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 680 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ "0", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 683, 685, 686, 688, 690 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1_DI": { + "hide_name": 0, + "bits": [ 682, 684, 687, 689, 692 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/techmap.v:270.26-270.27" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1_DI_LUT4_Z_2_D": { + "hide_name": 0, + "bits": [ 690, 691 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_1_DI_LUT4_Z_2_D_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 4, 28, 324 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_CE": { + "hide_name": 0, + "bits": [ 681 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.group_index_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 682, 685, 686, 688, 690 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/techmap.v:287.21-287.22" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[2].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[2].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[3].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[3].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[4].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[4].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[4].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[4].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[4].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[4].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[4].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[4].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[4].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[4].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[4].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[4].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[5].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[5].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[5].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[5].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[5].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[5].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[5].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[5].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[5].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[5].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[5].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[5].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[6].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[6].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[6].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[6].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[6].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[6].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[6].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[6].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[6].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[6].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[6].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[6].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[7].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[7].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[7].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[7].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[7].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[7].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[7].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[7].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[7].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[7].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.GEN_MAC[7].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 GEN_MAC[7].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ "0", 500, 319, 321, 506, 505, 504, 334, 337, 348, 347, 346, 323, 328, 350, 353, 356, 359, 361, 371, 383, 382, 381, 380, 389, 392, 404, 403, 402, 393, 417, 462 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ "0", 500, 319, 321, 506, 505, 504, 334, 337, 348, 347, 346, 323, 328, 350, 353, 356, 359, 361, 371, 383, 382, 381, 380, 389, 392, 404, 403, 402, 393, 417, 462 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[2]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[3]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[4]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[5]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[6]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[6]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.products[7]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 products[7]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[10]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[10]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[11]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[11]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[16]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[16]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[17]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[17]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[24]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[24]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[3]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[4]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[5]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[6]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[6]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[7]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[7]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[8]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[8]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.tree[9]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 tree[9]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y": { + "hide_name": 0, + "bits": [ 10, 11, 12, 13, 14, 15, 16, "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[1].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI": { + "hide_name": 0, + "bits": [ 694 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 695 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 698 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 700 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 701 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 699 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 702 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 703 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 696 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 704 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 706 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 707 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 705 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 708 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 709 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD": { + "hide_name": 0, + "bits": [ 444, 429, 386, 408, 412, 464, 697 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 710 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 712 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 713 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 711 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 714 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 715 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI": { + "hide_name": 0, + "bits": [ 716 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 717 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 720 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 722 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 723 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 721 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 724 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 725 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 718 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 726 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 728 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 729 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 727 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 730 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 731 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD": { + "hide_name": 0, + "bits": [ 444, 429, 386, 408, 412, 464, 719 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 732 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 734 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 735 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 733 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 736 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 737 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI": { + "hide_name": 0, + "bits": [ 738 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 739 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 742 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 744 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 745 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 743 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 746 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 747 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 740 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 748 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 750 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 751 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 749 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 752 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 753 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD": { + "hide_name": 0, + "bits": [ 444, 429, 386, 408, 412, 464, 741 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 754 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 756 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 757 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 755 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 758 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 759 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI": { + "hide_name": 0, + "bits": [ 760 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 761 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 764 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 766 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 767 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 765 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 768 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 769 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 762 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 770 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 772 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 773 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 771 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 774 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 775 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD": { + "hide_name": 0, + "bits": [ 444, 429, 386, 408, 412, 464, 763 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 776 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 778 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 779 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 777 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 780 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 781 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI": { + "hide_name": 0, + "bits": [ 782 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 783 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 785 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 787 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 788 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 786 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 789 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 790 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 784 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 791 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 793 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 794 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 792 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 795 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_5_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 796 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI": { + "hide_name": 0, + "bits": [ 797 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 798 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 800 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 801 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 799 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 802 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_6_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 803 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 693 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 804 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 807 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 809 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 810 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 808 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 811 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 812 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 805 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 813 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 815 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 816 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 814 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 817 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 818 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD": { + "hide_name": 0, + "bits": [ 444, 429, 386, 408, 412, 464, 806 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 819 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 821 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 822 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 820 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 823 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 824 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc": { + "hide_name": 0, + "bits": [ "0", "0", "0", 826, 828, 850, 870, 872, 874, 876, 878, 880, 882, 830, 832, 834, 836, 838, 840, 842, 844, 846, 848, 852, 854, 856, 858, 860, 862, 864, 866, 868 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ "0", "0", "0", 825, 827, 849, 869, 871, 873, 875, 877, 879, 881, 829, 831, 833, 835, 837, 839, 841, 843, 845, 847, 851, 853, 855, 857, 859, 861, 863, 865, 867 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 883 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 886 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 889 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 890 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 887 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 891 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 892 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 884 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 893 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 895 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 896 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 894 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 897 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 898 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_11_D": { + "hide_name": 0, + "bits": [ 842, 840, 900 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D": { + "hide_name": 0, + "bits": [ 862, 860, 858, 856, 854, 852, 901 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 902 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 904 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 906 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 907 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 905 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 908 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 909 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 903 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 910 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 912 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 913 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 911 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 914 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 915 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 862, 860, 858, 856, 854, 899, 918 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 916 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 919 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 920 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 840, 838, 836, 921, 885, 847 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 846, 838, 888, 922 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 917 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 923 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_12_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 924 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C": { + "hide_name": 0, + "bits": [ 864, 925 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 927 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 929 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 931 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 932 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 930 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 933 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 934 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 928 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 935 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 937 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 938 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 936 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 939 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 940 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 868, 866, 869, 958, 960, 941, 944 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 942 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 945 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 947 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 948 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 946 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 949 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 950 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 943 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 951 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 953 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 954 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 952 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 955 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 956 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 959, 833, 831, 957 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_D_LUT4_Z_B": { + "hide_name": 0, + "bits": [ 961, 877, 881 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_D_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 962 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_C_LUT4_D_Z_LUT4_Z_D_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 963 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_15_D": { + "hide_name": 0, + "bits": [ 860, 926 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D": { + "hide_name": 0, + "bits": [ 876, 874, 872, 965 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 834, 832, 830, 882, 880, 878, 964 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 967 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 969 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 971 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 972 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 970 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 973 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 974 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 968 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 975 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 977 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 978 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 976 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 979 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 980 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_3_D_LUT4_D_Z_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 848, 846, 840, 838, 836, 888, 885 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.acc_next_LUT4_Z_4_D": { + "hide_name": 0, + "bits": [ 830, 966 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy": { + "hide_name": 0, + "bits": [ 27 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 981 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done": { + "hide_name": 0, + "bits": [ 31 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 4, 27, 982 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z": { + "hide_name": 0, + "bits": [ 985 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 984 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 986, 987 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 996, 993, 992, 995, 988 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/techmap.v:270.26-270.27" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 983 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ "0", "0", "0", 825, 827, 849, 869, 871, 873, 875, 877, 879, 881, 829, 831, 833, 835, 837, 839, 841, 843, 845, 847, 851, 853, 855, 857, 859, 861, 863, 865, 867 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 991, 990, 989, 994, 986 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.group_index_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 996, 990, 989, 994, 986 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/techmap.v:287.21-287.22" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.product": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[2].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[2].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.product": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[3].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[3].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[4].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[4].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[4].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[4].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[4].u_mac.product": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[4].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[4].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[4].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[4].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[4].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[4].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[4].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[5].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[5].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[5].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[5].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[5].u_mac.product": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[5].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[5].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[5].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[5].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[5].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[5].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[5].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[6].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[6].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[6].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[6].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[6].u_mac.product": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[6].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[6].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[6].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[6].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[6].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[6].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[6].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[7].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[7].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[7].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[7].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[7].u_mac.product": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[7].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[7].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[7].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[7].u_mac.w": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[7].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.GEN_MAC[7].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 GEN_MAC[7].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", 826, 828, 850, 870, 872, 874, 876, 878, 880, 882, 830, 832, 834, 836, 838, 840, 842, 844, 846, 848, 852, 854, 856, 858, 860, 862, 864, 866, 868 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", 825, 827, 849, 869, 871, 873, 875, 877, 879, 881, 829, 831, 833, 835, 837, 839, 841, 843, 845, 847, 851, 853, 855, 857, 859, 861, 863, 865, 867 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[2]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[3]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[4]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[5]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[6]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[6]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.products[7]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 products[7]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[10]": { + "hide_name": 0, + "bits": [ "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[10]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[11]": { + "hide_name": 0, + "bits": [ "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[11]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[16]": { + "hide_name": 0, + "bits": [ "0", "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[16]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[17]": { + "hide_name": 0, + "bits": [ "0", "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[17]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[24]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[24]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[3]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[4]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[5]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[6]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[6]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[7]": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[7]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[8]": { + "hide_name": 0, + "bits": [ "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[8]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.tree[9]": { + "hide_name": 0, + "bits": [ "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 tree[9]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y": { + "hide_name": 0, + "bits": [ 17, 17, 17, 18, 19, 20, 21, "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[2].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI": { + "hide_name": 0, + "bits": [ 998 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 999 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1001 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1003 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1004 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1002 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1005 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1006 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1000 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1007 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1009 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1010 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1008 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1011 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1012 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI": { + "hide_name": 0, + "bits": [ 1013 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1014 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1016 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1018 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1019 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1017 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1020 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1021 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1015 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1022 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1024 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1025 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1023 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1026 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1027 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI": { + "hide_name": 0, + "bits": [ 1028 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1029 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1031 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1033 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1034 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1032 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1035 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1036 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1030 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1037 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1039 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1040 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1038 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1041 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1042 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI": { + "hide_name": 0, + "bits": [ 1043 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1044 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1046 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1048 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1049 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1047 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1050 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1051 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1045 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1052 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1054 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1055 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1053 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1056 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1057 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 997 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1058 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1059 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", 1087, 1089, 1091, 1093, 1095, 1097, 1099, 1107, 1069, 1061, 1063, 1085, 1101, 1103, 1105, 1109, 1111, 1113, 1065, 1067, 1071, 1073, 1075, 1077, 1079, 1081, 1083 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:55.32-55.35" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", 1086, 1088, 1090, 1092, 1094, 1096, 1098, 1106, 1068, 1060, 1062, 1084, 1100, 1102, 1104, 1108, 1110, 1112, 1064, 1066, 1070, 1072, 1074, 1076, 1078, 1080, 1082 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron acc_next", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:60.33-60.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1114 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1117 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1119 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1120 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1118 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1121 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1122 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1115 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1123 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1125 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1126 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1124 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1127 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1128 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_13_D": { + "hide_name": 0, + "bits": [ 1103, 1101, 1133 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_16_D": { + "hide_name": 0, + "bits": [ 1111, 1134 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D": { + "hide_name": 0, + "bits": [ 1113, 1111, 1109, 1105, 1135 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1136 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1138 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1140 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1141 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1139 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1142 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1143 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1137 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1144 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1146 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1147 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1145 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1148 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1149 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_ALUT": { + "hide_name": 0, + "bits": [ 1150 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_BLUT": { + "hide_name": 0, + "bits": [ 1151 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z": { + "hide_name": 0, + "bits": [ 1167, 1152, 1156, 1199, 1160, 1082, 1182 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D0": { + "hide_name": 0, + "bits": [ 1157 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1161 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1162 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D1": { + "hide_name": 0, + "bits": [ 1158 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1163 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1164 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0": { + "hide_name": 0, + "bits": [ 1165 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1168 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1170 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1171 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1169 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1172 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1173 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1": { + "hide_name": 0, + "bits": [ 1166 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1174 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1176 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1177 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1175 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1178 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1179 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D0": { + "hide_name": 0, + "bits": [ 1180 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1183 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1184 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D1": { + "hide_name": 0, + "bits": [ 1181 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1185 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_3_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1186 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1153 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1187 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1189 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1190 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1188 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1191 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1192 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1154 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1193 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1195 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1196 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1194 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1197 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_17_D_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1198 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D": { + "hide_name": 0, + "bits": [ 1083, 1081, 1079, 1077, 1075, 1073, 1116 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 1083, 1081, 1079, 1089, 1204, 1132, 1207 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D_LUT4_D_Z_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1205 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_1_D_LUT4_D_Z_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1206 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D": { + "hide_name": 0, + "bits": [ 1107, 1099, 1097, 1095, 1093, 1091, 1208 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0": { + "hide_name": 0, + "bits": [ 1211 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1214 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1216 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1217 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1215 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1218 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1219 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1": { + "hide_name": 0, + "bits": [ 1212 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1220 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1222 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1223 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1221 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1224 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1225 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z": { + "hide_name": 0, + "bits": [ 1085, 1063, 1061, 1069, 1213, 1130 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_ALUT": { + "hide_name": 0, + "bits": [ 1226 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_BLUT": { + "hide_name": 0, + "bits": [ 1227 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.26-141.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z": { + "hide_name": 0, + "bits": [ 1228 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_D1_D0": { + "hide_name": 0, + "bits": [ 1229 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1230 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.22-141.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1231 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.18-141.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_1_Z_PFUMX_C0_Z_L6MUX21_D1_Z": { + "hide_name": 0, + "bits": [ 1109, 1105, 1103, 1101, 1085, 1131, 1155 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 1209 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1232 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1234 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1235 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1233 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1236 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1237 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 1210 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1238 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1240 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1241 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1239 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1242 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1243 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 1103, 1101, 1085, 1063, 1061, 1069, 1130 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1244 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_20_D_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1245 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.18-133.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_6_D": { + "hide_name": 0, + "bits": [ 1083, 1081, 1079, 1087, 1246, 1132, 1207 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C": { + "hide_name": 0, + "bits": [ 1101, 1085, 1063, 1061, 1069, 1107, 1247 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 1248 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1251 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1253 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1254 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1252 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1255 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1256 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 1249 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1257 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1259 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1260 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1258 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1261 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1262 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 1065, 1113, 1111, 1109, 1105, 1103, 1250 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0": { + "hide_name": 0, + "bits": [ 1263 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1265 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1267 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1268 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1266 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1269 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1270 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1": { + "hide_name": 0, + "bits": [ 1264 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1271 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1273 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1274 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1272 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1275 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1276 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_SD_Z_L6MUX21_SD_Z": { + "hide_name": 0, + "bits": [ 1077, 1075, 1073, 1071, 1067, 1159 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1277 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1279 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1281 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1282 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1280 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1283 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1284 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1278 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1285 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1287 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1288 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1286 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1289 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_7_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1290 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_9_D": { + "hide_name": 0, + "bits": [ 1113, 1200 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.acc_next_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1099, 1097, 1095, 1129 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.bias": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron bias", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:13.35-13.39" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.bias_ext": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron bias_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:62.33-62.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy": { + "hide_name": 0, + "bits": [ 29 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:16.16-16.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.busy_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1291 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:7.11-7.14" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done": { + "hide_name": 0, + "bits": [ 33 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:17.16-17.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 4, 29, 1292 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 1294 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D": { + "hide_name": 0, + "bits": [ 1201, 1295 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z": { + "hide_name": 0, + "bits": [ 1302, 1299, 1301, 1300, 1296 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/techmap.v:270.26-270.27" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.done_TRELLIS_FF_Q_LSR": { + "hide_name": 0, + "bits": [ 1293 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.final_acc": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", 1086, 1088, 1090, 1092, 1094, 1096, 1098, 1106, 1068, 1060, 1062, 1084, 1100, 1102, 1104, 1108, 1110, 1112, 1064, 1066, 1070, 1072, 1074, 1076, 1078, 1080, 1082 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron final_acc", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:63.33-63.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index": { + "hide_name": 0, + "bits": [ 1298, 1297, 1203, 1202, 1201 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron group_index", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:53.33-53.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.group_index_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1302, 1297, 1203, 1202, 1201 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141.36-141.54|/opt/homebrew/bin/../share/yosys/techmap.v:287.21-287.22" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:8.11-8.14" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:9.11-9.16" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[0].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[0].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[1].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[2].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[2].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[3].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[3].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[4].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[4].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[4].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[4].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[4].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[4].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[4].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[4].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[4].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[4].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[4].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[4].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[5].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[5].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[5].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[5].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[5].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[5].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[5].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[5].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[5].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[5].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[5].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[5].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[6].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[6].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[6].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[6].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[6].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[6].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[6].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[6].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[6].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[6].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[6].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[6].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[7].u_mac.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[7].u_mac acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:7.35-7.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[7].u_mac.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[7].u_mac acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:8.35-8.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[7].u_mac.product": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[7].u_mac product", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:13.34-13.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[7].u_mac.product_ext": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[7].u_mac product_ext", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:14.33-14.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[7].u_mac.w": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[7].u_mac w", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:6.36-6.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[7].u_mac.x": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 GEN_MAC[7].u_mac x", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:5.36-5.37" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.acc_in": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", 1087, 1089, 1091, 1093, 1095, 1097, 1099, 1107, 1069, 1061, 1063, 1085, 1101, 1103, 1105, 1109, 1111, 1113, 1065, 1067, 1071, 1073, 1075, 1077, 1079, 1081, 1083 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 acc_in", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:8.34-8.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.acc_out": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", 1086, 1088, 1090, 1092, 1094, 1096, 1098, 1106, 1068, 1060, 1062, 1084, 1100, 1102, 1104, 1108, 1110, 1112, 1064, 1066, 1070, 1072, 1074, 1076, 1078, 1080, 1082 ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 acc_out", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[0]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[1]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[2]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[3]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[4]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[5]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[6]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[6]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[7]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 products[7]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:15.33-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[0]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[0]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[10]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[10]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[11]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[11]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[16]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[16]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[17]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[17]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[1]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[1]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[24]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[24]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[2]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[2]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[3]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[3]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[4]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[4]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[5]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[5]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[6]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[6]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[7]": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[7]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[8]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[8]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.tree[9]": { + "hide_name": 0, + "bits": [ "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 tree[9]", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:7.44-7.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron u_mac8 x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:6.44-6.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.w_bus": { + "hide_name": 0, + "bits": [ "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron w_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:12.44-12.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.w_group": { + "hide_name": 0, + "bits": [ "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron w_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:11.44-11.49" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.x_group": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron x_group", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:57.43-57.50" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y": { + "hide_name": 0, + "bits": [ 22, 22, 22, 22, 22, 23, 24, "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer GEN_NEURON[3].u_neuron y", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:15.40-15.41" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI": { + "hide_name": 0, + "bits": [ 1305 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1306 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1308 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1310 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1311 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1309 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1312 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1313 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1307 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1314 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1316 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1317 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1315 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1318 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1319 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI": { + "hide_name": 0, + "bits": [ 1320 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1321 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1323 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1325 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1326 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1324 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1327 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1328 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1322 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1329 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1331 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1332 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1330 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1333 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_2_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1334 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_CE": { + "hide_name": 0, + "bits": [ 1303 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI": { + "hide_name": 0, + "bits": [ 1304 ], + "attributes": { + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1335 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1337 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1339 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1340 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.18-157.20" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1338 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1341 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1342 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.26-157.28" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1336 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0": { + "hide_name": 0, + "bits": [ 1343 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.58-157.60" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1345 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.38-157.40" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1346 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.34-157.36" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1": { + "hide_name": 0, + "bits": [ 1344 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT": { + "hide_name": 0, + "bits": [ 1347 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48" + } + }, + "u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT": { + "hide_name": 0, + "bits": [ 1348 ], + "attributes": { + "src": "/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.42-157.44" + } + }, + "u_layer.bias_bus": { + "hide_name": 0, + "bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer bias_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:18.9-18.17" + } + }, + "u_layer.busy": { + "hide_name": 0, + "bits": [ 25 ], + "attributes": { + "hdlname": "u_layer busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:23.12-23.16" + } + }, + "u_layer.clk": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "hdlname": "u_layer clk", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:8.11-8.14" + } + }, + "u_layer.done": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "hdlname": "u_layer done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:24.12-24.16" + } + }, + "u_layer.neuron_busy": { + "hide_name": 0, + "bits": [ 30, 28, 27, 29 ], + "attributes": { + "hdlname": "u_layer neuron_busy", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:27.26-27.37" + } + }, + "u_layer.neuron_done": { + "hide_name": 0, + "bits": [ 34, 32, 31, 33 ], + "attributes": { + "hdlname": "u_layer neuron_done", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:28.26-28.37" + } + }, + "u_layer.rst": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "hdlname": "u_layer rst", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:9.11-9.14" + } + }, + "u_layer.start": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "hdlname": "u_layer start", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:10.11-10.16" + } + }, + "u_layer.weights_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer weights_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:15.9-15.20" + } + }, + "u_layer.x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer x_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:12.44-12.49" + } + }, + "u_layer.y_bus": { + "hide_name": 0, + "bits": [ 5, 5, 5, 6, 7, 8, 9, "0", 10, 11, 12, 13, 14, 15, 16, "0", 17, 17, 17, 18, 19, 20, 21, "0", 22, 22, 22, 22, 22, 23, 24, "0" ], + "signed": 1, + "attributes": { + "hdlname": "u_layer y_bus", + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:21.9-21.14" + } + }, + "weights_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:18.52-18.63" + } + }, + "x_bus": { + "hide_name": 0, + "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0", "1", "0", "0", "0", "0", "0", "0", "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:17.42-17.47" + } + }, + "y_bus": { + "hide_name": 0, + "bits": [ 5, 5, 5, 6, 7, 8, 9, "0", 10, 11, 12, 13, 14, 15, 16, "0", 17, 17, 17, 18, 19, 20, 21, "0", 22, 22, 22, 22, 22, 23, 24, "0" ], + "signed": 1, + "attributes": { + "src": "/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:6.26-6.31" + } + } + } + } + } +} diff --git a/synth/ecp5/p8/top.lpf b/synth/ecp5/p8/top.lpf new file mode 100644 index 0000000..e69de29 diff --git a/synth/ecp5/p8/top.v b/synth/ecp5/p8/top.v new file mode 100644 index 0000000..5621029 --- /dev/null +++ b/synth/ecp5/p8/top.v @@ -0,0 +1,125 @@ +module top #( + parameter DATA_WIDTH = 8, + parameter N_INPUTS = 256, + parameter N_NEURONS = 4, + parameter PARALLEL = 8, + parameter ACC_WIDTH = 32 +)( + input wire clk, + input wire rst, + input wire start, + + output wire signed [31:0] y_bus, + output wire busy, + output wire done +); + + localparam X_BITS = DATA_WIDTH * N_INPUTS; + localparam W_BITS = DATA_WIDTH * N_INPUTS * N_NEURONS; + localparam B_BITS = DATA_WIDTH * N_NEURONS; + + /* + * Internal neural-network data. + * + * These are deliberately registers, not parameters/constants. + * This prevents the complete datapath from disappearing during + * synthesis. + */ + + reg signed [X_BITS-1:0] x_bus; + reg signed [W_BITS-1:0] weights_bus; + reg signed [B_BITS-1:0] bias_bus; + + integer i; + integer n; + + /* + * Deterministic initialization. + * + * The actual datapath remains present because the vectors are + * stored in registers and loaded through the clocked process. + */ + + always @(posedge clk) begin + if (rst) begin + + x_bus <= '0; + weights_bus <= '0; + bias_bus <= '0; + + end + else if (start) begin + + /* + * INT8 input vector. + * + * Pattern: + * -16 ... +15 + */ + + for (i = 0; i < N_INPUTS; i = i + 1) begin + x_bus[i*DATA_WIDTH +: DATA_WIDTH] + <= ((i * 17 + 3) % 31) - 15; + end + + /* + * INT8 weights. + */ + + for (n = 0; n < N_NEURONS; n = n + 1) begin + + for (i = 0; i < N_INPUTS; i = i + 1) begin + + weights_bus[ + (n*N_INPUTS+i)*DATA_WIDTH + +: DATA_WIDTH + ] + <= ((n * 29 + i * 13 + 5) % 31) - 15; + + end + + end + + /* + * INT8 biases. + */ + + for (n = 0; n < N_NEURONS; n = n + 1) begin + + bias_bus[ + n*DATA_WIDTH + +: DATA_WIDTH + ] + <= ((n * 7 + 1) % 9) - 4; + + end + + end + end + + + /* + * Real neural-network layer. + */ + + layer #( + .DATA_WIDTH(DATA_WIDTH), + .N_INPUTS(N_INPUTS), + .N_NEURONS(N_NEURONS), + .PARALLEL(PARALLEL), + .ACC_WIDTH(ACC_WIDTH) + ) dut ( + .clk(clk), + .rst(rst), + .start(start), + + .x_bus(x_bus), + .weights_bus(weights_bus), + .bias_bus(bias_bus), + + .y_bus(y_bus), + .busy(busy), + .done(done) + ); + +endmodule diff --git a/synth/ecp5/p8/yosys.log b/synth/ecp5/p8/yosys.log new file mode 100644 index 0000000..9607f6c --- /dev/null +++ b/synth/ecp5/p8/yosys.log @@ -0,0 +1,11080 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Executing script file `synth/ecp5/p8/synth.ys' -- + +1. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v +Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v' to AST representation. +Generating RTLIL representation for module `\mac_unit'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v +Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v' to AST representation. +Generating RTLIL representation for module `\mac8'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v +Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v' to AST representation. +Generating RTLIL representation for module `\neuron_parallel'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v +Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v' to AST representation. +Generating RTLIL representation for module `\layer'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v +Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v' to AST representation. +Generating RTLIL representation for module `\top'. +Successfully finished Verilog frontend. + +6. Executing HIERARCHY pass (managing design hierarchy). + +6.1. Analyzing design hierarchy.. +Top module: \top +Used module: \layer +Used module: \neuron_parallel +Used module: \mac8 +Used module: \mac_unit +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \N_NEURONS = 4 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 + +6.2. Executing AST frontend in derive mode using pre-parsed AST for module `\layer'. +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \N_NEURONS = 4 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 +Generating RTLIL representation for module `$paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 + +6.3. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Generating RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Reprocessing module mac8 because instantiated module $paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit has become available. +Generating RTLIL representation for module `\mac8'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Parameter \PARALLEL = 8 + +6.4. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Parameter \PARALLEL = 8 +Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'. +Parameter \DATA_WIDTH = 16 +Parameter \N_INPUTS = 64 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 40 + +6.5. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'. +Parameter \DATA_WIDTH = 16 +Parameter \N_INPUTS = 64 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 40 +Generating RTLIL representation for module `$paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel'. +Parameter \DATA_WIDTH = 16 +Parameter \N_INPUTS = 64 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel'. +Parameter \DATA_WIDTH = 16 +Parameter \N_INPUTS = 64 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel'. +Parameter \DATA_WIDTH = 16 +Parameter \N_INPUTS = 64 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel'. +Parameter \DATA_WIDTH = 16 +Parameter \N_INPUTS = 64 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel'. +Parameter \DATA_WIDTH = 16 +Parameter \N_INPUTS = 64 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel'. +Parameter \DATA_WIDTH = 16 +Parameter \N_INPUTS = 64 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel'. +Parameter \DATA_WIDTH = 16 +Parameter \N_INPUTS = 64 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel'. +Reprocessing module layer because instantiated module $paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel has become available. +Generating RTLIL representation for module `\layer'. + +6.6. Analyzing design hierarchy.. +Top module: \top +Used module: $paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer +Used module: \neuron_parallel +Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 +Used module: \mac_unit +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 + +6.7. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'. +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 +Generating RTLIL representation for module `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel'. +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel'. +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel'. +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel'. +Reprocessing module $paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer because instantiated module $paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel has become available. +Generating RTLIL representation for module `$paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 + +6.8. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Generating RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Reprocessing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 because instantiated module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit has become available. +Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'. + +6.9. Analyzing design hierarchy.. +Top module: \top +Used module: $paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer +Used module: \neuron_parallel +Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 +Used module: \mac_unit +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel'. +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel'. +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel'. +Parameter \DATA_WIDTH = 8 +Parameter \N_INPUTS = 256 +Parameter \PARALLEL = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. + +6.10. Analyzing design hierarchy.. +Top module: \top +Used module: $paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer +Used module: $paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel +Used module: \mac8 +Used module: \mac_unit +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 16 +Parameter \ACC_WIDTH = 40 +Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Parameter \DATA_WIDTH = 8 +Parameter \ACC_WIDTH = 32 +Parameter \PARALLEL = 8 +Found cached RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'. + +6.11. Analyzing design hierarchy.. +Top module: \top +Used module: $paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer +Used module: $paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel +Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 +Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit + +6.12. Analyzing design hierarchy.. +Top module: \top +Used module: $paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer +Used module: $paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel +Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 +Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit +Removing unused module `\mac8'. +Removing unused module `\layer'. +Removing unused module `$paramod$ce07a61ab1150de6e75ef4e31da905e743f7e22c\neuron_parallel'. +Removing unused module `\neuron_parallel'. +Removing unused module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. +Removing unused module `\mac_unit'. +Removed 6 unused modules. + +7. Executing PROC pass (convert processes to netlists). + +7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 5 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$206 in module $paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel. +Removed a total of 0 dead cases. + +7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 1 redundant assignment. +Promoted 603 assignments to connections. + +7.4. Executing PROC_INIT pass (extract init attributes). + +7.5. Executing PROC_ARST pass (detect async resets in processes). + +7.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\top.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:23$48'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$298'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$296'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$294'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$292'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$290'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$288'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$286'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$285'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$284'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$283'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$282'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$281'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$280'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$279'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$278'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$277'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$276'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$275'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$274'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$273'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$272'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$271'. +Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$270'. +Creating decoders for process `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$206'. + 1/5: $0\done[0:0] + 2/5: $0\acc[31:0] + 3/5: $0\group_index[4:0] + 4/5: $0\busy[0:0] + 5/5: $0\y[7:0] + +7.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\top.\i' from process `\top.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:23$48'. +No latch inferred for signal `\top.\x_bus' from process `\top.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:23$48'. +No latch inferred for signal `\top.\weights_bus' from process `\top.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:23$48'. +No latch inferred for signal `\top.\bias_bus' from process `\top.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:23$48'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[24]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$298'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[17]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$296'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[16]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$294'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[11]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$292'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[10]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$290'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[9]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$288'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[8]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$286'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$285'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$284'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$283'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$282'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$281'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$280'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$279'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$278'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$277'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$276'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$275'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$274'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$273'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$272'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$271'. +No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$270'. + +7.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.\y' using process `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$206'. + created $dff cell `$procdff$361' with positive edge clock. +Creating register for signal `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.\busy' using process `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$206'. + created $dff cell `$procdff$362' with positive edge clock. +Creating register for signal `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.\done' using process `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$206'. + created $dff cell `$procdff$363' with positive edge clock. +Creating register for signal `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.\group_index' using process `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$206'. + created $dff cell `$procdff$364' with positive edge clock. +Creating register for signal `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.\acc' using process `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$206'. + created $dff cell `$procdff$365' with positive edge clock. + +7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `top.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:23$48'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$298'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$296'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$294'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$292'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$290'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$288'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$286'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$285'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$284'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$283'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$282'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$281'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$280'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$279'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$278'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$277'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$276'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$275'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$274'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$273'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$272'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$271'. +Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$270'. +Found and cleaned up 6 empty switches in `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$206'. +Removing empty process `$paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$206'. +Cleaned up 6 empty switches. + +7.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. +Optimizing module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit. +Optimizing module $paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer. +Optimizing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8. +Optimizing module $paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel. + +8. Executing FLATTEN pass (flatten design). +Deleting now unused module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit. +Deleting now unused module $paramod$59e7e65a6436847149e03e7e6295e76ee9d3ab17\layer. +Deleting now unused module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8. +Deleting now unused module $paramod$d84ce0e3b12c4023f3666203f6b5a6cc419f253b\neuron_parallel. + + +9. Executing OPT pass (performing simple optimizations). + +9.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +9.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 291 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 287 cells of `\top'. +Finding duplicate cells in `\top'. + +Removed a total of 4 cells. + +9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port A of cell $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procmux$336: \u_layer.GEN_NEURON[0].u_neuron.busy -> 1'0 + Replacing known input bits on port A of cell $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procmux$334: \u_layer.GEN_NEURON[0].u_neuron.busy -> 1'1 + Replacing known input bits on port A of cell $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$336: \u_layer.GEN_NEURON[1].u_neuron.busy -> 1'0 + Replacing known input bits on port A of cell $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$334: \u_layer.GEN_NEURON[1].u_neuron.busy -> 1'1 + Replacing known input bits on port A of cell $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procmux$336: \u_layer.GEN_NEURON[2].u_neuron.busy -> 1'0 + Replacing known input bits on port A of cell $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procmux$334: \u_layer.GEN_NEURON[2].u_neuron.busy -> 1'1 + Replacing known input bits on port A of cell $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procmux$336: \u_layer.GEN_NEURON[3].u_neuron.busy -> 1'0 + Replacing known input bits on port A of cell $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procmux$334: \u_layer.GEN_NEURON[3].u_neuron.busy -> 1'1 + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +9.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 287 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +9.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procdff$361 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procmux$356_Y, Q = \u_layer.GEN_NEURON[3].u_neuron.y, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$380 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procmux$349_Y, Q = \u_layer.GEN_NEURON[3].u_neuron.y). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procdff$362 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procmux$339_Y, Q = \u_layer.GEN_NEURON[3].u_neuron.busy, rval = 1'0). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procdff$363 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procmux$301_Y, Q = \u_layer.GEN_NEURON[3].u_neuron.done, rval = 1'0). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procdff$364 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procmux$325_Y, Q = \u_layer.GEN_NEURON[3].u_neuron.group_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$392 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[3].u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141$212_Y, Q = \u_layer.GEN_NEURON[3].u_neuron.group_index). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procdff$365 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procmux$314_Y, Q = \u_layer.GEN_NEURON[3].u_neuron.acc, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$400 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[3].u_neuron.$procmux$312_Y, Q = \u_layer.GEN_NEURON[3].u_neuron.acc). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procdff$361 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procmux$356_Y, Q = \u_layer.GEN_NEURON[2].u_neuron.y, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$404 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procmux$349_Y, Q = \u_layer.GEN_NEURON[2].u_neuron.y). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procdff$362 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procmux$339_Y, Q = \u_layer.GEN_NEURON[2].u_neuron.busy, rval = 1'0). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procdff$363 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procmux$301_Y, Q = \u_layer.GEN_NEURON[2].u_neuron.done, rval = 1'0). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procdff$364 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procmux$325_Y, Q = \u_layer.GEN_NEURON[2].u_neuron.group_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$416 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[2].u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141$212_Y, Q = \u_layer.GEN_NEURON[2].u_neuron.group_index). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procdff$365 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procmux$314_Y, Q = \u_layer.GEN_NEURON[2].u_neuron.acc, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$424 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[2].u_neuron.$procmux$312_Y, Q = \u_layer.GEN_NEURON[2].u_neuron.acc). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procdff$361 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$356_Y, Q = \u_layer.GEN_NEURON[1].u_neuron.y, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$428 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$349_Y, Q = \u_layer.GEN_NEURON[1].u_neuron.y). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procdff$362 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$339_Y, Q = \u_layer.GEN_NEURON[1].u_neuron.busy, rval = 1'0). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procdff$363 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$301_Y, Q = \u_layer.GEN_NEURON[1].u_neuron.done, rval = 1'0). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procdff$364 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$325_Y, Q = \u_layer.GEN_NEURON[1].u_neuron.group_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$440 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141$212_Y, Q = \u_layer.GEN_NEURON[1].u_neuron.group_index). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procdff$365 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$314_Y, Q = \u_layer.GEN_NEURON[1].u_neuron.acc, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$448 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y, Q = \u_layer.GEN_NEURON[1].u_neuron.acc). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procdff$361 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procmux$356_Y, Q = \u_layer.GEN_NEURON[0].u_neuron.y, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$452 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procmux$349_Y, Q = \u_layer.GEN_NEURON[0].u_neuron.y). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procdff$362 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procmux$339_Y, Q = \u_layer.GEN_NEURON[0].u_neuron.busy, rval = 1'0). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procdff$363 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procmux$301_Y, Q = \u_layer.GEN_NEURON[0].u_neuron.done, rval = 1'0). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procdff$364 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procmux$325_Y, Q = \u_layer.GEN_NEURON[0].u_neuron.group_index, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$464 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[0].u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141$212_Y, Q = \u_layer.GEN_NEURON[0].u_neuron.group_index). +Adding SRST signal on $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procdff$365 ($dff) from module top (D = $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procmux$314_Y, Q = \u_layer.GEN_NEURON[0].u_neuron.acc, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$472 ($sdff) from module top (D = $flatten\u_layer.\GEN_NEURON[0].u_neuron.$procmux$312_Y, Q = \u_layer.GEN_NEURON[0].u_neuron.acc). + +9.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 60 unused cells and 614 unused wires. + + +9.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +9.9. Rerunning OPT passes. (Maybe there is more to do..) + +9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +9.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 217 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 213 cells of `\top'. +Finding duplicate cells in `\top'. + +Removed a total of 4 cells. + +9.13. Executing OPT_DFF pass (perform DFF optimizations). + +9.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 0 unused cells and 7 unused wires. + + +9.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +9.16. Rerunning OPT passes. (Maybe there is more to do..) + +9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +9.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 213 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +9.20. Executing OPT_DFF pass (perform DFF optimizations). + +9.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +9.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +9.23. Finished fast OPT passes. (There is nothing left to do.) + +10. Executing MEMORY pass. + +10.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +10.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +10.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +10.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +10.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +10.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +10.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +10.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +10.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +10.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +10.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +11. Executing OPT pass (performing simple optimizations). + +11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 213 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +11.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 213 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +11.6. Executing OPT_DFF pass (perform DFF optimizations). + +11.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +11.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +11.9. Finished fast OPT passes. (There is nothing left to do.) + +12. Executing TECHMAP pass (map to technology primitives). + +12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +12.2. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $reduce_and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $sdff. +Using template $paramod$constmap:bb3aab9d7e3e1508d26b149e730a85068a1f5578$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx for cells of type $shiftx. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port B: 1'0 + Constant input on bit 1 of port B: 1'0 + Constant input on bit 2 of port B: 1'0 + Constant input on bit 3 of port B: 1'0 + Constant input on bit 4 of port B: 1'0 + Constant input on bit 5 of port B: 1'0 + Constant input on bit 11 of port B: 1'0 + Constant input on bit 12 of port B: 1'0 + Constant input on bit 13 of port B: 1'0 + Constant input on bit 14 of port B: 1'0 + Constant input on bit 15 of port B: 1'0 + Constant input on bit 16 of port B: 1'0 + Constant input on bit 17 of port B: 1'0 + Constant input on bit 18 of port B: 1'0 + Constant input on bit 19 of port B: 1'0 + Constant input on bit 20 of port B: 1'0 + Constant input on bit 21 of port B: 1'0 + Constant input on bit 22 of port B: 1'0 + Constant input on bit 23 of port B: 1'0 + Constant input on bit 24 of port B: 1'0 + Constant input on bit 25 of port B: 1'0 + Constant input on bit 26 of port B: 1'0 + Constant input on bit 27 of port B: 1'0 + Constant input on bit 28 of port B: 1'0 + Constant input on bit 29 of port B: 1'0 + Constant input on bit 30 of port B: 1'0 + Constant input on bit 31 of port B: 1'0 + Constant input on bit 0 of port A: 1'0 + Constant input on bit 1 of port A: 1'0 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'0 + Constant input on bit 4 of port A: 1'0 + Constant input on bit 5 of port A: 1'0 + Constant input on bit 6 of port A: 1'0 + Constant input on bit 7 of port A: 1'0 + Constant input on bit 8 of port A: 1'0 + Constant input on bit 9 of port A: 1'0 + Constant input on bit 10 of port A: 1'1 + Constant input on bit 11 of port A: 1'0 + Constant input on bit 12 of port A: 1'0 + Constant input on bit 13 of port A: 1'0 + Constant input on bit 14 of port A: 1'0 + Constant input on bit 15 of port A: 1'0 + Constant input on bit 16 of port A: 1'0 + Constant input on bit 17 of port A: 1'0 + Constant input on bit 18 of port A: 1'1 + Constant input on bit 19 of port A: 1'0 + Constant input on bit 20 of port A: 1'0 + Constant input on bit 21 of port A: 1'0 + Constant input on bit 22 of port A: 1'0 + Constant input on bit 23 of port A: 1'0 + Constant input on bit 24 of port A: 1'0 + Constant input on bit 25 of port A: 1'0 + Constant input on bit 26 of port A: 1'1 + Constant input on bit 27 of port A: 1'0 + Constant input on bit 28 of port A: 1'0 + Constant input on bit 29 of port A: 1'0 + Constant input on bit 30 of port A: 1'0 + Constant input on bit 31 of port A: 1'0 + Constant input on bit 32 of port A: 1'0 + Constant input on bit 33 of port A: 1'0 + Constant input on bit 34 of port A: 1'1 + Constant input on bit 35 of port A: 1'0 + Constant input on bit 36 of port A: 1'0 + Constant input on bit 37 of port A: 1'0 + Constant input on bit 38 of port A: 1'0 + Constant input on bit 39 of port A: 1'0 + Constant input on bit 40 of port A: 1'0 + Constant input on bit 41 of port A: 1'0 + Constant input on bit 42 of port A: 1'1 + Constant input on bit 43 of port A: 1'0 + Constant input on bit 44 of port A: 1'0 + Constant input on bit 45 of port A: 1'0 + Constant input on bit 46 of port A: 1'0 + Constant input on bit 47 of port A: 1'0 + Constant input on bit 48 of port A: 1'0 + Constant input on bit 49 of port A: 1'0 + Constant input on bit 50 of port A: 1'1 + Constant input on bit 51 of port A: 1'0 + Constant input on bit 52 of port A: 1'0 + Constant input on bit 53 of port A: 1'0 + Constant input on bit 54 of port A: 1'0 + Constant input on bit 55 of port A: 1'0 + Constant input on bit 56 of port A: 1'0 + Constant input on bit 57 of port A: 1'0 + Constant input on bit 58 of port A: 1'1 + Constant input on bit 59 of port A: 1'0 + Constant input on bit 60 of port A: 1'0 + Constant input on bit 61 of port A: 1'0 + Constant input on bit 62 of port A: 1'0 + Constant input on bit 63 of port A: 1'0 + Constant input on bit 64 of port A: 1'0 + Constant input on bit 65 of port A: 1'0 + Constant input on bit 66 of port A: 1'1 + Constant input on bit 67 of port A: 1'0 + Constant input on bit 68 of port A: 1'0 + Constant input on bit 69 of port A: 1'0 + Constant input on bit 70 of port A: 1'0 + Constant input on bit 71 of port A: 1'0 + Constant input on bit 72 of port A: 1'0 + Constant input on bit 73 of port A: 1'0 + Constant input on bit 74 of port A: 1'1 + Constant input on bit 75 of port A: 1'0 + Constant input on bit 76 of port A: 1'0 + Constant input on bit 77 of port A: 1'0 + Constant input on bit 78 of port A: 1'0 + Constant input on bit 79 of port A: 1'0 + Constant input on bit 80 of port A: 1'0 + Constant input on bit 81 of port A: 1'0 + Constant input on bit 82 of port A: 1'1 + Constant input on bit 83 of port A: 1'0 + Constant input on bit 84 of port A: 1'0 + Constant input on bit 85 of port A: 1'0 + Constant input on bit 86 of port A: 1'0 + Constant input on bit 87 of port A: 1'0 + Constant input on bit 88 of port A: 1'0 + Constant input on bit 89 of port A: 1'0 + Constant input on bit 90 of port A: 1'1 + Constant input on bit 91 of port A: 1'0 + Constant input on bit 92 of port A: 1'0 + Constant input on bit 93 of port A: 1'0 + Constant input on bit 94 of port A: 1'0 + Constant input on bit 95 of port A: 1'0 + Constant input on bit 96 of port A: 1'0 + Constant input on bit 97 of port A: 1'0 + Constant input on bit 98 of port A: 1'1 + Constant input on bit 99 of port A: 1'0 + Constant input on bit 100 of port A: 1'0 + Constant input on bit 101 of port A: 1'0 + Constant input on bit 102 of port A: 1'0 + Constant input on bit 103 of port A: 1'0 + Constant input on bit 104 of port A: 1'0 + Constant input on bit 105 of port A: 1'0 + Constant input on bit 106 of port A: 1'1 + Constant input on bit 107 of port A: 1'0 + Constant input on bit 108 of port A: 1'0 + Constant input on bit 109 of port A: 1'0 + Constant input on bit 110 of port A: 1'0 + Constant input on bit 111 of port A: 1'0 + Constant input on bit 112 of port A: 1'0 + Constant input on bit 113 of port A: 1'0 + Constant input on bit 114 of port A: 1'1 + Constant input on bit 115 of port A: 1'0 + Constant input on bit 116 of port A: 1'0 + Constant input on bit 117 of port A: 1'0 + Constant input on bit 118 of port A: 1'0 + Constant input on bit 119 of port A: 1'0 + Constant input on bit 120 of port A: 1'0 + Constant input on bit 121 of port A: 1'0 + Constant input on bit 122 of port A: 1'1 + Constant input on bit 123 of port A: 1'0 + Constant input on bit 124 of port A: 1'0 + Constant input on bit 125 of port A: 1'0 + Constant input on bit 126 of port A: 1'0 + Constant input on bit 127 of port A: 1'0 + Constant input on bit 128 of port A: 1'0 + Constant input on bit 129 of port A: 1'0 + Constant input on bit 130 of port A: 1'1 + Constant input on bit 131 of port A: 1'0 + Constant input on bit 132 of port A: 1'0 + Constant input on bit 133 of port A: 1'0 + Constant input on bit 134 of port A: 1'0 + Constant input on bit 135 of port A: 1'0 + Constant input on bit 136 of port A: 1'0 + Constant input on bit 137 of port A: 1'0 + Constant input on bit 138 of port A: 1'1 + Constant input on bit 139 of port A: 1'0 + Constant input on bit 140 of port A: 1'0 + Constant input on bit 141 of port A: 1'0 + Constant input on bit 142 of port A: 1'0 + Constant input on bit 143 of port A: 1'0 + Constant input on bit 144 of port A: 1'0 + Constant input on bit 145 of port A: 1'0 + Constant input on bit 146 of port A: 1'1 + Constant input on bit 147 of port A: 1'0 + Constant input on bit 148 of port A: 1'0 + Constant input on bit 149 of port A: 1'0 + Constant input on bit 150 of port A: 1'0 + Constant input on bit 151 of port A: 1'0 + Constant input on bit 152 of port A: 1'0 + Constant input on bit 153 of port A: 1'0 + Constant input on bit 154 of port A: 1'1 + Constant input on bit 155 of port A: 1'0 + Constant input on bit 156 of port A: 1'0 + Constant input on bit 157 of port A: 1'0 + Constant input on bit 158 of port A: 1'0 + Constant input on bit 159 of port A: 1'0 + Constant input on bit 160 of port A: 1'0 + Constant input on bit 161 of port A: 1'0 + Constant input on bit 162 of port A: 1'1 + Constant input on bit 163 of port A: 1'0 + Constant input on bit 164 of port A: 1'0 + Constant input on bit 165 of port A: 1'0 + Constant input on bit 166 of port A: 1'0 + Constant input on bit 167 of port A: 1'0 + Constant input on bit 168 of port A: 1'0 + Constant input on bit 169 of port A: 1'0 + Constant input on bit 170 of port A: 1'1 + Constant input on bit 171 of port A: 1'0 + Constant input on bit 172 of port A: 1'0 + Constant input on bit 173 of port A: 1'0 + Constant input on bit 174 of port A: 1'0 + Constant input on bit 175 of port A: 1'0 + Constant input on bit 176 of port A: 1'0 + Constant input on bit 177 of port A: 1'0 + Constant input on bit 178 of port A: 1'1 + Constant input on bit 179 of port A: 1'0 + Constant input on bit 180 of port A: 1'0 + Constant input on bit 181 of port A: 1'0 + Constant input on bit 182 of port A: 1'0 + Constant input on bit 183 of port A: 1'0 + Constant input on bit 184 of port A: 1'0 + Constant input on bit 185 of port A: 1'0 + Constant input on bit 186 of port A: 1'1 + Constant input on bit 187 of port A: 1'0 + Constant input on bit 188 of port A: 1'0 + Constant input on bit 189 of port A: 1'0 + Constant input on bit 190 of port A: 1'0 + Constant input on bit 191 of port A: 1'0 + Constant input on bit 192 of port A: 1'0 + Constant input on bit 193 of port A: 1'0 + Constant input on bit 194 of port A: 1'1 + Constant input on bit 195 of port A: 1'0 + Constant input on bit 196 of port A: 1'0 + Constant input on bit 197 of port A: 1'0 + Constant input on bit 198 of port A: 1'0 + Constant input on bit 199 of port A: 1'0 + Constant input on bit 200 of port A: 1'0 + Constant input on bit 201 of port A: 1'0 + Constant input on bit 202 of port A: 1'1 + Constant input on bit 203 of port A: 1'0 + Constant input on bit 204 of port A: 1'0 + Constant input on bit 205 of port A: 1'0 + Constant input on bit 206 of port A: 1'0 + Constant input on bit 207 of port A: 1'0 + Constant input on bit 208 of port A: 1'0 + Constant input on bit 209 of port A: 1'0 + Constant input on bit 210 of port A: 1'1 + Constant input on bit 211 of port A: 1'0 + Constant input on bit 212 of port A: 1'0 + Constant input on bit 213 of port A: 1'0 + Constant input on bit 214 of port A: 1'0 + Constant input on bit 215 of port A: 1'0 + Constant input on bit 216 of port A: 1'0 + Constant input on bit 217 of port A: 1'0 + Constant input on bit 218 of port A: 1'1 + Constant input on bit 219 of port A: 1'0 + Constant input on bit 220 of port A: 1'0 + Constant input on bit 221 of port A: 1'0 + Constant input on bit 222 of port A: 1'0 + Constant input on bit 223 of port A: 1'0 + Constant input on bit 224 of port A: 1'0 + Constant input on bit 225 of port A: 1'0 + Constant input on bit 226 of port A: 1'1 + Constant input on bit 227 of port A: 1'0 + Constant input on bit 228 of port A: 1'0 + Constant input on bit 229 of port A: 1'0 + Constant input on bit 230 of port A: 1'0 + Constant input on bit 231 of port A: 1'0 + Constant input on bit 232 of port A: 1'0 + Constant input on bit 233 of port A: 1'0 + Constant input on bit 234 of port A: 1'1 + Constant input on bit 235 of port A: 1'0 + Constant input on bit 236 of port A: 1'0 + Constant input on bit 237 of port A: 1'0 + Constant input on bit 238 of port A: 1'0 + Constant input on bit 239 of port A: 1'0 + Constant input on bit 240 of port A: 1'0 + Constant input on bit 241 of port A: 1'0 + Constant input on bit 242 of port A: 1'1 + Constant input on bit 243 of port A: 1'0 + Constant input on bit 244 of port A: 1'0 + Constant input on bit 245 of port A: 1'0 + Constant input on bit 246 of port A: 1'0 + Constant input on bit 247 of port A: 1'0 + Constant input on bit 248 of port A: 1'0 + Constant input on bit 249 of port A: 1'0 + Constant input on bit 250 of port A: 1'1 + Constant input on bit 251 of port A: 1'0 + Constant input on bit 252 of port A: 1'0 + Constant input on bit 253 of port A: 1'0 + Constant input on bit 254 of port A: 1'0 + Constant input on bit 255 of port A: 1'0 + Constant input on bit 256 of port A: 1'0 + Constant input on bit 257 of port A: 1'0 + Constant input on bit 258 of port A: 1'0 + Constant input on bit 259 of port A: 1'0 + Constant input on bit 260 of port A: 1'0 + Constant input on bit 261 of port A: 1'0 + Constant input on bit 262 of port A: 1'0 + Constant input on bit 263 of port A: 1'0 + Constant input on bit 264 of port A: 1'0 + Constant input on bit 265 of port A: 1'0 + Constant input on bit 266 of port A: 1'0 + Constant input on bit 267 of port A: 1'0 + Constant input on bit 268 of port A: 1'0 + Constant input on bit 269 of port A: 1'0 + Constant input on bit 270 of port A: 1'0 + Constant input on bit 271 of port A: 1'0 + Constant input on bit 272 of port A: 1'0 + Constant input on bit 273 of port A: 1'0 + Constant input on bit 274 of port A: 1'0 + Constant input on bit 275 of port A: 1'0 + Constant input on bit 276 of port A: 1'0 + Constant input on bit 277 of port A: 1'0 + Constant input on bit 278 of port A: 1'0 + Constant input on bit 279 of port A: 1'0 + Constant input on bit 280 of port A: 1'0 + Constant input on bit 281 of port A: 1'0 + Constant input on bit 282 of port A: 1'0 + Constant input on bit 283 of port A: 1'0 + Constant input on bit 284 of port A: 1'0 + Constant input on bit 285 of port A: 1'0 + Constant input on bit 286 of port A: 1'0 + Constant input on bit 287 of port A: 1'0 + Constant input on bit 288 of port A: 1'0 + Constant input on bit 289 of port A: 1'0 + Constant input on bit 290 of port A: 1'0 + Constant input on bit 291 of port A: 1'0 + Constant input on bit 292 of port A: 1'0 + Constant input on bit 293 of port A: 1'0 + Constant input on bit 294 of port A: 1'0 + Constant input on bit 295 of port A: 1'0 + Constant input on bit 296 of port A: 1'0 + Constant input on bit 297 of port A: 1'0 + Constant input on bit 298 of port A: 1'0 + Constant input on bit 299 of port A: 1'0 + Constant input on bit 300 of port A: 1'0 + Constant input on bit 301 of port A: 1'0 + Constant input on bit 302 of port A: 1'0 + Constant input on bit 303 of port A: 1'0 + Constant input on bit 304 of port A: 1'0 + Constant input on bit 305 of port A: 1'0 + Constant input on bit 306 of port A: 1'0 + Constant input on bit 307 of port A: 1'0 + Constant input on bit 308 of port A: 1'0 + Constant input on bit 309 of port A: 1'0 + Constant input on bit 310 of port A: 1'0 + Constant input on bit 311 of port A: 1'0 + Constant input on bit 312 of port A: 1'0 + Constant input on bit 313 of port A: 1'0 + Constant input on bit 314 of port A: 1'0 + Constant input on bit 315 of port A: 1'0 + Constant input on bit 316 of port A: 1'0 + Constant input on bit 317 of port A: 1'0 + Constant input on bit 318 of port A: 1'0 + Constant input on bit 319 of port A: 1'0 + Constant input on bit 320 of port A: 1'0 + Constant input on bit 321 of port A: 1'0 + Constant input on bit 322 of port A: 1'0 + Constant input on bit 323 of port A: 1'0 + Constant input on bit 324 of port A: 1'0 + Constant input on bit 325 of port A: 1'0 + Constant input on bit 326 of port A: 1'0 + Constant input on bit 327 of port A: 1'0 + Constant input on bit 328 of port A: 1'0 + Constant input on bit 329 of port A: 1'0 + Constant input on bit 330 of port A: 1'0 + Constant input on bit 331 of port A: 1'0 + Constant input on bit 332 of port A: 1'0 + Constant input on bit 333 of port A: 1'0 + Constant input on bit 334 of port A: 1'0 + Constant input on bit 335 of port A: 1'0 + Constant input on bit 336 of port A: 1'0 + Constant input on bit 337 of port A: 1'0 + Constant input on bit 338 of port A: 1'0 + Constant input on bit 339 of port A: 1'0 + Constant input on bit 340 of port A: 1'0 + Constant input on bit 341 of port A: 1'0 + Constant input on bit 342 of port A: 1'0 + Constant input on bit 343 of port A: 1'0 + Constant input on bit 344 of port A: 1'0 + Constant input on bit 345 of port A: 1'0 + Constant input on bit 346 of port A: 1'0 + Constant input on bit 347 of port A: 1'0 + Constant input on bit 348 of port A: 1'0 + Constant input on bit 349 of port A: 1'0 + Constant input on bit 350 of port A: 1'0 + Constant input on bit 351 of port A: 1'0 + Constant input on bit 352 of port A: 1'0 + Constant input on bit 353 of port A: 1'0 + Constant input on bit 354 of port A: 1'0 + Constant input on bit 355 of port A: 1'0 + Constant input on bit 356 of port A: 1'0 + Constant input on bit 357 of port A: 1'0 + Constant input on bit 358 of port A: 1'0 + Constant input on bit 359 of port A: 1'0 + Constant input on bit 360 of port A: 1'0 + Constant input on bit 361 of port A: 1'0 + Constant input on bit 362 of port A: 1'0 + Constant input on bit 363 of port A: 1'0 + Constant input on bit 364 of port A: 1'0 + Constant input on bit 365 of port A: 1'0 + Constant input on bit 366 of port A: 1'0 + Constant input on bit 367 of port A: 1'0 + Constant input on bit 368 of port A: 1'0 + Constant input on bit 369 of port A: 1'0 + Constant input on bit 370 of port A: 1'0 + Constant input on bit 371 of port A: 1'0 + Constant input on bit 372 of port A: 1'0 + Constant input on bit 373 of port A: 1'0 + Constant input on bit 374 of port A: 1'0 + Constant input on bit 375 of port A: 1'0 + Constant input on bit 376 of port A: 1'0 + Constant input on bit 377 of port A: 1'0 + Constant input on bit 378 of port A: 1'0 + Constant input on bit 379 of port A: 1'0 + Constant input on bit 380 of port A: 1'0 + Constant input on bit 381 of port A: 1'0 + Constant input on bit 382 of port A: 1'0 + Constant input on bit 383 of port A: 1'0 + Constant input on bit 384 of port A: 1'0 + Constant input on bit 385 of port A: 1'0 + Constant input on bit 386 of port A: 1'0 + Constant input on bit 387 of port A: 1'0 + Constant input on bit 388 of port A: 1'0 + Constant input on bit 389 of port A: 1'0 + Constant input on bit 390 of port A: 1'0 + Constant input on bit 391 of port A: 1'0 + Constant input on bit 392 of port A: 1'0 + Constant input on bit 393 of port A: 1'0 + Constant input on bit 394 of port A: 1'0 + Constant input on bit 395 of port A: 1'0 + Constant input on bit 396 of port A: 1'0 + Constant input on bit 397 of port A: 1'0 + Constant input on bit 398 of port A: 1'0 + Constant input on bit 399 of port A: 1'0 + Constant input on bit 400 of port A: 1'0 + Constant input on bit 401 of port A: 1'0 + Constant input on bit 402 of port A: 1'0 + Constant input on bit 403 of port A: 1'0 + Constant input on bit 404 of port A: 1'0 + Constant input on bit 405 of port A: 1'0 + Constant input on bit 406 of port A: 1'0 + Constant input on bit 407 of port A: 1'0 + Constant input on bit 408 of port A: 1'0 + Constant input on bit 409 of port A: 1'0 + Constant input on bit 410 of port A: 1'0 + Constant input on bit 411 of port A: 1'0 + Constant input on bit 412 of port A: 1'0 + Constant input on bit 413 of port A: 1'0 + Constant input on bit 414 of port A: 1'0 + Constant input on bit 415 of port A: 1'0 + Constant input on bit 416 of port A: 1'0 + Constant input on bit 417 of port A: 1'0 + Constant input on bit 418 of port A: 1'0 + Constant input on bit 419 of port A: 1'0 + Constant input on bit 420 of port A: 1'0 + Constant input on bit 421 of port A: 1'0 + Constant input on bit 422 of port A: 1'0 + Constant input on bit 423 of port A: 1'0 + Constant input on bit 424 of port A: 1'0 + Constant input on bit 425 of port A: 1'0 + Constant input on bit 426 of port A: 1'0 + Constant input on bit 427 of port A: 1'0 + Constant input on bit 428 of port A: 1'0 + Constant input on bit 429 of port A: 1'0 + Constant input on bit 430 of port A: 1'0 + Constant input on bit 431 of port A: 1'0 + Constant input on bit 432 of port A: 1'0 + Constant input on bit 433 of port A: 1'0 + Constant input on bit 434 of port A: 1'0 + Constant input on bit 435 of port A: 1'0 + Constant input on bit 436 of port A: 1'0 + Constant input on bit 437 of port A: 1'0 + Constant input on bit 438 of port A: 1'0 + Constant input on bit 439 of port A: 1'0 + Constant input on bit 440 of port A: 1'0 + Constant input on bit 441 of port A: 1'0 + Constant input on bit 442 of port A: 1'0 + Constant input on bit 443 of port A: 1'0 + Constant input on bit 444 of port A: 1'0 + Constant input on bit 445 of port A: 1'0 + Constant input on bit 446 of port A: 1'0 + Constant input on bit 447 of port A: 1'0 + Constant input on bit 448 of port A: 1'0 + Constant input on bit 449 of port A: 1'0 + Constant input on bit 450 of port A: 1'0 + Constant input on bit 451 of port A: 1'0 + Constant input on bit 452 of port A: 1'0 + Constant input on bit 453 of port A: 1'0 + Constant input on bit 454 of port A: 1'0 + Constant input on bit 455 of port A: 1'0 + Constant input on bit 456 of port A: 1'0 + Constant input on bit 457 of port A: 1'0 + Constant input on bit 458 of port A: 1'0 + Constant input on bit 459 of port A: 1'0 + Constant input on bit 460 of port A: 1'0 + Constant input on bit 461 of port A: 1'0 + Constant input on bit 462 of port A: 1'0 + Constant input on bit 463 of port A: 1'0 + Constant input on bit 464 of port A: 1'0 + Constant input on bit 465 of port A: 1'0 + Constant input on bit 466 of port A: 1'0 + Constant input on bit 467 of port A: 1'0 + Constant input on bit 468 of port A: 1'0 + Constant input on bit 469 of port A: 1'0 + Constant input on bit 470 of port A: 1'0 + Constant input on bit 471 of port A: 1'0 + Constant input on bit 472 of port A: 1'0 + Constant input on bit 473 of port A: 1'0 + Constant input on bit 474 of port A: 1'0 + Constant input on bit 475 of port A: 1'0 + Constant input on bit 476 of port A: 1'0 + Constant input on bit 477 of port A: 1'0 + Constant input on bit 478 of port A: 1'0 + Constant input on bit 479 of port A: 1'0 + Constant input on bit 480 of port A: 1'0 + Constant input on bit 481 of port A: 1'0 + Constant input on bit 482 of port A: 1'0 + Constant input on bit 483 of port A: 1'0 + Constant input on bit 484 of port A: 1'0 + Constant input on bit 485 of port A: 1'0 + Constant input on bit 486 of port A: 1'0 + Constant input on bit 487 of port A: 1'0 + Constant input on bit 488 of port A: 1'0 + Constant input on bit 489 of port A: 1'0 + Constant input on bit 490 of port A: 1'0 + Constant input on bit 491 of port A: 1'0 + Constant input on bit 492 of port A: 1'0 + Constant input on bit 493 of port A: 1'0 + Constant input on bit 494 of port A: 1'0 + Constant input on bit 495 of port A: 1'0 + Constant input on bit 496 of port A: 1'0 + Constant input on bit 497 of port A: 1'0 + Constant input on bit 498 of port A: 1'0 + Constant input on bit 499 of port A: 1'0 + Constant input on bit 500 of port A: 1'0 + Constant input on bit 501 of port A: 1'0 + Constant input on bit 502 of port A: 1'0 + Constant input on bit 503 of port A: 1'0 + Constant input on bit 504 of port A: 1'0 + Constant input on bit 505 of port A: 1'0 + Constant input on bit 506 of port A: 1'0 + Constant input on bit 507 of port A: 1'0 + Constant input on bit 508 of port A: 1'0 + Constant input on bit 509 of port A: 1'0 + Constant input on bit 510 of port A: 1'0 + Constant input on bit 511 of port A: 1'0 + Constant input on bit 512 of port A: 1'0 + Constant input on bit 513 of port A: 1'0 + Constant input on bit 514 of port A: 1'0 + Constant input on bit 515 of port A: 1'0 + Constant input on bit 516 of port A: 1'0 + Constant input on bit 517 of port A: 1'0 + Constant input on bit 518 of port A: 1'0 + Constant input on bit 519 of port A: 1'0 + Constant input on bit 520 of port A: 1'0 + Constant input on bit 521 of port A: 1'0 + Constant input on bit 522 of port A: 1'0 + Constant input on bit 523 of port A: 1'0 + Constant input on bit 524 of port A: 1'0 + Constant input on bit 525 of port A: 1'0 + Constant input on bit 526 of port A: 1'0 + Constant input on bit 527 of port A: 1'0 + Constant input on bit 528 of port A: 1'0 + Constant input on bit 529 of port A: 1'0 + Constant input on bit 530 of port A: 1'0 + Constant input on bit 531 of port A: 1'0 + Constant input on bit 532 of port A: 1'0 + Constant input on bit 533 of port A: 1'0 + Constant input on bit 534 of port A: 1'0 + Constant input on bit 535 of port A: 1'0 + Constant input on bit 536 of port A: 1'0 + Constant input on bit 537 of port A: 1'0 + Constant input on bit 538 of port A: 1'0 + Constant input on bit 539 of port A: 1'0 + Constant input on bit 540 of port A: 1'0 + Constant input on bit 541 of port A: 1'0 + Constant input on bit 542 of port A: 1'0 + Constant input on bit 543 of port A: 1'0 + Constant input on bit 544 of port A: 1'0 + Constant input on bit 545 of port A: 1'0 + Constant input on bit 546 of port A: 1'0 + Constant input on bit 547 of port A: 1'0 + Constant input on bit 548 of port A: 1'0 + Constant input on bit 549 of port A: 1'0 + Constant input on bit 550 of port A: 1'0 + Constant input on bit 551 of port A: 1'0 + Constant input on bit 552 of port A: 1'0 + Constant input on bit 553 of port A: 1'0 + Constant input on bit 554 of port A: 1'0 + Constant input on bit 555 of port A: 1'0 + Constant input on bit 556 of port A: 1'0 + Constant input on bit 557 of port A: 1'0 + Constant input on bit 558 of port A: 1'0 + Constant input on bit 559 of port A: 1'0 + Constant input on bit 560 of port A: 1'0 + Constant input on bit 561 of port A: 1'0 + Constant input on bit 562 of port A: 1'0 + Constant input on bit 563 of port A: 1'0 + Constant input on bit 564 of port A: 1'0 + Constant input on bit 565 of port A: 1'0 + Constant input on bit 566 of port A: 1'0 + Constant input on bit 567 of port A: 1'0 + Constant input on bit 568 of port A: 1'0 + Constant input on bit 569 of port A: 1'0 + Constant input on bit 570 of port A: 1'0 + Constant input on bit 571 of port A: 1'0 + Constant input on bit 572 of port A: 1'0 + Constant input on bit 573 of port A: 1'0 + Constant input on bit 574 of port A: 1'0 + Constant input on bit 575 of port A: 1'0 + Constant input on bit 576 of port A: 1'0 + Constant input on bit 577 of port A: 1'0 + Constant input on bit 578 of port A: 1'0 + Constant input on bit 579 of port A: 1'0 + Constant input on bit 580 of port A: 1'0 + Constant input on bit 581 of port A: 1'0 + Constant input on bit 582 of port A: 1'0 + Constant input on bit 583 of port A: 1'0 + Constant input on bit 584 of port A: 1'0 + Constant input on bit 585 of port A: 1'0 + Constant input on bit 586 of port A: 1'0 + Constant input on bit 587 of port A: 1'0 + Constant input on bit 588 of port A: 1'0 + Constant input on bit 589 of port A: 1'0 + Constant input on bit 590 of port A: 1'0 + Constant input on bit 591 of port A: 1'0 + Constant input on bit 592 of port A: 1'0 + Constant input on bit 593 of port A: 1'0 + Constant input on bit 594 of port A: 1'0 + Constant input on bit 595 of port A: 1'0 + Constant input on bit 596 of port A: 1'0 + Constant input on bit 597 of port A: 1'0 + Constant input on bit 598 of port A: 1'0 + Constant input on bit 599 of port A: 1'0 + Constant input on bit 600 of port A: 1'0 + Constant input on bit 601 of port A: 1'0 + Constant input on bit 602 of port A: 1'0 + Constant input on bit 603 of port A: 1'0 + Constant input on bit 604 of port A: 1'0 + Constant input on bit 605 of port A: 1'0 + Constant input on bit 606 of port A: 1'0 + Constant input on bit 607 of port A: 1'0 + Constant input on bit 608 of port A: 1'0 + Constant input on bit 609 of port A: 1'0 + Constant input on bit 610 of port A: 1'0 + Constant input on bit 611 of port A: 1'0 + Constant input on bit 612 of port A: 1'0 + Constant input on bit 613 of port A: 1'0 + Constant input on bit 614 of port A: 1'0 + Constant input on bit 615 of port A: 1'0 + Constant input on bit 616 of port A: 1'0 + Constant input on bit 617 of port A: 1'0 + Constant input on bit 618 of port A: 1'0 + Constant input on bit 619 of port A: 1'0 + Constant input on bit 620 of port A: 1'0 + Constant input on bit 621 of port A: 1'0 + Constant input on bit 622 of port A: 1'0 + Constant input on bit 623 of port A: 1'0 + Constant input on bit 624 of port A: 1'0 + Constant input on bit 625 of port A: 1'0 + Constant input on bit 626 of port A: 1'0 + Constant input on bit 627 of port A: 1'0 + Constant input on bit 628 of port A: 1'0 + Constant input on bit 629 of port A: 1'0 + Constant input on bit 630 of port A: 1'0 + Constant input on bit 631 of port A: 1'0 + Constant input on bit 632 of port A: 1'0 + Constant input on bit 633 of port A: 1'0 + Constant input on bit 634 of port A: 1'0 + Constant input on bit 635 of port A: 1'0 + Constant input on bit 636 of port A: 1'0 + Constant input on bit 637 of port A: 1'0 + Constant input on bit 638 of port A: 1'0 + Constant input on bit 639 of port A: 1'0 + Constant input on bit 640 of port A: 1'0 + Constant input on bit 641 of port A: 1'0 + Constant input on bit 642 of port A: 1'0 + Constant input on bit 643 of port A: 1'0 + Constant input on bit 644 of port A: 1'0 + Constant input on bit 645 of port A: 1'0 + Constant input on bit 646 of port A: 1'0 + Constant input on bit 647 of port A: 1'0 + Constant input on bit 648 of port A: 1'0 + Constant input on bit 649 of port A: 1'0 + Constant input on bit 650 of port A: 1'0 + Constant input on bit 651 of port A: 1'0 + Constant input on bit 652 of port A: 1'0 + Constant input on bit 653 of port A: 1'0 + Constant input on bit 654 of port A: 1'0 + Constant input on bit 655 of port A: 1'0 + Constant input on bit 656 of port A: 1'0 + Constant input on bit 657 of port A: 1'0 + Constant input on bit 658 of port A: 1'0 + Constant input on bit 659 of port A: 1'0 + Constant input on bit 660 of port A: 1'0 + Constant input on bit 661 of port A: 1'0 + Constant input on bit 662 of port A: 1'0 + Constant input on bit 663 of port A: 1'0 + Constant input on bit 664 of port A: 1'0 + Constant input on bit 665 of port A: 1'0 + Constant input on bit 666 of port A: 1'0 + Constant input on bit 667 of port A: 1'0 + Constant input on bit 668 of port A: 1'0 + Constant input on bit 669 of port A: 1'0 + Constant input on bit 670 of port A: 1'0 + Constant input on bit 671 of port A: 1'0 + Constant input on bit 672 of port A: 1'0 + Constant input on bit 673 of port A: 1'0 + Constant input on bit 674 of port A: 1'0 + Constant input on bit 675 of port A: 1'0 + Constant input on bit 676 of port A: 1'0 + Constant input on bit 677 of port A: 1'0 + Constant input on bit 678 of port A: 1'0 + Constant input on bit 679 of port A: 1'0 + Constant input on bit 680 of port A: 1'0 + Constant input on bit 681 of port A: 1'0 + Constant input on bit 682 of port A: 1'0 + Constant input on bit 683 of port A: 1'0 + Constant input on bit 684 of port A: 1'0 + Constant input on bit 685 of port A: 1'0 + Constant input on bit 686 of port A: 1'0 + Constant input on bit 687 of port A: 1'0 + Constant input on bit 688 of port A: 1'0 + Constant input on bit 689 of port A: 1'0 + Constant input on bit 690 of port A: 1'0 + Constant input on bit 691 of port A: 1'0 + Constant input on bit 692 of port A: 1'0 + Constant input on bit 693 of port A: 1'0 + Constant input on bit 694 of port A: 1'0 + Constant input on bit 695 of port A: 1'0 + Constant input on bit 696 of port A: 1'0 + Constant input on bit 697 of port A: 1'0 + Constant input on bit 698 of port A: 1'0 + Constant input on bit 699 of port A: 1'0 + Constant input on bit 700 of port A: 1'0 + Constant input on bit 701 of port A: 1'0 + Constant input on bit 702 of port A: 1'0 + Constant input on bit 703 of port A: 1'0 + Constant input on bit 704 of port A: 1'0 + Constant input on bit 705 of port A: 1'0 + Constant input on bit 706 of port A: 1'0 + Constant input on bit 707 of port A: 1'0 + Constant input on bit 708 of port A: 1'0 + Constant input on bit 709 of port A: 1'0 + Constant input on bit 710 of port A: 1'0 + Constant input on bit 711 of port A: 1'0 + Constant input on bit 712 of port A: 1'0 + Constant input on bit 713 of port A: 1'0 + Constant input on bit 714 of port A: 1'0 + Constant input on bit 715 of port A: 1'0 + Constant input on bit 716 of port A: 1'0 + Constant input on bit 717 of port A: 1'0 + Constant input on bit 718 of port A: 1'0 + Constant input on bit 719 of port A: 1'0 + Constant input on bit 720 of port A: 1'0 + Constant input on bit 721 of port A: 1'0 + Constant input on bit 722 of port A: 1'0 + Constant input on bit 723 of port A: 1'0 + Constant input on bit 724 of port A: 1'0 + Constant input on bit 725 of port A: 1'0 + Constant input on bit 726 of port A: 1'0 + Constant input on bit 727 of port A: 1'0 + Constant input on bit 728 of port A: 1'0 + Constant input on bit 729 of port A: 1'0 + Constant input on bit 730 of port A: 1'0 + Constant input on bit 731 of port A: 1'0 + Constant input on bit 732 of port A: 1'0 + Constant input on bit 733 of port A: 1'0 + Constant input on bit 734 of port A: 1'0 + Constant input on bit 735 of port A: 1'0 + Constant input on bit 736 of port A: 1'0 + Constant input on bit 737 of port A: 1'0 + Constant input on bit 738 of port A: 1'0 + Constant input on bit 739 of port A: 1'0 + Constant input on bit 740 of port A: 1'0 + Constant input on bit 741 of port A: 1'0 + Constant input on bit 742 of port A: 1'0 + Constant input on bit 743 of port A: 1'0 + Constant input on bit 744 of port A: 1'0 + Constant input on bit 745 of port A: 1'0 + Constant input on bit 746 of port A: 1'0 + Constant input on bit 747 of port A: 1'0 + Constant input on bit 748 of port A: 1'0 + Constant input on bit 749 of port A: 1'0 + Constant input on bit 750 of port A: 1'0 + Constant input on bit 751 of port A: 1'0 + Constant input on bit 752 of port A: 1'0 + Constant input on bit 753 of port A: 1'0 + Constant input on bit 754 of port A: 1'0 + Constant input on bit 755 of port A: 1'0 + Constant input on bit 756 of port A: 1'0 + Constant input on bit 757 of port A: 1'0 + Constant input on bit 758 of port A: 1'0 + Constant input on bit 759 of port A: 1'0 + Constant input on bit 760 of port A: 1'0 + Constant input on bit 761 of port A: 1'0 + Constant input on bit 762 of port A: 1'0 + Constant input on bit 763 of port A: 1'0 + Constant input on bit 764 of port A: 1'0 + Constant input on bit 765 of port A: 1'0 + Constant input on bit 766 of port A: 1'0 + Constant input on bit 767 of port A: 1'0 + Constant input on bit 768 of port A: 1'0 + Constant input on bit 769 of port A: 1'0 + Constant input on bit 770 of port A: 1'0 + Constant input on bit 771 of port A: 1'0 + Constant input on bit 772 of port A: 1'0 + Constant input on bit 773 of port A: 1'0 + Constant input on bit 774 of port A: 1'0 + Constant input on bit 775 of port A: 1'0 + Constant input on bit 776 of port A: 1'0 + Constant input on bit 777 of port A: 1'0 + Constant input on bit 778 of port A: 1'0 + Constant input on bit 779 of port A: 1'0 + Constant input on bit 780 of port A: 1'0 + Constant input on bit 781 of port A: 1'0 + Constant input on bit 782 of port A: 1'0 + Constant input on bit 783 of port A: 1'0 + Constant input on bit 784 of port A: 1'0 + Constant input on bit 785 of port A: 1'0 + Constant input on bit 786 of port A: 1'0 + Constant input on bit 787 of port A: 1'0 + Constant input on bit 788 of port A: 1'0 + Constant input on bit 789 of port A: 1'0 + Constant input on bit 790 of port A: 1'0 + Constant input on bit 791 of port A: 1'0 + Constant input on bit 792 of port A: 1'0 + Constant input on bit 793 of port A: 1'0 + Constant input on bit 794 of port A: 1'0 + Constant input on bit 795 of port A: 1'0 + Constant input on bit 796 of port A: 1'0 + Constant input on bit 797 of port A: 1'0 + Constant input on bit 798 of port A: 1'0 + Constant input on bit 799 of port A: 1'0 + Constant input on bit 800 of port A: 1'0 + Constant input on bit 801 of port A: 1'0 + Constant input on bit 802 of port A: 1'0 + Constant input on bit 803 of port A: 1'0 + Constant input on bit 804 of port A: 1'0 + Constant input on bit 805 of port A: 1'0 + Constant input on bit 806 of port A: 1'0 + Constant input on bit 807 of port A: 1'0 + Constant input on bit 808 of port A: 1'0 + Constant input on bit 809 of port A: 1'0 + Constant input on bit 810 of port A: 1'0 + Constant input on bit 811 of port A: 1'0 + Constant input on bit 812 of port A: 1'0 + Constant input on bit 813 of port A: 1'0 + Constant input on bit 814 of port A: 1'0 + Constant input on bit 815 of port A: 1'0 + Constant input on bit 816 of port A: 1'0 + Constant input on bit 817 of port A: 1'0 + Constant input on bit 818 of port A: 1'0 + Constant input on bit 819 of port A: 1'0 + Constant input on bit 820 of port A: 1'0 + Constant input on bit 821 of port A: 1'0 + Constant input on bit 822 of port A: 1'0 + Constant input on bit 823 of port A: 1'0 + Constant input on bit 824 of port A: 1'0 + Constant input on bit 825 of port A: 1'0 + Constant input on bit 826 of port A: 1'0 + Constant input on bit 827 of port A: 1'0 + Constant input on bit 828 of port A: 1'0 + Constant input on bit 829 of port A: 1'0 + Constant input on bit 830 of port A: 1'0 + Constant input on bit 831 of port A: 1'0 + Constant input on bit 832 of port A: 1'0 + Constant input on bit 833 of port A: 1'0 + Constant input on bit 834 of port A: 1'0 + Constant input on bit 835 of port A: 1'0 + Constant input on bit 836 of port A: 1'0 + Constant input on bit 837 of port A: 1'0 + Constant input on bit 838 of port A: 1'0 + Constant input on bit 839 of port A: 1'0 + Constant input on bit 840 of port A: 1'0 + Constant input on bit 841 of port A: 1'0 + Constant input on bit 842 of port A: 1'0 + Constant input on bit 843 of port A: 1'0 + Constant input on bit 844 of port A: 1'0 + Constant input on bit 845 of port A: 1'0 + Constant input on bit 846 of port A: 1'0 + Constant input on bit 847 of port A: 1'0 + Constant input on bit 848 of port A: 1'0 + Constant input on bit 849 of port A: 1'0 + Constant input on bit 850 of port A: 1'0 + Constant input on bit 851 of port A: 1'0 + Constant input on bit 852 of port A: 1'0 + Constant input on bit 853 of port A: 1'0 + Constant input on bit 854 of port A: 1'0 + Constant input on bit 855 of port A: 1'0 + Constant input on bit 856 of port A: 1'0 + Constant input on bit 857 of port A: 1'0 + Constant input on bit 858 of port A: 1'0 + Constant input on bit 859 of port A: 1'0 + Constant input on bit 860 of port A: 1'0 + Constant input on bit 861 of port A: 1'0 + Constant input on bit 862 of port A: 1'0 + Constant input on bit 863 of port A: 1'0 + Constant input on bit 864 of port A: 1'0 + Constant input on bit 865 of port A: 1'0 + Constant input on bit 866 of port A: 1'0 + Constant input on bit 867 of port A: 1'0 + Constant input on bit 868 of port A: 1'0 + Constant input on bit 869 of port A: 1'0 + Constant input on bit 870 of port A: 1'0 + Constant input on bit 871 of port A: 1'0 + Constant input on bit 872 of port A: 1'0 + Constant input on bit 873 of port A: 1'0 + Constant input on bit 874 of port A: 1'0 + Constant input on bit 875 of port A: 1'0 + Constant input on bit 876 of port A: 1'0 + Constant input on bit 877 of port A: 1'0 + Constant input on bit 878 of port A: 1'0 + Constant input on bit 879 of port A: 1'0 + Constant input on bit 880 of port A: 1'0 + Constant input on bit 881 of port A: 1'0 + Constant input on bit 882 of port A: 1'0 + Constant input on bit 883 of port A: 1'0 + Constant input on bit 884 of port A: 1'0 + Constant input on bit 885 of port A: 1'0 + Constant input on bit 886 of port A: 1'0 + Constant input on bit 887 of port A: 1'0 + Constant input on bit 888 of port A: 1'0 + Constant input on bit 889 of port A: 1'0 + Constant input on bit 890 of port A: 1'0 + Constant input on bit 891 of port A: 1'0 + Constant input on bit 892 of port A: 1'0 + Constant input on bit 893 of port A: 1'0 + Constant input on bit 894 of port A: 1'0 + Constant input on bit 895 of port A: 1'0 + Constant input on bit 896 of port A: 1'0 + Constant input on bit 897 of port A: 1'0 + Constant input on bit 898 of port A: 1'0 + Constant input on bit 899 of port A: 1'0 + Constant input on bit 900 of port A: 1'0 + Constant input on bit 901 of port A: 1'0 + Constant input on bit 902 of port A: 1'0 + Constant input on bit 903 of port A: 1'0 + Constant input on bit 904 of port A: 1'0 + Constant input on bit 905 of port A: 1'0 + Constant input on bit 906 of port A: 1'0 + Constant input on bit 907 of port A: 1'0 + Constant input on bit 908 of port A: 1'0 + Constant input on bit 909 of port A: 1'0 + Constant input on bit 910 of port A: 1'0 + Constant input on bit 911 of port A: 1'0 + Constant input on bit 912 of port A: 1'0 + Constant input on bit 913 of port A: 1'0 + Constant input on bit 914 of port A: 1'0 + Constant input on bit 915 of port A: 1'0 + Constant input on bit 916 of port A: 1'0 + Constant input on bit 917 of port A: 1'0 + Constant input on bit 918 of port A: 1'0 + Constant input on bit 919 of port A: 1'0 + Constant input on bit 920 of port A: 1'0 + Constant input on bit 921 of port A: 1'0 + Constant input on bit 922 of port A: 1'0 + Constant input on bit 923 of port A: 1'0 + Constant input on bit 924 of port A: 1'0 + Constant input on bit 925 of port A: 1'0 + Constant input on bit 926 of port A: 1'0 + Constant input on bit 927 of port A: 1'0 + Constant input on bit 928 of port A: 1'0 + Constant input on bit 929 of port A: 1'0 + Constant input on bit 930 of port A: 1'0 + Constant input on bit 931 of port A: 1'0 + Constant input on bit 932 of port A: 1'0 + Constant input on bit 933 of port A: 1'0 + Constant input on bit 934 of port A: 1'0 + Constant input on bit 935 of port A: 1'0 + Constant input on bit 936 of port A: 1'0 + Constant input on bit 937 of port A: 1'0 + Constant input on bit 938 of port A: 1'0 + Constant input on bit 939 of port A: 1'0 + Constant input on bit 940 of port A: 1'0 + Constant input on bit 941 of port A: 1'0 + Constant input on bit 942 of port A: 1'0 + Constant input on bit 943 of port A: 1'0 + Constant input on bit 944 of port A: 1'0 + Constant input on bit 945 of port A: 1'0 + Constant input on bit 946 of port A: 1'0 + Constant input on bit 947 of port A: 1'0 + Constant input on bit 948 of port A: 1'0 + Constant input on bit 949 of port A: 1'0 + Constant input on bit 950 of port A: 1'0 + Constant input on bit 951 of port A: 1'0 + Constant input on bit 952 of port A: 1'0 + Constant input on bit 953 of port A: 1'0 + Constant input on bit 954 of port A: 1'0 + Constant input on bit 955 of port A: 1'0 + Constant input on bit 956 of port A: 1'0 + Constant input on bit 957 of port A: 1'0 + Constant input on bit 958 of port A: 1'0 + Constant input on bit 959 of port A: 1'0 + Constant input on bit 960 of port A: 1'0 + Constant input on bit 961 of port A: 1'0 + Constant input on bit 962 of port A: 1'0 + Constant input on bit 963 of port A: 1'0 + Constant input on bit 964 of port A: 1'0 + Constant input on bit 965 of port A: 1'0 + Constant input on bit 966 of port A: 1'0 + Constant input on bit 967 of port A: 1'0 + Constant input on bit 968 of port A: 1'0 + Constant input on bit 969 of port A: 1'0 + Constant input on bit 970 of port A: 1'0 + Constant input on bit 971 of port A: 1'0 + Constant input on bit 972 of port A: 1'0 + Constant input on bit 973 of port A: 1'0 + Constant input on bit 974 of port A: 1'0 + Constant input on bit 975 of port A: 1'0 + Constant input on bit 976 of port A: 1'0 + Constant input on bit 977 of port A: 1'0 + Constant input on bit 978 of port A: 1'0 + Constant input on bit 979 of port A: 1'0 + Constant input on bit 980 of port A: 1'0 + Constant input on bit 981 of port A: 1'0 + Constant input on bit 982 of port A: 1'0 + Constant input on bit 983 of port A: 1'0 + Constant input on bit 984 of port A: 1'0 + Constant input on bit 985 of port A: 1'0 + Constant input on bit 986 of port A: 1'0 + Constant input on bit 987 of port A: 1'0 + Constant input on bit 988 of port A: 1'0 + Constant input on bit 989 of port A: 1'0 + Constant input on bit 990 of port A: 1'0 + Constant input on bit 991 of port A: 1'0 + Constant input on bit 992 of port A: 1'0 + Constant input on bit 993 of port A: 1'0 + Constant input on bit 994 of port A: 1'0 + Constant input on bit 995 of port A: 1'0 + Constant input on bit 996 of port A: 1'0 + Constant input on bit 997 of port A: 1'0 + Constant input on bit 998 of port A: 1'0 + Constant input on bit 999 of port A: 1'0 + Constant input on bit 1000 of port A: 1'0 + Constant input on bit 1001 of port A: 1'0 + Constant input on bit 1002 of port A: 1'0 + Constant input on bit 1003 of port A: 1'0 + Constant input on bit 1004 of port A: 1'0 + Constant input on bit 1005 of port A: 1'0 + Constant input on bit 1006 of port A: 1'0 + Constant input on bit 1007 of port A: 1'0 + Constant input on bit 1008 of port A: 1'0 + Constant input on bit 1009 of port A: 1'0 + Constant input on bit 1010 of port A: 1'0 + Constant input on bit 1011 of port A: 1'0 + Constant input on bit 1012 of port A: 1'0 + Constant input on bit 1013 of port A: 1'0 + Constant input on bit 1014 of port A: 1'0 + Constant input on bit 1015 of port A: 1'0 + Constant input on bit 1016 of port A: 1'0 + Constant input on bit 1017 of port A: 1'0 + Constant input on bit 1018 of port A: 1'0 + Constant input on bit 1019 of port A: 1'0 + Constant input on bit 1020 of port A: 1'0 + Constant input on bit 1021 of port A: 1'0 + Constant input on bit 1022 of port A: 1'0 + Constant input on bit 1023 of port A: 1'0 + Constant input on bit 1024 of port A: 1'0 + Constant input on bit 1025 of port A: 1'0 + Constant input on bit 1026 of port A: 1'0 + Constant input on bit 1027 of port A: 1'0 + Constant input on bit 1028 of port A: 1'0 + Constant input on bit 1029 of port A: 1'0 + Constant input on bit 1030 of port A: 1'0 + Constant input on bit 1031 of port A: 1'0 + Constant input on bit 1032 of port A: 1'0 + Constant input on bit 1033 of port A: 1'0 + Constant input on bit 1034 of port A: 1'0 + Constant input on bit 1035 of port A: 1'0 + Constant input on bit 1036 of port A: 1'0 + Constant input on bit 1037 of port A: 1'0 + Constant input on bit 1038 of port A: 1'0 + Constant input on bit 1039 of port A: 1'0 + Constant input on bit 1040 of port A: 1'0 + Constant input on bit 1041 of port A: 1'0 + Constant input on bit 1042 of port A: 1'0 + Constant input on bit 1043 of port A: 1'0 + Constant input on bit 1044 of port A: 1'0 + Constant input on bit 1045 of port A: 1'0 + Constant input on bit 1046 of port A: 1'0 + Constant input on bit 1047 of port A: 1'0 + Constant input on bit 1048 of port A: 1'0 + Constant input on bit 1049 of port A: 1'0 + Constant input on bit 1050 of port A: 1'0 + Constant input on bit 1051 of port A: 1'0 + Constant input on bit 1052 of port A: 1'0 + Constant input on bit 1053 of port A: 1'0 + Constant input on bit 1054 of port A: 1'0 + Constant input on bit 1055 of port A: 1'0 + Constant input on bit 1056 of port A: 1'0 + Constant input on bit 1057 of port A: 1'0 + Constant input on bit 1058 of port A: 1'0 + Constant input on bit 1059 of port A: 1'0 + Constant input on bit 1060 of port A: 1'0 + Constant input on bit 1061 of port A: 1'0 + Constant input on bit 1062 of port A: 1'0 + Constant input on bit 1063 of port A: 1'0 + Constant input on bit 1064 of port A: 1'0 + Constant input on bit 1065 of port A: 1'0 + Constant input on bit 1066 of port A: 1'0 + Constant input on bit 1067 of port A: 1'0 + Constant input on bit 1068 of port A: 1'0 + Constant input on bit 1069 of port A: 1'0 + Constant input on bit 1070 of port A: 1'0 + Constant input on bit 1071 of port A: 1'0 + Constant input on bit 1072 of port A: 1'0 + Constant input on bit 1073 of port A: 1'0 + Constant input on bit 1074 of port A: 1'0 + Constant input on bit 1075 of port A: 1'0 + Constant input on bit 1076 of port A: 1'0 + Constant input on bit 1077 of port A: 1'0 + Constant input on bit 1078 of port A: 1'0 + Constant input on bit 1079 of port A: 1'0 + Constant input on bit 1080 of port A: 1'0 + Constant input on bit 1081 of port A: 1'0 + Constant input on bit 1082 of port A: 1'0 + Constant input on bit 1083 of port A: 1'0 + Constant input on bit 1084 of port A: 1'0 + Constant input on bit 1085 of port A: 1'0 + Constant input on bit 1086 of port A: 1'0 + Constant input on bit 1087 of port A: 1'0 + Constant input on bit 1088 of port A: 1'0 + Constant input on bit 1089 of port A: 1'0 + Constant input on bit 1090 of port A: 1'0 + Constant input on bit 1091 of port A: 1'0 + Constant input on bit 1092 of port A: 1'0 + Constant input on bit 1093 of port A: 1'0 + Constant input on bit 1094 of port A: 1'0 + Constant input on bit 1095 of port A: 1'0 + Constant input on bit 1096 of port A: 1'0 + Constant input on bit 1097 of port A: 1'0 + Constant input on bit 1098 of port A: 1'0 + Constant input on bit 1099 of port A: 1'0 + Constant input on bit 1100 of port A: 1'0 + Constant input on bit 1101 of port A: 1'0 + Constant input on bit 1102 of port A: 1'0 + Constant input on bit 1103 of port A: 1'0 + Constant input on bit 1104 of port A: 1'0 + Constant input on bit 1105 of port A: 1'0 + Constant input on bit 1106 of port A: 1'0 + Constant input on bit 1107 of port A: 1'0 + Constant input on bit 1108 of port A: 1'0 + Constant input on bit 1109 of port A: 1'0 + Constant input on bit 1110 of port A: 1'0 + Constant input on bit 1111 of port A: 1'0 + Constant input on bit 1112 of port A: 1'0 + Constant input on bit 1113 of port A: 1'0 + Constant input on bit 1114 of port A: 1'0 + Constant input on bit 1115 of port A: 1'0 + Constant input on bit 1116 of port A: 1'0 + Constant input on bit 1117 of port A: 1'0 + Constant input on bit 1118 of port A: 1'0 + Constant input on bit 1119 of port A: 1'0 + Constant input on bit 1120 of port A: 1'0 + Constant input on bit 1121 of port A: 1'0 + Constant input on bit 1122 of port A: 1'0 + Constant input on bit 1123 of port A: 1'0 + Constant input on bit 1124 of port A: 1'0 + Constant input on bit 1125 of port A: 1'0 + Constant input on bit 1126 of port A: 1'0 + Constant input on bit 1127 of port A: 1'0 + Constant input on bit 1128 of port A: 1'0 + Constant input on bit 1129 of port A: 1'0 + Constant input on bit 1130 of port A: 1'0 + Constant input on bit 1131 of port A: 1'0 + Constant input on bit 1132 of port A: 1'0 + Constant input on bit 1133 of port A: 1'0 + Constant input on bit 1134 of port A: 1'0 + Constant input on bit 1135 of port A: 1'0 + Constant input on bit 1136 of port A: 1'0 + Constant input on bit 1137 of port A: 1'0 + Constant input on bit 1138 of port A: 1'0 + Constant input on bit 1139 of port A: 1'0 + Constant input on bit 1140 of port A: 1'0 + Constant input on bit 1141 of port A: 1'0 + Constant input on bit 1142 of port A: 1'0 + Constant input on bit 1143 of port A: 1'0 + Constant input on bit 1144 of port A: 1'0 + Constant input on bit 1145 of port A: 1'0 + Constant input on bit 1146 of port A: 1'0 + Constant input on bit 1147 of port A: 1'0 + Constant input on bit 1148 of port A: 1'0 + Constant input on bit 1149 of port A: 1'0 + Constant input on bit 1150 of port A: 1'0 + Constant input on bit 1151 of port A: 1'0 + Constant input on bit 1152 of port A: 1'0 + Constant input on bit 1153 of port A: 1'0 + Constant input on bit 1154 of port A: 1'0 + Constant input on bit 1155 of port A: 1'0 + Constant input on bit 1156 of port A: 1'0 + Constant input on bit 1157 of port A: 1'0 + Constant input on bit 1158 of port A: 1'0 + Constant input on bit 1159 of port A: 1'0 + Constant input on bit 1160 of port A: 1'0 + Constant input on bit 1161 of port A: 1'0 + Constant input on bit 1162 of port A: 1'0 + Constant input on bit 1163 of port A: 1'0 + Constant input on bit 1164 of port A: 1'0 + Constant input on bit 1165 of port A: 1'0 + Constant input on bit 1166 of port A: 1'0 + Constant input on bit 1167 of port A: 1'0 + Constant input on bit 1168 of port A: 1'0 + Constant input on bit 1169 of port A: 1'0 + Constant input on bit 1170 of port A: 1'0 + Constant input on bit 1171 of port A: 1'0 + Constant input on bit 1172 of port A: 1'0 + Constant input on bit 1173 of port A: 1'0 + Constant input on bit 1174 of port A: 1'0 + Constant input on bit 1175 of port A: 1'0 + Constant input on bit 1176 of port A: 1'0 + Constant input on bit 1177 of port A: 1'0 + Constant input on bit 1178 of port A: 1'0 + Constant input on bit 1179 of port A: 1'0 + Constant input on bit 1180 of port A: 1'0 + Constant input on bit 1181 of port A: 1'0 + Constant input on bit 1182 of port A: 1'0 + Constant input on bit 1183 of port A: 1'0 + Constant input on bit 1184 of port A: 1'0 + Constant input on bit 1185 of port A: 1'0 + Constant input on bit 1186 of port A: 1'0 + Constant input on bit 1187 of port A: 1'0 + Constant input on bit 1188 of port A: 1'0 + Constant input on bit 1189 of port A: 1'0 + Constant input on bit 1190 of port A: 1'0 + Constant input on bit 1191 of port A: 1'0 + Constant input on bit 1192 of port A: 1'0 + Constant input on bit 1193 of port A: 1'0 + Constant input on bit 1194 of port A: 1'0 + Constant input on bit 1195 of port A: 1'0 + Constant input on bit 1196 of port A: 1'0 + Constant input on bit 1197 of port A: 1'0 + Constant input on bit 1198 of port A: 1'0 + Constant input on bit 1199 of port A: 1'0 + Constant input on bit 1200 of port A: 1'0 + Constant input on bit 1201 of port A: 1'0 + Constant input on bit 1202 of port A: 1'0 + Constant input on bit 1203 of port A: 1'0 + Constant input on bit 1204 of port A: 1'0 + Constant input on bit 1205 of port A: 1'0 + Constant input on bit 1206 of port A: 1'0 + Constant input on bit 1207 of port A: 1'0 + Constant input on bit 1208 of port A: 1'0 + Constant input on bit 1209 of port A: 1'0 + Constant input on bit 1210 of port A: 1'0 + Constant input on bit 1211 of port A: 1'0 + Constant input on bit 1212 of port A: 1'0 + Constant input on bit 1213 of port A: 1'0 + Constant input on bit 1214 of port A: 1'0 + Constant input on bit 1215 of port A: 1'0 + Constant input on bit 1216 of port A: 1'0 + Constant input on bit 1217 of port A: 1'0 + Constant input on bit 1218 of port A: 1'0 + Constant input on bit 1219 of port A: 1'0 + Constant input on bit 1220 of port A: 1'0 + Constant input on bit 1221 of port A: 1'0 + Constant input on bit 1222 of port A: 1'0 + Constant input on bit 1223 of port A: 1'0 + Constant input on bit 1224 of port A: 1'0 + Constant input on bit 1225 of port A: 1'0 + Constant input on bit 1226 of port A: 1'0 + Constant input on bit 1227 of port A: 1'0 + Constant input on bit 1228 of port A: 1'0 + Constant input on bit 1229 of port A: 1'0 + Constant input on bit 1230 of port A: 1'0 + Constant input on bit 1231 of port A: 1'0 + Constant input on bit 1232 of port A: 1'0 + Constant input on bit 1233 of port A: 1'0 + Constant input on bit 1234 of port A: 1'0 + Constant input on bit 1235 of port A: 1'0 + Constant input on bit 1236 of port A: 1'0 + Constant input on bit 1237 of port A: 1'0 + Constant input on bit 1238 of port A: 1'0 + Constant input on bit 1239 of port A: 1'0 + Constant input on bit 1240 of port A: 1'0 + Constant input on bit 1241 of port A: 1'0 + Constant input on bit 1242 of port A: 1'0 + Constant input on bit 1243 of port A: 1'0 + Constant input on bit 1244 of port A: 1'0 + Constant input on bit 1245 of port A: 1'0 + Constant input on bit 1246 of port A: 1'0 + Constant input on bit 1247 of port A: 1'0 + Constant input on bit 1248 of port A: 1'0 + Constant input on bit 1249 of port A: 1'0 + Constant input on bit 1250 of port A: 1'0 + Constant input on bit 1251 of port A: 1'0 + Constant input on bit 1252 of port A: 1'0 + Constant input on bit 1253 of port A: 1'0 + Constant input on bit 1254 of port A: 1'0 + Constant input on bit 1255 of port A: 1'0 + Constant input on bit 1256 of port A: 1'0 + Constant input on bit 1257 of port A: 1'0 + Constant input on bit 1258 of port A: 1'0 + Constant input on bit 1259 of port A: 1'0 + Constant input on bit 1260 of port A: 1'0 + Constant input on bit 1261 of port A: 1'0 + Constant input on bit 1262 of port A: 1'0 + Constant input on bit 1263 of port A: 1'0 + Constant input on bit 1264 of port A: 1'0 + Constant input on bit 1265 of port A: 1'0 + Constant input on bit 1266 of port A: 1'0 + Constant input on bit 1267 of port A: 1'0 + Constant input on bit 1268 of port A: 1'0 + Constant input on bit 1269 of port A: 1'0 + Constant input on bit 1270 of port A: 1'0 + Constant input on bit 1271 of port A: 1'0 + Constant input on bit 1272 of port A: 1'0 + Constant input on bit 1273 of port A: 1'0 + Constant input on bit 1274 of port A: 1'0 + Constant input on bit 1275 of port A: 1'0 + Constant input on bit 1276 of port A: 1'0 + Constant input on bit 1277 of port A: 1'0 + Constant input on bit 1278 of port A: 1'0 + Constant input on bit 1279 of port A: 1'0 + Constant input on bit 1280 of port A: 1'0 + Constant input on bit 1281 of port A: 1'0 + Constant input on bit 1282 of port A: 1'0 + Constant input on bit 1283 of port A: 1'0 + Constant input on bit 1284 of port A: 1'0 + Constant input on bit 1285 of port A: 1'0 + Constant input on bit 1286 of port A: 1'0 + Constant input on bit 1287 of port A: 1'0 + Constant input on bit 1288 of port A: 1'0 + Constant input on bit 1289 of port A: 1'0 + Constant input on bit 1290 of port A: 1'0 + Constant input on bit 1291 of port A: 1'0 + Constant input on bit 1292 of port A: 1'0 + Constant input on bit 1293 of port A: 1'0 + Constant input on bit 1294 of port A: 1'0 + Constant input on bit 1295 of port A: 1'0 + Constant input on bit 1296 of port A: 1'0 + Constant input on bit 1297 of port A: 1'0 + Constant input on bit 1298 of port A: 1'0 + Constant input on bit 1299 of port A: 1'0 + Constant input on bit 1300 of port A: 1'0 + Constant input on bit 1301 of port A: 1'0 + Constant input on bit 1302 of port A: 1'0 + Constant input on bit 1303 of port A: 1'0 + Constant input on bit 1304 of port A: 1'0 + Constant input on bit 1305 of port A: 1'0 + Constant input on bit 1306 of port A: 1'0 + Constant input on bit 1307 of port A: 1'0 + Constant input on bit 1308 of port A: 1'0 + Constant input on bit 1309 of port A: 1'0 + Constant input on bit 1310 of port A: 1'0 + Constant input on bit 1311 of port A: 1'0 + Constant input on bit 1312 of port A: 1'0 + Constant input on bit 1313 of port A: 1'0 + Constant input on bit 1314 of port A: 1'0 + Constant input on bit 1315 of port A: 1'0 + Constant input on bit 1316 of port A: 1'0 + Constant input on bit 1317 of port A: 1'0 + Constant input on bit 1318 of port A: 1'0 + Constant input on bit 1319 of port A: 1'0 + Constant input on bit 1320 of port A: 1'0 + Constant input on bit 1321 of port A: 1'0 + Constant input on bit 1322 of port A: 1'0 + Constant input on bit 1323 of port A: 1'0 + Constant input on bit 1324 of port A: 1'0 + Constant input on bit 1325 of port A: 1'0 + Constant input on bit 1326 of port A: 1'0 + Constant input on bit 1327 of port A: 1'0 + Constant input on bit 1328 of port A: 1'0 + Constant input on bit 1329 of port A: 1'0 + Constant input on bit 1330 of port A: 1'0 + Constant input on bit 1331 of port A: 1'0 + Constant input on bit 1332 of port A: 1'0 + Constant input on bit 1333 of port A: 1'0 + Constant input on bit 1334 of port A: 1'0 + Constant input on bit 1335 of port A: 1'0 + Constant input on bit 1336 of port A: 1'0 + Constant input on bit 1337 of port A: 1'0 + Constant input on bit 1338 of port A: 1'0 + Constant input on bit 1339 of port A: 1'0 + Constant input on bit 1340 of port A: 1'0 + Constant input on bit 1341 of port A: 1'0 + Constant input on bit 1342 of port A: 1'0 + Constant input on bit 1343 of port A: 1'0 + Constant input on bit 1344 of port A: 1'0 + Constant input on bit 1345 of port A: 1'0 + Constant input on bit 1346 of port A: 1'0 + Constant input on bit 1347 of port A: 1'0 + Constant input on bit 1348 of port A: 1'0 + Constant input on bit 1349 of port A: 1'0 + Constant input on bit 1350 of port A: 1'0 + Constant input on bit 1351 of port A: 1'0 + Constant input on bit 1352 of port A: 1'0 + Constant input on bit 1353 of port A: 1'0 + Constant input on bit 1354 of port A: 1'0 + Constant input on bit 1355 of port A: 1'0 + Constant input on bit 1356 of port A: 1'0 + Constant input on bit 1357 of port A: 1'0 + Constant input on bit 1358 of port A: 1'0 + Constant input on bit 1359 of port A: 1'0 + Constant input on bit 1360 of port A: 1'0 + Constant input on bit 1361 of port A: 1'0 + Constant input on bit 1362 of port A: 1'0 + Constant input on bit 1363 of port A: 1'0 + Constant input on bit 1364 of port A: 1'0 + Constant input on bit 1365 of port A: 1'0 + Constant input on bit 1366 of port A: 1'0 + Constant input on bit 1367 of port A: 1'0 + Constant input on bit 1368 of port A: 1'0 + Constant input on bit 1369 of port A: 1'0 + Constant input on bit 1370 of port A: 1'0 + Constant input on bit 1371 of port A: 1'0 + Constant input on bit 1372 of port A: 1'0 + Constant input on bit 1373 of port A: 1'0 + Constant input on bit 1374 of port A: 1'0 + Constant input on bit 1375 of port A: 1'0 + Constant input on bit 1376 of port A: 1'0 + Constant input on bit 1377 of port A: 1'0 + Constant input on bit 1378 of port A: 1'0 + Constant input on bit 1379 of port A: 1'0 + Constant input on bit 1380 of port A: 1'0 + Constant input on bit 1381 of port A: 1'0 + Constant input on bit 1382 of port A: 1'0 + Constant input on bit 1383 of port A: 1'0 + Constant input on bit 1384 of port A: 1'0 + Constant input on bit 1385 of port A: 1'0 + Constant input on bit 1386 of port A: 1'0 + Constant input on bit 1387 of port A: 1'0 + Constant input on bit 1388 of port A: 1'0 + Constant input on bit 1389 of port A: 1'0 + Constant input on bit 1390 of port A: 1'0 + Constant input on bit 1391 of port A: 1'0 + Constant input on bit 1392 of port A: 1'0 + Constant input on bit 1393 of port A: 1'0 + Constant input on bit 1394 of port A: 1'0 + Constant input on bit 1395 of port A: 1'0 + Constant input on bit 1396 of port A: 1'0 + Constant input on bit 1397 of port A: 1'0 + Constant input on bit 1398 of port A: 1'0 + Constant input on bit 1399 of port A: 1'0 + Constant input on bit 1400 of port A: 1'0 + Constant input on bit 1401 of port A: 1'0 + Constant input on bit 1402 of port A: 1'0 + Constant input on bit 1403 of port A: 1'0 + Constant input on bit 1404 of port A: 1'0 + Constant input on bit 1405 of port A: 1'0 + Constant input on bit 1406 of port A: 1'0 + Constant input on bit 1407 of port A: 1'0 + Constant input on bit 1408 of port A: 1'0 + Constant input on bit 1409 of port A: 1'0 + Constant input on bit 1410 of port A: 1'0 + Constant input on bit 1411 of port A: 1'0 + Constant input on bit 1412 of port A: 1'0 + Constant input on bit 1413 of port A: 1'0 + Constant input on bit 1414 of port A: 1'0 + Constant input on bit 1415 of port A: 1'0 + Constant input on bit 1416 of port A: 1'0 + Constant input on bit 1417 of port A: 1'0 + Constant input on bit 1418 of port A: 1'0 + Constant input on bit 1419 of port A: 1'0 + Constant input on bit 1420 of port A: 1'0 + Constant input on bit 1421 of port A: 1'0 + Constant input on bit 1422 of port A: 1'0 + Constant input on bit 1423 of port A: 1'0 + Constant input on bit 1424 of port A: 1'0 + Constant input on bit 1425 of port A: 1'0 + Constant input on bit 1426 of port A: 1'0 + Constant input on bit 1427 of port A: 1'0 + Constant input on bit 1428 of port A: 1'0 + Constant input on bit 1429 of port A: 1'0 + Constant input on bit 1430 of port A: 1'0 + Constant input on bit 1431 of port A: 1'0 + Constant input on bit 1432 of port A: 1'0 + Constant input on bit 1433 of port A: 1'0 + Constant input on bit 1434 of port A: 1'0 + Constant input on bit 1435 of port A: 1'0 + Constant input on bit 1436 of port A: 1'0 + Constant input on bit 1437 of port A: 1'0 + Constant input on bit 1438 of port A: 1'0 + Constant input on bit 1439 of port A: 1'0 + Constant input on bit 1440 of port A: 1'0 + Constant input on bit 1441 of port A: 1'0 + Constant input on bit 1442 of port A: 1'0 + Constant input on bit 1443 of port A: 1'0 + Constant input on bit 1444 of port A: 1'0 + Constant input on bit 1445 of port A: 1'0 + Constant input on bit 1446 of port A: 1'0 + Constant input on bit 1447 of port A: 1'0 + Constant input on bit 1448 of port A: 1'0 + Constant input on bit 1449 of port A: 1'0 + Constant input on bit 1450 of port A: 1'0 + Constant input on bit 1451 of port A: 1'0 + Constant input on bit 1452 of port A: 1'0 + Constant input on bit 1453 of port A: 1'0 + Constant input on bit 1454 of port A: 1'0 + Constant input on bit 1455 of port A: 1'0 + Constant input on bit 1456 of port A: 1'0 + Constant input on bit 1457 of port A: 1'0 + Constant input on bit 1458 of port A: 1'0 + Constant input on bit 1459 of port A: 1'0 + Constant input on bit 1460 of port A: 1'0 + Constant input on bit 1461 of port A: 1'0 + Constant input on bit 1462 of port A: 1'0 + Constant input on bit 1463 of port A: 1'0 + Constant input on bit 1464 of port A: 1'0 + Constant input on bit 1465 of port A: 1'0 + Constant input on bit 1466 of port A: 1'0 + Constant input on bit 1467 of port A: 1'0 + Constant input on bit 1468 of port A: 1'0 + Constant input on bit 1469 of port A: 1'0 + Constant input on bit 1470 of port A: 1'0 + Constant input on bit 1471 of port A: 1'0 + Constant input on bit 1472 of port A: 1'0 + Constant input on bit 1473 of port A: 1'0 + Constant input on bit 1474 of port A: 1'0 + Constant input on bit 1475 of port A: 1'0 + Constant input on bit 1476 of port A: 1'0 + Constant input on bit 1477 of port A: 1'0 + Constant input on bit 1478 of port A: 1'0 + Constant input on bit 1479 of port A: 1'0 + Constant input on bit 1480 of port A: 1'0 + Constant input on bit 1481 of port A: 1'0 + Constant input on bit 1482 of port A: 1'0 + Constant input on bit 1483 of port A: 1'0 + Constant input on bit 1484 of port A: 1'0 + Constant input on bit 1485 of port A: 1'0 + Constant input on bit 1486 of port A: 1'0 + Constant input on bit 1487 of port A: 1'0 + Constant input on bit 1488 of port A: 1'0 + Constant input on bit 1489 of port A: 1'0 + Constant input on bit 1490 of port A: 1'0 + Constant input on bit 1491 of port A: 1'0 + Constant input on bit 1492 of port A: 1'0 + Constant input on bit 1493 of port A: 1'0 + Constant input on bit 1494 of port A: 1'0 + Constant input on bit 1495 of port A: 1'0 + Constant input on bit 1496 of port A: 1'0 + Constant input on bit 1497 of port A: 1'0 + Constant input on bit 1498 of port A: 1'0 + Constant input on bit 1499 of port A: 1'0 + Constant input on bit 1500 of port A: 1'0 + Constant input on bit 1501 of port A: 1'0 + Constant input on bit 1502 of port A: 1'0 + Constant input on bit 1503 of port A: 1'0 + Constant input on bit 1504 of port A: 1'0 + Constant input on bit 1505 of port A: 1'0 + Constant input on bit 1506 of port A: 1'0 + Constant input on bit 1507 of port A: 1'0 + Constant input on bit 1508 of port A: 1'0 + Constant input on bit 1509 of port A: 1'0 + Constant input on bit 1510 of port A: 1'0 + Constant input on bit 1511 of port A: 1'0 + Constant input on bit 1512 of port A: 1'0 + Constant input on bit 1513 of port A: 1'0 + Constant input on bit 1514 of port A: 1'0 + Constant input on bit 1515 of port A: 1'0 + Constant input on bit 1516 of port A: 1'0 + Constant input on bit 1517 of port A: 1'0 + Constant input on bit 1518 of port A: 1'0 + Constant input on bit 1519 of port A: 1'0 + Constant input on bit 1520 of port A: 1'0 + Constant input on bit 1521 of port A: 1'0 + Constant input on bit 1522 of port A: 1'0 + Constant input on bit 1523 of port A: 1'0 + Constant input on bit 1524 of port A: 1'0 + Constant input on bit 1525 of port A: 1'0 + Constant input on bit 1526 of port A: 1'0 + Constant input on bit 1527 of port A: 1'0 + Constant input on bit 1528 of port A: 1'0 + Constant input on bit 1529 of port A: 1'0 + Constant input on bit 1530 of port A: 1'0 + Constant input on bit 1531 of port A: 1'0 + Constant input on bit 1532 of port A: 1'0 + Constant input on bit 1533 of port A: 1'0 + Constant input on bit 1534 of port A: 1'0 + Constant input on bit 1535 of port A: 1'0 + Constant input on bit 1536 of port A: 1'0 + Constant input on bit 1537 of port A: 1'0 + Constant input on bit 1538 of port A: 1'0 + Constant input on bit 1539 of port A: 1'0 + Constant input on bit 1540 of port A: 1'0 + Constant input on bit 1541 of port A: 1'0 + Constant input on bit 1542 of port A: 1'0 + Constant input on bit 1543 of port A: 1'0 + Constant input on bit 1544 of port A: 1'0 + Constant input on bit 1545 of port A: 1'0 + Constant input on bit 1546 of port A: 1'0 + Constant input on bit 1547 of port A: 1'0 + Constant input on bit 1548 of port A: 1'0 + Constant input on bit 1549 of port A: 1'0 + Constant input on bit 1550 of port A: 1'0 + Constant input on bit 1551 of port A: 1'0 + Constant input on bit 1552 of port A: 1'0 + Constant input on bit 1553 of port A: 1'0 + Constant input on bit 1554 of port A: 1'0 + Constant input on bit 1555 of port A: 1'0 + Constant input on bit 1556 of port A: 1'0 + Constant input on bit 1557 of port A: 1'0 + Constant input on bit 1558 of port A: 1'0 + Constant input on bit 1559 of port A: 1'0 + Constant input on bit 1560 of port A: 1'0 + Constant input on bit 1561 of port A: 1'0 + Constant input on bit 1562 of port A: 1'0 + Constant input on bit 1563 of port A: 1'0 + Constant input on bit 1564 of port A: 1'0 + Constant input on bit 1565 of port A: 1'0 + Constant input on bit 1566 of port A: 1'0 + Constant input on bit 1567 of port A: 1'0 + Constant input on bit 1568 of port A: 1'0 + Constant input on bit 1569 of port A: 1'0 + Constant input on bit 1570 of port A: 1'0 + Constant input on bit 1571 of port A: 1'0 + Constant input on bit 1572 of port A: 1'0 + Constant input on bit 1573 of port A: 1'0 + Constant input on bit 1574 of port A: 1'0 + Constant input on bit 1575 of port A: 1'0 + Constant input on bit 1576 of port A: 1'0 + Constant input on bit 1577 of port A: 1'0 + Constant input on bit 1578 of port A: 1'0 + Constant input on bit 1579 of port A: 1'0 + Constant input on bit 1580 of port A: 1'0 + Constant input on bit 1581 of port A: 1'0 + Constant input on bit 1582 of port A: 1'0 + Constant input on bit 1583 of port A: 1'0 + Constant input on bit 1584 of port A: 1'0 + Constant input on bit 1585 of port A: 1'0 + Constant input on bit 1586 of port A: 1'0 + Constant input on bit 1587 of port A: 1'0 + Constant input on bit 1588 of port A: 1'0 + Constant input on bit 1589 of port A: 1'0 + Constant input on bit 1590 of port A: 1'0 + Constant input on bit 1591 of port A: 1'0 + Constant input on bit 1592 of port A: 1'0 + Constant input on bit 1593 of port A: 1'0 + Constant input on bit 1594 of port A: 1'0 + Constant input on bit 1595 of port A: 1'0 + Constant input on bit 1596 of port A: 1'0 + Constant input on bit 1597 of port A: 1'0 + Constant input on bit 1598 of port A: 1'0 + Constant input on bit 1599 of port A: 1'0 + Constant input on bit 1600 of port A: 1'0 + Constant input on bit 1601 of port A: 1'0 + Constant input on bit 1602 of port A: 1'0 + Constant input on bit 1603 of port A: 1'0 + Constant input on bit 1604 of port A: 1'0 + Constant input on bit 1605 of port A: 1'0 + Constant input on bit 1606 of port A: 1'0 + Constant input on bit 1607 of port A: 1'0 + Constant input on bit 1608 of port A: 1'0 + Constant input on bit 1609 of port A: 1'0 + Constant input on bit 1610 of port A: 1'0 + Constant input on bit 1611 of port A: 1'0 + Constant input on bit 1612 of port A: 1'0 + Constant input on bit 1613 of port A: 1'0 + Constant input on bit 1614 of port A: 1'0 + Constant input on bit 1615 of port A: 1'0 + Constant input on bit 1616 of port A: 1'0 + Constant input on bit 1617 of port A: 1'0 + Constant input on bit 1618 of port A: 1'0 + Constant input on bit 1619 of port A: 1'0 + Constant input on bit 1620 of port A: 1'0 + Constant input on bit 1621 of port A: 1'0 + Constant input on bit 1622 of port A: 1'0 + Constant input on bit 1623 of port A: 1'0 + Constant input on bit 1624 of port A: 1'0 + Constant input on bit 1625 of port A: 1'0 + Constant input on bit 1626 of port A: 1'0 + Constant input on bit 1627 of port A: 1'0 + Constant input on bit 1628 of port A: 1'0 + Constant input on bit 1629 of port A: 1'0 + Constant input on bit 1630 of port A: 1'0 + Constant input on bit 1631 of port A: 1'0 + Constant input on bit 1632 of port A: 1'0 + Constant input on bit 1633 of port A: 1'0 + Constant input on bit 1634 of port A: 1'0 + Constant input on bit 1635 of port A: 1'0 + Constant input on bit 1636 of port A: 1'0 + Constant input on bit 1637 of port A: 1'0 + Constant input on bit 1638 of port A: 1'0 + Constant input on bit 1639 of port A: 1'0 + Constant input on bit 1640 of port A: 1'0 + Constant input on bit 1641 of port A: 1'0 + Constant input on bit 1642 of port A: 1'0 + Constant input on bit 1643 of port A: 1'0 + Constant input on bit 1644 of port A: 1'0 + Constant input on bit 1645 of port A: 1'0 + Constant input on bit 1646 of port A: 1'0 + Constant input on bit 1647 of port A: 1'0 + Constant input on bit 1648 of port A: 1'0 + Constant input on bit 1649 of port A: 1'0 + Constant input on bit 1650 of port A: 1'0 + Constant input on bit 1651 of port A: 1'0 + Constant input on bit 1652 of port A: 1'0 + Constant input on bit 1653 of port A: 1'0 + Constant input on bit 1654 of port A: 1'0 + Constant input on bit 1655 of port A: 1'0 + Constant input on bit 1656 of port A: 1'0 + Constant input on bit 1657 of port A: 1'0 + Constant input on bit 1658 of port A: 1'0 + Constant input on bit 1659 of port A: 1'0 + Constant input on bit 1660 of port A: 1'0 + Constant input on bit 1661 of port A: 1'0 + Constant input on bit 1662 of port A: 1'0 + Constant input on bit 1663 of port A: 1'0 + Constant input on bit 1664 of port A: 1'0 + Constant input on bit 1665 of port A: 1'0 + Constant input on bit 1666 of port A: 1'0 + Constant input on bit 1667 of port A: 1'0 + Constant input on bit 1668 of port A: 1'0 + Constant input on bit 1669 of port A: 1'0 + Constant input on bit 1670 of port A: 1'0 + Constant input on bit 1671 of port A: 1'0 + Constant input on bit 1672 of port A: 1'0 + Constant input on bit 1673 of port A: 1'0 + Constant input on bit 1674 of port A: 1'0 + Constant input on bit 1675 of port A: 1'0 + Constant input on bit 1676 of port A: 1'0 + Constant input on bit 1677 of port A: 1'0 + Constant input on bit 1678 of port A: 1'0 + Constant input on bit 1679 of port A: 1'0 + Constant input on bit 1680 of port A: 1'0 + Constant input on bit 1681 of port A: 1'0 + Constant input on bit 1682 of port A: 1'0 + Constant input on bit 1683 of port A: 1'0 + Constant input on bit 1684 of port A: 1'0 + Constant input on bit 1685 of port A: 1'0 + Constant input on bit 1686 of port A: 1'0 + Constant input on bit 1687 of port A: 1'0 + Constant input on bit 1688 of port A: 1'0 + Constant input on bit 1689 of port A: 1'0 + Constant input on bit 1690 of port A: 1'0 + Constant input on bit 1691 of port A: 1'0 + Constant input on bit 1692 of port A: 1'0 + Constant input on bit 1693 of port A: 1'0 + Constant input on bit 1694 of port A: 1'0 + Constant input on bit 1695 of port A: 1'0 + Constant input on bit 1696 of port A: 1'0 + Constant input on bit 1697 of port A: 1'0 + Constant input on bit 1698 of port A: 1'0 + Constant input on bit 1699 of port A: 1'0 + Constant input on bit 1700 of port A: 1'0 + Constant input on bit 1701 of port A: 1'0 + Constant input on bit 1702 of port A: 1'0 + Constant input on bit 1703 of port A: 1'0 + Constant input on bit 1704 of port A: 1'0 + Constant input on bit 1705 of port A: 1'0 + Constant input on bit 1706 of port A: 1'0 + Constant input on bit 1707 of port A: 1'0 + Constant input on bit 1708 of port A: 1'0 + Constant input on bit 1709 of port A: 1'0 + Constant input on bit 1710 of port A: 1'0 + Constant input on bit 1711 of port A: 1'0 + Constant input on bit 1712 of port A: 1'0 + Constant input on bit 1713 of port A: 1'0 + Constant input on bit 1714 of port A: 1'0 + Constant input on bit 1715 of port A: 1'0 + Constant input on bit 1716 of port A: 1'0 + Constant input on bit 1717 of port A: 1'0 + Constant input on bit 1718 of port A: 1'0 + Constant input on bit 1719 of port A: 1'0 + Constant input on bit 1720 of port A: 1'0 + Constant input on bit 1721 of port A: 1'0 + Constant input on bit 1722 of port A: 1'0 + Constant input on bit 1723 of port A: 1'0 + Constant input on bit 1724 of port A: 1'0 + Constant input on bit 1725 of port A: 1'0 + Constant input on bit 1726 of port A: 1'0 + Constant input on bit 1727 of port A: 1'0 + Constant input on bit 1728 of port A: 1'0 + Constant input on bit 1729 of port A: 1'0 + Constant input on bit 1730 of port A: 1'0 + Constant input on bit 1731 of port A: 1'0 + Constant input on bit 1732 of port A: 1'0 + Constant input on bit 1733 of port A: 1'0 + Constant input on bit 1734 of port A: 1'0 + Constant input on bit 1735 of port A: 1'0 + Constant input on bit 1736 of port A: 1'0 + Constant input on bit 1737 of port A: 1'0 + Constant input on bit 1738 of port A: 1'0 + Constant input on bit 1739 of port A: 1'0 + Constant input on bit 1740 of port A: 1'0 + Constant input on bit 1741 of port A: 1'0 + Constant input on bit 1742 of port A: 1'0 + Constant input on bit 1743 of port A: 1'0 + Constant input on bit 1744 of port A: 1'0 + Constant input on bit 1745 of port A: 1'0 + Constant input on bit 1746 of port A: 1'0 + Constant input on bit 1747 of port A: 1'0 + Constant input on bit 1748 of port A: 1'0 + Constant input on bit 1749 of port A: 1'0 + Constant input on bit 1750 of port A: 1'0 + Constant input on bit 1751 of port A: 1'0 + Constant input on bit 1752 of port A: 1'0 + Constant input on bit 1753 of port A: 1'0 + Constant input on bit 1754 of port A: 1'0 + Constant input on bit 1755 of port A: 1'0 + Constant input on bit 1756 of port A: 1'0 + Constant input on bit 1757 of port A: 1'0 + Constant input on bit 1758 of port A: 1'0 + Constant input on bit 1759 of port A: 1'0 + Constant input on bit 1760 of port A: 1'0 + Constant input on bit 1761 of port A: 1'0 + Constant input on bit 1762 of port A: 1'0 + Constant input on bit 1763 of port A: 1'0 + Constant input on bit 1764 of port A: 1'0 + Constant input on bit 1765 of port A: 1'0 + Constant input on bit 1766 of port A: 1'0 + Constant input on bit 1767 of port A: 1'0 + Constant input on bit 1768 of port A: 1'0 + Constant input on bit 1769 of port A: 1'0 + Constant input on bit 1770 of port A: 1'0 + Constant input on bit 1771 of port A: 1'0 + Constant input on bit 1772 of port A: 1'0 + Constant input on bit 1773 of port A: 1'0 + Constant input on bit 1774 of port A: 1'0 + Constant input on bit 1775 of port A: 1'0 + Constant input on bit 1776 of port A: 1'0 + Constant input on bit 1777 of port A: 1'0 + Constant input on bit 1778 of port A: 1'0 + Constant input on bit 1779 of port A: 1'0 + Constant input on bit 1780 of port A: 1'0 + Constant input on bit 1781 of port A: 1'0 + Constant input on bit 1782 of port A: 1'0 + Constant input on bit 1783 of port A: 1'0 + Constant input on bit 1784 of port A: 1'0 + Constant input on bit 1785 of port A: 1'0 + Constant input on bit 1786 of port A: 1'0 + Constant input on bit 1787 of port A: 1'0 + Constant input on bit 1788 of port A: 1'0 + Constant input on bit 1789 of port A: 1'0 + Constant input on bit 1790 of port A: 1'0 + Constant input on bit 1791 of port A: 1'0 + Constant input on bit 1792 of port A: 1'0 + Constant input on bit 1793 of port A: 1'0 + Constant input on bit 1794 of port A: 1'0 + Constant input on bit 1795 of port A: 1'0 + Constant input on bit 1796 of port A: 1'0 + Constant input on bit 1797 of port A: 1'0 + Constant input on bit 1798 of port A: 1'0 + Constant input on bit 1799 of port A: 1'0 + Constant input on bit 1800 of port A: 1'0 + Constant input on bit 1801 of port A: 1'0 + Constant input on bit 1802 of port A: 1'0 + Constant input on bit 1803 of port A: 1'0 + Constant input on bit 1804 of port A: 1'0 + Constant input on bit 1805 of port A: 1'0 + Constant input on bit 1806 of port A: 1'0 + Constant input on bit 1807 of port A: 1'0 + Constant input on bit 1808 of port A: 1'0 + Constant input on bit 1809 of port A: 1'0 + Constant input on bit 1810 of port A: 1'0 + Constant input on bit 1811 of port A: 1'0 + Constant input on bit 1812 of port A: 1'0 + Constant input on bit 1813 of port A: 1'0 + Constant input on bit 1814 of port A: 1'0 + Constant input on bit 1815 of port A: 1'0 + Constant input on bit 1816 of port A: 1'0 + Constant input on bit 1817 of port A: 1'0 + Constant input on bit 1818 of port A: 1'0 + Constant input on bit 1819 of port A: 1'0 + Constant input on bit 1820 of port A: 1'0 + Constant input on bit 1821 of port A: 1'0 + Constant input on bit 1822 of port A: 1'0 + Constant input on bit 1823 of port A: 1'0 + Constant input on bit 1824 of port A: 1'0 + Constant input on bit 1825 of port A: 1'0 + Constant input on bit 1826 of port A: 1'0 + Constant input on bit 1827 of port A: 1'0 + Constant input on bit 1828 of port A: 1'0 + Constant input on bit 1829 of port A: 1'0 + Constant input on bit 1830 of port A: 1'0 + Constant input on bit 1831 of port A: 1'0 + Constant input on bit 1832 of port A: 1'0 + Constant input on bit 1833 of port A: 1'0 + Constant input on bit 1834 of port A: 1'0 + Constant input on bit 1835 of port A: 1'0 + Constant input on bit 1836 of port A: 1'0 + Constant input on bit 1837 of port A: 1'0 + Constant input on bit 1838 of port A: 1'0 + Constant input on bit 1839 of port A: 1'0 + Constant input on bit 1840 of port A: 1'0 + Constant input on bit 1841 of port A: 1'0 + Constant input on bit 1842 of port A: 1'0 + Constant input on bit 1843 of port A: 1'0 + Constant input on bit 1844 of port A: 1'0 + Constant input on bit 1845 of port A: 1'0 + Constant input on bit 1846 of port A: 1'0 + Constant input on bit 1847 of port A: 1'0 + Constant input on bit 1848 of port A: 1'0 + Constant input on bit 1849 of port A: 1'0 + Constant input on bit 1850 of port A: 1'0 + Constant input on bit 1851 of port A: 1'0 + Constant input on bit 1852 of port A: 1'0 + Constant input on bit 1853 of port A: 1'0 + Constant input on bit 1854 of port A: 1'0 + Constant input on bit 1855 of port A: 1'0 + Constant input on bit 1856 of port A: 1'0 + Constant input on bit 1857 of port A: 1'0 + Constant input on bit 1858 of port A: 1'0 + Constant input on bit 1859 of port A: 1'0 + Constant input on bit 1860 of port A: 1'0 + Constant input on bit 1861 of port A: 1'0 + Constant input on bit 1862 of port A: 1'0 + Constant input on bit 1863 of port A: 1'0 + Constant input on bit 1864 of port A: 1'0 + Constant input on bit 1865 of port A: 1'0 + Constant input on bit 1866 of port A: 1'0 + Constant input on bit 1867 of port A: 1'0 + Constant input on bit 1868 of port A: 1'0 + Constant input on bit 1869 of port A: 1'0 + Constant input on bit 1870 of port A: 1'0 + Constant input on bit 1871 of port A: 1'0 + Constant input on bit 1872 of port A: 1'0 + Constant input on bit 1873 of port A: 1'0 + Constant input on bit 1874 of port A: 1'0 + Constant input on bit 1875 of port A: 1'0 + Constant input on bit 1876 of port A: 1'0 + Constant input on bit 1877 of port A: 1'0 + Constant input on bit 1878 of port A: 1'0 + Constant input on bit 1879 of port A: 1'0 + Constant input on bit 1880 of port A: 1'0 + Constant input on bit 1881 of port A: 1'0 + Constant input on bit 1882 of port A: 1'0 + Constant input on bit 1883 of port A: 1'0 + Constant input on bit 1884 of port A: 1'0 + Constant input on bit 1885 of port A: 1'0 + Constant input on bit 1886 of port A: 1'0 + Constant input on bit 1887 of port A: 1'0 + Constant input on bit 1888 of port A: 1'0 + Constant input on bit 1889 of port A: 1'0 + Constant input on bit 1890 of port A: 1'0 + Constant input on bit 1891 of port A: 1'0 + Constant input on bit 1892 of port A: 1'0 + Constant input on bit 1893 of port A: 1'0 + Constant input on bit 1894 of port A: 1'0 + Constant input on bit 1895 of port A: 1'0 + Constant input on bit 1896 of port A: 1'0 + Constant input on bit 1897 of port A: 1'0 + Constant input on bit 1898 of port A: 1'0 + Constant input on bit 1899 of port A: 1'0 + Constant input on bit 1900 of port A: 1'0 + Constant input on bit 1901 of port A: 1'0 + Constant input on bit 1902 of port A: 1'0 + Constant input on bit 1903 of port A: 1'0 + Constant input on bit 1904 of port A: 1'0 + Constant input on bit 1905 of port A: 1'0 + Constant input on bit 1906 of port A: 1'0 + Constant input on bit 1907 of port A: 1'0 + Constant input on bit 1908 of port A: 1'0 + Constant input on bit 1909 of port A: 1'0 + Constant input on bit 1910 of port A: 1'0 + Constant input on bit 1911 of port A: 1'0 + Constant input on bit 1912 of port A: 1'0 + Constant input on bit 1913 of port A: 1'0 + Constant input on bit 1914 of port A: 1'0 + Constant input on bit 1915 of port A: 1'0 + Constant input on bit 1916 of port A: 1'0 + Constant input on bit 1917 of port A: 1'0 + Constant input on bit 1918 of port A: 1'0 + Constant input on bit 1919 of port A: 1'0 + Constant input on bit 1920 of port A: 1'0 + Constant input on bit 1921 of port A: 1'0 + Constant input on bit 1922 of port A: 1'0 + Constant input on bit 1923 of port A: 1'0 + Constant input on bit 1924 of port A: 1'0 + Constant input on bit 1925 of port A: 1'0 + Constant input on bit 1926 of port A: 1'0 + Constant input on bit 1927 of port A: 1'0 + Constant input on bit 1928 of port A: 1'0 + Constant input on bit 1929 of port A: 1'0 + Constant input on bit 1930 of port A: 1'0 + Constant input on bit 1931 of port A: 1'0 + Constant input on bit 1932 of port A: 1'0 + Constant input on bit 1933 of port A: 1'0 + Constant input on bit 1934 of port A: 1'0 + Constant input on bit 1935 of port A: 1'0 + Constant input on bit 1936 of port A: 1'0 + Constant input on bit 1937 of port A: 1'0 + Constant input on bit 1938 of port A: 1'0 + Constant input on bit 1939 of port A: 1'0 + Constant input on bit 1940 of port A: 1'0 + Constant input on bit 1941 of port A: 1'0 + Constant input on bit 1942 of port A: 1'0 + Constant input on bit 1943 of port A: 1'0 + Constant input on bit 1944 of port A: 1'0 + Constant input on bit 1945 of port A: 1'0 + Constant input on bit 1946 of port A: 1'0 + Constant input on bit 1947 of port A: 1'0 + Constant input on bit 1948 of port A: 1'0 + Constant input on bit 1949 of port A: 1'0 + Constant input on bit 1950 of port A: 1'0 + Constant input on bit 1951 of port A: 1'0 + Constant input on bit 1952 of port A: 1'0 + Constant input on bit 1953 of port A: 1'0 + Constant input on bit 1954 of port A: 1'0 + Constant input on bit 1955 of port A: 1'0 + Constant input on bit 1956 of port A: 1'0 + Constant input on bit 1957 of port A: 1'0 + Constant input on bit 1958 of port A: 1'0 + Constant input on bit 1959 of port A: 1'0 + Constant input on bit 1960 of port A: 1'0 + Constant input on bit 1961 of port A: 1'0 + Constant input on bit 1962 of port A: 1'0 + Constant input on bit 1963 of port A: 1'0 + Constant input on bit 1964 of port A: 1'0 + Constant input on bit 1965 of port A: 1'0 + Constant input on bit 1966 of port A: 1'0 + Constant input on bit 1967 of port A: 1'0 + Constant input on bit 1968 of port A: 1'0 + Constant input on bit 1969 of port A: 1'0 + Constant input on bit 1970 of port A: 1'0 + Constant input on bit 1971 of port A: 1'0 + Constant input on bit 1972 of port A: 1'0 + Constant input on bit 1973 of port A: 1'0 + Constant input on bit 1974 of port A: 1'0 + Constant input on bit 1975 of port A: 1'0 + Constant input on bit 1976 of port A: 1'0 + Constant input on bit 1977 of port A: 1'0 + Constant input on bit 1978 of port A: 1'0 + Constant input on bit 1979 of port A: 1'0 + Constant input on bit 1980 of port A: 1'0 + Constant input on bit 1981 of port A: 1'0 + Constant input on bit 1982 of port A: 1'0 + Constant input on bit 1983 of port A: 1'0 + Constant input on bit 1984 of port A: 1'0 + Constant input on bit 1985 of port A: 1'0 + Constant input on bit 1986 of port A: 1'0 + Constant input on bit 1987 of port A: 1'0 + Constant input on bit 1988 of port A: 1'0 + Constant input on bit 1989 of port A: 1'0 + Constant input on bit 1990 of port A: 1'0 + Constant input on bit 1991 of port A: 1'0 + Constant input on bit 1992 of port A: 1'0 + Constant input on bit 1993 of port A: 1'0 + Constant input on bit 1994 of port A: 1'0 + Constant input on bit 1995 of port A: 1'0 + Constant input on bit 1996 of port A: 1'0 + Constant input on bit 1997 of port A: 1'0 + Constant input on bit 1998 of port A: 1'0 + Constant input on bit 1999 of port A: 1'0 + Constant input on bit 2000 of port A: 1'0 + Constant input on bit 2001 of port A: 1'0 + Constant input on bit 2002 of port A: 1'0 + Constant input on bit 2003 of port A: 1'0 + Constant input on bit 2004 of port A: 1'0 + Constant input on bit 2005 of port A: 1'0 + Constant input on bit 2006 of port A: 1'0 + Constant input on bit 2007 of port A: 1'0 + Constant input on bit 2008 of port A: 1'0 + Constant input on bit 2009 of port A: 1'0 + Constant input on bit 2010 of port A: 1'0 + Constant input on bit 2011 of port A: 1'0 + Constant input on bit 2012 of port A: 1'0 + Constant input on bit 2013 of port A: 1'0 + Constant input on bit 2014 of port A: 1'0 + Constant input on bit 2015 of port A: 1'0 + Constant input on bit 2016 of port A: 1'0 + Constant input on bit 2017 of port A: 1'0 + Constant input on bit 2018 of port A: 1'0 + Constant input on bit 2019 of port A: 1'0 + Constant input on bit 2020 of port A: 1'0 + Constant input on bit 2021 of port A: 1'0 + Constant input on bit 2022 of port A: 1'0 + Constant input on bit 2023 of port A: 1'0 + Constant input on bit 2024 of port A: 1'0 + Constant input on bit 2025 of port A: 1'0 + Constant input on bit 2026 of port A: 1'0 + Constant input on bit 2027 of port A: 1'0 + Constant input on bit 2028 of port A: 1'0 + Constant input on bit 2029 of port A: 1'0 + Constant input on bit 2030 of port A: 1'0 + Constant input on bit 2031 of port A: 1'0 + Constant input on bit 2032 of port A: 1'0 + Constant input on bit 2033 of port A: 1'0 + Constant input on bit 2034 of port A: 1'0 + Constant input on bit 2035 of port A: 1'0 + Constant input on bit 2036 of port A: 1'0 + Constant input on bit 2037 of port A: 1'0 + Constant input on bit 2038 of port A: 1'0 + Constant input on bit 2039 of port A: 1'0 + Constant input on bit 2040 of port A: 1'0 + Constant input on bit 2041 of port A: 1'0 + Constant input on bit 2042 of port A: 1'0 + Constant input on bit 2043 of port A: 1'0 + Constant input on bit 2044 of port A: 1'0 + Constant input on bit 2045 of port A: 1'0 + Constant input on bit 2046 of port A: 1'0 + Constant input on bit 2047 of port A: 1'0 +Creating constmapped module `$paramod$constmap:d41c3e6700281f3d49fe96d4ea47a4e4eb91446f$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx'. + +12.8. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:d41c3e6700281f3d49fe96d4ea47a4e4eb91446f$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$817. + dead port 2/2 on $mux $procmux$817. + dead port 1/2 on $mux $procmux$820. + dead port 2/2 on $mux $procmux$823. + dead port 2/2 on $mux $procmux$829. + dead port 2/2 on $mux $procmux$835. + dead port 2/2 on $mux $procmux$841. + dead port 2/2 on $mux $procmux$847. + dead port 1/2 on $mux $procmux$853. + dead port 2/2 on $mux $procmux$853. + dead port 1/2 on $mux $procmux$856. + dead port 1/2 on $mux $procmux$859. + dead port 2/2 on $mux $procmux$859. + dead port 1/2 on $mux $procmux$862. + dead port 1/2 on $mux $procmux$865. + dead port 2/2 on $mux $procmux$865. + dead port 1/2 on $mux $procmux$868. + dead port 1/2 on $mux $procmux$871. + dead port 2/2 on $mux $procmux$871. + dead port 1/2 on $mux $procmux$874. + dead port 1/2 on $mux $procmux$877. + dead port 2/2 on $mux $procmux$877. + dead port 1/2 on $mux $procmux$880. + dead port 1/2 on $mux $procmux$883. + dead port 2/2 on $mux $procmux$883. + dead port 1/2 on $mux $procmux$886. +Removed 26 multiplexer ports. + + +12.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:d41c3e6700281f3d49fe96d4ea47a4e4eb91446f$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx. + +Removed 0 unused cells and 64 unused wires. +Using template $paramod$constmap:d41c3e6700281f3d49fe96d4ea47a4e4eb91446f$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx for cells of type $shiftx. +Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $logic_and. +Using extmapper simplemap for cells of type $eq. +Running "alumacc" on wrapper $extern:wrap:$le:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$le:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$le:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$gt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$gt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$gt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. +Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=5:B_WIDTH=1:A_WIDTH=5:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$add:Y_WIDTH=5:B_WIDTH=1:A_WIDTH=5:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=5:B_WIDTH=1:A_WIDTH=5:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. +Using extmapper simplemap for cells of type $mux. +Running "alumacc" on wrapper $extern:wrap:$mul:Y_WIDTH=16:B_WIDTH=8:A_WIDTH=8:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$mul:Y_WIDTH=16:B_WIDTH=8:A_WIDTH=8:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:Y_WIDTH=16:B_WIDTH=8:A_WIDTH=8:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port B: 1'0 + Constant input on bit 1 of port B: 1'0 + Constant input on bit 2 of port B: 1'0 + Constant input on bit 3 of port B: 1'0 + Constant input on bit 4 of port B: 1'0 + Constant input on bit 5 of port B: 1'0 + Constant input on bit 11 of port B: 1'0 + Constant input on bit 12 of port B: 1'0 + Constant input on bit 13 of port B: 1'0 + Constant input on bit 14 of port B: 1'0 + Constant input on bit 15 of port B: 1'0 + Constant input on bit 16 of port B: 1'0 + Constant input on bit 17 of port B: 1'0 + Constant input on bit 18 of port B: 1'0 + Constant input on bit 19 of port B: 1'0 + Constant input on bit 20 of port B: 1'0 + Constant input on bit 21 of port B: 1'0 + Constant input on bit 22 of port B: 1'0 + Constant input on bit 23 of port B: 1'0 + Constant input on bit 24 of port B: 1'0 + Constant input on bit 25 of port B: 1'0 + Constant input on bit 26 of port B: 1'0 + Constant input on bit 27 of port B: 1'0 + Constant input on bit 28 of port B: 1'0 + Constant input on bit 29 of port B: 1'0 + Constant input on bit 30 of port B: 1'0 + Constant input on bit 31 of port B: 1'0 + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Constant input on bit 4 of port A: 1'1 + Constant input on bit 5 of port A: 1'1 + Constant input on bit 6 of port A: 1'1 + Constant input on bit 7 of port A: 1'1 + Constant input on bit 8 of port A: 1'1 + Constant input on bit 9 of port A: 1'1 + Constant input on bit 10 of port A: 1'1 + Constant input on bit 11 of port A: 1'1 + Constant input on bit 12 of port A: 1'1 + Constant input on bit 13 of port A: 1'1 + Constant input on bit 14 of port A: 1'1 + Constant input on bit 15 of port A: 1'1 + Constant input on bit 16 of port A: 1'1 + Constant input on bit 17 of port A: 1'1 + Constant input on bit 18 of port A: 1'1 + Constant input on bit 19 of port A: 1'1 + Constant input on bit 20 of port A: 1'1 + Constant input on bit 21 of port A: 1'1 + Constant input on bit 22 of port A: 1'1 + Constant input on bit 23 of port A: 1'1 + Constant input on bit 24 of port A: 1'1 + Constant input on bit 25 of port A: 1'1 + Constant input on bit 26 of port A: 1'1 + Constant input on bit 27 of port A: 1'1 + Constant input on bit 28 of port A: 1'1 + Constant input on bit 29 of port A: 1'1 + Constant input on bit 30 of port A: 1'1 + Constant input on bit 31 of port A: 1'1 + Constant input on bit 32 of port A: 1'1 + Constant input on bit 33 of port A: 1'1 + Constant input on bit 34 of port A: 1'1 + Constant input on bit 35 of port A: 1'1 + Constant input on bit 36 of port A: 1'1 + Constant input on bit 37 of port A: 1'1 + Constant input on bit 38 of port A: 1'1 + Constant input on bit 39 of port A: 1'1 + Constant input on bit 40 of port A: 1'1 + Constant input on bit 41 of port A: 1'1 + Constant input on bit 42 of port A: 1'1 + Constant input on bit 43 of port A: 1'1 + Constant input on bit 44 of port A: 1'1 + Constant input on bit 45 of port A: 1'1 + Constant input on bit 46 of port A: 1'1 + Constant input on bit 47 of port A: 1'1 + Constant input on bit 48 of port A: 1'1 + Constant input on bit 49 of port A: 1'1 + Constant input on bit 50 of port A: 1'1 + Constant input on bit 51 of port A: 1'1 + Constant input on bit 52 of port A: 1'1 + Constant input on bit 53 of port A: 1'1 + Constant input on bit 54 of port A: 1'1 + Constant input on bit 55 of port A: 1'1 + Constant input on bit 56 of port A: 1'1 + Constant input on bit 57 of port A: 1'1 + Constant input on bit 58 of port A: 1'1 + Constant input on bit 59 of port A: 1'1 + Constant input on bit 60 of port A: 1'1 + Constant input on bit 61 of port A: 1'1 + Constant input on bit 62 of port A: 1'1 + Constant input on bit 63 of port A: 1'1 + Constant input on bit 64 of port A: 1'1 + Constant input on bit 65 of port A: 1'1 + Constant input on bit 66 of port A: 1'1 + Constant input on bit 67 of port A: 1'1 + Constant input on bit 68 of port A: 1'1 + Constant input on bit 69 of port A: 1'1 + Constant input on bit 70 of port A: 1'1 + Constant input on bit 71 of port A: 1'1 + Constant input on bit 72 of port A: 1'1 + Constant input on bit 73 of port A: 1'1 + Constant input on bit 74 of port A: 1'1 + Constant input on bit 75 of port A: 1'1 + Constant input on bit 76 of port A: 1'1 + Constant input on bit 77 of port A: 1'1 + Constant input on bit 78 of port A: 1'1 + Constant input on bit 79 of port A: 1'1 + Constant input on bit 80 of port A: 1'1 + Constant input on bit 81 of port A: 1'1 + Constant input on bit 82 of port A: 1'1 + Constant input on bit 83 of port A: 1'1 + Constant input on bit 84 of port A: 1'1 + Constant input on bit 85 of port A: 1'1 + Constant input on bit 86 of port A: 1'1 + Constant input on bit 87 of port A: 1'1 + Constant input on bit 88 of port A: 1'1 + Constant input on bit 89 of port A: 1'1 + Constant input on bit 90 of port A: 1'1 + Constant input on bit 91 of port A: 1'1 + Constant input on bit 92 of port A: 1'1 + Constant input on bit 93 of port A: 1'1 + Constant input on bit 94 of port A: 1'1 + Constant input on bit 95 of port A: 1'1 + Constant input on bit 96 of port A: 1'1 + Constant input on bit 97 of port A: 1'1 + Constant input on bit 98 of port A: 1'1 + Constant input on bit 99 of port A: 1'1 + Constant input on bit 100 of port A: 1'1 + Constant input on bit 101 of port A: 1'1 + Constant input on bit 102 of port A: 1'1 + Constant input on bit 103 of port A: 1'1 + Constant input on bit 104 of port A: 1'1 + Constant input on bit 105 of port A: 1'1 + Constant input on bit 106 of port A: 1'1 + Constant input on bit 107 of port A: 1'1 + Constant input on bit 108 of port A: 1'1 + Constant input on bit 109 of port A: 1'1 + Constant input on bit 110 of port A: 1'1 + Constant input on bit 111 of port A: 1'1 + Constant input on bit 112 of port A: 1'1 + Constant input on bit 113 of port A: 1'1 + Constant input on bit 114 of port A: 1'1 + Constant input on bit 115 of port A: 1'1 + Constant input on bit 116 of port A: 1'1 + Constant input on bit 117 of port A: 1'1 + Constant input on bit 118 of port A: 1'1 + Constant input on bit 119 of port A: 1'1 + Constant input on bit 120 of port A: 1'1 + Constant input on bit 121 of port A: 1'1 + Constant input on bit 122 of port A: 1'1 + Constant input on bit 123 of port A: 1'1 + Constant input on bit 124 of port A: 1'1 + Constant input on bit 125 of port A: 1'1 + Constant input on bit 126 of port A: 1'1 + Constant input on bit 127 of port A: 1'1 + Constant input on bit 128 of port A: 1'1 + Constant input on bit 129 of port A: 1'1 + Constant input on bit 130 of port A: 1'1 + Constant input on bit 131 of port A: 1'1 + Constant input on bit 132 of port A: 1'1 + Constant input on bit 133 of port A: 1'1 + Constant input on bit 134 of port A: 1'1 + Constant input on bit 135 of port A: 1'1 + Constant input on bit 136 of port A: 1'1 + Constant input on bit 137 of port A: 1'1 + Constant input on bit 138 of port A: 1'1 + Constant input on bit 139 of port A: 1'1 + Constant input on bit 140 of port A: 1'1 + Constant input on bit 141 of port A: 1'1 + Constant input on bit 142 of port A: 1'1 + Constant input on bit 143 of port A: 1'1 + Constant input on bit 144 of port A: 1'1 + Constant input on bit 145 of port A: 1'1 + Constant input on bit 146 of port A: 1'1 + Constant input on bit 147 of port A: 1'1 + Constant input on bit 148 of port A: 1'1 + Constant input on bit 149 of port A: 1'1 + Constant input on bit 150 of port A: 1'1 + Constant input on bit 151 of port A: 1'1 + Constant input on bit 152 of port A: 1'1 + Constant input on bit 153 of port A: 1'1 + Constant input on bit 154 of port A: 1'1 + Constant input on bit 155 of port A: 1'1 + Constant input on bit 156 of port A: 1'1 + Constant input on bit 157 of port A: 1'1 + Constant input on bit 158 of port A: 1'1 + Constant input on bit 159 of port A: 1'1 + Constant input on bit 160 of port A: 1'1 + Constant input on bit 161 of port A: 1'1 + Constant input on bit 162 of port A: 1'1 + Constant input on bit 163 of port A: 1'1 + Constant input on bit 164 of port A: 1'1 + Constant input on bit 165 of port A: 1'1 + Constant input on bit 166 of port A: 1'1 + Constant input on bit 167 of port A: 1'1 + Constant input on bit 168 of port A: 1'1 + Constant input on bit 169 of port A: 1'1 + Constant input on bit 170 of port A: 1'1 + Constant input on bit 171 of port A: 1'1 + Constant input on bit 172 of port A: 1'1 + Constant input on bit 173 of port A: 1'1 + Constant input on bit 174 of port A: 1'1 + Constant input on bit 175 of port A: 1'1 + Constant input on bit 176 of port A: 1'1 + Constant input on bit 177 of port A: 1'1 + Constant input on bit 178 of port A: 1'1 + Constant input on bit 179 of port A: 1'1 + Constant input on bit 180 of port A: 1'1 + Constant input on bit 181 of port A: 1'1 + Constant input on bit 182 of port A: 1'1 + Constant input on bit 183 of port A: 1'1 + Constant input on bit 184 of port A: 1'1 + Constant input on bit 185 of port A: 1'1 + Constant input on bit 186 of port A: 1'1 + Constant input on bit 187 of port A: 1'1 + Constant input on bit 188 of port A: 1'1 + Constant input on bit 189 of port A: 1'1 + Constant input on bit 190 of port A: 1'1 + Constant input on bit 191 of port A: 1'1 + Constant input on bit 192 of port A: 1'1 + Constant input on bit 193 of port A: 1'1 + Constant input on bit 194 of port A: 1'1 + Constant input on bit 195 of port A: 1'1 + Constant input on bit 196 of port A: 1'1 + Constant input on bit 197 of port A: 1'1 + Constant input on bit 198 of port A: 1'1 + Constant input on bit 199 of port A: 1'1 + Constant input on bit 200 of port A: 1'1 + Constant input on bit 201 of port A: 1'1 + Constant input on bit 202 of port A: 1'1 + Constant input on bit 203 of port A: 1'1 + Constant input on bit 204 of port A: 1'1 + Constant input on bit 205 of port A: 1'1 + Constant input on bit 206 of port A: 1'1 + Constant input on bit 207 of port A: 1'1 + Constant input on bit 208 of port A: 1'1 + Constant input on bit 209 of port A: 1'1 + Constant input on bit 210 of port A: 1'1 + Constant input on bit 211 of port A: 1'1 + Constant input on bit 212 of port A: 1'1 + Constant input on bit 213 of port A: 1'1 + Constant input on bit 214 of port A: 1'1 + Constant input on bit 215 of port A: 1'1 + Constant input on bit 216 of port A: 1'1 + Constant input on bit 217 of port A: 1'1 + Constant input on bit 218 of port A: 1'1 + Constant input on bit 219 of port A: 1'1 + Constant input on bit 220 of port A: 1'1 + Constant input on bit 221 of port A: 1'1 + Constant input on bit 222 of port A: 1'1 + Constant input on bit 223 of port A: 1'1 + Constant input on bit 224 of port A: 1'1 + Constant input on bit 225 of port A: 1'1 + Constant input on bit 226 of port A: 1'1 + Constant input on bit 227 of port A: 1'1 + Constant input on bit 228 of port A: 1'1 + Constant input on bit 229 of port A: 1'1 + Constant input on bit 230 of port A: 1'1 + Constant input on bit 231 of port A: 1'1 + Constant input on bit 232 of port A: 1'1 + Constant input on bit 233 of port A: 1'1 + Constant input on bit 234 of port A: 1'1 + Constant input on bit 235 of port A: 1'1 + Constant input on bit 236 of port A: 1'1 + Constant input on bit 237 of port A: 1'1 + Constant input on bit 238 of port A: 1'1 + Constant input on bit 239 of port A: 1'1 + Constant input on bit 240 of port A: 1'1 + Constant input on bit 241 of port A: 1'1 + Constant input on bit 242 of port A: 1'1 + Constant input on bit 243 of port A: 1'1 + Constant input on bit 244 of port A: 1'1 + Constant input on bit 245 of port A: 1'1 + Constant input on bit 246 of port A: 1'1 + Constant input on bit 247 of port A: 1'1 + Constant input on bit 248 of port A: 1'1 + Constant input on bit 249 of port A: 1'1 + Constant input on bit 250 of port A: 1'1 + Constant input on bit 251 of port A: 1'1 + Constant input on bit 252 of port A: 1'1 + Constant input on bit 253 of port A: 1'1 + Constant input on bit 254 of port A: 1'1 + Constant input on bit 255 of port A: 1'1 + Constant input on bit 256 of port A: 1'1 + Constant input on bit 257 of port A: 1'1 + Constant input on bit 258 of port A: 1'1 + Constant input on bit 259 of port A: 1'1 + Constant input on bit 260 of port A: 1'1 + Constant input on bit 261 of port A: 1'1 + Constant input on bit 262 of port A: 1'1 + Constant input on bit 263 of port A: 1'1 + Constant input on bit 264 of port A: 1'1 + Constant input on bit 265 of port A: 1'1 + Constant input on bit 266 of port A: 1'1 + Constant input on bit 267 of port A: 1'1 + Constant input on bit 268 of port A: 1'1 + Constant input on bit 269 of port A: 1'1 + Constant input on bit 270 of port A: 1'1 + Constant input on bit 271 of port A: 1'1 + Constant input on bit 272 of port A: 1'1 + Constant input on bit 273 of port A: 1'1 + Constant input on bit 274 of port A: 1'1 + Constant input on bit 275 of port A: 1'1 + Constant input on bit 276 of port A: 1'1 + Constant input on bit 277 of port A: 1'1 + Constant input on bit 278 of port A: 1'1 + Constant input on bit 279 of port A: 1'1 + Constant input on bit 280 of port A: 1'1 + Constant input on bit 281 of port A: 1'1 + Constant input on bit 282 of port A: 1'1 + Constant input on bit 283 of port A: 1'1 + Constant input on bit 284 of port A: 1'1 + Constant input on bit 285 of port A: 1'1 + Constant input on bit 286 of port A: 1'1 + Constant input on bit 287 of port A: 1'1 + Constant input on bit 288 of port A: 1'1 + Constant input on bit 289 of port A: 1'1 + Constant input on bit 290 of port A: 1'1 + Constant input on bit 291 of port A: 1'1 + Constant input on bit 292 of port A: 1'1 + Constant input on bit 293 of port A: 1'1 + Constant input on bit 294 of port A: 1'1 + Constant input on bit 295 of port A: 1'1 + Constant input on bit 296 of port A: 1'1 + Constant input on bit 297 of port A: 1'1 + Constant input on bit 298 of port A: 1'1 + Constant input on bit 299 of port A: 1'1 + Constant input on bit 300 of port A: 1'1 + Constant input on bit 301 of port A: 1'1 + Constant input on bit 302 of port A: 1'1 + Constant input on bit 303 of port A: 1'1 + Constant input on bit 304 of port A: 1'1 + Constant input on bit 305 of port A: 1'1 + Constant input on bit 306 of port A: 1'1 + Constant input on bit 307 of port A: 1'1 + Constant input on bit 308 of port A: 1'1 + Constant input on bit 309 of port A: 1'1 + Constant input on bit 310 of port A: 1'1 + Constant input on bit 311 of port A: 1'1 + Constant input on bit 312 of port A: 1'1 + Constant input on bit 313 of port A: 1'1 + Constant input on bit 314 of port A: 1'1 + Constant input on bit 315 of port A: 1'1 + Constant input on bit 316 of port A: 1'1 + Constant input on bit 317 of port A: 1'1 + Constant input on bit 318 of port A: 1'1 + Constant input on bit 319 of port A: 1'1 + Constant input on bit 320 of port A: 1'1 + Constant input on bit 321 of port A: 1'1 + Constant input on bit 322 of port A: 1'1 + Constant input on bit 323 of port A: 1'1 + Constant input on bit 324 of port A: 1'1 + Constant input on bit 325 of port A: 1'1 + Constant input on bit 326 of port A: 1'1 + Constant input on bit 327 of port A: 1'1 + Constant input on bit 328 of port A: 1'1 + Constant input on bit 329 of port A: 1'1 + Constant input on bit 330 of port A: 1'1 + Constant input on bit 331 of port A: 1'1 + Constant input on bit 332 of port A: 1'1 + Constant input on bit 333 of port A: 1'1 + Constant input on bit 334 of port A: 1'1 + Constant input on bit 335 of port A: 1'1 + Constant input on bit 336 of port A: 1'1 + Constant input on bit 337 of port A: 1'1 + Constant input on bit 338 of port A: 1'1 + Constant input on bit 339 of port A: 1'1 + Constant input on bit 340 of port A: 1'1 + Constant input on bit 341 of port A: 1'1 + Constant input on bit 342 of port A: 1'1 + Constant input on bit 343 of port A: 1'1 + Constant input on bit 344 of port A: 1'1 + Constant input on bit 345 of port A: 1'1 + Constant input on bit 346 of port A: 1'1 + Constant input on bit 347 of port A: 1'1 + Constant input on bit 348 of port A: 1'1 + Constant input on bit 349 of port A: 1'1 + Constant input on bit 350 of port A: 1'1 + Constant input on bit 351 of port A: 1'1 + Constant input on bit 352 of port A: 1'1 + Constant input on bit 353 of port A: 1'1 + Constant input on bit 354 of port A: 1'1 + Constant input on bit 355 of port A: 1'1 + Constant input on bit 356 of port A: 1'1 + Constant input on bit 357 of port A: 1'1 + Constant input on bit 358 of port A: 1'1 + Constant input on bit 359 of port A: 1'1 + Constant input on bit 360 of port A: 1'1 + Constant input on bit 361 of port A: 1'1 + Constant input on bit 362 of port A: 1'1 + Constant input on bit 363 of port A: 1'1 + Constant input on bit 364 of port A: 1'1 + Constant input on bit 365 of port A: 1'1 + Constant input on bit 366 of port A: 1'1 + Constant input on bit 367 of port A: 1'1 + Constant input on bit 368 of port A: 1'1 + Constant input on bit 369 of port A: 1'1 + Constant input on bit 370 of port A: 1'1 + Constant input on bit 371 of port A: 1'1 + Constant input on bit 372 of port A: 1'1 + Constant input on bit 373 of port A: 1'1 + Constant input on bit 374 of port A: 1'1 + Constant input on bit 375 of port A: 1'1 + Constant input on bit 376 of port A: 1'1 + Constant input on bit 377 of port A: 1'1 + Constant input on bit 378 of port A: 1'1 + Constant input on bit 379 of port A: 1'1 + Constant input on bit 380 of port A: 1'1 + Constant input on bit 381 of port A: 1'1 + Constant input on bit 382 of port A: 1'1 + Constant input on bit 383 of port A: 1'1 + Constant input on bit 384 of port A: 1'1 + Constant input on bit 385 of port A: 1'1 + Constant input on bit 386 of port A: 1'1 + Constant input on bit 387 of port A: 1'1 + Constant input on bit 388 of port A: 1'1 + Constant input on bit 389 of port A: 1'1 + Constant input on bit 390 of port A: 1'1 + Constant input on bit 391 of port A: 1'1 + Constant input on bit 392 of port A: 1'1 + Constant input on bit 393 of port A: 1'1 + Constant input on bit 394 of port A: 1'1 + Constant input on bit 395 of port A: 1'1 + Constant input on bit 396 of port A: 1'1 + Constant input on bit 397 of port A: 1'1 + Constant input on bit 398 of port A: 1'1 + Constant input on bit 399 of port A: 1'1 + Constant input on bit 400 of port A: 1'1 + Constant input on bit 401 of port A: 1'1 + Constant input on bit 402 of port A: 1'1 + Constant input on bit 403 of port A: 1'1 + Constant input on bit 404 of port A: 1'1 + Constant input on bit 405 of port A: 1'1 + Constant input on bit 406 of port A: 1'1 + Constant input on bit 407 of port A: 1'1 + Constant input on bit 408 of port A: 1'1 + Constant input on bit 409 of port A: 1'1 + Constant input on bit 410 of port A: 1'1 + Constant input on bit 411 of port A: 1'1 + Constant input on bit 412 of port A: 1'1 + Constant input on bit 413 of port A: 1'1 + Constant input on bit 414 of port A: 1'1 + Constant input on bit 415 of port A: 1'1 + Constant input on bit 416 of port A: 1'1 + Constant input on bit 417 of port A: 1'1 + Constant input on bit 418 of port A: 1'1 + Constant input on bit 419 of port A: 1'1 + Constant input on bit 420 of port A: 1'1 + Constant input on bit 421 of port A: 1'1 + Constant input on bit 422 of port A: 1'1 + Constant input on bit 423 of port A: 1'1 + Constant input on bit 424 of port A: 1'1 + Constant input on bit 425 of port A: 1'1 + Constant input on bit 426 of port A: 1'1 + Constant input on bit 427 of port A: 1'1 + Constant input on bit 428 of port A: 1'1 + Constant input on bit 429 of port A: 1'1 + Constant input on bit 430 of port A: 1'1 + Constant input on bit 431 of port A: 1'1 + Constant input on bit 432 of port A: 1'1 + Constant input on bit 433 of port A: 1'1 + Constant input on bit 434 of port A: 1'1 + Constant input on bit 435 of port A: 1'1 + Constant input on bit 436 of port A: 1'1 + Constant input on bit 437 of port A: 1'1 + Constant input on bit 438 of port A: 1'1 + Constant input on bit 439 of port A: 1'1 + Constant input on bit 440 of port A: 1'1 + Constant input on bit 441 of port A: 1'1 + Constant input on bit 442 of port A: 1'1 + Constant input on bit 443 of port A: 1'1 + Constant input on bit 444 of port A: 1'1 + Constant input on bit 445 of port A: 1'1 + Constant input on bit 446 of port A: 1'1 + Constant input on bit 447 of port A: 1'1 + Constant input on bit 448 of port A: 1'1 + Constant input on bit 449 of port A: 1'1 + Constant input on bit 450 of port A: 1'1 + Constant input on bit 451 of port A: 1'1 + Constant input on bit 452 of port A: 1'1 + Constant input on bit 453 of port A: 1'1 + Constant input on bit 454 of port A: 1'1 + Constant input on bit 455 of port A: 1'1 + Constant input on bit 456 of port A: 1'1 + Constant input on bit 457 of port A: 1'1 + Constant input on bit 458 of port A: 1'1 + Constant input on bit 459 of port A: 1'1 + Constant input on bit 460 of port A: 1'1 + Constant input on bit 461 of port A: 1'1 + Constant input on bit 462 of port A: 1'1 + Constant input on bit 463 of port A: 1'1 + Constant input on bit 464 of port A: 1'1 + Constant input on bit 465 of port A: 1'1 + Constant input on bit 466 of port A: 1'1 + Constant input on bit 467 of port A: 1'1 + Constant input on bit 468 of port A: 1'1 + Constant input on bit 469 of port A: 1'1 + Constant input on bit 470 of port A: 1'1 + Constant input on bit 471 of port A: 1'1 + Constant input on bit 472 of port A: 1'1 + Constant input on bit 473 of port A: 1'1 + Constant input on bit 474 of port A: 1'1 + Constant input on bit 475 of port A: 1'1 + Constant input on bit 476 of port A: 1'1 + Constant input on bit 477 of port A: 1'1 + Constant input on bit 478 of port A: 1'1 + Constant input on bit 479 of port A: 1'1 + Constant input on bit 480 of port A: 1'1 + Constant input on bit 481 of port A: 1'1 + Constant input on bit 482 of port A: 1'1 + Constant input on bit 483 of port A: 1'1 + Constant input on bit 484 of port A: 1'1 + Constant input on bit 485 of port A: 1'1 + Constant input on bit 486 of port A: 1'1 + Constant input on bit 487 of port A: 1'1 + Constant input on bit 488 of port A: 1'1 + Constant input on bit 489 of port A: 1'1 + Constant input on bit 490 of port A: 1'1 + Constant input on bit 491 of port A: 1'1 + Constant input on bit 492 of port A: 1'1 + Constant input on bit 493 of port A: 1'1 + Constant input on bit 494 of port A: 1'1 + Constant input on bit 495 of port A: 1'1 + Constant input on bit 496 of port A: 1'1 + Constant input on bit 497 of port A: 1'1 + Constant input on bit 498 of port A: 1'1 + Constant input on bit 499 of port A: 1'1 + Constant input on bit 500 of port A: 1'1 + Constant input on bit 501 of port A: 1'1 + Constant input on bit 502 of port A: 1'1 + Constant input on bit 503 of port A: 1'1 + Constant input on bit 504 of port A: 1'1 + Constant input on bit 505 of port A: 1'1 + Constant input on bit 506 of port A: 1'1 + Constant input on bit 507 of port A: 1'1 + Constant input on bit 508 of port A: 1'1 + Constant input on bit 509 of port A: 1'1 + Constant input on bit 510 of port A: 1'1 + Constant input on bit 511 of port A: 1'1 + Constant input on bit 512 of port A: 1'1 + Constant input on bit 513 of port A: 1'1 + Constant input on bit 514 of port A: 1'1 + Constant input on bit 515 of port A: 1'1 + Constant input on bit 516 of port A: 1'1 + Constant input on bit 517 of port A: 1'1 + Constant input on bit 518 of port A: 1'1 + Constant input on bit 519 of port A: 1'1 + Constant input on bit 520 of port A: 1'1 + Constant input on bit 521 of port A: 1'1 + Constant input on bit 522 of port A: 1'1 + Constant input on bit 523 of port A: 1'1 + Constant input on bit 524 of port A: 1'1 + Constant input on bit 525 of port A: 1'1 + Constant input on bit 526 of port A: 1'1 + Constant input on bit 527 of port A: 1'1 + Constant input on bit 528 of port A: 1'1 + Constant input on bit 529 of port A: 1'1 + Constant input on bit 530 of port A: 1'1 + Constant input on bit 531 of port A: 1'1 + Constant input on bit 532 of port A: 1'1 + Constant input on bit 533 of port A: 1'1 + Constant input on bit 534 of port A: 1'1 + Constant input on bit 535 of port A: 1'1 + Constant input on bit 536 of port A: 1'1 + Constant input on bit 537 of port A: 1'1 + Constant input on bit 538 of port A: 1'1 + Constant input on bit 539 of port A: 1'1 + Constant input on bit 540 of port A: 1'1 + Constant input on bit 541 of port A: 1'1 + Constant input on bit 542 of port A: 1'1 + Constant input on bit 543 of port A: 1'1 + Constant input on bit 544 of port A: 1'1 + Constant input on bit 545 of port A: 1'1 + Constant input on bit 546 of port A: 1'1 + Constant input on bit 547 of port A: 1'1 + Constant input on bit 548 of port A: 1'1 + Constant input on bit 549 of port A: 1'1 + Constant input on bit 550 of port A: 1'1 + Constant input on bit 551 of port A: 1'1 + Constant input on bit 552 of port A: 1'1 + Constant input on bit 553 of port A: 1'1 + Constant input on bit 554 of port A: 1'1 + Constant input on bit 555 of port A: 1'1 + Constant input on bit 556 of port A: 1'1 + Constant input on bit 557 of port A: 1'1 + Constant input on bit 558 of port A: 1'1 + Constant input on bit 559 of port A: 1'1 + Constant input on bit 560 of port A: 1'1 + Constant input on bit 561 of port A: 1'1 + Constant input on bit 562 of port A: 1'1 + Constant input on bit 563 of port A: 1'1 + Constant input on bit 564 of port A: 1'1 + Constant input on bit 565 of port A: 1'1 + Constant input on bit 566 of port A: 1'1 + Constant input on bit 567 of port A: 1'1 + Constant input on bit 568 of port A: 1'1 + Constant input on bit 569 of port A: 1'1 + Constant input on bit 570 of port A: 1'1 + Constant input on bit 571 of port A: 1'1 + Constant input on bit 572 of port A: 1'1 + Constant input on bit 573 of port A: 1'1 + Constant input on bit 574 of port A: 1'1 + Constant input on bit 575 of port A: 1'1 + Constant input on bit 576 of port A: 1'1 + Constant input on bit 577 of port A: 1'1 + Constant input on bit 578 of port A: 1'1 + Constant input on bit 579 of port A: 1'1 + Constant input on bit 580 of port A: 1'1 + Constant input on bit 581 of port A: 1'1 + Constant input on bit 582 of port A: 1'1 + Constant input on bit 583 of port A: 1'1 + Constant input on bit 584 of port A: 1'1 + Constant input on bit 585 of port A: 1'1 + Constant input on bit 586 of port A: 1'1 + Constant input on bit 587 of port A: 1'1 + Constant input on bit 588 of port A: 1'1 + Constant input on bit 589 of port A: 1'1 + Constant input on bit 590 of port A: 1'1 + Constant input on bit 591 of port A: 1'1 + Constant input on bit 592 of port A: 1'1 + Constant input on bit 593 of port A: 1'1 + Constant input on bit 594 of port A: 1'1 + Constant input on bit 595 of port A: 1'1 + Constant input on bit 596 of port A: 1'1 + Constant input on bit 597 of port A: 1'1 + Constant input on bit 598 of port A: 1'1 + Constant input on bit 599 of port A: 1'1 + Constant input on bit 600 of port A: 1'1 + Constant input on bit 601 of port A: 1'1 + Constant input on bit 602 of port A: 1'1 + Constant input on bit 603 of port A: 1'1 + Constant input on bit 604 of port A: 1'1 + Constant input on bit 605 of port A: 1'1 + Constant input on bit 606 of port A: 1'1 + Constant input on bit 607 of port A: 1'1 + Constant input on bit 608 of port A: 1'1 + Constant input on bit 609 of port A: 1'1 + Constant input on bit 610 of port A: 1'1 + Constant input on bit 611 of port A: 1'1 + Constant input on bit 612 of port A: 1'1 + Constant input on bit 613 of port A: 1'1 + Constant input on bit 614 of port A: 1'1 + Constant input on bit 615 of port A: 1'1 + Constant input on bit 616 of port A: 1'1 + Constant input on bit 617 of port A: 1'1 + Constant input on bit 618 of port A: 1'1 + Constant input on bit 619 of port A: 1'1 + Constant input on bit 620 of port A: 1'1 + Constant input on bit 621 of port A: 1'1 + Constant input on bit 622 of port A: 1'1 + Constant input on bit 623 of port A: 1'1 + Constant input on bit 624 of port A: 1'1 + Constant input on bit 625 of port A: 1'1 + Constant input on bit 626 of port A: 1'1 + Constant input on bit 627 of port A: 1'1 + Constant input on bit 628 of port A: 1'1 + Constant input on bit 629 of port A: 1'1 + Constant input on bit 630 of port A: 1'1 + Constant input on bit 631 of port A: 1'1 + Constant input on bit 632 of port A: 1'1 + Constant input on bit 633 of port A: 1'1 + Constant input on bit 634 of port A: 1'1 + Constant input on bit 635 of port A: 1'1 + Constant input on bit 636 of port A: 1'1 + Constant input on bit 637 of port A: 1'1 + Constant input on bit 638 of port A: 1'1 + Constant input on bit 639 of port A: 1'1 + Constant input on bit 640 of port A: 1'1 + Constant input on bit 641 of port A: 1'1 + Constant input on bit 642 of port A: 1'1 + Constant input on bit 643 of port A: 1'1 + Constant input on bit 644 of port A: 1'1 + Constant input on bit 645 of port A: 1'1 + Constant input on bit 646 of port A: 1'1 + Constant input on bit 647 of port A: 1'1 + Constant input on bit 648 of port A: 1'1 + Constant input on bit 649 of port A: 1'1 + Constant input on bit 650 of port A: 1'1 + Constant input on bit 651 of port A: 1'1 + Constant input on bit 652 of port A: 1'1 + Constant input on bit 653 of port A: 1'1 + Constant input on bit 654 of port A: 1'1 + Constant input on bit 655 of port A: 1'1 + Constant input on bit 656 of port A: 1'1 + Constant input on bit 657 of port A: 1'1 + Constant input on bit 658 of port A: 1'1 + Constant input on bit 659 of port A: 1'1 + Constant input on bit 660 of port A: 1'1 + Constant input on bit 661 of port A: 1'1 + Constant input on bit 662 of port A: 1'1 + Constant input on bit 663 of port A: 1'1 + Constant input on bit 664 of port A: 1'1 + Constant input on bit 665 of port A: 1'1 + Constant input on bit 666 of port A: 1'1 + Constant input on bit 667 of port A: 1'1 + Constant input on bit 668 of port A: 1'1 + Constant input on bit 669 of port A: 1'1 + Constant input on bit 670 of port A: 1'1 + Constant input on bit 671 of port A: 1'1 + Constant input on bit 672 of port A: 1'1 + Constant input on bit 673 of port A: 1'1 + Constant input on bit 674 of port A: 1'1 + Constant input on bit 675 of port A: 1'1 + Constant input on bit 676 of port A: 1'1 + Constant input on bit 677 of port A: 1'1 + Constant input on bit 678 of port A: 1'1 + Constant input on bit 679 of port A: 1'1 + Constant input on bit 680 of port A: 1'1 + Constant input on bit 681 of port A: 1'1 + Constant input on bit 682 of port A: 1'1 + Constant input on bit 683 of port A: 1'1 + Constant input on bit 684 of port A: 1'1 + Constant input on bit 685 of port A: 1'1 + Constant input on bit 686 of port A: 1'1 + Constant input on bit 687 of port A: 1'1 + Constant input on bit 688 of port A: 1'1 + Constant input on bit 689 of port A: 1'1 + Constant input on bit 690 of port A: 1'1 + Constant input on bit 691 of port A: 1'1 + Constant input on bit 692 of port A: 1'1 + Constant input on bit 693 of port A: 1'1 + Constant input on bit 694 of port A: 1'1 + Constant input on bit 695 of port A: 1'1 + Constant input on bit 696 of port A: 1'1 + Constant input on bit 697 of port A: 1'1 + Constant input on bit 698 of port A: 1'1 + Constant input on bit 699 of port A: 1'1 + Constant input on bit 700 of port A: 1'1 + Constant input on bit 701 of port A: 1'1 + Constant input on bit 702 of port A: 1'1 + Constant input on bit 703 of port A: 1'1 + Constant input on bit 704 of port A: 1'1 + Constant input on bit 705 of port A: 1'1 + Constant input on bit 706 of port A: 1'1 + Constant input on bit 707 of port A: 1'1 + Constant input on bit 708 of port A: 1'1 + Constant input on bit 709 of port A: 1'1 + Constant input on bit 710 of port A: 1'1 + Constant input on bit 711 of port A: 1'1 + Constant input on bit 712 of port A: 1'1 + Constant input on bit 713 of port A: 1'1 + Constant input on bit 714 of port A: 1'1 + Constant input on bit 715 of port A: 1'1 + Constant input on bit 716 of port A: 1'1 + Constant input on bit 717 of port A: 1'1 + Constant input on bit 718 of port A: 1'1 + Constant input on bit 719 of port A: 1'1 + Constant input on bit 720 of port A: 1'1 + Constant input on bit 721 of port A: 1'1 + Constant input on bit 722 of port A: 1'1 + Constant input on bit 723 of port A: 1'1 + Constant input on bit 724 of port A: 1'1 + Constant input on bit 725 of port A: 1'1 + Constant input on bit 726 of port A: 1'1 + Constant input on bit 727 of port A: 1'1 + Constant input on bit 728 of port A: 1'1 + Constant input on bit 729 of port A: 1'1 + Constant input on bit 730 of port A: 1'1 + Constant input on bit 731 of port A: 1'1 + Constant input on bit 732 of port A: 1'1 + Constant input on bit 733 of port A: 1'1 + Constant input on bit 734 of port A: 1'1 + Constant input on bit 735 of port A: 1'1 + Constant input on bit 736 of port A: 1'1 + Constant input on bit 737 of port A: 1'1 + Constant input on bit 738 of port A: 1'1 + Constant input on bit 739 of port A: 1'1 + Constant input on bit 740 of port A: 1'1 + Constant input on bit 741 of port A: 1'1 + Constant input on bit 742 of port A: 1'1 + Constant input on bit 743 of port A: 1'1 + Constant input on bit 744 of port A: 1'1 + Constant input on bit 745 of port A: 1'1 + Constant input on bit 746 of port A: 1'1 + Constant input on bit 747 of port A: 1'1 + Constant input on bit 748 of port A: 1'1 + Constant input on bit 749 of port A: 1'1 + Constant input on bit 750 of port A: 1'1 + Constant input on bit 751 of port A: 1'1 + Constant input on bit 752 of port A: 1'1 + Constant input on bit 753 of port A: 1'1 + Constant input on bit 754 of port A: 1'1 + Constant input on bit 755 of port A: 1'1 + Constant input on bit 756 of port A: 1'1 + Constant input on bit 757 of port A: 1'1 + Constant input on bit 758 of port A: 1'1 + Constant input on bit 759 of port A: 1'1 + Constant input on bit 760 of port A: 1'1 + Constant input on bit 761 of port A: 1'1 + Constant input on bit 762 of port A: 1'1 + Constant input on bit 763 of port A: 1'1 + Constant input on bit 764 of port A: 1'1 + Constant input on bit 765 of port A: 1'1 + Constant input on bit 766 of port A: 1'1 + Constant input on bit 767 of port A: 1'1 + Constant input on bit 768 of port A: 1'1 + Constant input on bit 769 of port A: 1'1 + Constant input on bit 770 of port A: 1'1 + Constant input on bit 771 of port A: 1'1 + Constant input on bit 772 of port A: 1'1 + Constant input on bit 773 of port A: 1'1 + Constant input on bit 774 of port A: 1'1 + Constant input on bit 775 of port A: 1'1 + Constant input on bit 776 of port A: 1'1 + Constant input on bit 777 of port A: 1'1 + Constant input on bit 778 of port A: 1'1 + Constant input on bit 779 of port A: 1'1 + Constant input on bit 780 of port A: 1'1 + Constant input on bit 781 of port A: 1'1 + Constant input on bit 782 of port A: 1'1 + Constant input on bit 783 of port A: 1'1 + Constant input on bit 784 of port A: 1'1 + Constant input on bit 785 of port A: 1'1 + Constant input on bit 786 of port A: 1'1 + Constant input on bit 787 of port A: 1'1 + Constant input on bit 788 of port A: 1'1 + Constant input on bit 789 of port A: 1'1 + Constant input on bit 790 of port A: 1'1 + Constant input on bit 791 of port A: 1'1 + Constant input on bit 792 of port A: 1'1 + Constant input on bit 793 of port A: 1'1 + Constant input on bit 794 of port A: 1'1 + Constant input on bit 795 of port A: 1'1 + Constant input on bit 796 of port A: 1'1 + Constant input on bit 797 of port A: 1'1 + Constant input on bit 798 of port A: 1'1 + Constant input on bit 799 of port A: 1'1 + Constant input on bit 800 of port A: 1'1 + Constant input on bit 801 of port A: 1'1 + Constant input on bit 802 of port A: 1'1 + Constant input on bit 803 of port A: 1'1 + Constant input on bit 804 of port A: 1'1 + Constant input on bit 805 of port A: 1'1 + Constant input on bit 806 of port A: 1'1 + Constant input on bit 807 of port A: 1'1 + Constant input on bit 808 of port A: 1'1 + Constant input on bit 809 of port A: 1'1 + Constant input on bit 810 of port A: 1'1 + Constant input on bit 811 of port A: 1'1 + Constant input on bit 812 of port A: 1'1 + Constant input on bit 813 of port A: 1'1 + Constant input on bit 814 of port A: 1'1 + Constant input on bit 815 of port A: 1'1 + Constant input on bit 816 of port A: 1'1 + Constant input on bit 817 of port A: 1'1 + Constant input on bit 818 of port A: 1'1 + Constant input on bit 819 of port A: 1'1 + Constant input on bit 820 of port A: 1'1 + Constant input on bit 821 of port A: 1'1 + Constant input on bit 822 of port A: 1'1 + Constant input on bit 823 of port A: 1'1 + Constant input on bit 824 of port A: 1'1 + Constant input on bit 825 of port A: 1'1 + Constant input on bit 826 of port A: 1'1 + Constant input on bit 827 of port A: 1'1 + Constant input on bit 828 of port A: 1'1 + Constant input on bit 829 of port A: 1'1 + Constant input on bit 830 of port A: 1'1 + Constant input on bit 831 of port A: 1'1 + Constant input on bit 832 of port A: 1'1 + Constant input on bit 833 of port A: 1'1 + Constant input on bit 834 of port A: 1'1 + Constant input on bit 835 of port A: 1'1 + Constant input on bit 836 of port A: 1'1 + Constant input on bit 837 of port A: 1'1 + Constant input on bit 838 of port A: 1'1 + Constant input on bit 839 of port A: 1'1 + Constant input on bit 840 of port A: 1'1 + Constant input on bit 841 of port A: 1'1 + Constant input on bit 842 of port A: 1'1 + Constant input on bit 843 of port A: 1'1 + Constant input on bit 844 of port A: 1'1 + Constant input on bit 845 of port A: 1'1 + Constant input on bit 846 of port A: 1'1 + Constant input on bit 847 of port A: 1'1 + Constant input on bit 848 of port A: 1'1 + Constant input on bit 849 of port A: 1'1 + Constant input on bit 850 of port A: 1'1 + Constant input on bit 851 of port A: 1'1 + Constant input on bit 852 of port A: 1'1 + Constant input on bit 853 of port A: 1'1 + Constant input on bit 854 of port A: 1'1 + Constant input on bit 855 of port A: 1'1 + Constant input on bit 856 of port A: 1'1 + Constant input on bit 857 of port A: 1'1 + Constant input on bit 858 of port A: 1'1 + Constant input on bit 859 of port A: 1'1 + Constant input on bit 860 of port A: 1'1 + Constant input on bit 861 of port A: 1'1 + Constant input on bit 862 of port A: 1'1 + Constant input on bit 863 of port A: 1'1 + Constant input on bit 864 of port A: 1'1 + Constant input on bit 865 of port A: 1'1 + Constant input on bit 866 of port A: 1'1 + Constant input on bit 867 of port A: 1'1 + Constant input on bit 868 of port A: 1'1 + Constant input on bit 869 of port A: 1'1 + Constant input on bit 870 of port A: 1'1 + Constant input on bit 871 of port A: 1'1 + Constant input on bit 872 of port A: 1'1 + Constant input on bit 873 of port A: 1'1 + Constant input on bit 874 of port A: 1'1 + Constant input on bit 875 of port A: 1'1 + Constant input on bit 876 of port A: 1'1 + Constant input on bit 877 of port A: 1'1 + Constant input on bit 878 of port A: 1'1 + Constant input on bit 879 of port A: 1'1 + Constant input on bit 880 of port A: 1'1 + Constant input on bit 881 of port A: 1'1 + Constant input on bit 882 of port A: 1'1 + Constant input on bit 883 of port A: 1'1 + Constant input on bit 884 of port A: 1'1 + Constant input on bit 885 of port A: 1'1 + Constant input on bit 886 of port A: 1'1 + Constant input on bit 887 of port A: 1'1 + Constant input on bit 888 of port A: 1'1 + Constant input on bit 889 of port A: 1'1 + Constant input on bit 890 of port A: 1'1 + Constant input on bit 891 of port A: 1'1 + Constant input on bit 892 of port A: 1'1 + Constant input on bit 893 of port A: 1'1 + Constant input on bit 894 of port A: 1'1 + Constant input on bit 895 of port A: 1'1 + Constant input on bit 896 of port A: 1'1 + Constant input on bit 897 of port A: 1'1 + Constant input on bit 898 of port A: 1'1 + Constant input on bit 899 of port A: 1'1 + Constant input on bit 900 of port A: 1'1 + Constant input on bit 901 of port A: 1'1 + Constant input on bit 902 of port A: 1'1 + Constant input on bit 903 of port A: 1'1 + Constant input on bit 904 of port A: 1'1 + Constant input on bit 905 of port A: 1'1 + Constant input on bit 906 of port A: 1'1 + Constant input on bit 907 of port A: 1'1 + Constant input on bit 908 of port A: 1'1 + Constant input on bit 909 of port A: 1'1 + Constant input on bit 910 of port A: 1'1 + Constant input on bit 911 of port A: 1'1 + Constant input on bit 912 of port A: 1'1 + Constant input on bit 913 of port A: 1'1 + Constant input on bit 914 of port A: 1'1 + Constant input on bit 915 of port A: 1'1 + Constant input on bit 916 of port A: 1'1 + Constant input on bit 917 of port A: 1'1 + Constant input on bit 918 of port A: 1'1 + Constant input on bit 919 of port A: 1'1 + Constant input on bit 920 of port A: 1'1 + Constant input on bit 921 of port A: 1'1 + Constant input on bit 922 of port A: 1'1 + Constant input on bit 923 of port A: 1'1 + Constant input on bit 924 of port A: 1'1 + Constant input on bit 925 of port A: 1'1 + Constant input on bit 926 of port A: 1'1 + Constant input on bit 927 of port A: 1'1 + Constant input on bit 928 of port A: 1'1 + Constant input on bit 929 of port A: 1'1 + Constant input on bit 930 of port A: 1'1 + Constant input on bit 931 of port A: 1'1 + Constant input on bit 932 of port A: 1'1 + Constant input on bit 933 of port A: 1'1 + Constant input on bit 934 of port A: 1'1 + Constant input on bit 935 of port A: 1'1 + Constant input on bit 936 of port A: 1'1 + Constant input on bit 937 of port A: 1'1 + Constant input on bit 938 of port A: 1'1 + Constant input on bit 939 of port A: 1'1 + Constant input on bit 940 of port A: 1'1 + Constant input on bit 941 of port A: 1'1 + Constant input on bit 942 of port A: 1'1 + Constant input on bit 943 of port A: 1'1 + Constant input on bit 944 of port A: 1'1 + Constant input on bit 945 of port A: 1'1 + Constant input on bit 946 of port A: 1'1 + Constant input on bit 947 of port A: 1'1 + Constant input on bit 948 of port A: 1'1 + Constant input on bit 949 of port A: 1'1 + Constant input on bit 950 of port A: 1'1 + Constant input on bit 951 of port A: 1'1 + Constant input on bit 952 of port A: 1'1 + Constant input on bit 953 of port A: 1'1 + Constant input on bit 954 of port A: 1'1 + Constant input on bit 955 of port A: 1'1 + Constant input on bit 956 of port A: 1'1 + Constant input on bit 957 of port A: 1'1 + Constant input on bit 958 of port A: 1'1 + Constant input on bit 959 of port A: 1'1 + Constant input on bit 960 of port A: 1'1 + Constant input on bit 961 of port A: 1'1 + Constant input on bit 962 of port A: 1'1 + Constant input on bit 963 of port A: 1'1 + Constant input on bit 964 of port A: 1'1 + Constant input on bit 965 of port A: 1'1 + Constant input on bit 966 of port A: 1'1 + Constant input on bit 967 of port A: 1'1 + Constant input on bit 968 of port A: 1'1 + Constant input on bit 969 of port A: 1'1 + Constant input on bit 970 of port A: 1'1 + Constant input on bit 971 of port A: 1'1 + Constant input on bit 972 of port A: 1'1 + Constant input on bit 973 of port A: 1'1 + Constant input on bit 974 of port A: 1'1 + Constant input on bit 975 of port A: 1'1 + Constant input on bit 976 of port A: 1'1 + Constant input on bit 977 of port A: 1'1 + Constant input on bit 978 of port A: 1'1 + Constant input on bit 979 of port A: 1'1 + Constant input on bit 980 of port A: 1'1 + Constant input on bit 981 of port A: 1'1 + Constant input on bit 982 of port A: 1'1 + Constant input on bit 983 of port A: 1'1 + Constant input on bit 984 of port A: 1'1 + Constant input on bit 985 of port A: 1'1 + Constant input on bit 986 of port A: 1'1 + Constant input on bit 987 of port A: 1'1 + Constant input on bit 988 of port A: 1'1 + Constant input on bit 989 of port A: 1'1 + Constant input on bit 990 of port A: 1'1 + Constant input on bit 991 of port A: 1'1 + Constant input on bit 992 of port A: 1'1 + Constant input on bit 993 of port A: 1'1 + Constant input on bit 994 of port A: 1'1 + Constant input on bit 995 of port A: 1'1 + Constant input on bit 996 of port A: 1'1 + Constant input on bit 997 of port A: 1'1 + Constant input on bit 998 of port A: 1'1 + Constant input on bit 999 of port A: 1'1 + Constant input on bit 1000 of port A: 1'1 + Constant input on bit 1001 of port A: 1'1 + Constant input on bit 1002 of port A: 1'1 + Constant input on bit 1003 of port A: 1'1 + Constant input on bit 1004 of port A: 1'1 + Constant input on bit 1005 of port A: 1'1 + Constant input on bit 1006 of port A: 1'1 + Constant input on bit 1007 of port A: 1'1 + Constant input on bit 1008 of port A: 1'1 + Constant input on bit 1009 of port A: 1'1 + Constant input on bit 1010 of port A: 1'1 + Constant input on bit 1011 of port A: 1'1 + Constant input on bit 1012 of port A: 1'1 + Constant input on bit 1013 of port A: 1'1 + Constant input on bit 1014 of port A: 1'1 + Constant input on bit 1015 of port A: 1'1 + Constant input on bit 1016 of port A: 1'1 + Constant input on bit 1017 of port A: 1'1 + Constant input on bit 1018 of port A: 1'1 + Constant input on bit 1019 of port A: 1'1 + Constant input on bit 1020 of port A: 1'1 + Constant input on bit 1021 of port A: 1'1 + Constant input on bit 1022 of port A: 1'1 + Constant input on bit 1023 of port A: 1'1 + Constant input on bit 1024 of port A: 1'1 + Constant input on bit 1025 of port A: 1'1 + Constant input on bit 1026 of port A: 1'1 + Constant input on bit 1027 of port A: 1'1 + Constant input on bit 1028 of port A: 1'1 + Constant input on bit 1029 of port A: 1'1 + Constant input on bit 1030 of port A: 1'1 + Constant input on bit 1031 of port A: 1'1 + Constant input on bit 1032 of port A: 1'1 + Constant input on bit 1033 of port A: 1'1 + Constant input on bit 1034 of port A: 1'1 + Constant input on bit 1035 of port A: 1'1 + Constant input on bit 1036 of port A: 1'1 + Constant input on bit 1037 of port A: 1'1 + Constant input on bit 1038 of port A: 1'1 + Constant input on bit 1039 of port A: 1'1 + Constant input on bit 1040 of port A: 1'1 + Constant input on bit 1041 of port A: 1'1 + Constant input on bit 1042 of port A: 1'1 + Constant input on bit 1043 of port A: 1'1 + Constant input on bit 1044 of port A: 1'1 + Constant input on bit 1045 of port A: 1'1 + Constant input on bit 1046 of port A: 1'1 + Constant input on bit 1047 of port A: 1'1 + Constant input on bit 1048 of port A: 1'1 + Constant input on bit 1049 of port A: 1'1 + Constant input on bit 1050 of port A: 1'1 + Constant input on bit 1051 of port A: 1'1 + Constant input on bit 1052 of port A: 1'1 + Constant input on bit 1053 of port A: 1'1 + Constant input on bit 1054 of port A: 1'1 + Constant input on bit 1055 of port A: 1'1 + Constant input on bit 1056 of port A: 1'1 + Constant input on bit 1057 of port A: 1'1 + Constant input on bit 1058 of port A: 1'1 + Constant input on bit 1059 of port A: 1'1 + Constant input on bit 1060 of port A: 1'1 + Constant input on bit 1061 of port A: 1'1 + Constant input on bit 1062 of port A: 1'1 + Constant input on bit 1063 of port A: 1'1 + Constant input on bit 1064 of port A: 1'1 + Constant input on bit 1065 of port A: 1'1 + Constant input on bit 1066 of port A: 1'1 + Constant input on bit 1067 of port A: 1'1 + Constant input on bit 1068 of port A: 1'1 + Constant input on bit 1069 of port A: 1'1 + Constant input on bit 1070 of port A: 1'1 + Constant input on bit 1071 of port A: 1'1 + Constant input on bit 1072 of port A: 1'1 + Constant input on bit 1073 of port A: 1'1 + Constant input on bit 1074 of port A: 1'1 + Constant input on bit 1075 of port A: 1'1 + Constant input on bit 1076 of port A: 1'1 + Constant input on bit 1077 of port A: 1'1 + Constant input on bit 1078 of port A: 1'1 + Constant input on bit 1079 of port A: 1'1 + Constant input on bit 1080 of port A: 1'1 + Constant input on bit 1081 of port A: 1'1 + Constant input on bit 1082 of port A: 1'1 + Constant input on bit 1083 of port A: 1'1 + Constant input on bit 1084 of port A: 1'1 + Constant input on bit 1085 of port A: 1'1 + Constant input on bit 1086 of port A: 1'1 + Constant input on bit 1087 of port A: 1'1 + Constant input on bit 1088 of port A: 1'1 + Constant input on bit 1089 of port A: 1'1 + Constant input on bit 1090 of port A: 1'1 + Constant input on bit 1091 of port A: 1'1 + Constant input on bit 1092 of port A: 1'1 + Constant input on bit 1093 of port A: 1'1 + Constant input on bit 1094 of port A: 1'1 + Constant input on bit 1095 of port A: 1'1 + Constant input on bit 1096 of port A: 1'1 + Constant input on bit 1097 of port A: 1'1 + Constant input on bit 1098 of port A: 1'1 + Constant input on bit 1099 of port A: 1'1 + Constant input on bit 1100 of port A: 1'1 + Constant input on bit 1101 of port A: 1'1 + Constant input on bit 1102 of port A: 1'1 + Constant input on bit 1103 of port A: 1'1 + Constant input on bit 1104 of port A: 1'1 + Constant input on bit 1105 of port A: 1'1 + Constant input on bit 1106 of port A: 1'1 + Constant input on bit 1107 of port A: 1'1 + Constant input on bit 1108 of port A: 1'1 + Constant input on bit 1109 of port A: 1'1 + Constant input on bit 1110 of port A: 1'1 + Constant input on bit 1111 of port A: 1'1 + Constant input on bit 1112 of port A: 1'1 + Constant input on bit 1113 of port A: 1'1 + Constant input on bit 1114 of port A: 1'1 + Constant input on bit 1115 of port A: 1'1 + Constant input on bit 1116 of port A: 1'1 + Constant input on bit 1117 of port A: 1'1 + Constant input on bit 1118 of port A: 1'1 + Constant input on bit 1119 of port A: 1'1 + Constant input on bit 1120 of port A: 1'1 + Constant input on bit 1121 of port A: 1'1 + Constant input on bit 1122 of port A: 1'1 + Constant input on bit 1123 of port A: 1'1 + Constant input on bit 1124 of port A: 1'1 + Constant input on bit 1125 of port A: 1'1 + Constant input on bit 1126 of port A: 1'1 + Constant input on bit 1127 of port A: 1'1 + Constant input on bit 1128 of port A: 1'1 + Constant input on bit 1129 of port A: 1'1 + Constant input on bit 1130 of port A: 1'1 + Constant input on bit 1131 of port A: 1'1 + Constant input on bit 1132 of port A: 1'1 + Constant input on bit 1133 of port A: 1'1 + Constant input on bit 1134 of port A: 1'1 + Constant input on bit 1135 of port A: 1'1 + Constant input on bit 1136 of port A: 1'1 + Constant input on bit 1137 of port A: 1'1 + Constant input on bit 1138 of port A: 1'1 + Constant input on bit 1139 of port A: 1'1 + Constant input on bit 1140 of port A: 1'1 + Constant input on bit 1141 of port A: 1'1 + Constant input on bit 1142 of port A: 1'1 + Constant input on bit 1143 of port A: 1'1 + Constant input on bit 1144 of port A: 1'1 + Constant input on bit 1145 of port A: 1'1 + Constant input on bit 1146 of port A: 1'1 + Constant input on bit 1147 of port A: 1'1 + Constant input on bit 1148 of port A: 1'1 + Constant input on bit 1149 of port A: 1'1 + Constant input on bit 1150 of port A: 1'1 + Constant input on bit 1151 of port A: 1'1 + Constant input on bit 1152 of port A: 1'1 + Constant input on bit 1153 of port A: 1'1 + Constant input on bit 1154 of port A: 1'1 + Constant input on bit 1155 of port A: 1'1 + Constant input on bit 1156 of port A: 1'1 + Constant input on bit 1157 of port A: 1'1 + Constant input on bit 1158 of port A: 1'1 + Constant input on bit 1159 of port A: 1'1 + Constant input on bit 1160 of port A: 1'1 + Constant input on bit 1161 of port A: 1'1 + Constant input on bit 1162 of port A: 1'1 + Constant input on bit 1163 of port A: 1'1 + Constant input on bit 1164 of port A: 1'1 + Constant input on bit 1165 of port A: 1'1 + Constant input on bit 1166 of port A: 1'1 + Constant input on bit 1167 of port A: 1'1 + Constant input on bit 1168 of port A: 1'1 + Constant input on bit 1169 of port A: 1'1 + Constant input on bit 1170 of port A: 1'1 + Constant input on bit 1171 of port A: 1'1 + Constant input on bit 1172 of port A: 1'1 + Constant input on bit 1173 of port A: 1'1 + Constant input on bit 1174 of port A: 1'1 + Constant input on bit 1175 of port A: 1'1 + Constant input on bit 1176 of port A: 1'1 + Constant input on bit 1177 of port A: 1'1 + Constant input on bit 1178 of port A: 1'1 + Constant input on bit 1179 of port A: 1'1 + Constant input on bit 1180 of port A: 1'1 + Constant input on bit 1181 of port A: 1'1 + Constant input on bit 1182 of port A: 1'1 + Constant input on bit 1183 of port A: 1'1 + Constant input on bit 1184 of port A: 1'1 + Constant input on bit 1185 of port A: 1'1 + Constant input on bit 1186 of port A: 1'1 + Constant input on bit 1187 of port A: 1'1 + Constant input on bit 1188 of port A: 1'1 + Constant input on bit 1189 of port A: 1'1 + Constant input on bit 1190 of port A: 1'1 + Constant input on bit 1191 of port A: 1'1 + Constant input on bit 1192 of port A: 1'1 + Constant input on bit 1193 of port A: 1'1 + Constant input on bit 1194 of port A: 1'1 + Constant input on bit 1195 of port A: 1'1 + Constant input on bit 1196 of port A: 1'1 + Constant input on bit 1197 of port A: 1'1 + Constant input on bit 1198 of port A: 1'1 + Constant input on bit 1199 of port A: 1'1 + Constant input on bit 1200 of port A: 1'1 + Constant input on bit 1201 of port A: 1'1 + Constant input on bit 1202 of port A: 1'1 + Constant input on bit 1203 of port A: 1'1 + Constant input on bit 1204 of port A: 1'1 + Constant input on bit 1205 of port A: 1'1 + Constant input on bit 1206 of port A: 1'1 + Constant input on bit 1207 of port A: 1'1 + Constant input on bit 1208 of port A: 1'1 + Constant input on bit 1209 of port A: 1'1 + Constant input on bit 1210 of port A: 1'1 + Constant input on bit 1211 of port A: 1'1 + Constant input on bit 1212 of port A: 1'1 + Constant input on bit 1213 of port A: 1'1 + Constant input on bit 1214 of port A: 1'1 + Constant input on bit 1215 of port A: 1'1 + Constant input on bit 1216 of port A: 1'1 + Constant input on bit 1217 of port A: 1'1 + Constant input on bit 1218 of port A: 1'1 + Constant input on bit 1219 of port A: 1'1 + Constant input on bit 1220 of port A: 1'1 + Constant input on bit 1221 of port A: 1'1 + Constant input on bit 1222 of port A: 1'1 + Constant input on bit 1223 of port A: 1'1 + Constant input on bit 1224 of port A: 1'1 + Constant input on bit 1225 of port A: 1'1 + Constant input on bit 1226 of port A: 1'1 + Constant input on bit 1227 of port A: 1'1 + Constant input on bit 1228 of port A: 1'1 + Constant input on bit 1229 of port A: 1'1 + Constant input on bit 1230 of port A: 1'1 + Constant input on bit 1231 of port A: 1'1 + Constant input on bit 1232 of port A: 1'1 + Constant input on bit 1233 of port A: 1'1 + Constant input on bit 1234 of port A: 1'1 + Constant input on bit 1235 of port A: 1'1 + Constant input on bit 1236 of port A: 1'1 + Constant input on bit 1237 of port A: 1'1 + Constant input on bit 1238 of port A: 1'1 + Constant input on bit 1239 of port A: 1'1 + Constant input on bit 1240 of port A: 1'1 + Constant input on bit 1241 of port A: 1'1 + Constant input on bit 1242 of port A: 1'1 + Constant input on bit 1243 of port A: 1'1 + Constant input on bit 1244 of port A: 1'1 + Constant input on bit 1245 of port A: 1'1 + Constant input on bit 1246 of port A: 1'1 + Constant input on bit 1247 of port A: 1'1 + Constant input on bit 1248 of port A: 1'1 + Constant input on bit 1249 of port A: 1'1 + Constant input on bit 1250 of port A: 1'1 + Constant input on bit 1251 of port A: 1'1 + Constant input on bit 1252 of port A: 1'1 + Constant input on bit 1253 of port A: 1'1 + Constant input on bit 1254 of port A: 1'1 + Constant input on bit 1255 of port A: 1'1 + Constant input on bit 1256 of port A: 1'1 + Constant input on bit 1257 of port A: 1'1 + Constant input on bit 1258 of port A: 1'1 + Constant input on bit 1259 of port A: 1'1 + Constant input on bit 1260 of port A: 1'1 + Constant input on bit 1261 of port A: 1'1 + Constant input on bit 1262 of port A: 1'1 + Constant input on bit 1263 of port A: 1'1 + Constant input on bit 1264 of port A: 1'1 + Constant input on bit 1265 of port A: 1'1 + Constant input on bit 1266 of port A: 1'1 + Constant input on bit 1267 of port A: 1'1 + Constant input on bit 1268 of port A: 1'1 + Constant input on bit 1269 of port A: 1'1 + Constant input on bit 1270 of port A: 1'1 + Constant input on bit 1271 of port A: 1'1 + Constant input on bit 1272 of port A: 1'1 + Constant input on bit 1273 of port A: 1'1 + Constant input on bit 1274 of port A: 1'1 + Constant input on bit 1275 of port A: 1'1 + Constant input on bit 1276 of port A: 1'1 + Constant input on bit 1277 of port A: 1'1 + Constant input on bit 1278 of port A: 1'1 + Constant input on bit 1279 of port A: 1'1 + Constant input on bit 1280 of port A: 1'1 + Constant input on bit 1281 of port A: 1'1 + Constant input on bit 1282 of port A: 1'1 + Constant input on bit 1283 of port A: 1'1 + Constant input on bit 1284 of port A: 1'1 + Constant input on bit 1285 of port A: 1'1 + Constant input on bit 1286 of port A: 1'1 + Constant input on bit 1287 of port A: 1'1 + Constant input on bit 1288 of port A: 1'1 + Constant input on bit 1289 of port A: 1'1 + Constant input on bit 1290 of port A: 1'1 + Constant input on bit 1291 of port A: 1'1 + Constant input on bit 1292 of port A: 1'1 + Constant input on bit 1293 of port A: 1'1 + Constant input on bit 1294 of port A: 1'1 + Constant input on bit 1295 of port A: 1'1 + Constant input on bit 1296 of port A: 1'1 + Constant input on bit 1297 of port A: 1'1 + Constant input on bit 1298 of port A: 1'1 + Constant input on bit 1299 of port A: 1'1 + Constant input on bit 1300 of port A: 1'1 + Constant input on bit 1301 of port A: 1'1 + Constant input on bit 1302 of port A: 1'1 + Constant input on bit 1303 of port A: 1'1 + Constant input on bit 1304 of port A: 1'1 + Constant input on bit 1305 of port A: 1'1 + Constant input on bit 1306 of port A: 1'1 + Constant input on bit 1307 of port A: 1'1 + Constant input on bit 1308 of port A: 1'1 + Constant input on bit 1309 of port A: 1'1 + Constant input on bit 1310 of port A: 1'1 + Constant input on bit 1311 of port A: 1'1 + Constant input on bit 1312 of port A: 1'1 + Constant input on bit 1313 of port A: 1'1 + Constant input on bit 1314 of port A: 1'1 + Constant input on bit 1315 of port A: 1'1 + Constant input on bit 1316 of port A: 1'1 + Constant input on bit 1317 of port A: 1'1 + Constant input on bit 1318 of port A: 1'1 + Constant input on bit 1319 of port A: 1'1 + Constant input on bit 1320 of port A: 1'1 + Constant input on bit 1321 of port A: 1'1 + Constant input on bit 1322 of port A: 1'1 + Constant input on bit 1323 of port A: 1'1 + Constant input on bit 1324 of port A: 1'1 + Constant input on bit 1325 of port A: 1'1 + Constant input on bit 1326 of port A: 1'1 + Constant input on bit 1327 of port A: 1'1 + Constant input on bit 1328 of port A: 1'1 + Constant input on bit 1329 of port A: 1'1 + Constant input on bit 1330 of port A: 1'1 + Constant input on bit 1331 of port A: 1'1 + Constant input on bit 1332 of port A: 1'1 + Constant input on bit 1333 of port A: 1'1 + Constant input on bit 1334 of port A: 1'1 + Constant input on bit 1335 of port A: 1'1 + Constant input on bit 1336 of port A: 1'1 + Constant input on bit 1337 of port A: 1'1 + Constant input on bit 1338 of port A: 1'1 + Constant input on bit 1339 of port A: 1'1 + Constant input on bit 1340 of port A: 1'1 + Constant input on bit 1341 of port A: 1'1 + Constant input on bit 1342 of port A: 1'1 + Constant input on bit 1343 of port A: 1'1 + Constant input on bit 1344 of port A: 1'1 + Constant input on bit 1345 of port A: 1'1 + Constant input on bit 1346 of port A: 1'1 + Constant input on bit 1347 of port A: 1'1 + Constant input on bit 1348 of port A: 1'1 + Constant input on bit 1349 of port A: 1'1 + Constant input on bit 1350 of port A: 1'1 + Constant input on bit 1351 of port A: 1'1 + Constant input on bit 1352 of port A: 1'1 + Constant input on bit 1353 of port A: 1'1 + Constant input on bit 1354 of port A: 1'1 + Constant input on bit 1355 of port A: 1'1 + Constant input on bit 1356 of port A: 1'1 + Constant input on bit 1357 of port A: 1'1 + Constant input on bit 1358 of port A: 1'1 + Constant input on bit 1359 of port A: 1'1 + Constant input on bit 1360 of port A: 1'1 + Constant input on bit 1361 of port A: 1'1 + Constant input on bit 1362 of port A: 1'1 + Constant input on bit 1363 of port A: 1'1 + Constant input on bit 1364 of port A: 1'1 + Constant input on bit 1365 of port A: 1'1 + Constant input on bit 1366 of port A: 1'1 + Constant input on bit 1367 of port A: 1'1 + Constant input on bit 1368 of port A: 1'1 + Constant input on bit 1369 of port A: 1'1 + Constant input on bit 1370 of port A: 1'1 + Constant input on bit 1371 of port A: 1'1 + Constant input on bit 1372 of port A: 1'1 + Constant input on bit 1373 of port A: 1'1 + Constant input on bit 1374 of port A: 1'1 + Constant input on bit 1375 of port A: 1'1 + Constant input on bit 1376 of port A: 1'1 + Constant input on bit 1377 of port A: 1'1 + Constant input on bit 1378 of port A: 1'1 + Constant input on bit 1379 of port A: 1'1 + Constant input on bit 1380 of port A: 1'1 + Constant input on bit 1381 of port A: 1'1 + Constant input on bit 1382 of port A: 1'1 + Constant input on bit 1383 of port A: 1'1 + Constant input on bit 1384 of port A: 1'1 + Constant input on bit 1385 of port A: 1'1 + Constant input on bit 1386 of port A: 1'1 + Constant input on bit 1387 of port A: 1'1 + Constant input on bit 1388 of port A: 1'1 + Constant input on bit 1389 of port A: 1'1 + Constant input on bit 1390 of port A: 1'1 + Constant input on bit 1391 of port A: 1'1 + Constant input on bit 1392 of port A: 1'1 + Constant input on bit 1393 of port A: 1'1 + Constant input on bit 1394 of port A: 1'1 + Constant input on bit 1395 of port A: 1'1 + Constant input on bit 1396 of port A: 1'1 + Constant input on bit 1397 of port A: 1'1 + Constant input on bit 1398 of port A: 1'1 + Constant input on bit 1399 of port A: 1'1 + Constant input on bit 1400 of port A: 1'1 + Constant input on bit 1401 of port A: 1'1 + Constant input on bit 1402 of port A: 1'1 + Constant input on bit 1403 of port A: 1'1 + Constant input on bit 1404 of port A: 1'1 + Constant input on bit 1405 of port A: 1'1 + Constant input on bit 1406 of port A: 1'1 + Constant input on bit 1407 of port A: 1'1 + Constant input on bit 1408 of port A: 1'1 + Constant input on bit 1409 of port A: 1'1 + Constant input on bit 1410 of port A: 1'1 + Constant input on bit 1411 of port A: 1'1 + Constant input on bit 1412 of port A: 1'1 + Constant input on bit 1413 of port A: 1'1 + Constant input on bit 1414 of port A: 1'1 + Constant input on bit 1415 of port A: 1'1 + Constant input on bit 1416 of port A: 1'1 + Constant input on bit 1417 of port A: 1'1 + Constant input on bit 1418 of port A: 1'1 + Constant input on bit 1419 of port A: 1'1 + Constant input on bit 1420 of port A: 1'1 + Constant input on bit 1421 of port A: 1'1 + Constant input on bit 1422 of port A: 1'1 + Constant input on bit 1423 of port A: 1'1 + Constant input on bit 1424 of port A: 1'1 + Constant input on bit 1425 of port A: 1'1 + Constant input on bit 1426 of port A: 1'1 + Constant input on bit 1427 of port A: 1'1 + Constant input on bit 1428 of port A: 1'1 + Constant input on bit 1429 of port A: 1'1 + Constant input on bit 1430 of port A: 1'1 + Constant input on bit 1431 of port A: 1'1 + Constant input on bit 1432 of port A: 1'1 + Constant input on bit 1433 of port A: 1'1 + Constant input on bit 1434 of port A: 1'1 + Constant input on bit 1435 of port A: 1'1 + Constant input on bit 1436 of port A: 1'1 + Constant input on bit 1437 of port A: 1'1 + Constant input on bit 1438 of port A: 1'1 + Constant input on bit 1439 of port A: 1'1 + Constant input on bit 1440 of port A: 1'1 + Constant input on bit 1441 of port A: 1'1 + Constant input on bit 1442 of port A: 1'1 + Constant input on bit 1443 of port A: 1'1 + Constant input on bit 1444 of port A: 1'1 + Constant input on bit 1445 of port A: 1'1 + Constant input on bit 1446 of port A: 1'1 + Constant input on bit 1447 of port A: 1'1 + Constant input on bit 1448 of port A: 1'1 + Constant input on bit 1449 of port A: 1'1 + Constant input on bit 1450 of port A: 1'1 + Constant input on bit 1451 of port A: 1'1 + Constant input on bit 1452 of port A: 1'1 + Constant input on bit 1453 of port A: 1'1 + Constant input on bit 1454 of port A: 1'1 + Constant input on bit 1455 of port A: 1'1 + Constant input on bit 1456 of port A: 1'1 + Constant input on bit 1457 of port A: 1'1 + Constant input on bit 1458 of port A: 1'1 + Constant input on bit 1459 of port A: 1'1 + Constant input on bit 1460 of port A: 1'1 + Constant input on bit 1461 of port A: 1'1 + Constant input on bit 1462 of port A: 1'1 + Constant input on bit 1463 of port A: 1'1 + Constant input on bit 1464 of port A: 1'1 + Constant input on bit 1465 of port A: 1'1 + Constant input on bit 1466 of port A: 1'1 + Constant input on bit 1467 of port A: 1'1 + Constant input on bit 1468 of port A: 1'1 + Constant input on bit 1469 of port A: 1'1 + Constant input on bit 1470 of port A: 1'1 + Constant input on bit 1471 of port A: 1'1 + Constant input on bit 1472 of port A: 1'1 + Constant input on bit 1473 of port A: 1'1 + Constant input on bit 1474 of port A: 1'1 + Constant input on bit 1475 of port A: 1'1 + Constant input on bit 1476 of port A: 1'1 + Constant input on bit 1477 of port A: 1'1 + Constant input on bit 1478 of port A: 1'1 + Constant input on bit 1479 of port A: 1'1 + Constant input on bit 1480 of port A: 1'1 + Constant input on bit 1481 of port A: 1'1 + Constant input on bit 1482 of port A: 1'1 + Constant input on bit 1483 of port A: 1'1 + Constant input on bit 1484 of port A: 1'1 + Constant input on bit 1485 of port A: 1'1 + Constant input on bit 1486 of port A: 1'1 + Constant input on bit 1487 of port A: 1'1 + Constant input on bit 1488 of port A: 1'1 + Constant input on bit 1489 of port A: 1'1 + Constant input on bit 1490 of port A: 1'1 + Constant input on bit 1491 of port A: 1'1 + Constant input on bit 1492 of port A: 1'1 + Constant input on bit 1493 of port A: 1'1 + Constant input on bit 1494 of port A: 1'1 + Constant input on bit 1495 of port A: 1'1 + Constant input on bit 1496 of port A: 1'1 + Constant input on bit 1497 of port A: 1'1 + Constant input on bit 1498 of port A: 1'1 + Constant input on bit 1499 of port A: 1'1 + Constant input on bit 1500 of port A: 1'1 + Constant input on bit 1501 of port A: 1'1 + Constant input on bit 1502 of port A: 1'1 + Constant input on bit 1503 of port A: 1'1 + Constant input on bit 1504 of port A: 1'1 + Constant input on bit 1505 of port A: 1'1 + Constant input on bit 1506 of port A: 1'1 + Constant input on bit 1507 of port A: 1'1 + Constant input on bit 1508 of port A: 1'1 + Constant input on bit 1509 of port A: 1'1 + Constant input on bit 1510 of port A: 1'1 + Constant input on bit 1511 of port A: 1'1 + Constant input on bit 1512 of port A: 1'1 + Constant input on bit 1513 of port A: 1'1 + Constant input on bit 1514 of port A: 1'1 + Constant input on bit 1515 of port A: 1'1 + Constant input on bit 1516 of port A: 1'1 + Constant input on bit 1517 of port A: 1'1 + Constant input on bit 1518 of port A: 1'1 + Constant input on bit 1519 of port A: 1'1 + Constant input on bit 1520 of port A: 1'1 + Constant input on bit 1521 of port A: 1'1 + Constant input on bit 1522 of port A: 1'1 + Constant input on bit 1523 of port A: 1'1 + Constant input on bit 1524 of port A: 1'1 + Constant input on bit 1525 of port A: 1'1 + Constant input on bit 1526 of port A: 1'1 + Constant input on bit 1527 of port A: 1'1 + Constant input on bit 1528 of port A: 1'1 + Constant input on bit 1529 of port A: 1'1 + Constant input on bit 1530 of port A: 1'1 + Constant input on bit 1531 of port A: 1'1 + Constant input on bit 1532 of port A: 1'1 + Constant input on bit 1533 of port A: 1'1 + Constant input on bit 1534 of port A: 1'1 + Constant input on bit 1535 of port A: 1'1 + Constant input on bit 1536 of port A: 1'1 + Constant input on bit 1537 of port A: 1'1 + Constant input on bit 1538 of port A: 1'1 + Constant input on bit 1539 of port A: 1'1 + Constant input on bit 1540 of port A: 1'1 + Constant input on bit 1541 of port A: 1'1 + Constant input on bit 1542 of port A: 1'1 + Constant input on bit 1543 of port A: 1'1 + Constant input on bit 1544 of port A: 1'1 + Constant input on bit 1545 of port A: 1'1 + Constant input on bit 1546 of port A: 1'1 + Constant input on bit 1547 of port A: 1'1 + Constant input on bit 1548 of port A: 1'1 + Constant input on bit 1549 of port A: 1'1 + Constant input on bit 1550 of port A: 1'1 + Constant input on bit 1551 of port A: 1'1 + Constant input on bit 1552 of port A: 1'1 + Constant input on bit 1553 of port A: 1'1 + Constant input on bit 1554 of port A: 1'1 + Constant input on bit 1555 of port A: 1'1 + Constant input on bit 1556 of port A: 1'1 + Constant input on bit 1557 of port A: 1'1 + Constant input on bit 1558 of port A: 1'1 + Constant input on bit 1559 of port A: 1'1 + Constant input on bit 1560 of port A: 1'1 + Constant input on bit 1561 of port A: 1'1 + Constant input on bit 1562 of port A: 1'1 + Constant input on bit 1563 of port A: 1'1 + Constant input on bit 1564 of port A: 1'1 + Constant input on bit 1565 of port A: 1'1 + Constant input on bit 1566 of port A: 1'1 + Constant input on bit 1567 of port A: 1'1 + Constant input on bit 1568 of port A: 1'1 + Constant input on bit 1569 of port A: 1'1 + Constant input on bit 1570 of port A: 1'1 + Constant input on bit 1571 of port A: 1'1 + Constant input on bit 1572 of port A: 1'1 + Constant input on bit 1573 of port A: 1'1 + Constant input on bit 1574 of port A: 1'1 + Constant input on bit 1575 of port A: 1'1 + Constant input on bit 1576 of port A: 1'1 + Constant input on bit 1577 of port A: 1'1 + Constant input on bit 1578 of port A: 1'1 + Constant input on bit 1579 of port A: 1'1 + Constant input on bit 1580 of port A: 1'1 + Constant input on bit 1581 of port A: 1'1 + Constant input on bit 1582 of port A: 1'1 + Constant input on bit 1583 of port A: 1'1 + Constant input on bit 1584 of port A: 1'1 + Constant input on bit 1585 of port A: 1'1 + Constant input on bit 1586 of port A: 1'1 + Constant input on bit 1587 of port A: 1'1 + Constant input on bit 1588 of port A: 1'1 + Constant input on bit 1589 of port A: 1'1 + Constant input on bit 1590 of port A: 1'1 + Constant input on bit 1591 of port A: 1'1 + Constant input on bit 1592 of port A: 1'1 + Constant input on bit 1593 of port A: 1'1 + Constant input on bit 1594 of port A: 1'1 + Constant input on bit 1595 of port A: 1'1 + Constant input on bit 1596 of port A: 1'1 + Constant input on bit 1597 of port A: 1'1 + Constant input on bit 1598 of port A: 1'1 + Constant input on bit 1599 of port A: 1'1 + Constant input on bit 1600 of port A: 1'1 + Constant input on bit 1601 of port A: 1'1 + Constant input on bit 1602 of port A: 1'1 + Constant input on bit 1603 of port A: 1'1 + Constant input on bit 1604 of port A: 1'1 + Constant input on bit 1605 of port A: 1'1 + Constant input on bit 1606 of port A: 1'1 + Constant input on bit 1607 of port A: 1'1 + Constant input on bit 1608 of port A: 1'1 + Constant input on bit 1609 of port A: 1'1 + Constant input on bit 1610 of port A: 1'1 + Constant input on bit 1611 of port A: 1'1 + Constant input on bit 1612 of port A: 1'1 + Constant input on bit 1613 of port A: 1'1 + Constant input on bit 1614 of port A: 1'1 + Constant input on bit 1615 of port A: 1'1 + Constant input on bit 1616 of port A: 1'1 + Constant input on bit 1617 of port A: 1'1 + Constant input on bit 1618 of port A: 1'1 + Constant input on bit 1619 of port A: 1'1 + Constant input on bit 1620 of port A: 1'1 + Constant input on bit 1621 of port A: 1'1 + Constant input on bit 1622 of port A: 1'1 + Constant input on bit 1623 of port A: 1'1 + Constant input on bit 1624 of port A: 1'1 + Constant input on bit 1625 of port A: 1'1 + Constant input on bit 1626 of port A: 1'1 + Constant input on bit 1627 of port A: 1'1 + Constant input on bit 1628 of port A: 1'1 + Constant input on bit 1629 of port A: 1'1 + Constant input on bit 1630 of port A: 1'1 + Constant input on bit 1631 of port A: 1'1 + Constant input on bit 1632 of port A: 1'1 + Constant input on bit 1633 of port A: 1'1 + Constant input on bit 1634 of port A: 1'1 + Constant input on bit 1635 of port A: 1'1 + Constant input on bit 1636 of port A: 1'1 + Constant input on bit 1637 of port A: 1'1 + Constant input on bit 1638 of port A: 1'1 + Constant input on bit 1639 of port A: 1'1 + Constant input on bit 1640 of port A: 1'1 + Constant input on bit 1641 of port A: 1'1 + Constant input on bit 1642 of port A: 1'1 + Constant input on bit 1643 of port A: 1'1 + Constant input on bit 1644 of port A: 1'1 + Constant input on bit 1645 of port A: 1'1 + Constant input on bit 1646 of port A: 1'1 + Constant input on bit 1647 of port A: 1'1 + Constant input on bit 1648 of port A: 1'1 + Constant input on bit 1649 of port A: 1'1 + Constant input on bit 1650 of port A: 1'1 + Constant input on bit 1651 of port A: 1'1 + Constant input on bit 1652 of port A: 1'1 + Constant input on bit 1653 of port A: 1'1 + Constant input on bit 1654 of port A: 1'1 + Constant input on bit 1655 of port A: 1'1 + Constant input on bit 1656 of port A: 1'1 + Constant input on bit 1657 of port A: 1'1 + Constant input on bit 1658 of port A: 1'1 + Constant input on bit 1659 of port A: 1'1 + Constant input on bit 1660 of port A: 1'1 + Constant input on bit 1661 of port A: 1'1 + Constant input on bit 1662 of port A: 1'1 + Constant input on bit 1663 of port A: 1'1 + Constant input on bit 1664 of port A: 1'1 + Constant input on bit 1665 of port A: 1'1 + Constant input on bit 1666 of port A: 1'1 + Constant input on bit 1667 of port A: 1'1 + Constant input on bit 1668 of port A: 1'1 + Constant input on bit 1669 of port A: 1'1 + Constant input on bit 1670 of port A: 1'1 + Constant input on bit 1671 of port A: 1'1 + Constant input on bit 1672 of port A: 1'1 + Constant input on bit 1673 of port A: 1'1 + Constant input on bit 1674 of port A: 1'1 + Constant input on bit 1675 of port A: 1'1 + Constant input on bit 1676 of port A: 1'1 + Constant input on bit 1677 of port A: 1'1 + Constant input on bit 1678 of port A: 1'1 + Constant input on bit 1679 of port A: 1'1 + Constant input on bit 1680 of port A: 1'1 + Constant input on bit 1681 of port A: 1'1 + Constant input on bit 1682 of port A: 1'1 + Constant input on bit 1683 of port A: 1'1 + Constant input on bit 1684 of port A: 1'1 + Constant input on bit 1685 of port A: 1'1 + Constant input on bit 1686 of port A: 1'1 + Constant input on bit 1687 of port A: 1'1 + Constant input on bit 1688 of port A: 1'1 + Constant input on bit 1689 of port A: 1'1 + Constant input on bit 1690 of port A: 1'1 + Constant input on bit 1691 of port A: 1'1 + Constant input on bit 1692 of port A: 1'1 + Constant input on bit 1693 of port A: 1'1 + Constant input on bit 1694 of port A: 1'1 + Constant input on bit 1695 of port A: 1'1 + Constant input on bit 1696 of port A: 1'1 + Constant input on bit 1697 of port A: 1'1 + Constant input on bit 1698 of port A: 1'1 + Constant input on bit 1699 of port A: 1'1 + Constant input on bit 1700 of port A: 1'1 + Constant input on bit 1701 of port A: 1'1 + Constant input on bit 1702 of port A: 1'1 + Constant input on bit 1703 of port A: 1'1 + Constant input on bit 1704 of port A: 1'1 + Constant input on bit 1705 of port A: 1'1 + Constant input on bit 1706 of port A: 1'1 + Constant input on bit 1707 of port A: 1'1 + Constant input on bit 1708 of port A: 1'1 + Constant input on bit 1709 of port A: 1'1 + Constant input on bit 1710 of port A: 1'1 + Constant input on bit 1711 of port A: 1'1 + Constant input on bit 1712 of port A: 1'1 + Constant input on bit 1713 of port A: 1'1 + Constant input on bit 1714 of port A: 1'1 + Constant input on bit 1715 of port A: 1'1 + Constant input on bit 1716 of port A: 1'1 + Constant input on bit 1717 of port A: 1'1 + Constant input on bit 1718 of port A: 1'1 + Constant input on bit 1719 of port A: 1'1 + Constant input on bit 1720 of port A: 1'1 + Constant input on bit 1721 of port A: 1'1 + Constant input on bit 1722 of port A: 1'1 + Constant input on bit 1723 of port A: 1'1 + Constant input on bit 1724 of port A: 1'1 + Constant input on bit 1725 of port A: 1'1 + Constant input on bit 1726 of port A: 1'1 + Constant input on bit 1727 of port A: 1'1 + Constant input on bit 1728 of port A: 1'1 + Constant input on bit 1729 of port A: 1'1 + Constant input on bit 1730 of port A: 1'1 + Constant input on bit 1731 of port A: 1'1 + Constant input on bit 1732 of port A: 1'1 + Constant input on bit 1733 of port A: 1'1 + Constant input on bit 1734 of port A: 1'1 + Constant input on bit 1735 of port A: 1'1 + Constant input on bit 1736 of port A: 1'1 + Constant input on bit 1737 of port A: 1'1 + Constant input on bit 1738 of port A: 1'1 + Constant input on bit 1739 of port A: 1'1 + Constant input on bit 1740 of port A: 1'1 + Constant input on bit 1741 of port A: 1'1 + Constant input on bit 1742 of port A: 1'1 + Constant input on bit 1743 of port A: 1'1 + Constant input on bit 1744 of port A: 1'1 + Constant input on bit 1745 of port A: 1'1 + Constant input on bit 1746 of port A: 1'1 + Constant input on bit 1747 of port A: 1'1 + Constant input on bit 1748 of port A: 1'1 + Constant input on bit 1749 of port A: 1'1 + Constant input on bit 1750 of port A: 1'1 + Constant input on bit 1751 of port A: 1'1 + Constant input on bit 1752 of port A: 1'1 + Constant input on bit 1753 of port A: 1'1 + Constant input on bit 1754 of port A: 1'1 + Constant input on bit 1755 of port A: 1'1 + Constant input on bit 1756 of port A: 1'1 + Constant input on bit 1757 of port A: 1'1 + Constant input on bit 1758 of port A: 1'1 + Constant input on bit 1759 of port A: 1'1 + Constant input on bit 1760 of port A: 1'1 + Constant input on bit 1761 of port A: 1'1 + Constant input on bit 1762 of port A: 1'1 + Constant input on bit 1763 of port A: 1'1 + Constant input on bit 1764 of port A: 1'1 + Constant input on bit 1765 of port A: 1'1 + Constant input on bit 1766 of port A: 1'1 + Constant input on bit 1767 of port A: 1'1 + Constant input on bit 1768 of port A: 1'1 + Constant input on bit 1769 of port A: 1'1 + Constant input on bit 1770 of port A: 1'1 + Constant input on bit 1771 of port A: 1'1 + Constant input on bit 1772 of port A: 1'1 + Constant input on bit 1773 of port A: 1'1 + Constant input on bit 1774 of port A: 1'1 + Constant input on bit 1775 of port A: 1'1 + Constant input on bit 1776 of port A: 1'1 + Constant input on bit 1777 of port A: 1'1 + Constant input on bit 1778 of port A: 1'1 + Constant input on bit 1779 of port A: 1'1 + Constant input on bit 1780 of port A: 1'1 + Constant input on bit 1781 of port A: 1'1 + Constant input on bit 1782 of port A: 1'1 + Constant input on bit 1783 of port A: 1'1 + Constant input on bit 1784 of port A: 1'1 + Constant input on bit 1785 of port A: 1'1 + Constant input on bit 1786 of port A: 1'1 + Constant input on bit 1787 of port A: 1'1 + Constant input on bit 1788 of port A: 1'1 + Constant input on bit 1789 of port A: 1'1 + Constant input on bit 1790 of port A: 1'1 + Constant input on bit 1791 of port A: 1'1 + Constant input on bit 1792 of port A: 1'1 + Constant input on bit 1793 of port A: 1'1 + Constant input on bit 1794 of port A: 1'1 + Constant input on bit 1795 of port A: 1'1 + Constant input on bit 1796 of port A: 1'1 + Constant input on bit 1797 of port A: 1'1 + Constant input on bit 1798 of port A: 1'1 + Constant input on bit 1799 of port A: 1'1 + Constant input on bit 1800 of port A: 1'1 + Constant input on bit 1801 of port A: 1'1 + Constant input on bit 1802 of port A: 1'1 + Constant input on bit 1803 of port A: 1'1 + Constant input on bit 1804 of port A: 1'1 + Constant input on bit 1805 of port A: 1'1 + Constant input on bit 1806 of port A: 1'1 + Constant input on bit 1807 of port A: 1'1 + Constant input on bit 1808 of port A: 1'1 + Constant input on bit 1809 of port A: 1'1 + Constant input on bit 1810 of port A: 1'1 + Constant input on bit 1811 of port A: 1'1 + Constant input on bit 1812 of port A: 1'1 + Constant input on bit 1813 of port A: 1'1 + Constant input on bit 1814 of port A: 1'1 + Constant input on bit 1815 of port A: 1'1 + Constant input on bit 1816 of port A: 1'1 + Constant input on bit 1817 of port A: 1'1 + Constant input on bit 1818 of port A: 1'1 + Constant input on bit 1819 of port A: 1'1 + Constant input on bit 1820 of port A: 1'1 + Constant input on bit 1821 of port A: 1'1 + Constant input on bit 1822 of port A: 1'1 + Constant input on bit 1823 of port A: 1'1 + Constant input on bit 1824 of port A: 1'1 + Constant input on bit 1825 of port A: 1'1 + Constant input on bit 1826 of port A: 1'1 + Constant input on bit 1827 of port A: 1'1 + Constant input on bit 1828 of port A: 1'1 + Constant input on bit 1829 of port A: 1'1 + Constant input on bit 1830 of port A: 1'1 + Constant input on bit 1831 of port A: 1'1 + Constant input on bit 1832 of port A: 1'1 + Constant input on bit 1833 of port A: 1'1 + Constant input on bit 1834 of port A: 1'1 + Constant input on bit 1835 of port A: 1'1 + Constant input on bit 1836 of port A: 1'1 + Constant input on bit 1837 of port A: 1'1 + Constant input on bit 1838 of port A: 1'1 + Constant input on bit 1839 of port A: 1'1 + Constant input on bit 1840 of port A: 1'1 + Constant input on bit 1841 of port A: 1'1 + Constant input on bit 1842 of port A: 1'1 + Constant input on bit 1843 of port A: 1'1 + Constant input on bit 1844 of port A: 1'1 + Constant input on bit 1845 of port A: 1'1 + Constant input on bit 1846 of port A: 1'1 + Constant input on bit 1847 of port A: 1'1 + Constant input on bit 1848 of port A: 1'1 + Constant input on bit 1849 of port A: 1'1 + Constant input on bit 1850 of port A: 1'1 + Constant input on bit 1851 of port A: 1'1 + Constant input on bit 1852 of port A: 1'1 + Constant input on bit 1853 of port A: 1'1 + Constant input on bit 1854 of port A: 1'1 + Constant input on bit 1855 of port A: 1'1 + Constant input on bit 1856 of port A: 1'1 + Constant input on bit 1857 of port A: 1'1 + Constant input on bit 1858 of port A: 1'1 + Constant input on bit 1859 of port A: 1'1 + Constant input on bit 1860 of port A: 1'1 + Constant input on bit 1861 of port A: 1'1 + Constant input on bit 1862 of port A: 1'1 + Constant input on bit 1863 of port A: 1'1 + Constant input on bit 1864 of port A: 1'1 + Constant input on bit 1865 of port A: 1'1 + Constant input on bit 1866 of port A: 1'1 + Constant input on bit 1867 of port A: 1'1 + Constant input on bit 1868 of port A: 1'1 + Constant input on bit 1869 of port A: 1'1 + Constant input on bit 1870 of port A: 1'1 + Constant input on bit 1871 of port A: 1'1 + Constant input on bit 1872 of port A: 1'1 + Constant input on bit 1873 of port A: 1'1 + Constant input on bit 1874 of port A: 1'1 + Constant input on bit 1875 of port A: 1'1 + Constant input on bit 1876 of port A: 1'1 + Constant input on bit 1877 of port A: 1'1 + Constant input on bit 1878 of port A: 1'1 + Constant input on bit 1879 of port A: 1'1 + Constant input on bit 1880 of port A: 1'1 + Constant input on bit 1881 of port A: 1'1 + Constant input on bit 1882 of port A: 1'1 + Constant input on bit 1883 of port A: 1'1 + Constant input on bit 1884 of port A: 1'1 + Constant input on bit 1885 of port A: 1'1 + Constant input on bit 1886 of port A: 1'1 + Constant input on bit 1887 of port A: 1'1 + Constant input on bit 1888 of port A: 1'1 + Constant input on bit 1889 of port A: 1'1 + Constant input on bit 1890 of port A: 1'1 + Constant input on bit 1891 of port A: 1'1 + Constant input on bit 1892 of port A: 1'1 + Constant input on bit 1893 of port A: 1'1 + Constant input on bit 1894 of port A: 1'1 + Constant input on bit 1895 of port A: 1'1 + Constant input on bit 1896 of port A: 1'1 + Constant input on bit 1897 of port A: 1'1 + Constant input on bit 1898 of port A: 1'1 + Constant input on bit 1899 of port A: 1'1 + Constant input on bit 1900 of port A: 1'1 + Constant input on bit 1901 of port A: 1'1 + Constant input on bit 1902 of port A: 1'1 + Constant input on bit 1903 of port A: 1'1 + Constant input on bit 1904 of port A: 1'1 + Constant input on bit 1905 of port A: 1'1 + Constant input on bit 1906 of port A: 1'1 + Constant input on bit 1907 of port A: 1'1 + Constant input on bit 1908 of port A: 1'1 + Constant input on bit 1909 of port A: 1'1 + Constant input on bit 1910 of port A: 1'1 + Constant input on bit 1911 of port A: 1'1 + Constant input on bit 1912 of port A: 1'1 + Constant input on bit 1913 of port A: 1'1 + Constant input on bit 1914 of port A: 1'1 + Constant input on bit 1915 of port A: 1'1 + Constant input on bit 1916 of port A: 1'1 + Constant input on bit 1917 of port A: 1'1 + Constant input on bit 1918 of port A: 1'1 + Constant input on bit 1919 of port A: 1'1 + Constant input on bit 1920 of port A: 1'1 + Constant input on bit 1921 of port A: 1'1 + Constant input on bit 1922 of port A: 1'1 + Constant input on bit 1923 of port A: 1'1 + Constant input on bit 1924 of port A: 1'1 + Constant input on bit 1925 of port A: 1'1 + Constant input on bit 1926 of port A: 1'1 + Constant input on bit 1927 of port A: 1'1 + Constant input on bit 1928 of port A: 1'1 + Constant input on bit 1929 of port A: 1'1 + Constant input on bit 1930 of port A: 1'1 + Constant input on bit 1931 of port A: 1'1 + Constant input on bit 1932 of port A: 1'1 + Constant input on bit 1933 of port A: 1'1 + Constant input on bit 1934 of port A: 1'1 + Constant input on bit 1935 of port A: 1'1 + Constant input on bit 1936 of port A: 1'1 + Constant input on bit 1937 of port A: 1'1 + Constant input on bit 1938 of port A: 1'1 + Constant input on bit 1939 of port A: 1'1 + Constant input on bit 1940 of port A: 1'1 + Constant input on bit 1941 of port A: 1'1 + Constant input on bit 1942 of port A: 1'1 + Constant input on bit 1943 of port A: 1'1 + Constant input on bit 1944 of port A: 1'1 + Constant input on bit 1945 of port A: 1'1 + Constant input on bit 1946 of port A: 1'1 + Constant input on bit 1947 of port A: 1'1 + Constant input on bit 1948 of port A: 1'1 + Constant input on bit 1949 of port A: 1'1 + Constant input on bit 1950 of port A: 1'1 + Constant input on bit 1951 of port A: 1'1 + Constant input on bit 1952 of port A: 1'1 + Constant input on bit 1953 of port A: 1'1 + Constant input on bit 1954 of port A: 1'1 + Constant input on bit 1955 of port A: 1'1 + Constant input on bit 1956 of port A: 1'1 + Constant input on bit 1957 of port A: 1'1 + Constant input on bit 1958 of port A: 1'1 + Constant input on bit 1959 of port A: 1'1 + Constant input on bit 1960 of port A: 1'1 + Constant input on bit 1961 of port A: 1'1 + Constant input on bit 1962 of port A: 1'1 + Constant input on bit 1963 of port A: 1'1 + Constant input on bit 1964 of port A: 1'1 + Constant input on bit 1965 of port A: 1'1 + Constant input on bit 1966 of port A: 1'1 + Constant input on bit 1967 of port A: 1'1 + Constant input on bit 1968 of port A: 1'1 + Constant input on bit 1969 of port A: 1'1 + Constant input on bit 1970 of port A: 1'1 + Constant input on bit 1971 of port A: 1'1 + Constant input on bit 1972 of port A: 1'1 + Constant input on bit 1973 of port A: 1'1 + Constant input on bit 1974 of port A: 1'1 + Constant input on bit 1975 of port A: 1'1 + Constant input on bit 1976 of port A: 1'1 + Constant input on bit 1977 of port A: 1'1 + Constant input on bit 1978 of port A: 1'1 + Constant input on bit 1979 of port A: 1'1 + Constant input on bit 1980 of port A: 1'1 + Constant input on bit 1981 of port A: 1'1 + Constant input on bit 1982 of port A: 1'1 + Constant input on bit 1983 of port A: 1'1 + Constant input on bit 1984 of port A: 1'1 + Constant input on bit 1985 of port A: 1'1 + Constant input on bit 1986 of port A: 1'1 + Constant input on bit 1987 of port A: 1'1 + Constant input on bit 1988 of port A: 1'1 + Constant input on bit 1989 of port A: 1'1 + Constant input on bit 1990 of port A: 1'1 + Constant input on bit 1991 of port A: 1'1 + Constant input on bit 1992 of port A: 1'1 + Constant input on bit 1993 of port A: 1'1 + Constant input on bit 1994 of port A: 1'1 + Constant input on bit 1995 of port A: 1'1 + Constant input on bit 1996 of port A: 1'1 + Constant input on bit 1997 of port A: 1'1 + Constant input on bit 1998 of port A: 1'1 + Constant input on bit 1999 of port A: 1'1 + Constant input on bit 2000 of port A: 1'1 + Constant input on bit 2001 of port A: 1'1 + Constant input on bit 2002 of port A: 1'1 + Constant input on bit 2003 of port A: 1'1 + Constant input on bit 2004 of port A: 1'1 + Constant input on bit 2005 of port A: 1'1 + Constant input on bit 2006 of port A: 1'1 + Constant input on bit 2007 of port A: 1'1 + Constant input on bit 2008 of port A: 1'1 + Constant input on bit 2009 of port A: 1'1 + Constant input on bit 2010 of port A: 1'1 + Constant input on bit 2011 of port A: 1'1 + Constant input on bit 2012 of port A: 1'1 + Constant input on bit 2013 of port A: 1'1 + Constant input on bit 2014 of port A: 1'1 + Constant input on bit 2015 of port A: 1'1 + Constant input on bit 2016 of port A: 1'1 + Constant input on bit 2017 of port A: 1'1 + Constant input on bit 2018 of port A: 1'1 + Constant input on bit 2019 of port A: 1'1 + Constant input on bit 2020 of port A: 1'1 + Constant input on bit 2021 of port A: 1'1 + Constant input on bit 2022 of port A: 1'1 + Constant input on bit 2023 of port A: 1'1 + Constant input on bit 2024 of port A: 1'1 + Constant input on bit 2025 of port A: 1'1 + Constant input on bit 2026 of port A: 1'1 + Constant input on bit 2027 of port A: 1'1 + Constant input on bit 2028 of port A: 1'1 + Constant input on bit 2029 of port A: 1'1 + Constant input on bit 2030 of port A: 1'1 + Constant input on bit 2031 of port A: 1'1 + Constant input on bit 2032 of port A: 1'1 + Constant input on bit 2033 of port A: 1'1 + Constant input on bit 2034 of port A: 1'1 + Constant input on bit 2035 of port A: 1'1 + Constant input on bit 2036 of port A: 1'1 + Constant input on bit 2037 of port A: 1'1 + Constant input on bit 2038 of port A: 1'1 + Constant input on bit 2039 of port A: 1'1 + Constant input on bit 2040 of port A: 1'1 + Constant input on bit 2041 of port A: 1'1 + Constant input on bit 2042 of port A: 1'1 + Constant input on bit 2043 of port A: 1'1 + Constant input on bit 2044 of port A: 1'1 + Constant input on bit 2045 of port A: 1'1 + Constant input on bit 2046 of port A: 1'1 + Constant input on bit 2047 of port A: 1'1 +Creating constmapped module `$paramod$constmap:3581dd07aa838894cc02f97fb98493f05b8aa029$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx'. + +12.20. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:3581dd07aa838894cc02f97fb98493f05b8aa029$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$817. + dead port 2/2 on $mux $procmux$817. + dead port 1/2 on $mux $procmux$820. + dead port 2/2 on $mux $procmux$823. + dead port 2/2 on $mux $procmux$829. + dead port 2/2 on $mux $procmux$835. + dead port 2/2 on $mux $procmux$841. + dead port 2/2 on $mux $procmux$847. + dead port 1/2 on $mux $procmux$853. + dead port 2/2 on $mux $procmux$853. + dead port 1/2 on $mux $procmux$856. + dead port 1/2 on $mux $procmux$859. + dead port 2/2 on $mux $procmux$859. + dead port 1/2 on $mux $procmux$862. + dead port 1/2 on $mux $procmux$865. + dead port 2/2 on $mux $procmux$865. + dead port 1/2 on $mux $procmux$868. + dead port 1/2 on $mux $procmux$871. + dead port 2/2 on $mux $procmux$871. + dead port 1/2 on $mux $procmux$874. + dead port 1/2 on $mux $procmux$877. + dead port 2/2 on $mux $procmux$877. + dead port 1/2 on $mux $procmux$880. + dead port 1/2 on $mux $procmux$883. + dead port 2/2 on $mux $procmux$883. + dead port 1/2 on $mux $procmux$886. +Removed 26 multiplexer ports. + + +12.21. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:3581dd07aa838894cc02f97fb98493f05b8aa029$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx. + +Removed 0 unused cells and 64 unused wires. +Using template $paramod$constmap:3581dd07aa838894cc02f97fb98493f05b8aa029$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx for cells of type $shiftx. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port B: 1'0 + Constant input on bit 1 of port B: 1'0 + Constant input on bit 2 of port B: 1'0 + Constant input on bit 3 of port B: 1'0 + Constant input on bit 4 of port B: 1'0 + Constant input on bit 5 of port B: 1'0 + Constant input on bit 11 of port B: 1'0 + Constant input on bit 12 of port B: 1'0 + Constant input on bit 13 of port B: 1'0 + Constant input on bit 14 of port B: 1'0 + Constant input on bit 15 of port B: 1'0 + Constant input on bit 16 of port B: 1'0 + Constant input on bit 17 of port B: 1'0 + Constant input on bit 18 of port B: 1'0 + Constant input on bit 19 of port B: 1'0 + Constant input on bit 20 of port B: 1'0 + Constant input on bit 21 of port B: 1'0 + Constant input on bit 22 of port B: 1'0 + Constant input on bit 23 of port B: 1'0 + Constant input on bit 24 of port B: 1'0 + Constant input on bit 25 of port B: 1'0 + Constant input on bit 26 of port B: 1'0 + Constant input on bit 27 of port B: 1'0 + Constant input on bit 28 of port B: 1'0 + Constant input on bit 29 of port B: 1'0 + Constant input on bit 30 of port B: 1'0 + Constant input on bit 31 of port B: 1'0 + Constant input on bit 0 of port A: 1'0 + Constant input on bit 1 of port A: 1'0 + Constant input on bit 2 of port A: 1'0 + Constant input on bit 3 of port A: 1'0 + Constant input on bit 4 of port A: 1'0 + Constant input on bit 5 of port A: 1'0 + Constant input on bit 6 of port A: 1'0 + Constant input on bit 7 of port A: 1'0 + Constant input on bit 8 of port A: 1'0 + Constant input on bit 9 of port A: 1'0 + Constant input on bit 10 of port A: 1'0 + Constant input on bit 11 of port A: 1'0 + Constant input on bit 12 of port A: 1'0 + Constant input on bit 13 of port A: 1'0 + Constant input on bit 14 of port A: 1'0 + Constant input on bit 15 of port A: 1'0 + Constant input on bit 16 of port A: 1'0 + Constant input on bit 17 of port A: 1'0 + Constant input on bit 18 of port A: 1'0 + Constant input on bit 19 of port A: 1'0 + Constant input on bit 20 of port A: 1'0 + Constant input on bit 21 of port A: 1'0 + Constant input on bit 22 of port A: 1'0 + Constant input on bit 23 of port A: 1'0 + Constant input on bit 24 of port A: 1'0 + Constant input on bit 25 of port A: 1'0 + Constant input on bit 26 of port A: 1'0 + Constant input on bit 27 of port A: 1'0 + Constant input on bit 28 of port A: 1'0 + Constant input on bit 29 of port A: 1'0 + Constant input on bit 30 of port A: 1'0 + Constant input on bit 31 of port A: 1'0 + Constant input on bit 32 of port A: 1'0 + Constant input on bit 33 of port A: 1'0 + Constant input on bit 34 of port A: 1'0 + Constant input on bit 35 of port A: 1'0 + Constant input on bit 36 of port A: 1'0 + Constant input on bit 37 of port A: 1'0 + Constant input on bit 38 of port A: 1'0 + Constant input on bit 39 of port A: 1'0 + Constant input on bit 40 of port A: 1'0 + Constant input on bit 41 of port A: 1'0 + Constant input on bit 42 of port A: 1'0 + Constant input on bit 43 of port A: 1'0 + Constant input on bit 44 of port A: 1'0 + Constant input on bit 45 of port A: 1'0 + Constant input on bit 46 of port A: 1'0 + Constant input on bit 47 of port A: 1'0 + Constant input on bit 48 of port A: 1'0 + Constant input on bit 49 of port A: 1'0 + Constant input on bit 50 of port A: 1'0 + Constant input on bit 51 of port A: 1'0 + Constant input on bit 52 of port A: 1'0 + Constant input on bit 53 of port A: 1'0 + Constant input on bit 54 of port A: 1'0 + Constant input on bit 55 of port A: 1'0 + Constant input on bit 56 of port A: 1'0 + Constant input on bit 57 of port A: 1'0 + Constant input on bit 58 of port A: 1'0 + Constant input on bit 59 of port A: 1'0 + Constant input on bit 60 of port A: 1'0 + Constant input on bit 61 of port A: 1'0 + Constant input on bit 62 of port A: 1'0 + Constant input on bit 63 of port A: 1'0 + Constant input on bit 64 of port A: 1'0 + Constant input on bit 65 of port A: 1'0 + Constant input on bit 66 of port A: 1'0 + Constant input on bit 67 of port A: 1'0 + Constant input on bit 68 of port A: 1'0 + Constant input on bit 69 of port A: 1'0 + Constant input on bit 70 of port A: 1'0 + Constant input on bit 71 of port A: 1'0 + Constant input on bit 72 of port A: 1'0 + Constant input on bit 73 of port A: 1'0 + Constant input on bit 74 of port A: 1'0 + Constant input on bit 75 of port A: 1'0 + Constant input on bit 76 of port A: 1'0 + Constant input on bit 77 of port A: 1'0 + Constant input on bit 78 of port A: 1'0 + Constant input on bit 79 of port A: 1'0 + Constant input on bit 80 of port A: 1'0 + Constant input on bit 81 of port A: 1'0 + Constant input on bit 82 of port A: 1'0 + Constant input on bit 83 of port A: 1'0 + Constant input on bit 84 of port A: 1'0 + Constant input on bit 85 of port A: 1'0 + Constant input on bit 86 of port A: 1'0 + Constant input on bit 87 of port A: 1'0 + Constant input on bit 88 of port A: 1'0 + Constant input on bit 89 of port A: 1'0 + Constant input on bit 90 of port A: 1'0 + Constant input on bit 91 of port A: 1'0 + Constant input on bit 92 of port A: 1'0 + Constant input on bit 93 of port A: 1'0 + Constant input on bit 94 of port A: 1'0 + Constant input on bit 95 of port A: 1'0 + Constant input on bit 96 of port A: 1'0 + Constant input on bit 97 of port A: 1'0 + Constant input on bit 98 of port A: 1'0 + Constant input on bit 99 of port A: 1'0 + Constant input on bit 100 of port A: 1'0 + Constant input on bit 101 of port A: 1'0 + Constant input on bit 102 of port A: 1'0 + Constant input on bit 103 of port A: 1'0 + Constant input on bit 104 of port A: 1'0 + Constant input on bit 105 of port A: 1'0 + Constant input on bit 106 of port A: 1'0 + Constant input on bit 107 of port A: 1'0 + Constant input on bit 108 of port A: 1'0 + Constant input on bit 109 of port A: 1'0 + Constant input on bit 110 of port A: 1'0 + Constant input on bit 111 of port A: 1'0 + Constant input on bit 112 of port A: 1'0 + Constant input on bit 113 of port A: 1'0 + Constant input on bit 114 of port A: 1'0 + Constant input on bit 115 of port A: 1'0 + Constant input on bit 116 of port A: 1'0 + Constant input on bit 117 of port A: 1'0 + Constant input on bit 118 of port A: 1'0 + Constant input on bit 119 of port A: 1'0 + Constant input on bit 120 of port A: 1'0 + Constant input on bit 121 of port A: 1'0 + Constant input on bit 122 of port A: 1'0 + Constant input on bit 123 of port A: 1'0 + Constant input on bit 124 of port A: 1'0 + Constant input on bit 125 of port A: 1'0 + Constant input on bit 126 of port A: 1'0 + Constant input on bit 127 of port A: 1'0 + Constant input on bit 128 of port A: 1'0 + Constant input on bit 129 of port A: 1'0 + Constant input on bit 130 of port A: 1'0 + Constant input on bit 131 of port A: 1'0 + Constant input on bit 132 of port A: 1'0 + Constant input on bit 133 of port A: 1'0 + Constant input on bit 134 of port A: 1'0 + Constant input on bit 135 of port A: 1'0 + Constant input on bit 136 of port A: 1'0 + Constant input on bit 137 of port A: 1'0 + Constant input on bit 138 of port A: 1'0 + Constant input on bit 139 of port A: 1'0 + Constant input on bit 140 of port A: 1'0 + Constant input on bit 141 of port A: 1'0 + Constant input on bit 142 of port A: 1'0 + Constant input on bit 143 of port A: 1'0 + Constant input on bit 144 of port A: 1'0 + Constant input on bit 145 of port A: 1'0 + Constant input on bit 146 of port A: 1'0 + Constant input on bit 147 of port A: 1'0 + Constant input on bit 148 of port A: 1'0 + Constant input on bit 149 of port A: 1'0 + Constant input on bit 150 of port A: 1'0 + Constant input on bit 151 of port A: 1'0 + Constant input on bit 152 of port A: 1'0 + Constant input on bit 153 of port A: 1'0 + Constant input on bit 154 of port A: 1'0 + Constant input on bit 155 of port A: 1'0 + Constant input on bit 156 of port A: 1'0 + Constant input on bit 157 of port A: 1'0 + Constant input on bit 158 of port A: 1'0 + Constant input on bit 159 of port A: 1'0 + Constant input on bit 160 of port A: 1'0 + Constant input on bit 161 of port A: 1'0 + Constant input on bit 162 of port A: 1'0 + Constant input on bit 163 of port A: 1'0 + Constant input on bit 164 of port A: 1'0 + Constant input on bit 165 of port A: 1'0 + Constant input on bit 166 of port A: 1'0 + Constant input on bit 167 of port A: 1'0 + Constant input on bit 168 of port A: 1'0 + Constant input on bit 169 of port A: 1'0 + Constant input on bit 170 of port A: 1'0 + Constant input on bit 171 of port A: 1'0 + Constant input on bit 172 of port A: 1'0 + Constant input on bit 173 of port A: 1'0 + Constant input on bit 174 of port A: 1'0 + Constant input on bit 175 of port A: 1'0 + Constant input on bit 176 of port A: 1'0 + Constant input on bit 177 of port A: 1'0 + Constant input on bit 178 of port A: 1'0 + Constant input on bit 179 of port A: 1'0 + Constant input on bit 180 of port A: 1'0 + Constant input on bit 181 of port A: 1'0 + Constant input on bit 182 of port A: 1'0 + Constant input on bit 183 of port A: 1'0 + Constant input on bit 184 of port A: 1'0 + Constant input on bit 185 of port A: 1'0 + Constant input on bit 186 of port A: 1'0 + Constant input on bit 187 of port A: 1'0 + Constant input on bit 188 of port A: 1'0 + Constant input on bit 189 of port A: 1'0 + Constant input on bit 190 of port A: 1'0 + Constant input on bit 191 of port A: 1'0 + Constant input on bit 192 of port A: 1'0 + Constant input on bit 193 of port A: 1'0 + Constant input on bit 194 of port A: 1'0 + Constant input on bit 195 of port A: 1'0 + Constant input on bit 196 of port A: 1'0 + Constant input on bit 197 of port A: 1'0 + Constant input on bit 198 of port A: 1'0 + Constant input on bit 199 of port A: 1'0 + Constant input on bit 200 of port A: 1'0 + Constant input on bit 201 of port A: 1'0 + Constant input on bit 202 of port A: 1'0 + Constant input on bit 203 of port A: 1'0 + Constant input on bit 204 of port A: 1'0 + Constant input on bit 205 of port A: 1'0 + Constant input on bit 206 of port A: 1'0 + Constant input on bit 207 of port A: 1'0 + Constant input on bit 208 of port A: 1'0 + Constant input on bit 209 of port A: 1'0 + Constant input on bit 210 of port A: 1'0 + Constant input on bit 211 of port A: 1'0 + Constant input on bit 212 of port A: 1'0 + Constant input on bit 213 of port A: 1'0 + Constant input on bit 214 of port A: 1'0 + Constant input on bit 215 of port A: 1'0 + Constant input on bit 216 of port A: 1'0 + Constant input on bit 217 of port A: 1'0 + Constant input on bit 218 of port A: 1'0 + Constant input on bit 219 of port A: 1'0 + Constant input on bit 220 of port A: 1'0 + Constant input on bit 221 of port A: 1'0 + Constant input on bit 222 of port A: 1'0 + Constant input on bit 223 of port A: 1'0 + Constant input on bit 224 of port A: 1'0 + Constant input on bit 225 of port A: 1'0 + Constant input on bit 226 of port A: 1'0 + Constant input on bit 227 of port A: 1'0 + Constant input on bit 228 of port A: 1'0 + Constant input on bit 229 of port A: 1'0 + Constant input on bit 230 of port A: 1'0 + Constant input on bit 231 of port A: 1'0 + Constant input on bit 232 of port A: 1'0 + Constant input on bit 233 of port A: 1'0 + Constant input on bit 234 of port A: 1'0 + Constant input on bit 235 of port A: 1'0 + Constant input on bit 236 of port A: 1'0 + Constant input on bit 237 of port A: 1'0 + Constant input on bit 238 of port A: 1'0 + Constant input on bit 239 of port A: 1'0 + Constant input on bit 240 of port A: 1'0 + Constant input on bit 241 of port A: 1'0 + Constant input on bit 242 of port A: 1'0 + Constant input on bit 243 of port A: 1'0 + Constant input on bit 244 of port A: 1'0 + Constant input on bit 245 of port A: 1'0 + Constant input on bit 246 of port A: 1'0 + Constant input on bit 247 of port A: 1'0 + Constant input on bit 248 of port A: 1'0 + Constant input on bit 249 of port A: 1'0 + Constant input on bit 250 of port A: 1'0 + Constant input on bit 251 of port A: 1'0 + Constant input on bit 252 of port A: 1'0 + Constant input on bit 253 of port A: 1'0 + Constant input on bit 254 of port A: 1'0 + Constant input on bit 255 of port A: 1'0 + Constant input on bit 256 of port A: 1'0 + Constant input on bit 257 of port A: 1'0 + Constant input on bit 258 of port A: 1'0 + Constant input on bit 259 of port A: 1'0 + Constant input on bit 260 of port A: 1'0 + Constant input on bit 261 of port A: 1'0 + Constant input on bit 262 of port A: 1'0 + Constant input on bit 263 of port A: 1'0 + Constant input on bit 264 of port A: 1'0 + Constant input on bit 265 of port A: 1'0 + Constant input on bit 266 of port A: 1'0 + Constant input on bit 267 of port A: 1'0 + Constant input on bit 268 of port A: 1'0 + Constant input on bit 269 of port A: 1'0 + Constant input on bit 270 of port A: 1'0 + Constant input on bit 271 of port A: 1'0 + Constant input on bit 272 of port A: 1'0 + Constant input on bit 273 of port A: 1'0 + Constant input on bit 274 of port A: 1'0 + Constant input on bit 275 of port A: 1'0 + Constant input on bit 276 of port A: 1'0 + Constant input on bit 277 of port A: 1'0 + Constant input on bit 278 of port A: 1'0 + Constant input on bit 279 of port A: 1'0 + Constant input on bit 280 of port A: 1'0 + Constant input on bit 281 of port A: 1'0 + Constant input on bit 282 of port A: 1'0 + Constant input on bit 283 of port A: 1'0 + Constant input on bit 284 of port A: 1'0 + Constant input on bit 285 of port A: 1'0 + Constant input on bit 286 of port A: 1'0 + Constant input on bit 287 of port A: 1'0 + Constant input on bit 288 of port A: 1'0 + Constant input on bit 289 of port A: 1'0 + Constant input on bit 290 of port A: 1'0 + Constant input on bit 291 of port A: 1'0 + Constant input on bit 292 of port A: 1'0 + Constant input on bit 293 of port A: 1'0 + Constant input on bit 294 of port A: 1'0 + Constant input on bit 295 of port A: 1'0 + Constant input on bit 296 of port A: 1'0 + Constant input on bit 297 of port A: 1'0 + Constant input on bit 298 of port A: 1'0 + Constant input on bit 299 of port A: 1'0 + Constant input on bit 300 of port A: 1'0 + Constant input on bit 301 of port A: 1'0 + Constant input on bit 302 of port A: 1'0 + Constant input on bit 303 of port A: 1'0 + Constant input on bit 304 of port A: 1'0 + Constant input on bit 305 of port A: 1'0 + Constant input on bit 306 of port A: 1'0 + Constant input on bit 307 of port A: 1'0 + Constant input on bit 308 of port A: 1'0 + Constant input on bit 309 of port A: 1'0 + Constant input on bit 310 of port A: 1'0 + Constant input on bit 311 of port A: 1'0 + Constant input on bit 312 of port A: 1'0 + Constant input on bit 313 of port A: 1'0 + Constant input on bit 314 of port A: 1'0 + Constant input on bit 315 of port A: 1'0 + Constant input on bit 316 of port A: 1'0 + Constant input on bit 317 of port A: 1'0 + Constant input on bit 318 of port A: 1'0 + Constant input on bit 319 of port A: 1'0 + Constant input on bit 320 of port A: 1'0 + Constant input on bit 321 of port A: 1'0 + Constant input on bit 322 of port A: 1'0 + Constant input on bit 323 of port A: 1'0 + Constant input on bit 324 of port A: 1'0 + Constant input on bit 325 of port A: 1'0 + Constant input on bit 326 of port A: 1'0 + Constant input on bit 327 of port A: 1'0 + Constant input on bit 328 of port A: 1'0 + Constant input on bit 329 of port A: 1'0 + Constant input on bit 330 of port A: 1'0 + Constant input on bit 331 of port A: 1'0 + Constant input on bit 332 of port A: 1'0 + Constant input on bit 333 of port A: 1'0 + Constant input on bit 334 of port A: 1'0 + Constant input on bit 335 of port A: 1'0 + Constant input on bit 336 of port A: 1'0 + Constant input on bit 337 of port A: 1'0 + Constant input on bit 338 of port A: 1'0 + Constant input on bit 339 of port A: 1'0 + Constant input on bit 340 of port A: 1'0 + Constant input on bit 341 of port A: 1'0 + Constant input on bit 342 of port A: 1'0 + Constant input on bit 343 of port A: 1'0 + Constant input on bit 344 of port A: 1'0 + Constant input on bit 345 of port A: 1'0 + Constant input on bit 346 of port A: 1'0 + Constant input on bit 347 of port A: 1'0 + Constant input on bit 348 of port A: 1'0 + Constant input on bit 349 of port A: 1'0 + Constant input on bit 350 of port A: 1'0 + Constant input on bit 351 of port A: 1'0 + Constant input on bit 352 of port A: 1'0 + Constant input on bit 353 of port A: 1'0 + Constant input on bit 354 of port A: 1'0 + Constant input on bit 355 of port A: 1'0 + Constant input on bit 356 of port A: 1'0 + Constant input on bit 357 of port A: 1'0 + Constant input on bit 358 of port A: 1'0 + Constant input on bit 359 of port A: 1'0 + Constant input on bit 360 of port A: 1'0 + Constant input on bit 361 of port A: 1'0 + Constant input on bit 362 of port A: 1'0 + Constant input on bit 363 of port A: 1'0 + Constant input on bit 364 of port A: 1'0 + Constant input on bit 365 of port A: 1'0 + Constant input on bit 366 of port A: 1'0 + Constant input on bit 367 of port A: 1'0 + Constant input on bit 368 of port A: 1'0 + Constant input on bit 369 of port A: 1'0 + Constant input on bit 370 of port A: 1'0 + Constant input on bit 371 of port A: 1'0 + Constant input on bit 372 of port A: 1'0 + Constant input on bit 373 of port A: 1'0 + Constant input on bit 374 of port A: 1'0 + Constant input on bit 375 of port A: 1'0 + Constant input on bit 376 of port A: 1'0 + Constant input on bit 377 of port A: 1'0 + Constant input on bit 378 of port A: 1'0 + Constant input on bit 379 of port A: 1'0 + Constant input on bit 380 of port A: 1'0 + Constant input on bit 381 of port A: 1'0 + Constant input on bit 382 of port A: 1'0 + Constant input on bit 383 of port A: 1'0 + Constant input on bit 384 of port A: 1'0 + Constant input on bit 385 of port A: 1'0 + Constant input on bit 386 of port A: 1'0 + Constant input on bit 387 of port A: 1'0 + Constant input on bit 388 of port A: 1'0 + Constant input on bit 389 of port A: 1'0 + Constant input on bit 390 of port A: 1'0 + Constant input on bit 391 of port A: 1'0 + Constant input on bit 392 of port A: 1'0 + Constant input on bit 393 of port A: 1'0 + Constant input on bit 394 of port A: 1'0 + Constant input on bit 395 of port A: 1'0 + Constant input on bit 396 of port A: 1'0 + Constant input on bit 397 of port A: 1'0 + Constant input on bit 398 of port A: 1'0 + Constant input on bit 399 of port A: 1'0 + Constant input on bit 400 of port A: 1'0 + Constant input on bit 401 of port A: 1'0 + Constant input on bit 402 of port A: 1'0 + Constant input on bit 403 of port A: 1'0 + Constant input on bit 404 of port A: 1'0 + Constant input on bit 405 of port A: 1'0 + Constant input on bit 406 of port A: 1'0 + Constant input on bit 407 of port A: 1'0 + Constant input on bit 408 of port A: 1'0 + Constant input on bit 409 of port A: 1'0 + Constant input on bit 410 of port A: 1'0 + Constant input on bit 411 of port A: 1'0 + Constant input on bit 412 of port A: 1'0 + Constant input on bit 413 of port A: 1'0 + Constant input on bit 414 of port A: 1'0 + Constant input on bit 415 of port A: 1'0 + Constant input on bit 416 of port A: 1'0 + Constant input on bit 417 of port A: 1'0 + Constant input on bit 418 of port A: 1'0 + Constant input on bit 419 of port A: 1'0 + Constant input on bit 420 of port A: 1'0 + Constant input on bit 421 of port A: 1'0 + Constant input on bit 422 of port A: 1'0 + Constant input on bit 423 of port A: 1'0 + Constant input on bit 424 of port A: 1'0 + Constant input on bit 425 of port A: 1'0 + Constant input on bit 426 of port A: 1'0 + Constant input on bit 427 of port A: 1'0 + Constant input on bit 428 of port A: 1'0 + Constant input on bit 429 of port A: 1'0 + Constant input on bit 430 of port A: 1'0 + Constant input on bit 431 of port A: 1'0 + Constant input on bit 432 of port A: 1'0 + Constant input on bit 433 of port A: 1'0 + Constant input on bit 434 of port A: 1'0 + Constant input on bit 435 of port A: 1'0 + Constant input on bit 436 of port A: 1'0 + Constant input on bit 437 of port A: 1'0 + Constant input on bit 438 of port A: 1'0 + Constant input on bit 439 of port A: 1'0 + Constant input on bit 440 of port A: 1'0 + Constant input on bit 441 of port A: 1'0 + Constant input on bit 442 of port A: 1'0 + Constant input on bit 443 of port A: 1'0 + Constant input on bit 444 of port A: 1'0 + Constant input on bit 445 of port A: 1'0 + Constant input on bit 446 of port A: 1'0 + Constant input on bit 447 of port A: 1'0 + Constant input on bit 448 of port A: 1'0 + Constant input on bit 449 of port A: 1'0 + Constant input on bit 450 of port A: 1'0 + Constant input on bit 451 of port A: 1'0 + Constant input on bit 452 of port A: 1'0 + Constant input on bit 453 of port A: 1'0 + Constant input on bit 454 of port A: 1'0 + Constant input on bit 455 of port A: 1'0 + Constant input on bit 456 of port A: 1'0 + Constant input on bit 457 of port A: 1'0 + Constant input on bit 458 of port A: 1'0 + Constant input on bit 459 of port A: 1'0 + Constant input on bit 460 of port A: 1'0 + Constant input on bit 461 of port A: 1'0 + Constant input on bit 462 of port A: 1'0 + Constant input on bit 463 of port A: 1'0 + Constant input on bit 464 of port A: 1'0 + Constant input on bit 465 of port A: 1'0 + Constant input on bit 466 of port A: 1'0 + Constant input on bit 467 of port A: 1'0 + Constant input on bit 468 of port A: 1'0 + Constant input on bit 469 of port A: 1'0 + Constant input on bit 470 of port A: 1'0 + Constant input on bit 471 of port A: 1'0 + Constant input on bit 472 of port A: 1'0 + Constant input on bit 473 of port A: 1'0 + Constant input on bit 474 of port A: 1'0 + Constant input on bit 475 of port A: 1'0 + Constant input on bit 476 of port A: 1'0 + Constant input on bit 477 of port A: 1'0 + Constant input on bit 478 of port A: 1'0 + Constant input on bit 479 of port A: 1'0 + Constant input on bit 480 of port A: 1'0 + Constant input on bit 481 of port A: 1'0 + Constant input on bit 482 of port A: 1'0 + Constant input on bit 483 of port A: 1'0 + Constant input on bit 484 of port A: 1'0 + Constant input on bit 485 of port A: 1'0 + Constant input on bit 486 of port A: 1'0 + Constant input on bit 487 of port A: 1'0 + Constant input on bit 488 of port A: 1'0 + Constant input on bit 489 of port A: 1'0 + Constant input on bit 490 of port A: 1'0 + Constant input on bit 491 of port A: 1'0 + Constant input on bit 492 of port A: 1'0 + Constant input on bit 493 of port A: 1'0 + Constant input on bit 494 of port A: 1'0 + Constant input on bit 495 of port A: 1'0 + Constant input on bit 496 of port A: 1'0 + Constant input on bit 497 of port A: 1'0 + Constant input on bit 498 of port A: 1'0 + Constant input on bit 499 of port A: 1'0 + Constant input on bit 500 of port A: 1'0 + Constant input on bit 501 of port A: 1'0 + Constant input on bit 502 of port A: 1'0 + Constant input on bit 503 of port A: 1'0 + Constant input on bit 504 of port A: 1'0 + Constant input on bit 505 of port A: 1'0 + Constant input on bit 506 of port A: 1'0 + Constant input on bit 507 of port A: 1'0 + Constant input on bit 508 of port A: 1'0 + Constant input on bit 509 of port A: 1'0 + Constant input on bit 510 of port A: 1'0 + Constant input on bit 511 of port A: 1'0 + Constant input on bit 512 of port A: 1'0 + Constant input on bit 513 of port A: 1'0 + Constant input on bit 514 of port A: 1'0 + Constant input on bit 515 of port A: 1'0 + Constant input on bit 516 of port A: 1'0 + Constant input on bit 517 of port A: 1'0 + Constant input on bit 518 of port A: 1'0 + Constant input on bit 519 of port A: 1'0 + Constant input on bit 520 of port A: 1'0 + Constant input on bit 521 of port A: 1'0 + Constant input on bit 522 of port A: 1'0 + Constant input on bit 523 of port A: 1'0 + Constant input on bit 524 of port A: 1'0 + Constant input on bit 525 of port A: 1'0 + Constant input on bit 526 of port A: 1'0 + Constant input on bit 527 of port A: 1'0 + Constant input on bit 528 of port A: 1'0 + Constant input on bit 529 of port A: 1'0 + Constant input on bit 530 of port A: 1'0 + Constant input on bit 531 of port A: 1'0 + Constant input on bit 532 of port A: 1'0 + Constant input on bit 533 of port A: 1'0 + Constant input on bit 534 of port A: 1'0 + Constant input on bit 535 of port A: 1'0 + Constant input on bit 536 of port A: 1'0 + Constant input on bit 537 of port A: 1'0 + Constant input on bit 538 of port A: 1'0 + Constant input on bit 539 of port A: 1'0 + Constant input on bit 540 of port A: 1'0 + Constant input on bit 541 of port A: 1'0 + Constant input on bit 542 of port A: 1'0 + Constant input on bit 543 of port A: 1'0 + Constant input on bit 544 of port A: 1'0 + Constant input on bit 545 of port A: 1'0 + Constant input on bit 546 of port A: 1'0 + Constant input on bit 547 of port A: 1'0 + Constant input on bit 548 of port A: 1'0 + Constant input on bit 549 of port A: 1'0 + Constant input on bit 550 of port A: 1'0 + Constant input on bit 551 of port A: 1'0 + Constant input on bit 552 of port A: 1'0 + Constant input on bit 553 of port A: 1'0 + Constant input on bit 554 of port A: 1'0 + Constant input on bit 555 of port A: 1'0 + Constant input on bit 556 of port A: 1'0 + Constant input on bit 557 of port A: 1'0 + Constant input on bit 558 of port A: 1'0 + Constant input on bit 559 of port A: 1'0 + Constant input on bit 560 of port A: 1'0 + Constant input on bit 561 of port A: 1'0 + Constant input on bit 562 of port A: 1'0 + Constant input on bit 563 of port A: 1'0 + Constant input on bit 564 of port A: 1'0 + Constant input on bit 565 of port A: 1'0 + Constant input on bit 566 of port A: 1'0 + Constant input on bit 567 of port A: 1'0 + Constant input on bit 568 of port A: 1'0 + Constant input on bit 569 of port A: 1'0 + Constant input on bit 570 of port A: 1'0 + Constant input on bit 571 of port A: 1'0 + Constant input on bit 572 of port A: 1'0 + Constant input on bit 573 of port A: 1'0 + Constant input on bit 574 of port A: 1'0 + Constant input on bit 575 of port A: 1'0 + Constant input on bit 576 of port A: 1'0 + Constant input on bit 577 of port A: 1'0 + Constant input on bit 578 of port A: 1'0 + Constant input on bit 579 of port A: 1'0 + Constant input on bit 580 of port A: 1'0 + Constant input on bit 581 of port A: 1'0 + Constant input on bit 582 of port A: 1'0 + Constant input on bit 583 of port A: 1'0 + Constant input on bit 584 of port A: 1'0 + Constant input on bit 585 of port A: 1'0 + Constant input on bit 586 of port A: 1'0 + Constant input on bit 587 of port A: 1'0 + Constant input on bit 588 of port A: 1'0 + Constant input on bit 589 of port A: 1'0 + Constant input on bit 590 of port A: 1'0 + Constant input on bit 591 of port A: 1'0 + Constant input on bit 592 of port A: 1'0 + Constant input on bit 593 of port A: 1'0 + Constant input on bit 594 of port A: 1'0 + Constant input on bit 595 of port A: 1'0 + Constant input on bit 596 of port A: 1'0 + Constant input on bit 597 of port A: 1'0 + Constant input on bit 598 of port A: 1'0 + Constant input on bit 599 of port A: 1'0 + Constant input on bit 600 of port A: 1'0 + Constant input on bit 601 of port A: 1'0 + Constant input on bit 602 of port A: 1'0 + Constant input on bit 603 of port A: 1'0 + Constant input on bit 604 of port A: 1'0 + Constant input on bit 605 of port A: 1'0 + Constant input on bit 606 of port A: 1'0 + Constant input on bit 607 of port A: 1'0 + Constant input on bit 608 of port A: 1'0 + Constant input on bit 609 of port A: 1'0 + Constant input on bit 610 of port A: 1'0 + Constant input on bit 611 of port A: 1'0 + Constant input on bit 612 of port A: 1'0 + Constant input on bit 613 of port A: 1'0 + Constant input on bit 614 of port A: 1'0 + Constant input on bit 615 of port A: 1'0 + Constant input on bit 616 of port A: 1'0 + Constant input on bit 617 of port A: 1'0 + Constant input on bit 618 of port A: 1'0 + Constant input on bit 619 of port A: 1'0 + Constant input on bit 620 of port A: 1'0 + Constant input on bit 621 of port A: 1'0 + Constant input on bit 622 of port A: 1'0 + Constant input on bit 623 of port A: 1'0 + Constant input on bit 624 of port A: 1'0 + Constant input on bit 625 of port A: 1'0 + Constant input on bit 626 of port A: 1'0 + Constant input on bit 627 of port A: 1'0 + Constant input on bit 628 of port A: 1'0 + Constant input on bit 629 of port A: 1'0 + Constant input on bit 630 of port A: 1'0 + Constant input on bit 631 of port A: 1'0 + Constant input on bit 632 of port A: 1'0 + Constant input on bit 633 of port A: 1'0 + Constant input on bit 634 of port A: 1'0 + Constant input on bit 635 of port A: 1'0 + Constant input on bit 636 of port A: 1'0 + Constant input on bit 637 of port A: 1'0 + Constant input on bit 638 of port A: 1'0 + Constant input on bit 639 of port A: 1'0 + Constant input on bit 640 of port A: 1'0 + Constant input on bit 641 of port A: 1'0 + Constant input on bit 642 of port A: 1'0 + Constant input on bit 643 of port A: 1'0 + Constant input on bit 644 of port A: 1'0 + Constant input on bit 645 of port A: 1'0 + Constant input on bit 646 of port A: 1'0 + Constant input on bit 647 of port A: 1'0 + Constant input on bit 648 of port A: 1'0 + Constant input on bit 649 of port A: 1'0 + Constant input on bit 650 of port A: 1'0 + Constant input on bit 651 of port A: 1'0 + Constant input on bit 652 of port A: 1'0 + Constant input on bit 653 of port A: 1'0 + Constant input on bit 654 of port A: 1'0 + Constant input on bit 655 of port A: 1'0 + Constant input on bit 656 of port A: 1'0 + Constant input on bit 657 of port A: 1'0 + Constant input on bit 658 of port A: 1'0 + Constant input on bit 659 of port A: 1'0 + Constant input on bit 660 of port A: 1'0 + Constant input on bit 661 of port A: 1'0 + Constant input on bit 662 of port A: 1'0 + Constant input on bit 663 of port A: 1'0 + Constant input on bit 664 of port A: 1'0 + Constant input on bit 665 of port A: 1'0 + Constant input on bit 666 of port A: 1'0 + Constant input on bit 667 of port A: 1'0 + Constant input on bit 668 of port A: 1'0 + Constant input on bit 669 of port A: 1'0 + Constant input on bit 670 of port A: 1'0 + Constant input on bit 671 of port A: 1'0 + Constant input on bit 672 of port A: 1'0 + Constant input on bit 673 of port A: 1'0 + Constant input on bit 674 of port A: 1'0 + Constant input on bit 675 of port A: 1'0 + Constant input on bit 676 of port A: 1'0 + Constant input on bit 677 of port A: 1'0 + Constant input on bit 678 of port A: 1'0 + Constant input on bit 679 of port A: 1'0 + Constant input on bit 680 of port A: 1'0 + Constant input on bit 681 of port A: 1'0 + Constant input on bit 682 of port A: 1'0 + Constant input on bit 683 of port A: 1'0 + Constant input on bit 684 of port A: 1'0 + Constant input on bit 685 of port A: 1'0 + Constant input on bit 686 of port A: 1'0 + Constant input on bit 687 of port A: 1'0 + Constant input on bit 688 of port A: 1'0 + Constant input on bit 689 of port A: 1'0 + Constant input on bit 690 of port A: 1'0 + Constant input on bit 691 of port A: 1'0 + Constant input on bit 692 of port A: 1'0 + Constant input on bit 693 of port A: 1'0 + Constant input on bit 694 of port A: 1'0 + Constant input on bit 695 of port A: 1'0 + Constant input on bit 696 of port A: 1'0 + Constant input on bit 697 of port A: 1'0 + Constant input on bit 698 of port A: 1'0 + Constant input on bit 699 of port A: 1'0 + Constant input on bit 700 of port A: 1'0 + Constant input on bit 701 of port A: 1'0 + Constant input on bit 702 of port A: 1'0 + Constant input on bit 703 of port A: 1'0 + Constant input on bit 704 of port A: 1'0 + Constant input on bit 705 of port A: 1'0 + Constant input on bit 706 of port A: 1'0 + Constant input on bit 707 of port A: 1'0 + Constant input on bit 708 of port A: 1'0 + Constant input on bit 709 of port A: 1'0 + Constant input on bit 710 of port A: 1'0 + Constant input on bit 711 of port A: 1'0 + Constant input on bit 712 of port A: 1'0 + Constant input on bit 713 of port A: 1'0 + Constant input on bit 714 of port A: 1'0 + Constant input on bit 715 of port A: 1'0 + Constant input on bit 716 of port A: 1'0 + Constant input on bit 717 of port A: 1'0 + Constant input on bit 718 of port A: 1'0 + Constant input on bit 719 of port A: 1'0 + Constant input on bit 720 of port A: 1'0 + Constant input on bit 721 of port A: 1'0 + Constant input on bit 722 of port A: 1'0 + Constant input on bit 723 of port A: 1'0 + Constant input on bit 724 of port A: 1'0 + Constant input on bit 725 of port A: 1'0 + Constant input on bit 726 of port A: 1'0 + Constant input on bit 727 of port A: 1'0 + Constant input on bit 728 of port A: 1'0 + Constant input on bit 729 of port A: 1'0 + Constant input on bit 730 of port A: 1'0 + Constant input on bit 731 of port A: 1'0 + Constant input on bit 732 of port A: 1'0 + Constant input on bit 733 of port A: 1'0 + Constant input on bit 734 of port A: 1'0 + Constant input on bit 735 of port A: 1'0 + Constant input on bit 736 of port A: 1'0 + Constant input on bit 737 of port A: 1'0 + Constant input on bit 738 of port A: 1'0 + Constant input on bit 739 of port A: 1'0 + Constant input on bit 740 of port A: 1'0 + Constant input on bit 741 of port A: 1'0 + Constant input on bit 742 of port A: 1'0 + Constant input on bit 743 of port A: 1'0 + Constant input on bit 744 of port A: 1'0 + Constant input on bit 745 of port A: 1'0 + Constant input on bit 746 of port A: 1'0 + Constant input on bit 747 of port A: 1'0 + Constant input on bit 748 of port A: 1'0 + Constant input on bit 749 of port A: 1'0 + Constant input on bit 750 of port A: 1'0 + Constant input on bit 751 of port A: 1'0 + Constant input on bit 752 of port A: 1'0 + Constant input on bit 753 of port A: 1'0 + Constant input on bit 754 of port A: 1'0 + Constant input on bit 755 of port A: 1'0 + Constant input on bit 756 of port A: 1'0 + Constant input on bit 757 of port A: 1'0 + Constant input on bit 758 of port A: 1'0 + Constant input on bit 759 of port A: 1'0 + Constant input on bit 760 of port A: 1'0 + Constant input on bit 761 of port A: 1'0 + Constant input on bit 762 of port A: 1'0 + Constant input on bit 763 of port A: 1'0 + Constant input on bit 764 of port A: 1'0 + Constant input on bit 765 of port A: 1'0 + Constant input on bit 766 of port A: 1'0 + Constant input on bit 767 of port A: 1'0 + Constant input on bit 768 of port A: 1'0 + Constant input on bit 769 of port A: 1'0 + Constant input on bit 770 of port A: 1'0 + Constant input on bit 771 of port A: 1'0 + Constant input on bit 772 of port A: 1'0 + Constant input on bit 773 of port A: 1'0 + Constant input on bit 774 of port A: 1'0 + Constant input on bit 775 of port A: 1'0 + Constant input on bit 776 of port A: 1'0 + Constant input on bit 777 of port A: 1'0 + Constant input on bit 778 of port A: 1'0 + Constant input on bit 779 of port A: 1'0 + Constant input on bit 780 of port A: 1'0 + Constant input on bit 781 of port A: 1'0 + Constant input on bit 782 of port A: 1'0 + Constant input on bit 783 of port A: 1'0 + Constant input on bit 784 of port A: 1'0 + Constant input on bit 785 of port A: 1'0 + Constant input on bit 786 of port A: 1'0 + Constant input on bit 787 of port A: 1'0 + Constant input on bit 788 of port A: 1'0 + Constant input on bit 789 of port A: 1'0 + Constant input on bit 790 of port A: 1'0 + Constant input on bit 791 of port A: 1'0 + Constant input on bit 792 of port A: 1'0 + Constant input on bit 793 of port A: 1'0 + Constant input on bit 794 of port A: 1'0 + Constant input on bit 795 of port A: 1'0 + Constant input on bit 796 of port A: 1'0 + Constant input on bit 797 of port A: 1'0 + Constant input on bit 798 of port A: 1'0 + Constant input on bit 799 of port A: 1'0 + Constant input on bit 800 of port A: 1'0 + Constant input on bit 801 of port A: 1'0 + Constant input on bit 802 of port A: 1'0 + Constant input on bit 803 of port A: 1'0 + Constant input on bit 804 of port A: 1'0 + Constant input on bit 805 of port A: 1'0 + Constant input on bit 806 of port A: 1'0 + Constant input on bit 807 of port A: 1'0 + Constant input on bit 808 of port A: 1'0 + Constant input on bit 809 of port A: 1'0 + Constant input on bit 810 of port A: 1'0 + Constant input on bit 811 of port A: 1'0 + Constant input on bit 812 of port A: 1'0 + Constant input on bit 813 of port A: 1'0 + Constant input on bit 814 of port A: 1'0 + Constant input on bit 815 of port A: 1'0 + Constant input on bit 816 of port A: 1'0 + Constant input on bit 817 of port A: 1'0 + Constant input on bit 818 of port A: 1'0 + Constant input on bit 819 of port A: 1'0 + Constant input on bit 820 of port A: 1'0 + Constant input on bit 821 of port A: 1'0 + Constant input on bit 822 of port A: 1'0 + Constant input on bit 823 of port A: 1'0 + Constant input on bit 824 of port A: 1'0 + Constant input on bit 825 of port A: 1'0 + Constant input on bit 826 of port A: 1'0 + Constant input on bit 827 of port A: 1'0 + Constant input on bit 828 of port A: 1'0 + Constant input on bit 829 of port A: 1'0 + Constant input on bit 830 of port A: 1'0 + Constant input on bit 831 of port A: 1'0 + Constant input on bit 832 of port A: 1'0 + Constant input on bit 833 of port A: 1'0 + Constant input on bit 834 of port A: 1'0 + Constant input on bit 835 of port A: 1'0 + Constant input on bit 836 of port A: 1'0 + Constant input on bit 837 of port A: 1'0 + Constant input on bit 838 of port A: 1'0 + Constant input on bit 839 of port A: 1'0 + Constant input on bit 840 of port A: 1'0 + Constant input on bit 841 of port A: 1'0 + Constant input on bit 842 of port A: 1'0 + Constant input on bit 843 of port A: 1'0 + Constant input on bit 844 of port A: 1'0 + Constant input on bit 845 of port A: 1'0 + Constant input on bit 846 of port A: 1'0 + Constant input on bit 847 of port A: 1'0 + Constant input on bit 848 of port A: 1'0 + Constant input on bit 849 of port A: 1'0 + Constant input on bit 850 of port A: 1'0 + Constant input on bit 851 of port A: 1'0 + Constant input on bit 852 of port A: 1'0 + Constant input on bit 853 of port A: 1'0 + Constant input on bit 854 of port A: 1'0 + Constant input on bit 855 of port A: 1'0 + Constant input on bit 856 of port A: 1'0 + Constant input on bit 857 of port A: 1'0 + Constant input on bit 858 of port A: 1'0 + Constant input on bit 859 of port A: 1'0 + Constant input on bit 860 of port A: 1'0 + Constant input on bit 861 of port A: 1'0 + Constant input on bit 862 of port A: 1'0 + Constant input on bit 863 of port A: 1'0 + Constant input on bit 864 of port A: 1'0 + Constant input on bit 865 of port A: 1'0 + Constant input on bit 866 of port A: 1'0 + Constant input on bit 867 of port A: 1'0 + Constant input on bit 868 of port A: 1'0 + Constant input on bit 869 of port A: 1'0 + Constant input on bit 870 of port A: 1'0 + Constant input on bit 871 of port A: 1'0 + Constant input on bit 872 of port A: 1'0 + Constant input on bit 873 of port A: 1'0 + Constant input on bit 874 of port A: 1'0 + Constant input on bit 875 of port A: 1'0 + Constant input on bit 876 of port A: 1'0 + Constant input on bit 877 of port A: 1'0 + Constant input on bit 878 of port A: 1'0 + Constant input on bit 879 of port A: 1'0 + Constant input on bit 880 of port A: 1'0 + Constant input on bit 881 of port A: 1'0 + Constant input on bit 882 of port A: 1'0 + Constant input on bit 883 of port A: 1'0 + Constant input on bit 884 of port A: 1'0 + Constant input on bit 885 of port A: 1'0 + Constant input on bit 886 of port A: 1'0 + Constant input on bit 887 of port A: 1'0 + Constant input on bit 888 of port A: 1'0 + Constant input on bit 889 of port A: 1'0 + Constant input on bit 890 of port A: 1'0 + Constant input on bit 891 of port A: 1'0 + Constant input on bit 892 of port A: 1'0 + Constant input on bit 893 of port A: 1'0 + Constant input on bit 894 of port A: 1'0 + Constant input on bit 895 of port A: 1'0 + Constant input on bit 896 of port A: 1'0 + Constant input on bit 897 of port A: 1'0 + Constant input on bit 898 of port A: 1'0 + Constant input on bit 899 of port A: 1'0 + Constant input on bit 900 of port A: 1'0 + Constant input on bit 901 of port A: 1'0 + Constant input on bit 902 of port A: 1'0 + Constant input on bit 903 of port A: 1'0 + Constant input on bit 904 of port A: 1'0 + Constant input on bit 905 of port A: 1'0 + Constant input on bit 906 of port A: 1'0 + Constant input on bit 907 of port A: 1'0 + Constant input on bit 908 of port A: 1'0 + Constant input on bit 909 of port A: 1'0 + Constant input on bit 910 of port A: 1'0 + Constant input on bit 911 of port A: 1'0 + Constant input on bit 912 of port A: 1'0 + Constant input on bit 913 of port A: 1'0 + Constant input on bit 914 of port A: 1'0 + Constant input on bit 915 of port A: 1'0 + Constant input on bit 916 of port A: 1'0 + Constant input on bit 917 of port A: 1'0 + Constant input on bit 918 of port A: 1'0 + Constant input on bit 919 of port A: 1'0 + Constant input on bit 920 of port A: 1'0 + Constant input on bit 921 of port A: 1'0 + Constant input on bit 922 of port A: 1'0 + Constant input on bit 923 of port A: 1'0 + Constant input on bit 924 of port A: 1'0 + Constant input on bit 925 of port A: 1'0 + Constant input on bit 926 of port A: 1'0 + Constant input on bit 927 of port A: 1'0 + Constant input on bit 928 of port A: 1'0 + Constant input on bit 929 of port A: 1'0 + Constant input on bit 930 of port A: 1'0 + Constant input on bit 931 of port A: 1'0 + Constant input on bit 932 of port A: 1'0 + Constant input on bit 933 of port A: 1'0 + Constant input on bit 934 of port A: 1'0 + Constant input on bit 935 of port A: 1'0 + Constant input on bit 936 of port A: 1'0 + Constant input on bit 937 of port A: 1'0 + Constant input on bit 938 of port A: 1'0 + Constant input on bit 939 of port A: 1'0 + Constant input on bit 940 of port A: 1'0 + Constant input on bit 941 of port A: 1'0 + Constant input on bit 942 of port A: 1'0 + Constant input on bit 943 of port A: 1'0 + Constant input on bit 944 of port A: 1'0 + Constant input on bit 945 of port A: 1'0 + Constant input on bit 946 of port A: 1'0 + Constant input on bit 947 of port A: 1'0 + Constant input on bit 948 of port A: 1'0 + Constant input on bit 949 of port A: 1'0 + Constant input on bit 950 of port A: 1'0 + Constant input on bit 951 of port A: 1'0 + Constant input on bit 952 of port A: 1'0 + Constant input on bit 953 of port A: 1'0 + Constant input on bit 954 of port A: 1'0 + Constant input on bit 955 of port A: 1'0 + Constant input on bit 956 of port A: 1'0 + Constant input on bit 957 of port A: 1'0 + Constant input on bit 958 of port A: 1'0 + Constant input on bit 959 of port A: 1'0 + Constant input on bit 960 of port A: 1'0 + Constant input on bit 961 of port A: 1'0 + Constant input on bit 962 of port A: 1'0 + Constant input on bit 963 of port A: 1'0 + Constant input on bit 964 of port A: 1'0 + Constant input on bit 965 of port A: 1'0 + Constant input on bit 966 of port A: 1'0 + Constant input on bit 967 of port A: 1'0 + Constant input on bit 968 of port A: 1'0 + Constant input on bit 969 of port A: 1'0 + Constant input on bit 970 of port A: 1'0 + Constant input on bit 971 of port A: 1'0 + Constant input on bit 972 of port A: 1'0 + Constant input on bit 973 of port A: 1'0 + Constant input on bit 974 of port A: 1'0 + Constant input on bit 975 of port A: 1'0 + Constant input on bit 976 of port A: 1'0 + Constant input on bit 977 of port A: 1'0 + Constant input on bit 978 of port A: 1'0 + Constant input on bit 979 of port A: 1'0 + Constant input on bit 980 of port A: 1'0 + Constant input on bit 981 of port A: 1'0 + Constant input on bit 982 of port A: 1'0 + Constant input on bit 983 of port A: 1'0 + Constant input on bit 984 of port A: 1'0 + Constant input on bit 985 of port A: 1'0 + Constant input on bit 986 of port A: 1'0 + Constant input on bit 987 of port A: 1'0 + Constant input on bit 988 of port A: 1'0 + Constant input on bit 989 of port A: 1'0 + Constant input on bit 990 of port A: 1'0 + Constant input on bit 991 of port A: 1'0 + Constant input on bit 992 of port A: 1'0 + Constant input on bit 993 of port A: 1'0 + Constant input on bit 994 of port A: 1'0 + Constant input on bit 995 of port A: 1'0 + Constant input on bit 996 of port A: 1'0 + Constant input on bit 997 of port A: 1'0 + Constant input on bit 998 of port A: 1'0 + Constant input on bit 999 of port A: 1'0 + Constant input on bit 1000 of port A: 1'0 + Constant input on bit 1001 of port A: 1'0 + Constant input on bit 1002 of port A: 1'0 + Constant input on bit 1003 of port A: 1'0 + Constant input on bit 1004 of port A: 1'0 + Constant input on bit 1005 of port A: 1'0 + Constant input on bit 1006 of port A: 1'0 + Constant input on bit 1007 of port A: 1'0 + Constant input on bit 1008 of port A: 1'0 + Constant input on bit 1009 of port A: 1'0 + Constant input on bit 1010 of port A: 1'0 + Constant input on bit 1011 of port A: 1'0 + Constant input on bit 1012 of port A: 1'0 + Constant input on bit 1013 of port A: 1'0 + Constant input on bit 1014 of port A: 1'0 + Constant input on bit 1015 of port A: 1'0 + Constant input on bit 1016 of port A: 1'0 + Constant input on bit 1017 of port A: 1'0 + Constant input on bit 1018 of port A: 1'0 + Constant input on bit 1019 of port A: 1'0 + Constant input on bit 1020 of port A: 1'0 + Constant input on bit 1021 of port A: 1'0 + Constant input on bit 1022 of port A: 1'0 + Constant input on bit 1023 of port A: 1'0 + Constant input on bit 1024 of port A: 1'0 + Constant input on bit 1025 of port A: 1'0 + Constant input on bit 1026 of port A: 1'0 + Constant input on bit 1027 of port A: 1'0 + Constant input on bit 1028 of port A: 1'0 + Constant input on bit 1029 of port A: 1'0 + Constant input on bit 1030 of port A: 1'0 + Constant input on bit 1031 of port A: 1'0 + Constant input on bit 1032 of port A: 1'0 + Constant input on bit 1033 of port A: 1'0 + Constant input on bit 1034 of port A: 1'0 + Constant input on bit 1035 of port A: 1'0 + Constant input on bit 1036 of port A: 1'0 + Constant input on bit 1037 of port A: 1'0 + Constant input on bit 1038 of port A: 1'0 + Constant input on bit 1039 of port A: 1'0 + Constant input on bit 1040 of port A: 1'0 + Constant input on bit 1041 of port A: 1'0 + Constant input on bit 1042 of port A: 1'0 + Constant input on bit 1043 of port A: 1'0 + Constant input on bit 1044 of port A: 1'0 + Constant input on bit 1045 of port A: 1'0 + Constant input on bit 1046 of port A: 1'0 + Constant input on bit 1047 of port A: 1'0 + Constant input on bit 1048 of port A: 1'0 + Constant input on bit 1049 of port A: 1'0 + Constant input on bit 1050 of port A: 1'0 + Constant input on bit 1051 of port A: 1'0 + Constant input on bit 1052 of port A: 1'0 + Constant input on bit 1053 of port A: 1'0 + Constant input on bit 1054 of port A: 1'0 + Constant input on bit 1055 of port A: 1'0 + Constant input on bit 1056 of port A: 1'0 + Constant input on bit 1057 of port A: 1'0 + Constant input on bit 1058 of port A: 1'0 + Constant input on bit 1059 of port A: 1'0 + Constant input on bit 1060 of port A: 1'0 + Constant input on bit 1061 of port A: 1'0 + Constant input on bit 1062 of port A: 1'0 + Constant input on bit 1063 of port A: 1'0 + Constant input on bit 1064 of port A: 1'0 + Constant input on bit 1065 of port A: 1'0 + Constant input on bit 1066 of port A: 1'0 + Constant input on bit 1067 of port A: 1'0 + Constant input on bit 1068 of port A: 1'0 + Constant input on bit 1069 of port A: 1'0 + Constant input on bit 1070 of port A: 1'0 + Constant input on bit 1071 of port A: 1'0 + Constant input on bit 1072 of port A: 1'0 + Constant input on bit 1073 of port A: 1'0 + Constant input on bit 1074 of port A: 1'0 + Constant input on bit 1075 of port A: 1'0 + Constant input on bit 1076 of port A: 1'0 + Constant input on bit 1077 of port A: 1'0 + Constant input on bit 1078 of port A: 1'0 + Constant input on bit 1079 of port A: 1'0 + Constant input on bit 1080 of port A: 1'0 + Constant input on bit 1081 of port A: 1'0 + Constant input on bit 1082 of port A: 1'0 + Constant input on bit 1083 of port A: 1'0 + Constant input on bit 1084 of port A: 1'0 + Constant input on bit 1085 of port A: 1'0 + Constant input on bit 1086 of port A: 1'0 + Constant input on bit 1087 of port A: 1'0 + Constant input on bit 1088 of port A: 1'0 + Constant input on bit 1089 of port A: 1'0 + Constant input on bit 1090 of port A: 1'0 + Constant input on bit 1091 of port A: 1'0 + Constant input on bit 1092 of port A: 1'0 + Constant input on bit 1093 of port A: 1'0 + Constant input on bit 1094 of port A: 1'0 + Constant input on bit 1095 of port A: 1'0 + Constant input on bit 1096 of port A: 1'0 + Constant input on bit 1097 of port A: 1'0 + Constant input on bit 1098 of port A: 1'0 + Constant input on bit 1099 of port A: 1'0 + Constant input on bit 1100 of port A: 1'0 + Constant input on bit 1101 of port A: 1'0 + Constant input on bit 1102 of port A: 1'0 + Constant input on bit 1103 of port A: 1'0 + Constant input on bit 1104 of port A: 1'0 + Constant input on bit 1105 of port A: 1'0 + Constant input on bit 1106 of port A: 1'0 + Constant input on bit 1107 of port A: 1'0 + Constant input on bit 1108 of port A: 1'0 + Constant input on bit 1109 of port A: 1'0 + Constant input on bit 1110 of port A: 1'0 + Constant input on bit 1111 of port A: 1'0 + Constant input on bit 1112 of port A: 1'0 + Constant input on bit 1113 of port A: 1'0 + Constant input on bit 1114 of port A: 1'0 + Constant input on bit 1115 of port A: 1'0 + Constant input on bit 1116 of port A: 1'0 + Constant input on bit 1117 of port A: 1'0 + Constant input on bit 1118 of port A: 1'0 + Constant input on bit 1119 of port A: 1'0 + Constant input on bit 1120 of port A: 1'0 + Constant input on bit 1121 of port A: 1'0 + Constant input on bit 1122 of port A: 1'0 + Constant input on bit 1123 of port A: 1'0 + Constant input on bit 1124 of port A: 1'0 + Constant input on bit 1125 of port A: 1'0 + Constant input on bit 1126 of port A: 1'0 + Constant input on bit 1127 of port A: 1'0 + Constant input on bit 1128 of port A: 1'0 + Constant input on bit 1129 of port A: 1'0 + Constant input on bit 1130 of port A: 1'0 + Constant input on bit 1131 of port A: 1'0 + Constant input on bit 1132 of port A: 1'0 + Constant input on bit 1133 of port A: 1'0 + Constant input on bit 1134 of port A: 1'0 + Constant input on bit 1135 of port A: 1'0 + Constant input on bit 1136 of port A: 1'0 + Constant input on bit 1137 of port A: 1'0 + Constant input on bit 1138 of port A: 1'0 + Constant input on bit 1139 of port A: 1'0 + Constant input on bit 1140 of port A: 1'0 + Constant input on bit 1141 of port A: 1'0 + Constant input on bit 1142 of port A: 1'0 + Constant input on bit 1143 of port A: 1'0 + Constant input on bit 1144 of port A: 1'0 + Constant input on bit 1145 of port A: 1'0 + Constant input on bit 1146 of port A: 1'0 + Constant input on bit 1147 of port A: 1'0 + Constant input on bit 1148 of port A: 1'0 + Constant input on bit 1149 of port A: 1'0 + Constant input on bit 1150 of port A: 1'0 + Constant input on bit 1151 of port A: 1'0 + Constant input on bit 1152 of port A: 1'0 + Constant input on bit 1153 of port A: 1'0 + Constant input on bit 1154 of port A: 1'0 + Constant input on bit 1155 of port A: 1'0 + Constant input on bit 1156 of port A: 1'0 + Constant input on bit 1157 of port A: 1'0 + Constant input on bit 1158 of port A: 1'0 + Constant input on bit 1159 of port A: 1'0 + Constant input on bit 1160 of port A: 1'0 + Constant input on bit 1161 of port A: 1'0 + Constant input on bit 1162 of port A: 1'0 + Constant input on bit 1163 of port A: 1'0 + Constant input on bit 1164 of port A: 1'0 + Constant input on bit 1165 of port A: 1'0 + Constant input on bit 1166 of port A: 1'0 + Constant input on bit 1167 of port A: 1'0 + Constant input on bit 1168 of port A: 1'0 + Constant input on bit 1169 of port A: 1'0 + Constant input on bit 1170 of port A: 1'0 + Constant input on bit 1171 of port A: 1'0 + Constant input on bit 1172 of port A: 1'0 + Constant input on bit 1173 of port A: 1'0 + Constant input on bit 1174 of port A: 1'0 + Constant input on bit 1175 of port A: 1'0 + Constant input on bit 1176 of port A: 1'0 + Constant input on bit 1177 of port A: 1'0 + Constant input on bit 1178 of port A: 1'0 + Constant input on bit 1179 of port A: 1'0 + Constant input on bit 1180 of port A: 1'0 + Constant input on bit 1181 of port A: 1'0 + Constant input on bit 1182 of port A: 1'0 + Constant input on bit 1183 of port A: 1'0 + Constant input on bit 1184 of port A: 1'0 + Constant input on bit 1185 of port A: 1'0 + Constant input on bit 1186 of port A: 1'0 + Constant input on bit 1187 of port A: 1'0 + Constant input on bit 1188 of port A: 1'0 + Constant input on bit 1189 of port A: 1'0 + Constant input on bit 1190 of port A: 1'0 + Constant input on bit 1191 of port A: 1'0 + Constant input on bit 1192 of port A: 1'0 + Constant input on bit 1193 of port A: 1'0 + Constant input on bit 1194 of port A: 1'0 + Constant input on bit 1195 of port A: 1'0 + Constant input on bit 1196 of port A: 1'0 + Constant input on bit 1197 of port A: 1'0 + Constant input on bit 1198 of port A: 1'0 + Constant input on bit 1199 of port A: 1'0 + Constant input on bit 1200 of port A: 1'0 + Constant input on bit 1201 of port A: 1'0 + Constant input on bit 1202 of port A: 1'0 + Constant input on bit 1203 of port A: 1'0 + Constant input on bit 1204 of port A: 1'0 + Constant input on bit 1205 of port A: 1'0 + Constant input on bit 1206 of port A: 1'0 + Constant input on bit 1207 of port A: 1'0 + Constant input on bit 1208 of port A: 1'0 + Constant input on bit 1209 of port A: 1'0 + Constant input on bit 1210 of port A: 1'0 + Constant input on bit 1211 of port A: 1'0 + Constant input on bit 1212 of port A: 1'0 + Constant input on bit 1213 of port A: 1'0 + Constant input on bit 1214 of port A: 1'0 + Constant input on bit 1215 of port A: 1'0 + Constant input on bit 1216 of port A: 1'0 + Constant input on bit 1217 of port A: 1'0 + Constant input on bit 1218 of port A: 1'0 + Constant input on bit 1219 of port A: 1'0 + Constant input on bit 1220 of port A: 1'0 + Constant input on bit 1221 of port A: 1'0 + Constant input on bit 1222 of port A: 1'0 + Constant input on bit 1223 of port A: 1'0 + Constant input on bit 1224 of port A: 1'0 + Constant input on bit 1225 of port A: 1'0 + Constant input on bit 1226 of port A: 1'0 + Constant input on bit 1227 of port A: 1'0 + Constant input on bit 1228 of port A: 1'0 + Constant input on bit 1229 of port A: 1'0 + Constant input on bit 1230 of port A: 1'0 + Constant input on bit 1231 of port A: 1'0 + Constant input on bit 1232 of port A: 1'0 + Constant input on bit 1233 of port A: 1'0 + Constant input on bit 1234 of port A: 1'0 + Constant input on bit 1235 of port A: 1'0 + Constant input on bit 1236 of port A: 1'0 + Constant input on bit 1237 of port A: 1'0 + Constant input on bit 1238 of port A: 1'0 + Constant input on bit 1239 of port A: 1'0 + Constant input on bit 1240 of port A: 1'0 + Constant input on bit 1241 of port A: 1'0 + Constant input on bit 1242 of port A: 1'0 + Constant input on bit 1243 of port A: 1'0 + Constant input on bit 1244 of port A: 1'0 + Constant input on bit 1245 of port A: 1'0 + Constant input on bit 1246 of port A: 1'0 + Constant input on bit 1247 of port A: 1'0 + Constant input on bit 1248 of port A: 1'0 + Constant input on bit 1249 of port A: 1'0 + Constant input on bit 1250 of port A: 1'0 + Constant input on bit 1251 of port A: 1'0 + Constant input on bit 1252 of port A: 1'0 + Constant input on bit 1253 of port A: 1'0 + Constant input on bit 1254 of port A: 1'0 + Constant input on bit 1255 of port A: 1'0 + Constant input on bit 1256 of port A: 1'0 + Constant input on bit 1257 of port A: 1'0 + Constant input on bit 1258 of port A: 1'0 + Constant input on bit 1259 of port A: 1'0 + Constant input on bit 1260 of port A: 1'0 + Constant input on bit 1261 of port A: 1'0 + Constant input on bit 1262 of port A: 1'0 + Constant input on bit 1263 of port A: 1'0 + Constant input on bit 1264 of port A: 1'0 + Constant input on bit 1265 of port A: 1'0 + Constant input on bit 1266 of port A: 1'0 + Constant input on bit 1267 of port A: 1'0 + Constant input on bit 1268 of port A: 1'0 + Constant input on bit 1269 of port A: 1'0 + Constant input on bit 1270 of port A: 1'0 + Constant input on bit 1271 of port A: 1'0 + Constant input on bit 1272 of port A: 1'0 + Constant input on bit 1273 of port A: 1'0 + Constant input on bit 1274 of port A: 1'0 + Constant input on bit 1275 of port A: 1'0 + Constant input on bit 1276 of port A: 1'0 + Constant input on bit 1277 of port A: 1'0 + Constant input on bit 1278 of port A: 1'0 + Constant input on bit 1279 of port A: 1'0 + Constant input on bit 1280 of port A: 1'0 + Constant input on bit 1281 of port A: 1'0 + Constant input on bit 1282 of port A: 1'0 + Constant input on bit 1283 of port A: 1'0 + Constant input on bit 1284 of port A: 1'0 + Constant input on bit 1285 of port A: 1'0 + Constant input on bit 1286 of port A: 1'0 + Constant input on bit 1287 of port A: 1'0 + Constant input on bit 1288 of port A: 1'0 + Constant input on bit 1289 of port A: 1'0 + Constant input on bit 1290 of port A: 1'0 + Constant input on bit 1291 of port A: 1'0 + Constant input on bit 1292 of port A: 1'0 + Constant input on bit 1293 of port A: 1'0 + Constant input on bit 1294 of port A: 1'0 + Constant input on bit 1295 of port A: 1'0 + Constant input on bit 1296 of port A: 1'0 + Constant input on bit 1297 of port A: 1'0 + Constant input on bit 1298 of port A: 1'0 + Constant input on bit 1299 of port A: 1'0 + Constant input on bit 1300 of port A: 1'0 + Constant input on bit 1301 of port A: 1'0 + Constant input on bit 1302 of port A: 1'0 + Constant input on bit 1303 of port A: 1'0 + Constant input on bit 1304 of port A: 1'0 + Constant input on bit 1305 of port A: 1'0 + Constant input on bit 1306 of port A: 1'0 + Constant input on bit 1307 of port A: 1'0 + Constant input on bit 1308 of port A: 1'0 + Constant input on bit 1309 of port A: 1'0 + Constant input on bit 1310 of port A: 1'0 + Constant input on bit 1311 of port A: 1'0 + Constant input on bit 1312 of port A: 1'0 + Constant input on bit 1313 of port A: 1'0 + Constant input on bit 1314 of port A: 1'0 + Constant input on bit 1315 of port A: 1'0 + Constant input on bit 1316 of port A: 1'0 + Constant input on bit 1317 of port A: 1'0 + Constant input on bit 1318 of port A: 1'0 + Constant input on bit 1319 of port A: 1'0 + Constant input on bit 1320 of port A: 1'0 + Constant input on bit 1321 of port A: 1'0 + Constant input on bit 1322 of port A: 1'0 + Constant input on bit 1323 of port A: 1'0 + Constant input on bit 1324 of port A: 1'0 + Constant input on bit 1325 of port A: 1'0 + Constant input on bit 1326 of port A: 1'0 + Constant input on bit 1327 of port A: 1'0 + Constant input on bit 1328 of port A: 1'0 + Constant input on bit 1329 of port A: 1'0 + Constant input on bit 1330 of port A: 1'0 + Constant input on bit 1331 of port A: 1'0 + Constant input on bit 1332 of port A: 1'0 + Constant input on bit 1333 of port A: 1'0 + Constant input on bit 1334 of port A: 1'0 + Constant input on bit 1335 of port A: 1'0 + Constant input on bit 1336 of port A: 1'0 + Constant input on bit 1337 of port A: 1'0 + Constant input on bit 1338 of port A: 1'0 + Constant input on bit 1339 of port A: 1'0 + Constant input on bit 1340 of port A: 1'0 + Constant input on bit 1341 of port A: 1'0 + Constant input on bit 1342 of port A: 1'0 + Constant input on bit 1343 of port A: 1'0 + Constant input on bit 1344 of port A: 1'0 + Constant input on bit 1345 of port A: 1'0 + Constant input on bit 1346 of port A: 1'0 + Constant input on bit 1347 of port A: 1'0 + Constant input on bit 1348 of port A: 1'0 + Constant input on bit 1349 of port A: 1'0 + Constant input on bit 1350 of port A: 1'0 + Constant input on bit 1351 of port A: 1'0 + Constant input on bit 1352 of port A: 1'0 + Constant input on bit 1353 of port A: 1'0 + Constant input on bit 1354 of port A: 1'0 + Constant input on bit 1355 of port A: 1'0 + Constant input on bit 1356 of port A: 1'0 + Constant input on bit 1357 of port A: 1'0 + Constant input on bit 1358 of port A: 1'0 + Constant input on bit 1359 of port A: 1'0 + Constant input on bit 1360 of port A: 1'0 + Constant input on bit 1361 of port A: 1'0 + Constant input on bit 1362 of port A: 1'0 + Constant input on bit 1363 of port A: 1'0 + Constant input on bit 1364 of port A: 1'0 + Constant input on bit 1365 of port A: 1'0 + Constant input on bit 1366 of port A: 1'0 + Constant input on bit 1367 of port A: 1'0 + Constant input on bit 1368 of port A: 1'0 + Constant input on bit 1369 of port A: 1'0 + Constant input on bit 1370 of port A: 1'0 + Constant input on bit 1371 of port A: 1'0 + Constant input on bit 1372 of port A: 1'0 + Constant input on bit 1373 of port A: 1'0 + Constant input on bit 1374 of port A: 1'0 + Constant input on bit 1375 of port A: 1'0 + Constant input on bit 1376 of port A: 1'0 + Constant input on bit 1377 of port A: 1'0 + Constant input on bit 1378 of port A: 1'0 + Constant input on bit 1379 of port A: 1'0 + Constant input on bit 1380 of port A: 1'0 + Constant input on bit 1381 of port A: 1'0 + Constant input on bit 1382 of port A: 1'0 + Constant input on bit 1383 of port A: 1'0 + Constant input on bit 1384 of port A: 1'0 + Constant input on bit 1385 of port A: 1'0 + Constant input on bit 1386 of port A: 1'0 + Constant input on bit 1387 of port A: 1'0 + Constant input on bit 1388 of port A: 1'0 + Constant input on bit 1389 of port A: 1'0 + Constant input on bit 1390 of port A: 1'0 + Constant input on bit 1391 of port A: 1'0 + Constant input on bit 1392 of port A: 1'0 + Constant input on bit 1393 of port A: 1'0 + Constant input on bit 1394 of port A: 1'0 + Constant input on bit 1395 of port A: 1'0 + Constant input on bit 1396 of port A: 1'0 + Constant input on bit 1397 of port A: 1'0 + Constant input on bit 1398 of port A: 1'0 + Constant input on bit 1399 of port A: 1'0 + Constant input on bit 1400 of port A: 1'0 + Constant input on bit 1401 of port A: 1'0 + Constant input on bit 1402 of port A: 1'0 + Constant input on bit 1403 of port A: 1'0 + Constant input on bit 1404 of port A: 1'0 + Constant input on bit 1405 of port A: 1'0 + Constant input on bit 1406 of port A: 1'0 + Constant input on bit 1407 of port A: 1'0 + Constant input on bit 1408 of port A: 1'0 + Constant input on bit 1409 of port A: 1'0 + Constant input on bit 1410 of port A: 1'0 + Constant input on bit 1411 of port A: 1'0 + Constant input on bit 1412 of port A: 1'0 + Constant input on bit 1413 of port A: 1'0 + Constant input on bit 1414 of port A: 1'0 + Constant input on bit 1415 of port A: 1'0 + Constant input on bit 1416 of port A: 1'0 + Constant input on bit 1417 of port A: 1'0 + Constant input on bit 1418 of port A: 1'0 + Constant input on bit 1419 of port A: 1'0 + Constant input on bit 1420 of port A: 1'0 + Constant input on bit 1421 of port A: 1'0 + Constant input on bit 1422 of port A: 1'0 + Constant input on bit 1423 of port A: 1'0 + Constant input on bit 1424 of port A: 1'0 + Constant input on bit 1425 of port A: 1'0 + Constant input on bit 1426 of port A: 1'0 + Constant input on bit 1427 of port A: 1'0 + Constant input on bit 1428 of port A: 1'0 + Constant input on bit 1429 of port A: 1'0 + Constant input on bit 1430 of port A: 1'0 + Constant input on bit 1431 of port A: 1'0 + Constant input on bit 1432 of port A: 1'0 + Constant input on bit 1433 of port A: 1'0 + Constant input on bit 1434 of port A: 1'0 + Constant input on bit 1435 of port A: 1'0 + Constant input on bit 1436 of port A: 1'0 + Constant input on bit 1437 of port A: 1'0 + Constant input on bit 1438 of port A: 1'0 + Constant input on bit 1439 of port A: 1'0 + Constant input on bit 1440 of port A: 1'0 + Constant input on bit 1441 of port A: 1'0 + Constant input on bit 1442 of port A: 1'0 + Constant input on bit 1443 of port A: 1'0 + Constant input on bit 1444 of port A: 1'0 + Constant input on bit 1445 of port A: 1'0 + Constant input on bit 1446 of port A: 1'0 + Constant input on bit 1447 of port A: 1'0 + Constant input on bit 1448 of port A: 1'0 + Constant input on bit 1449 of port A: 1'0 + Constant input on bit 1450 of port A: 1'0 + Constant input on bit 1451 of port A: 1'0 + Constant input on bit 1452 of port A: 1'0 + Constant input on bit 1453 of port A: 1'0 + Constant input on bit 1454 of port A: 1'0 + Constant input on bit 1455 of port A: 1'0 + Constant input on bit 1456 of port A: 1'0 + Constant input on bit 1457 of port A: 1'0 + Constant input on bit 1458 of port A: 1'0 + Constant input on bit 1459 of port A: 1'0 + Constant input on bit 1460 of port A: 1'0 + Constant input on bit 1461 of port A: 1'0 + Constant input on bit 1462 of port A: 1'0 + Constant input on bit 1463 of port A: 1'0 + Constant input on bit 1464 of port A: 1'0 + Constant input on bit 1465 of port A: 1'0 + Constant input on bit 1466 of port A: 1'0 + Constant input on bit 1467 of port A: 1'0 + Constant input on bit 1468 of port A: 1'0 + Constant input on bit 1469 of port A: 1'0 + Constant input on bit 1470 of port A: 1'0 + Constant input on bit 1471 of port A: 1'0 + Constant input on bit 1472 of port A: 1'0 + Constant input on bit 1473 of port A: 1'0 + Constant input on bit 1474 of port A: 1'0 + Constant input on bit 1475 of port A: 1'0 + Constant input on bit 1476 of port A: 1'0 + Constant input on bit 1477 of port A: 1'0 + Constant input on bit 1478 of port A: 1'0 + Constant input on bit 1479 of port A: 1'0 + Constant input on bit 1480 of port A: 1'0 + Constant input on bit 1481 of port A: 1'0 + Constant input on bit 1482 of port A: 1'0 + Constant input on bit 1483 of port A: 1'0 + Constant input on bit 1484 of port A: 1'0 + Constant input on bit 1485 of port A: 1'0 + Constant input on bit 1486 of port A: 1'0 + Constant input on bit 1487 of port A: 1'0 + Constant input on bit 1488 of port A: 1'0 + Constant input on bit 1489 of port A: 1'0 + Constant input on bit 1490 of port A: 1'0 + Constant input on bit 1491 of port A: 1'0 + Constant input on bit 1492 of port A: 1'0 + Constant input on bit 1493 of port A: 1'0 + Constant input on bit 1494 of port A: 1'0 + Constant input on bit 1495 of port A: 1'0 + Constant input on bit 1496 of port A: 1'0 + Constant input on bit 1497 of port A: 1'0 + Constant input on bit 1498 of port A: 1'0 + Constant input on bit 1499 of port A: 1'0 + Constant input on bit 1500 of port A: 1'0 + Constant input on bit 1501 of port A: 1'0 + Constant input on bit 1502 of port A: 1'0 + Constant input on bit 1503 of port A: 1'0 + Constant input on bit 1504 of port A: 1'0 + Constant input on bit 1505 of port A: 1'0 + Constant input on bit 1506 of port A: 1'0 + Constant input on bit 1507 of port A: 1'0 + Constant input on bit 1508 of port A: 1'0 + Constant input on bit 1509 of port A: 1'0 + Constant input on bit 1510 of port A: 1'0 + Constant input on bit 1511 of port A: 1'0 + Constant input on bit 1512 of port A: 1'0 + Constant input on bit 1513 of port A: 1'0 + Constant input on bit 1514 of port A: 1'0 + Constant input on bit 1515 of port A: 1'0 + Constant input on bit 1516 of port A: 1'0 + Constant input on bit 1517 of port A: 1'0 + Constant input on bit 1518 of port A: 1'0 + Constant input on bit 1519 of port A: 1'0 + Constant input on bit 1520 of port A: 1'0 + Constant input on bit 1521 of port A: 1'0 + Constant input on bit 1522 of port A: 1'0 + Constant input on bit 1523 of port A: 1'0 + Constant input on bit 1524 of port A: 1'0 + Constant input on bit 1525 of port A: 1'0 + Constant input on bit 1526 of port A: 1'0 + Constant input on bit 1527 of port A: 1'0 + Constant input on bit 1528 of port A: 1'0 + Constant input on bit 1529 of port A: 1'0 + Constant input on bit 1530 of port A: 1'0 + Constant input on bit 1531 of port A: 1'0 + Constant input on bit 1532 of port A: 1'0 + Constant input on bit 1533 of port A: 1'0 + Constant input on bit 1534 of port A: 1'0 + Constant input on bit 1535 of port A: 1'0 + Constant input on bit 1536 of port A: 1'0 + Constant input on bit 1537 of port A: 1'0 + Constant input on bit 1538 of port A: 1'0 + Constant input on bit 1539 of port A: 1'0 + Constant input on bit 1540 of port A: 1'0 + Constant input on bit 1541 of port A: 1'0 + Constant input on bit 1542 of port A: 1'0 + Constant input on bit 1543 of port A: 1'0 + Constant input on bit 1544 of port A: 1'0 + Constant input on bit 1545 of port A: 1'0 + Constant input on bit 1546 of port A: 1'0 + Constant input on bit 1547 of port A: 1'0 + Constant input on bit 1548 of port A: 1'0 + Constant input on bit 1549 of port A: 1'0 + Constant input on bit 1550 of port A: 1'0 + Constant input on bit 1551 of port A: 1'0 + Constant input on bit 1552 of port A: 1'0 + Constant input on bit 1553 of port A: 1'0 + Constant input on bit 1554 of port A: 1'0 + Constant input on bit 1555 of port A: 1'0 + Constant input on bit 1556 of port A: 1'0 + Constant input on bit 1557 of port A: 1'0 + Constant input on bit 1558 of port A: 1'0 + Constant input on bit 1559 of port A: 1'0 + Constant input on bit 1560 of port A: 1'0 + Constant input on bit 1561 of port A: 1'0 + Constant input on bit 1562 of port A: 1'0 + Constant input on bit 1563 of port A: 1'0 + Constant input on bit 1564 of port A: 1'0 + Constant input on bit 1565 of port A: 1'0 + Constant input on bit 1566 of port A: 1'0 + Constant input on bit 1567 of port A: 1'0 + Constant input on bit 1568 of port A: 1'0 + Constant input on bit 1569 of port A: 1'0 + Constant input on bit 1570 of port A: 1'0 + Constant input on bit 1571 of port A: 1'0 + Constant input on bit 1572 of port A: 1'0 + Constant input on bit 1573 of port A: 1'0 + Constant input on bit 1574 of port A: 1'0 + Constant input on bit 1575 of port A: 1'0 + Constant input on bit 1576 of port A: 1'0 + Constant input on bit 1577 of port A: 1'0 + Constant input on bit 1578 of port A: 1'0 + Constant input on bit 1579 of port A: 1'0 + Constant input on bit 1580 of port A: 1'0 + Constant input on bit 1581 of port A: 1'0 + Constant input on bit 1582 of port A: 1'0 + Constant input on bit 1583 of port A: 1'0 + Constant input on bit 1584 of port A: 1'0 + Constant input on bit 1585 of port A: 1'0 + Constant input on bit 1586 of port A: 1'0 + Constant input on bit 1587 of port A: 1'0 + Constant input on bit 1588 of port A: 1'0 + Constant input on bit 1589 of port A: 1'0 + Constant input on bit 1590 of port A: 1'0 + Constant input on bit 1591 of port A: 1'0 + Constant input on bit 1592 of port A: 1'0 + Constant input on bit 1593 of port A: 1'0 + Constant input on bit 1594 of port A: 1'0 + Constant input on bit 1595 of port A: 1'0 + Constant input on bit 1596 of port A: 1'0 + Constant input on bit 1597 of port A: 1'0 + Constant input on bit 1598 of port A: 1'0 + Constant input on bit 1599 of port A: 1'0 + Constant input on bit 1600 of port A: 1'0 + Constant input on bit 1601 of port A: 1'0 + Constant input on bit 1602 of port A: 1'0 + Constant input on bit 1603 of port A: 1'0 + Constant input on bit 1604 of port A: 1'0 + Constant input on bit 1605 of port A: 1'0 + Constant input on bit 1606 of port A: 1'0 + Constant input on bit 1607 of port A: 1'0 + Constant input on bit 1608 of port A: 1'0 + Constant input on bit 1609 of port A: 1'0 + Constant input on bit 1610 of port A: 1'0 + Constant input on bit 1611 of port A: 1'0 + Constant input on bit 1612 of port A: 1'0 + Constant input on bit 1613 of port A: 1'0 + Constant input on bit 1614 of port A: 1'0 + Constant input on bit 1615 of port A: 1'0 + Constant input on bit 1616 of port A: 1'0 + Constant input on bit 1617 of port A: 1'0 + Constant input on bit 1618 of port A: 1'0 + Constant input on bit 1619 of port A: 1'0 + Constant input on bit 1620 of port A: 1'0 + Constant input on bit 1621 of port A: 1'0 + Constant input on bit 1622 of port A: 1'0 + Constant input on bit 1623 of port A: 1'0 + Constant input on bit 1624 of port A: 1'0 + Constant input on bit 1625 of port A: 1'0 + Constant input on bit 1626 of port A: 1'0 + Constant input on bit 1627 of port A: 1'0 + Constant input on bit 1628 of port A: 1'0 + Constant input on bit 1629 of port A: 1'0 + Constant input on bit 1630 of port A: 1'0 + Constant input on bit 1631 of port A: 1'0 + Constant input on bit 1632 of port A: 1'0 + Constant input on bit 1633 of port A: 1'0 + Constant input on bit 1634 of port A: 1'0 + Constant input on bit 1635 of port A: 1'0 + Constant input on bit 1636 of port A: 1'0 + Constant input on bit 1637 of port A: 1'0 + Constant input on bit 1638 of port A: 1'0 + Constant input on bit 1639 of port A: 1'0 + Constant input on bit 1640 of port A: 1'0 + Constant input on bit 1641 of port A: 1'0 + Constant input on bit 1642 of port A: 1'0 + Constant input on bit 1643 of port A: 1'0 + Constant input on bit 1644 of port A: 1'0 + Constant input on bit 1645 of port A: 1'0 + Constant input on bit 1646 of port A: 1'0 + Constant input on bit 1647 of port A: 1'0 + Constant input on bit 1648 of port A: 1'0 + Constant input on bit 1649 of port A: 1'0 + Constant input on bit 1650 of port A: 1'0 + Constant input on bit 1651 of port A: 1'0 + Constant input on bit 1652 of port A: 1'0 + Constant input on bit 1653 of port A: 1'0 + Constant input on bit 1654 of port A: 1'0 + Constant input on bit 1655 of port A: 1'0 + Constant input on bit 1656 of port A: 1'0 + Constant input on bit 1657 of port A: 1'0 + Constant input on bit 1658 of port A: 1'0 + Constant input on bit 1659 of port A: 1'0 + Constant input on bit 1660 of port A: 1'0 + Constant input on bit 1661 of port A: 1'0 + Constant input on bit 1662 of port A: 1'0 + Constant input on bit 1663 of port A: 1'0 + Constant input on bit 1664 of port A: 1'0 + Constant input on bit 1665 of port A: 1'0 + Constant input on bit 1666 of port A: 1'0 + Constant input on bit 1667 of port A: 1'0 + Constant input on bit 1668 of port A: 1'0 + Constant input on bit 1669 of port A: 1'0 + Constant input on bit 1670 of port A: 1'0 + Constant input on bit 1671 of port A: 1'0 + Constant input on bit 1672 of port A: 1'0 + Constant input on bit 1673 of port A: 1'0 + Constant input on bit 1674 of port A: 1'0 + Constant input on bit 1675 of port A: 1'0 + Constant input on bit 1676 of port A: 1'0 + Constant input on bit 1677 of port A: 1'0 + Constant input on bit 1678 of port A: 1'0 + Constant input on bit 1679 of port A: 1'0 + Constant input on bit 1680 of port A: 1'0 + Constant input on bit 1681 of port A: 1'0 + Constant input on bit 1682 of port A: 1'0 + Constant input on bit 1683 of port A: 1'0 + Constant input on bit 1684 of port A: 1'0 + Constant input on bit 1685 of port A: 1'0 + Constant input on bit 1686 of port A: 1'0 + Constant input on bit 1687 of port A: 1'0 + Constant input on bit 1688 of port A: 1'0 + Constant input on bit 1689 of port A: 1'0 + Constant input on bit 1690 of port A: 1'0 + Constant input on bit 1691 of port A: 1'0 + Constant input on bit 1692 of port A: 1'0 + Constant input on bit 1693 of port A: 1'0 + Constant input on bit 1694 of port A: 1'0 + Constant input on bit 1695 of port A: 1'0 + Constant input on bit 1696 of port A: 1'0 + Constant input on bit 1697 of port A: 1'0 + Constant input on bit 1698 of port A: 1'0 + Constant input on bit 1699 of port A: 1'0 + Constant input on bit 1700 of port A: 1'0 + Constant input on bit 1701 of port A: 1'0 + Constant input on bit 1702 of port A: 1'0 + Constant input on bit 1703 of port A: 1'0 + Constant input on bit 1704 of port A: 1'0 + Constant input on bit 1705 of port A: 1'0 + Constant input on bit 1706 of port A: 1'0 + Constant input on bit 1707 of port A: 1'0 + Constant input on bit 1708 of port A: 1'0 + Constant input on bit 1709 of port A: 1'0 + Constant input on bit 1710 of port A: 1'0 + Constant input on bit 1711 of port A: 1'0 + Constant input on bit 1712 of port A: 1'0 + Constant input on bit 1713 of port A: 1'0 + Constant input on bit 1714 of port A: 1'0 + Constant input on bit 1715 of port A: 1'0 + Constant input on bit 1716 of port A: 1'0 + Constant input on bit 1717 of port A: 1'0 + Constant input on bit 1718 of port A: 1'0 + Constant input on bit 1719 of port A: 1'0 + Constant input on bit 1720 of port A: 1'0 + Constant input on bit 1721 of port A: 1'0 + Constant input on bit 1722 of port A: 1'0 + Constant input on bit 1723 of port A: 1'0 + Constant input on bit 1724 of port A: 1'0 + Constant input on bit 1725 of port A: 1'0 + Constant input on bit 1726 of port A: 1'0 + Constant input on bit 1727 of port A: 1'0 + Constant input on bit 1728 of port A: 1'0 + Constant input on bit 1729 of port A: 1'0 + Constant input on bit 1730 of port A: 1'0 + Constant input on bit 1731 of port A: 1'0 + Constant input on bit 1732 of port A: 1'0 + Constant input on bit 1733 of port A: 1'0 + Constant input on bit 1734 of port A: 1'0 + Constant input on bit 1735 of port A: 1'0 + Constant input on bit 1736 of port A: 1'0 + Constant input on bit 1737 of port A: 1'0 + Constant input on bit 1738 of port A: 1'0 + Constant input on bit 1739 of port A: 1'0 + Constant input on bit 1740 of port A: 1'0 + Constant input on bit 1741 of port A: 1'0 + Constant input on bit 1742 of port A: 1'0 + Constant input on bit 1743 of port A: 1'0 + Constant input on bit 1744 of port A: 1'0 + Constant input on bit 1745 of port A: 1'0 + Constant input on bit 1746 of port A: 1'0 + Constant input on bit 1747 of port A: 1'0 + Constant input on bit 1748 of port A: 1'0 + Constant input on bit 1749 of port A: 1'0 + Constant input on bit 1750 of port A: 1'0 + Constant input on bit 1751 of port A: 1'0 + Constant input on bit 1752 of port A: 1'0 + Constant input on bit 1753 of port A: 1'0 + Constant input on bit 1754 of port A: 1'0 + Constant input on bit 1755 of port A: 1'0 + Constant input on bit 1756 of port A: 1'0 + Constant input on bit 1757 of port A: 1'0 + Constant input on bit 1758 of port A: 1'0 + Constant input on bit 1759 of port A: 1'0 + Constant input on bit 1760 of port A: 1'0 + Constant input on bit 1761 of port A: 1'0 + Constant input on bit 1762 of port A: 1'0 + Constant input on bit 1763 of port A: 1'0 + Constant input on bit 1764 of port A: 1'0 + Constant input on bit 1765 of port A: 1'0 + Constant input on bit 1766 of port A: 1'0 + Constant input on bit 1767 of port A: 1'0 + Constant input on bit 1768 of port A: 1'0 + Constant input on bit 1769 of port A: 1'0 + Constant input on bit 1770 of port A: 1'0 + Constant input on bit 1771 of port A: 1'0 + Constant input on bit 1772 of port A: 1'0 + Constant input on bit 1773 of port A: 1'0 + Constant input on bit 1774 of port A: 1'0 + Constant input on bit 1775 of port A: 1'0 + Constant input on bit 1776 of port A: 1'0 + Constant input on bit 1777 of port A: 1'0 + Constant input on bit 1778 of port A: 1'0 + Constant input on bit 1779 of port A: 1'0 + Constant input on bit 1780 of port A: 1'0 + Constant input on bit 1781 of port A: 1'0 + Constant input on bit 1782 of port A: 1'0 + Constant input on bit 1783 of port A: 1'0 + Constant input on bit 1784 of port A: 1'0 + Constant input on bit 1785 of port A: 1'0 + Constant input on bit 1786 of port A: 1'0 + Constant input on bit 1787 of port A: 1'0 + Constant input on bit 1788 of port A: 1'0 + Constant input on bit 1789 of port A: 1'0 + Constant input on bit 1790 of port A: 1'0 + Constant input on bit 1791 of port A: 1'0 + Constant input on bit 1792 of port A: 1'0 + Constant input on bit 1793 of port A: 1'0 + Constant input on bit 1794 of port A: 1'0 + Constant input on bit 1795 of port A: 1'0 + Constant input on bit 1796 of port A: 1'0 + Constant input on bit 1797 of port A: 1'0 + Constant input on bit 1798 of port A: 1'0 + Constant input on bit 1799 of port A: 1'0 + Constant input on bit 1800 of port A: 1'0 + Constant input on bit 1801 of port A: 1'0 + Constant input on bit 1802 of port A: 1'0 + Constant input on bit 1803 of port A: 1'0 + Constant input on bit 1804 of port A: 1'0 + Constant input on bit 1805 of port A: 1'0 + Constant input on bit 1806 of port A: 1'0 + Constant input on bit 1807 of port A: 1'0 + Constant input on bit 1808 of port A: 1'0 + Constant input on bit 1809 of port A: 1'0 + Constant input on bit 1810 of port A: 1'0 + Constant input on bit 1811 of port A: 1'0 + Constant input on bit 1812 of port A: 1'0 + Constant input on bit 1813 of port A: 1'0 + Constant input on bit 1814 of port A: 1'0 + Constant input on bit 1815 of port A: 1'0 + Constant input on bit 1816 of port A: 1'0 + Constant input on bit 1817 of port A: 1'0 + Constant input on bit 1818 of port A: 1'0 + Constant input on bit 1819 of port A: 1'0 + Constant input on bit 1820 of port A: 1'0 + Constant input on bit 1821 of port A: 1'0 + Constant input on bit 1822 of port A: 1'0 + Constant input on bit 1823 of port A: 1'0 + Constant input on bit 1824 of port A: 1'0 + Constant input on bit 1825 of port A: 1'0 + Constant input on bit 1826 of port A: 1'0 + Constant input on bit 1827 of port A: 1'0 + Constant input on bit 1828 of port A: 1'0 + Constant input on bit 1829 of port A: 1'0 + Constant input on bit 1830 of port A: 1'0 + Constant input on bit 1831 of port A: 1'0 + Constant input on bit 1832 of port A: 1'0 + Constant input on bit 1833 of port A: 1'0 + Constant input on bit 1834 of port A: 1'0 + Constant input on bit 1835 of port A: 1'0 + Constant input on bit 1836 of port A: 1'0 + Constant input on bit 1837 of port A: 1'0 + Constant input on bit 1838 of port A: 1'0 + Constant input on bit 1839 of port A: 1'0 + Constant input on bit 1840 of port A: 1'0 + Constant input on bit 1841 of port A: 1'0 + Constant input on bit 1842 of port A: 1'0 + Constant input on bit 1843 of port A: 1'0 + Constant input on bit 1844 of port A: 1'0 + Constant input on bit 1845 of port A: 1'0 + Constant input on bit 1846 of port A: 1'0 + Constant input on bit 1847 of port A: 1'0 + Constant input on bit 1848 of port A: 1'0 + Constant input on bit 1849 of port A: 1'0 + Constant input on bit 1850 of port A: 1'0 + Constant input on bit 1851 of port A: 1'0 + Constant input on bit 1852 of port A: 1'0 + Constant input on bit 1853 of port A: 1'0 + Constant input on bit 1854 of port A: 1'0 + Constant input on bit 1855 of port A: 1'0 + Constant input on bit 1856 of port A: 1'0 + Constant input on bit 1857 of port A: 1'0 + Constant input on bit 1858 of port A: 1'0 + Constant input on bit 1859 of port A: 1'0 + Constant input on bit 1860 of port A: 1'0 + Constant input on bit 1861 of port A: 1'0 + Constant input on bit 1862 of port A: 1'0 + Constant input on bit 1863 of port A: 1'0 + Constant input on bit 1864 of port A: 1'0 + Constant input on bit 1865 of port A: 1'0 + Constant input on bit 1866 of port A: 1'0 + Constant input on bit 1867 of port A: 1'0 + Constant input on bit 1868 of port A: 1'0 + Constant input on bit 1869 of port A: 1'0 + Constant input on bit 1870 of port A: 1'0 + Constant input on bit 1871 of port A: 1'0 + Constant input on bit 1872 of port A: 1'0 + Constant input on bit 1873 of port A: 1'0 + Constant input on bit 1874 of port A: 1'0 + Constant input on bit 1875 of port A: 1'0 + Constant input on bit 1876 of port A: 1'0 + Constant input on bit 1877 of port A: 1'0 + Constant input on bit 1878 of port A: 1'0 + Constant input on bit 1879 of port A: 1'0 + Constant input on bit 1880 of port A: 1'0 + Constant input on bit 1881 of port A: 1'0 + Constant input on bit 1882 of port A: 1'0 + Constant input on bit 1883 of port A: 1'0 + Constant input on bit 1884 of port A: 1'0 + Constant input on bit 1885 of port A: 1'0 + Constant input on bit 1886 of port A: 1'0 + Constant input on bit 1887 of port A: 1'0 + Constant input on bit 1888 of port A: 1'0 + Constant input on bit 1889 of port A: 1'0 + Constant input on bit 1890 of port A: 1'0 + Constant input on bit 1891 of port A: 1'0 + Constant input on bit 1892 of port A: 1'0 + Constant input on bit 1893 of port A: 1'0 + Constant input on bit 1894 of port A: 1'0 + Constant input on bit 1895 of port A: 1'0 + Constant input on bit 1896 of port A: 1'0 + Constant input on bit 1897 of port A: 1'0 + Constant input on bit 1898 of port A: 1'0 + Constant input on bit 1899 of port A: 1'0 + Constant input on bit 1900 of port A: 1'0 + Constant input on bit 1901 of port A: 1'0 + Constant input on bit 1902 of port A: 1'0 + Constant input on bit 1903 of port A: 1'0 + Constant input on bit 1904 of port A: 1'0 + Constant input on bit 1905 of port A: 1'0 + Constant input on bit 1906 of port A: 1'0 + Constant input on bit 1907 of port A: 1'0 + Constant input on bit 1908 of port A: 1'0 + Constant input on bit 1909 of port A: 1'0 + Constant input on bit 1910 of port A: 1'0 + Constant input on bit 1911 of port A: 1'0 + Constant input on bit 1912 of port A: 1'0 + Constant input on bit 1913 of port A: 1'0 + Constant input on bit 1914 of port A: 1'0 + Constant input on bit 1915 of port A: 1'0 + Constant input on bit 1916 of port A: 1'0 + Constant input on bit 1917 of port A: 1'0 + Constant input on bit 1918 of port A: 1'0 + Constant input on bit 1919 of port A: 1'0 + Constant input on bit 1920 of port A: 1'0 + Constant input on bit 1921 of port A: 1'0 + Constant input on bit 1922 of port A: 1'0 + Constant input on bit 1923 of port A: 1'0 + Constant input on bit 1924 of port A: 1'0 + Constant input on bit 1925 of port A: 1'0 + Constant input on bit 1926 of port A: 1'0 + Constant input on bit 1927 of port A: 1'0 + Constant input on bit 1928 of port A: 1'0 + Constant input on bit 1929 of port A: 1'0 + Constant input on bit 1930 of port A: 1'0 + Constant input on bit 1931 of port A: 1'0 + Constant input on bit 1932 of port A: 1'0 + Constant input on bit 1933 of port A: 1'0 + Constant input on bit 1934 of port A: 1'0 + Constant input on bit 1935 of port A: 1'0 + Constant input on bit 1936 of port A: 1'0 + Constant input on bit 1937 of port A: 1'0 + Constant input on bit 1938 of port A: 1'0 + Constant input on bit 1939 of port A: 1'0 + Constant input on bit 1940 of port A: 1'0 + Constant input on bit 1941 of port A: 1'0 + Constant input on bit 1942 of port A: 1'0 + Constant input on bit 1943 of port A: 1'0 + Constant input on bit 1944 of port A: 1'0 + Constant input on bit 1945 of port A: 1'0 + Constant input on bit 1946 of port A: 1'0 + Constant input on bit 1947 of port A: 1'0 + Constant input on bit 1948 of port A: 1'0 + Constant input on bit 1949 of port A: 1'0 + Constant input on bit 1950 of port A: 1'0 + Constant input on bit 1951 of port A: 1'0 + Constant input on bit 1952 of port A: 1'0 + Constant input on bit 1953 of port A: 1'0 + Constant input on bit 1954 of port A: 1'0 + Constant input on bit 1955 of port A: 1'0 + Constant input on bit 1956 of port A: 1'0 + Constant input on bit 1957 of port A: 1'0 + Constant input on bit 1958 of port A: 1'0 + Constant input on bit 1959 of port A: 1'0 + Constant input on bit 1960 of port A: 1'0 + Constant input on bit 1961 of port A: 1'0 + Constant input on bit 1962 of port A: 1'0 + Constant input on bit 1963 of port A: 1'0 + Constant input on bit 1964 of port A: 1'0 + Constant input on bit 1965 of port A: 1'0 + Constant input on bit 1966 of port A: 1'0 + Constant input on bit 1967 of port A: 1'0 + Constant input on bit 1968 of port A: 1'0 + Constant input on bit 1969 of port A: 1'0 + Constant input on bit 1970 of port A: 1'0 + Constant input on bit 1971 of port A: 1'0 + Constant input on bit 1972 of port A: 1'0 + Constant input on bit 1973 of port A: 1'0 + Constant input on bit 1974 of port A: 1'0 + Constant input on bit 1975 of port A: 1'0 + Constant input on bit 1976 of port A: 1'0 + Constant input on bit 1977 of port A: 1'0 + Constant input on bit 1978 of port A: 1'0 + Constant input on bit 1979 of port A: 1'0 + Constant input on bit 1980 of port A: 1'0 + Constant input on bit 1981 of port A: 1'0 + Constant input on bit 1982 of port A: 1'0 + Constant input on bit 1983 of port A: 1'0 + Constant input on bit 1984 of port A: 1'0 + Constant input on bit 1985 of port A: 1'0 + Constant input on bit 1986 of port A: 1'0 + Constant input on bit 1987 of port A: 1'0 + Constant input on bit 1988 of port A: 1'0 + Constant input on bit 1989 of port A: 1'0 + Constant input on bit 1990 of port A: 1'0 + Constant input on bit 1991 of port A: 1'0 + Constant input on bit 1992 of port A: 1'0 + Constant input on bit 1993 of port A: 1'0 + Constant input on bit 1994 of port A: 1'0 + Constant input on bit 1995 of port A: 1'0 + Constant input on bit 1996 of port A: 1'0 + Constant input on bit 1997 of port A: 1'0 + Constant input on bit 1998 of port A: 1'0 + Constant input on bit 1999 of port A: 1'0 + Constant input on bit 2000 of port A: 1'0 + Constant input on bit 2001 of port A: 1'0 + Constant input on bit 2002 of port A: 1'0 + Constant input on bit 2003 of port A: 1'0 + Constant input on bit 2004 of port A: 1'0 + Constant input on bit 2005 of port A: 1'0 + Constant input on bit 2006 of port A: 1'0 + Constant input on bit 2007 of port A: 1'0 + Constant input on bit 2008 of port A: 1'0 + Constant input on bit 2009 of port A: 1'0 + Constant input on bit 2010 of port A: 1'0 + Constant input on bit 2011 of port A: 1'0 + Constant input on bit 2012 of port A: 1'0 + Constant input on bit 2013 of port A: 1'0 + Constant input on bit 2014 of port A: 1'0 + Constant input on bit 2015 of port A: 1'0 + Constant input on bit 2016 of port A: 1'0 + Constant input on bit 2017 of port A: 1'0 + Constant input on bit 2018 of port A: 1'0 + Constant input on bit 2019 of port A: 1'0 + Constant input on bit 2020 of port A: 1'0 + Constant input on bit 2021 of port A: 1'0 + Constant input on bit 2022 of port A: 1'0 + Constant input on bit 2023 of port A: 1'0 + Constant input on bit 2024 of port A: 1'0 + Constant input on bit 2025 of port A: 1'0 + Constant input on bit 2026 of port A: 1'0 + Constant input on bit 2027 of port A: 1'0 + Constant input on bit 2028 of port A: 1'0 + Constant input on bit 2029 of port A: 1'0 + Constant input on bit 2030 of port A: 1'0 + Constant input on bit 2031 of port A: 1'0 + Constant input on bit 2032 of port A: 1'0 + Constant input on bit 2033 of port A: 1'0 + Constant input on bit 2034 of port A: 1'0 + Constant input on bit 2035 of port A: 1'0 + Constant input on bit 2036 of port A: 1'0 + Constant input on bit 2037 of port A: 1'0 + Constant input on bit 2038 of port A: 1'0 + Constant input on bit 2039 of port A: 1'0 + Constant input on bit 2040 of port A: 1'0 + Constant input on bit 2041 of port A: 1'0 + Constant input on bit 2042 of port A: 1'0 + Constant input on bit 2043 of port A: 1'0 + Constant input on bit 2044 of port A: 1'0 + Constant input on bit 2045 of port A: 1'0 + Constant input on bit 2046 of port A: 1'0 + Constant input on bit 2047 of port A: 1'0 +Creating constmapped module `$paramod$constmap:4258b4649ecd518d1b26cd3b097673bcbc6d5eec$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx'. + +12.22. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:4258b4649ecd518d1b26cd3b097673bcbc6d5eec$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$817. + dead port 2/2 on $mux $procmux$817. + dead port 1/2 on $mux $procmux$820. + dead port 2/2 on $mux $procmux$823. + dead port 2/2 on $mux $procmux$829. + dead port 2/2 on $mux $procmux$835. + dead port 2/2 on $mux $procmux$841. + dead port 2/2 on $mux $procmux$847. + dead port 1/2 on $mux $procmux$853. + dead port 2/2 on $mux $procmux$853. + dead port 1/2 on $mux $procmux$856. + dead port 1/2 on $mux $procmux$859. + dead port 2/2 on $mux $procmux$859. + dead port 1/2 on $mux $procmux$862. + dead port 1/2 on $mux $procmux$865. + dead port 2/2 on $mux $procmux$865. + dead port 1/2 on $mux $procmux$868. + dead port 1/2 on $mux $procmux$871. + dead port 2/2 on $mux $procmux$871. + dead port 1/2 on $mux $procmux$874. + dead port 1/2 on $mux $procmux$877. + dead port 2/2 on $mux $procmux$877. + dead port 1/2 on $mux $procmux$880. + dead port 1/2 on $mux $procmux$883. + dead port 2/2 on $mux $procmux$883. + dead port 1/2 on $mux $procmux$886. +Removed 26 multiplexer ports. + + +12.23. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:4258b4649ecd518d1b26cd3b097673bcbc6d5eec$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx. + +Removed 0 unused cells and 64 unused wires. +Using template $paramod$constmap:4258b4649ecd518d1b26cd3b097673bcbc6d5eec$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx for cells of type $shiftx. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port B: 1'0 + Constant input on bit 1 of port B: 1'0 + Constant input on bit 2 of port B: 1'0 + Constant input on bit 3 of port B: 1'0 + Constant input on bit 4 of port B: 1'0 + Constant input on bit 5 of port B: 1'0 + Constant input on bit 11 of port B: 1'0 + Constant input on bit 12 of port B: 1'0 + Constant input on bit 13 of port B: 1'0 + Constant input on bit 14 of port B: 1'0 + Constant input on bit 15 of port B: 1'0 + Constant input on bit 16 of port B: 1'0 + Constant input on bit 17 of port B: 1'0 + Constant input on bit 18 of port B: 1'0 + Constant input on bit 19 of port B: 1'0 + Constant input on bit 20 of port B: 1'0 + Constant input on bit 21 of port B: 1'0 + Constant input on bit 22 of port B: 1'0 + Constant input on bit 23 of port B: 1'0 + Constant input on bit 24 of port B: 1'0 + Constant input on bit 25 of port B: 1'0 + Constant input on bit 26 of port B: 1'0 + Constant input on bit 27 of port B: 1'0 + Constant input on bit 28 of port B: 1'0 + Constant input on bit 29 of port B: 1'0 + Constant input on bit 30 of port B: 1'0 + Constant input on bit 31 of port B: 1'0 + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'0 + Constant input on bit 2 of port A: 1'0 + Constant input on bit 3 of port A: 1'0 + Constant input on bit 4 of port A: 1'0 + Constant input on bit 5 of port A: 1'0 + Constant input on bit 6 of port A: 1'0 + Constant input on bit 7 of port A: 1'0 + Constant input on bit 8 of port A: 1'1 + Constant input on bit 9 of port A: 1'0 + Constant input on bit 10 of port A: 1'0 + Constant input on bit 11 of port A: 1'0 + Constant input on bit 12 of port A: 1'0 + Constant input on bit 13 of port A: 1'0 + Constant input on bit 14 of port A: 1'0 + Constant input on bit 15 of port A: 1'0 + Constant input on bit 16 of port A: 1'1 + Constant input on bit 17 of port A: 1'0 + Constant input on bit 18 of port A: 1'0 + Constant input on bit 19 of port A: 1'0 + Constant input on bit 20 of port A: 1'0 + Constant input on bit 21 of port A: 1'0 + Constant input on bit 22 of port A: 1'0 + Constant input on bit 23 of port A: 1'0 + Constant input on bit 24 of port A: 1'1 + Constant input on bit 25 of port A: 1'0 + Constant input on bit 26 of port A: 1'0 + Constant input on bit 27 of port A: 1'0 + Constant input on bit 28 of port A: 1'0 + Constant input on bit 29 of port A: 1'0 + Constant input on bit 30 of port A: 1'0 + Constant input on bit 31 of port A: 1'0 + Constant input on bit 32 of port A: 1'1 + Constant input on bit 33 of port A: 1'0 + Constant input on bit 34 of port A: 1'0 + Constant input on bit 35 of port A: 1'0 + Constant input on bit 36 of port A: 1'0 + Constant input on bit 37 of port A: 1'0 + Constant input on bit 38 of port A: 1'0 + Constant input on bit 39 of port A: 1'0 + Constant input on bit 40 of port A: 1'1 + Constant input on bit 41 of port A: 1'0 + Constant input on bit 42 of port A: 1'0 + Constant input on bit 43 of port A: 1'0 + Constant input on bit 44 of port A: 1'0 + Constant input on bit 45 of port A: 1'0 + Constant input on bit 46 of port A: 1'0 + Constant input on bit 47 of port A: 1'0 + Constant input on bit 48 of port A: 1'1 + Constant input on bit 49 of port A: 1'0 + Constant input on bit 50 of port A: 1'0 + Constant input on bit 51 of port A: 1'0 + Constant input on bit 52 of port A: 1'0 + Constant input on bit 53 of port A: 1'0 + Constant input on bit 54 of port A: 1'0 + Constant input on bit 55 of port A: 1'0 + Constant input on bit 56 of port A: 1'1 + Constant input on bit 57 of port A: 1'0 + Constant input on bit 58 of port A: 1'0 + Constant input on bit 59 of port A: 1'0 + Constant input on bit 60 of port A: 1'0 + Constant input on bit 61 of port A: 1'0 + Constant input on bit 62 of port A: 1'0 + Constant input on bit 63 of port A: 1'0 + Constant input on bit 64 of port A: 1'1 + Constant input on bit 65 of port A: 1'0 + Constant input on bit 66 of port A: 1'0 + Constant input on bit 67 of port A: 1'0 + Constant input on bit 68 of port A: 1'0 + Constant input on bit 69 of port A: 1'0 + Constant input on bit 70 of port A: 1'0 + Constant input on bit 71 of port A: 1'0 + Constant input on bit 72 of port A: 1'1 + Constant input on bit 73 of port A: 1'0 + Constant input on bit 74 of port A: 1'0 + Constant input on bit 75 of port A: 1'0 + Constant input on bit 76 of port A: 1'0 + Constant input on bit 77 of port A: 1'0 + Constant input on bit 78 of port A: 1'0 + Constant input on bit 79 of port A: 1'0 + Constant input on bit 80 of port A: 1'1 + Constant input on bit 81 of port A: 1'0 + Constant input on bit 82 of port A: 1'0 + Constant input on bit 83 of port A: 1'0 + Constant input on bit 84 of port A: 1'0 + Constant input on bit 85 of port A: 1'0 + Constant input on bit 86 of port A: 1'0 + Constant input on bit 87 of port A: 1'0 + Constant input on bit 88 of port A: 1'1 + Constant input on bit 89 of port A: 1'0 + Constant input on bit 90 of port A: 1'0 + Constant input on bit 91 of port A: 1'0 + Constant input on bit 92 of port A: 1'0 + Constant input on bit 93 of port A: 1'0 + Constant input on bit 94 of port A: 1'0 + Constant input on bit 95 of port A: 1'0 + Constant input on bit 96 of port A: 1'1 + Constant input on bit 97 of port A: 1'0 + Constant input on bit 98 of port A: 1'0 + Constant input on bit 99 of port A: 1'0 + Constant input on bit 100 of port A: 1'0 + Constant input on bit 101 of port A: 1'0 + Constant input on bit 102 of port A: 1'0 + Constant input on bit 103 of port A: 1'0 + Constant input on bit 104 of port A: 1'1 + Constant input on bit 105 of port A: 1'0 + Constant input on bit 106 of port A: 1'0 + Constant input on bit 107 of port A: 1'0 + Constant input on bit 108 of port A: 1'0 + Constant input on bit 109 of port A: 1'0 + Constant input on bit 110 of port A: 1'0 + Constant input on bit 111 of port A: 1'0 + Constant input on bit 112 of port A: 1'1 + Constant input on bit 113 of port A: 1'0 + Constant input on bit 114 of port A: 1'0 + Constant input on bit 115 of port A: 1'0 + Constant input on bit 116 of port A: 1'0 + Constant input on bit 117 of port A: 1'0 + Constant input on bit 118 of port A: 1'0 + Constant input on bit 119 of port A: 1'0 + Constant input on bit 120 of port A: 1'1 + Constant input on bit 121 of port A: 1'0 + Constant input on bit 122 of port A: 1'0 + Constant input on bit 123 of port A: 1'0 + Constant input on bit 124 of port A: 1'0 + Constant input on bit 125 of port A: 1'0 + Constant input on bit 126 of port A: 1'0 + Constant input on bit 127 of port A: 1'0 + Constant input on bit 128 of port A: 1'1 + Constant input on bit 129 of port A: 1'0 + Constant input on bit 130 of port A: 1'0 + Constant input on bit 131 of port A: 1'0 + Constant input on bit 132 of port A: 1'0 + Constant input on bit 133 of port A: 1'0 + Constant input on bit 134 of port A: 1'0 + Constant input on bit 135 of port A: 1'0 + Constant input on bit 136 of port A: 1'1 + Constant input on bit 137 of port A: 1'0 + Constant input on bit 138 of port A: 1'0 + Constant input on bit 139 of port A: 1'0 + Constant input on bit 140 of port A: 1'0 + Constant input on bit 141 of port A: 1'0 + Constant input on bit 142 of port A: 1'0 + Constant input on bit 143 of port A: 1'0 + Constant input on bit 144 of port A: 1'1 + Constant input on bit 145 of port A: 1'0 + Constant input on bit 146 of port A: 1'0 + Constant input on bit 147 of port A: 1'0 + Constant input on bit 148 of port A: 1'0 + Constant input on bit 149 of port A: 1'0 + Constant input on bit 150 of port A: 1'0 + Constant input on bit 151 of port A: 1'0 + Constant input on bit 152 of port A: 1'1 + Constant input on bit 153 of port A: 1'0 + Constant input on bit 154 of port A: 1'0 + Constant input on bit 155 of port A: 1'0 + Constant input on bit 156 of port A: 1'0 + Constant input on bit 157 of port A: 1'0 + Constant input on bit 158 of port A: 1'0 + Constant input on bit 159 of port A: 1'0 + Constant input on bit 160 of port A: 1'1 + Constant input on bit 161 of port A: 1'0 + Constant input on bit 162 of port A: 1'0 + Constant input on bit 163 of port A: 1'0 + Constant input on bit 164 of port A: 1'0 + Constant input on bit 165 of port A: 1'0 + Constant input on bit 166 of port A: 1'0 + Constant input on bit 167 of port A: 1'0 + Constant input on bit 168 of port A: 1'1 + Constant input on bit 169 of port A: 1'0 + Constant input on bit 170 of port A: 1'0 + Constant input on bit 171 of port A: 1'0 + Constant input on bit 172 of port A: 1'0 + Constant input on bit 173 of port A: 1'0 + Constant input on bit 174 of port A: 1'0 + Constant input on bit 175 of port A: 1'0 + Constant input on bit 176 of port A: 1'1 + Constant input on bit 177 of port A: 1'0 + Constant input on bit 178 of port A: 1'0 + Constant input on bit 179 of port A: 1'0 + Constant input on bit 180 of port A: 1'0 + Constant input on bit 181 of port A: 1'0 + Constant input on bit 182 of port A: 1'0 + Constant input on bit 183 of port A: 1'0 + Constant input on bit 184 of port A: 1'1 + Constant input on bit 185 of port A: 1'0 + Constant input on bit 186 of port A: 1'0 + Constant input on bit 187 of port A: 1'0 + Constant input on bit 188 of port A: 1'0 + Constant input on bit 189 of port A: 1'0 + Constant input on bit 190 of port A: 1'0 + Constant input on bit 191 of port A: 1'0 + Constant input on bit 192 of port A: 1'1 + Constant input on bit 193 of port A: 1'0 + Constant input on bit 194 of port A: 1'0 + Constant input on bit 195 of port A: 1'0 + Constant input on bit 196 of port A: 1'0 + Constant input on bit 197 of port A: 1'0 + Constant input on bit 198 of port A: 1'0 + Constant input on bit 199 of port A: 1'0 + Constant input on bit 200 of port A: 1'1 + Constant input on bit 201 of port A: 1'0 + Constant input on bit 202 of port A: 1'0 + Constant input on bit 203 of port A: 1'0 + Constant input on bit 204 of port A: 1'0 + Constant input on bit 205 of port A: 1'0 + Constant input on bit 206 of port A: 1'0 + Constant input on bit 207 of port A: 1'0 + Constant input on bit 208 of port A: 1'1 + Constant input on bit 209 of port A: 1'0 + Constant input on bit 210 of port A: 1'0 + Constant input on bit 211 of port A: 1'0 + Constant input on bit 212 of port A: 1'0 + Constant input on bit 213 of port A: 1'0 + Constant input on bit 214 of port A: 1'0 + Constant input on bit 215 of port A: 1'0 + Constant input on bit 216 of port A: 1'1 + Constant input on bit 217 of port A: 1'0 + Constant input on bit 218 of port A: 1'0 + Constant input on bit 219 of port A: 1'0 + Constant input on bit 220 of port A: 1'0 + Constant input on bit 221 of port A: 1'0 + Constant input on bit 222 of port A: 1'0 + Constant input on bit 223 of port A: 1'0 + Constant input on bit 224 of port A: 1'1 + Constant input on bit 225 of port A: 1'0 + Constant input on bit 226 of port A: 1'0 + Constant input on bit 227 of port A: 1'0 + Constant input on bit 228 of port A: 1'0 + Constant input on bit 229 of port A: 1'0 + Constant input on bit 230 of port A: 1'0 + Constant input on bit 231 of port A: 1'0 + Constant input on bit 232 of port A: 1'1 + Constant input on bit 233 of port A: 1'0 + Constant input on bit 234 of port A: 1'0 + Constant input on bit 235 of port A: 1'0 + Constant input on bit 236 of port A: 1'0 + Constant input on bit 237 of port A: 1'0 + Constant input on bit 238 of port A: 1'0 + Constant input on bit 239 of port A: 1'0 + Constant input on bit 240 of port A: 1'1 + Constant input on bit 241 of port A: 1'0 + Constant input on bit 242 of port A: 1'0 + Constant input on bit 243 of port A: 1'0 + Constant input on bit 244 of port A: 1'0 + Constant input on bit 245 of port A: 1'0 + Constant input on bit 246 of port A: 1'0 + Constant input on bit 247 of port A: 1'0 + Constant input on bit 248 of port A: 1'1 + Constant input on bit 249 of port A: 1'0 + Constant input on bit 250 of port A: 1'0 + Constant input on bit 251 of port A: 1'0 + Constant input on bit 252 of port A: 1'0 + Constant input on bit 253 of port A: 1'0 + Constant input on bit 254 of port A: 1'0 + Constant input on bit 255 of port A: 1'0 + Constant input on bit 256 of port A: 1'0 + Constant input on bit 257 of port A: 1'0 + Constant input on bit 258 of port A: 1'0 + Constant input on bit 259 of port A: 1'0 + Constant input on bit 260 of port A: 1'0 + Constant input on bit 261 of port A: 1'0 + Constant input on bit 262 of port A: 1'0 + Constant input on bit 263 of port A: 1'0 + Constant input on bit 264 of port A: 1'0 + Constant input on bit 265 of port A: 1'0 + Constant input on bit 266 of port A: 1'0 + Constant input on bit 267 of port A: 1'0 + Constant input on bit 268 of port A: 1'0 + Constant input on bit 269 of port A: 1'0 + Constant input on bit 270 of port A: 1'0 + Constant input on bit 271 of port A: 1'0 + Constant input on bit 272 of port A: 1'0 + Constant input on bit 273 of port A: 1'0 + Constant input on bit 274 of port A: 1'0 + Constant input on bit 275 of port A: 1'0 + Constant input on bit 276 of port A: 1'0 + Constant input on bit 277 of port A: 1'0 + Constant input on bit 278 of port A: 1'0 + Constant input on bit 279 of port A: 1'0 + Constant input on bit 280 of port A: 1'0 + Constant input on bit 281 of port A: 1'0 + Constant input on bit 282 of port A: 1'0 + Constant input on bit 283 of port A: 1'0 + Constant input on bit 284 of port A: 1'0 + Constant input on bit 285 of port A: 1'0 + Constant input on bit 286 of port A: 1'0 + Constant input on bit 287 of port A: 1'0 + Constant input on bit 288 of port A: 1'0 + Constant input on bit 289 of port A: 1'0 + Constant input on bit 290 of port A: 1'0 + Constant input on bit 291 of port A: 1'0 + Constant input on bit 292 of port A: 1'0 + Constant input on bit 293 of port A: 1'0 + Constant input on bit 294 of port A: 1'0 + Constant input on bit 295 of port A: 1'0 + Constant input on bit 296 of port A: 1'0 + Constant input on bit 297 of port A: 1'0 + Constant input on bit 298 of port A: 1'0 + Constant input on bit 299 of port A: 1'0 + Constant input on bit 300 of port A: 1'0 + Constant input on bit 301 of port A: 1'0 + Constant input on bit 302 of port A: 1'0 + Constant input on bit 303 of port A: 1'0 + Constant input on bit 304 of port A: 1'0 + Constant input on bit 305 of port A: 1'0 + Constant input on bit 306 of port A: 1'0 + Constant input on bit 307 of port A: 1'0 + Constant input on bit 308 of port A: 1'0 + Constant input on bit 309 of port A: 1'0 + Constant input on bit 310 of port A: 1'0 + Constant input on bit 311 of port A: 1'0 + Constant input on bit 312 of port A: 1'0 + Constant input on bit 313 of port A: 1'0 + Constant input on bit 314 of port A: 1'0 + Constant input on bit 315 of port A: 1'0 + Constant input on bit 316 of port A: 1'0 + Constant input on bit 317 of port A: 1'0 + Constant input on bit 318 of port A: 1'0 + Constant input on bit 319 of port A: 1'0 + Constant input on bit 320 of port A: 1'0 + Constant input on bit 321 of port A: 1'0 + Constant input on bit 322 of port A: 1'0 + Constant input on bit 323 of port A: 1'0 + Constant input on bit 324 of port A: 1'0 + Constant input on bit 325 of port A: 1'0 + Constant input on bit 326 of port A: 1'0 + Constant input on bit 327 of port A: 1'0 + Constant input on bit 328 of port A: 1'0 + Constant input on bit 329 of port A: 1'0 + Constant input on bit 330 of port A: 1'0 + Constant input on bit 331 of port A: 1'0 + Constant input on bit 332 of port A: 1'0 + Constant input on bit 333 of port A: 1'0 + Constant input on bit 334 of port A: 1'0 + Constant input on bit 335 of port A: 1'0 + Constant input on bit 336 of port A: 1'0 + Constant input on bit 337 of port A: 1'0 + Constant input on bit 338 of port A: 1'0 + Constant input on bit 339 of port A: 1'0 + Constant input on bit 340 of port A: 1'0 + Constant input on bit 341 of port A: 1'0 + Constant input on bit 342 of port A: 1'0 + Constant input on bit 343 of port A: 1'0 + Constant input on bit 344 of port A: 1'0 + Constant input on bit 345 of port A: 1'0 + Constant input on bit 346 of port A: 1'0 + Constant input on bit 347 of port A: 1'0 + Constant input on bit 348 of port A: 1'0 + Constant input on bit 349 of port A: 1'0 + Constant input on bit 350 of port A: 1'0 + Constant input on bit 351 of port A: 1'0 + Constant input on bit 352 of port A: 1'0 + Constant input on bit 353 of port A: 1'0 + Constant input on bit 354 of port A: 1'0 + Constant input on bit 355 of port A: 1'0 + Constant input on bit 356 of port A: 1'0 + Constant input on bit 357 of port A: 1'0 + Constant input on bit 358 of port A: 1'0 + Constant input on bit 359 of port A: 1'0 + Constant input on bit 360 of port A: 1'0 + Constant input on bit 361 of port A: 1'0 + Constant input on bit 362 of port A: 1'0 + Constant input on bit 363 of port A: 1'0 + Constant input on bit 364 of port A: 1'0 + Constant input on bit 365 of port A: 1'0 + Constant input on bit 366 of port A: 1'0 + Constant input on bit 367 of port A: 1'0 + Constant input on bit 368 of port A: 1'0 + Constant input on bit 369 of port A: 1'0 + Constant input on bit 370 of port A: 1'0 + Constant input on bit 371 of port A: 1'0 + Constant input on bit 372 of port A: 1'0 + Constant input on bit 373 of port A: 1'0 + Constant input on bit 374 of port A: 1'0 + Constant input on bit 375 of port A: 1'0 + Constant input on bit 376 of port A: 1'0 + Constant input on bit 377 of port A: 1'0 + Constant input on bit 378 of port A: 1'0 + Constant input on bit 379 of port A: 1'0 + Constant input on bit 380 of port A: 1'0 + Constant input on bit 381 of port A: 1'0 + Constant input on bit 382 of port A: 1'0 + Constant input on bit 383 of port A: 1'0 + Constant input on bit 384 of port A: 1'0 + Constant input on bit 385 of port A: 1'0 + Constant input on bit 386 of port A: 1'0 + Constant input on bit 387 of port A: 1'0 + Constant input on bit 388 of port A: 1'0 + Constant input on bit 389 of port A: 1'0 + Constant input on bit 390 of port A: 1'0 + Constant input on bit 391 of port A: 1'0 + Constant input on bit 392 of port A: 1'0 + Constant input on bit 393 of port A: 1'0 + Constant input on bit 394 of port A: 1'0 + Constant input on bit 395 of port A: 1'0 + Constant input on bit 396 of port A: 1'0 + Constant input on bit 397 of port A: 1'0 + Constant input on bit 398 of port A: 1'0 + Constant input on bit 399 of port A: 1'0 + Constant input on bit 400 of port A: 1'0 + Constant input on bit 401 of port A: 1'0 + Constant input on bit 402 of port A: 1'0 + Constant input on bit 403 of port A: 1'0 + Constant input on bit 404 of port A: 1'0 + Constant input on bit 405 of port A: 1'0 + Constant input on bit 406 of port A: 1'0 + Constant input on bit 407 of port A: 1'0 + Constant input on bit 408 of port A: 1'0 + Constant input on bit 409 of port A: 1'0 + Constant input on bit 410 of port A: 1'0 + Constant input on bit 411 of port A: 1'0 + Constant input on bit 412 of port A: 1'0 + Constant input on bit 413 of port A: 1'0 + Constant input on bit 414 of port A: 1'0 + Constant input on bit 415 of port A: 1'0 + Constant input on bit 416 of port A: 1'0 + Constant input on bit 417 of port A: 1'0 + Constant input on bit 418 of port A: 1'0 + Constant input on bit 419 of port A: 1'0 + Constant input on bit 420 of port A: 1'0 + Constant input on bit 421 of port A: 1'0 + Constant input on bit 422 of port A: 1'0 + Constant input on bit 423 of port A: 1'0 + Constant input on bit 424 of port A: 1'0 + Constant input on bit 425 of port A: 1'0 + Constant input on bit 426 of port A: 1'0 + Constant input on bit 427 of port A: 1'0 + Constant input on bit 428 of port A: 1'0 + Constant input on bit 429 of port A: 1'0 + Constant input on bit 430 of port A: 1'0 + Constant input on bit 431 of port A: 1'0 + Constant input on bit 432 of port A: 1'0 + Constant input on bit 433 of port A: 1'0 + Constant input on bit 434 of port A: 1'0 + Constant input on bit 435 of port A: 1'0 + Constant input on bit 436 of port A: 1'0 + Constant input on bit 437 of port A: 1'0 + Constant input on bit 438 of port A: 1'0 + Constant input on bit 439 of port A: 1'0 + Constant input on bit 440 of port A: 1'0 + Constant input on bit 441 of port A: 1'0 + Constant input on bit 442 of port A: 1'0 + Constant input on bit 443 of port A: 1'0 + Constant input on bit 444 of port A: 1'0 + Constant input on bit 445 of port A: 1'0 + Constant input on bit 446 of port A: 1'0 + Constant input on bit 447 of port A: 1'0 + Constant input on bit 448 of port A: 1'0 + Constant input on bit 449 of port A: 1'0 + Constant input on bit 450 of port A: 1'0 + Constant input on bit 451 of port A: 1'0 + Constant input on bit 452 of port A: 1'0 + Constant input on bit 453 of port A: 1'0 + Constant input on bit 454 of port A: 1'0 + Constant input on bit 455 of port A: 1'0 + Constant input on bit 456 of port A: 1'0 + Constant input on bit 457 of port A: 1'0 + Constant input on bit 458 of port A: 1'0 + Constant input on bit 459 of port A: 1'0 + Constant input on bit 460 of port A: 1'0 + Constant input on bit 461 of port A: 1'0 + Constant input on bit 462 of port A: 1'0 + Constant input on bit 463 of port A: 1'0 + Constant input on bit 464 of port A: 1'0 + Constant input on bit 465 of port A: 1'0 + Constant input on bit 466 of port A: 1'0 + Constant input on bit 467 of port A: 1'0 + Constant input on bit 468 of port A: 1'0 + Constant input on bit 469 of port A: 1'0 + Constant input on bit 470 of port A: 1'0 + Constant input on bit 471 of port A: 1'0 + Constant input on bit 472 of port A: 1'0 + Constant input on bit 473 of port A: 1'0 + Constant input on bit 474 of port A: 1'0 + Constant input on bit 475 of port A: 1'0 + Constant input on bit 476 of port A: 1'0 + Constant input on bit 477 of port A: 1'0 + Constant input on bit 478 of port A: 1'0 + Constant input on bit 479 of port A: 1'0 + Constant input on bit 480 of port A: 1'0 + Constant input on bit 481 of port A: 1'0 + Constant input on bit 482 of port A: 1'0 + Constant input on bit 483 of port A: 1'0 + Constant input on bit 484 of port A: 1'0 + Constant input on bit 485 of port A: 1'0 + Constant input on bit 486 of port A: 1'0 + Constant input on bit 487 of port A: 1'0 + Constant input on bit 488 of port A: 1'0 + Constant input on bit 489 of port A: 1'0 + Constant input on bit 490 of port A: 1'0 + Constant input on bit 491 of port A: 1'0 + Constant input on bit 492 of port A: 1'0 + Constant input on bit 493 of port A: 1'0 + Constant input on bit 494 of port A: 1'0 + Constant input on bit 495 of port A: 1'0 + Constant input on bit 496 of port A: 1'0 + Constant input on bit 497 of port A: 1'0 + Constant input on bit 498 of port A: 1'0 + Constant input on bit 499 of port A: 1'0 + Constant input on bit 500 of port A: 1'0 + Constant input on bit 501 of port A: 1'0 + Constant input on bit 502 of port A: 1'0 + Constant input on bit 503 of port A: 1'0 + Constant input on bit 504 of port A: 1'0 + Constant input on bit 505 of port A: 1'0 + Constant input on bit 506 of port A: 1'0 + Constant input on bit 507 of port A: 1'0 + Constant input on bit 508 of port A: 1'0 + Constant input on bit 509 of port A: 1'0 + Constant input on bit 510 of port A: 1'0 + Constant input on bit 511 of port A: 1'0 + Constant input on bit 512 of port A: 1'0 + Constant input on bit 513 of port A: 1'0 + Constant input on bit 514 of port A: 1'0 + Constant input on bit 515 of port A: 1'0 + Constant input on bit 516 of port A: 1'0 + Constant input on bit 517 of port A: 1'0 + Constant input on bit 518 of port A: 1'0 + Constant input on bit 519 of port A: 1'0 + Constant input on bit 520 of port A: 1'0 + Constant input on bit 521 of port A: 1'0 + Constant input on bit 522 of port A: 1'0 + Constant input on bit 523 of port A: 1'0 + Constant input on bit 524 of port A: 1'0 + Constant input on bit 525 of port A: 1'0 + Constant input on bit 526 of port A: 1'0 + Constant input on bit 527 of port A: 1'0 + Constant input on bit 528 of port A: 1'0 + Constant input on bit 529 of port A: 1'0 + Constant input on bit 530 of port A: 1'0 + Constant input on bit 531 of port A: 1'0 + Constant input on bit 532 of port A: 1'0 + Constant input on bit 533 of port A: 1'0 + Constant input on bit 534 of port A: 1'0 + Constant input on bit 535 of port A: 1'0 + Constant input on bit 536 of port A: 1'0 + Constant input on bit 537 of port A: 1'0 + Constant input on bit 538 of port A: 1'0 + Constant input on bit 539 of port A: 1'0 + Constant input on bit 540 of port A: 1'0 + Constant input on bit 541 of port A: 1'0 + Constant input on bit 542 of port A: 1'0 + Constant input on bit 543 of port A: 1'0 + Constant input on bit 544 of port A: 1'0 + Constant input on bit 545 of port A: 1'0 + Constant input on bit 546 of port A: 1'0 + Constant input on bit 547 of port A: 1'0 + Constant input on bit 548 of port A: 1'0 + Constant input on bit 549 of port A: 1'0 + Constant input on bit 550 of port A: 1'0 + Constant input on bit 551 of port A: 1'0 + Constant input on bit 552 of port A: 1'0 + Constant input on bit 553 of port A: 1'0 + Constant input on bit 554 of port A: 1'0 + Constant input on bit 555 of port A: 1'0 + Constant input on bit 556 of port A: 1'0 + Constant input on bit 557 of port A: 1'0 + Constant input on bit 558 of port A: 1'0 + Constant input on bit 559 of port A: 1'0 + Constant input on bit 560 of port A: 1'0 + Constant input on bit 561 of port A: 1'0 + Constant input on bit 562 of port A: 1'0 + Constant input on bit 563 of port A: 1'0 + Constant input on bit 564 of port A: 1'0 + Constant input on bit 565 of port A: 1'0 + Constant input on bit 566 of port A: 1'0 + Constant input on bit 567 of port A: 1'0 + Constant input on bit 568 of port A: 1'0 + Constant input on bit 569 of port A: 1'0 + Constant input on bit 570 of port A: 1'0 + Constant input on bit 571 of port A: 1'0 + Constant input on bit 572 of port A: 1'0 + Constant input on bit 573 of port A: 1'0 + Constant input on bit 574 of port A: 1'0 + Constant input on bit 575 of port A: 1'0 + Constant input on bit 576 of port A: 1'0 + Constant input on bit 577 of port A: 1'0 + Constant input on bit 578 of port A: 1'0 + Constant input on bit 579 of port A: 1'0 + Constant input on bit 580 of port A: 1'0 + Constant input on bit 581 of port A: 1'0 + Constant input on bit 582 of port A: 1'0 + Constant input on bit 583 of port A: 1'0 + Constant input on bit 584 of port A: 1'0 + Constant input on bit 585 of port A: 1'0 + Constant input on bit 586 of port A: 1'0 + Constant input on bit 587 of port A: 1'0 + Constant input on bit 588 of port A: 1'0 + Constant input on bit 589 of port A: 1'0 + Constant input on bit 590 of port A: 1'0 + Constant input on bit 591 of port A: 1'0 + Constant input on bit 592 of port A: 1'0 + Constant input on bit 593 of port A: 1'0 + Constant input on bit 594 of port A: 1'0 + Constant input on bit 595 of port A: 1'0 + Constant input on bit 596 of port A: 1'0 + Constant input on bit 597 of port A: 1'0 + Constant input on bit 598 of port A: 1'0 + Constant input on bit 599 of port A: 1'0 + Constant input on bit 600 of port A: 1'0 + Constant input on bit 601 of port A: 1'0 + Constant input on bit 602 of port A: 1'0 + Constant input on bit 603 of port A: 1'0 + Constant input on bit 604 of port A: 1'0 + Constant input on bit 605 of port A: 1'0 + Constant input on bit 606 of port A: 1'0 + Constant input on bit 607 of port A: 1'0 + Constant input on bit 608 of port A: 1'0 + Constant input on bit 609 of port A: 1'0 + Constant input on bit 610 of port A: 1'0 + Constant input on bit 611 of port A: 1'0 + Constant input on bit 612 of port A: 1'0 + Constant input on bit 613 of port A: 1'0 + Constant input on bit 614 of port A: 1'0 + Constant input on bit 615 of port A: 1'0 + Constant input on bit 616 of port A: 1'0 + Constant input on bit 617 of port A: 1'0 + Constant input on bit 618 of port A: 1'0 + Constant input on bit 619 of port A: 1'0 + Constant input on bit 620 of port A: 1'0 + Constant input on bit 621 of port A: 1'0 + Constant input on bit 622 of port A: 1'0 + Constant input on bit 623 of port A: 1'0 + Constant input on bit 624 of port A: 1'0 + Constant input on bit 625 of port A: 1'0 + Constant input on bit 626 of port A: 1'0 + Constant input on bit 627 of port A: 1'0 + Constant input on bit 628 of port A: 1'0 + Constant input on bit 629 of port A: 1'0 + Constant input on bit 630 of port A: 1'0 + Constant input on bit 631 of port A: 1'0 + Constant input on bit 632 of port A: 1'0 + Constant input on bit 633 of port A: 1'0 + Constant input on bit 634 of port A: 1'0 + Constant input on bit 635 of port A: 1'0 + Constant input on bit 636 of port A: 1'0 + Constant input on bit 637 of port A: 1'0 + Constant input on bit 638 of port A: 1'0 + Constant input on bit 639 of port A: 1'0 + Constant input on bit 640 of port A: 1'0 + Constant input on bit 641 of port A: 1'0 + Constant input on bit 642 of port A: 1'0 + Constant input on bit 643 of port A: 1'0 + Constant input on bit 644 of port A: 1'0 + Constant input on bit 645 of port A: 1'0 + Constant input on bit 646 of port A: 1'0 + Constant input on bit 647 of port A: 1'0 + Constant input on bit 648 of port A: 1'0 + Constant input on bit 649 of port A: 1'0 + Constant input on bit 650 of port A: 1'0 + Constant input on bit 651 of port A: 1'0 + Constant input on bit 652 of port A: 1'0 + Constant input on bit 653 of port A: 1'0 + Constant input on bit 654 of port A: 1'0 + Constant input on bit 655 of port A: 1'0 + Constant input on bit 656 of port A: 1'0 + Constant input on bit 657 of port A: 1'0 + Constant input on bit 658 of port A: 1'0 + Constant input on bit 659 of port A: 1'0 + Constant input on bit 660 of port A: 1'0 + Constant input on bit 661 of port A: 1'0 + Constant input on bit 662 of port A: 1'0 + Constant input on bit 663 of port A: 1'0 + Constant input on bit 664 of port A: 1'0 + Constant input on bit 665 of port A: 1'0 + Constant input on bit 666 of port A: 1'0 + Constant input on bit 667 of port A: 1'0 + Constant input on bit 668 of port A: 1'0 + Constant input on bit 669 of port A: 1'0 + Constant input on bit 670 of port A: 1'0 + Constant input on bit 671 of port A: 1'0 + Constant input on bit 672 of port A: 1'0 + Constant input on bit 673 of port A: 1'0 + Constant input on bit 674 of port A: 1'0 + Constant input on bit 675 of port A: 1'0 + Constant input on bit 676 of port A: 1'0 + Constant input on bit 677 of port A: 1'0 + Constant input on bit 678 of port A: 1'0 + Constant input on bit 679 of port A: 1'0 + Constant input on bit 680 of port A: 1'0 + Constant input on bit 681 of port A: 1'0 + Constant input on bit 682 of port A: 1'0 + Constant input on bit 683 of port A: 1'0 + Constant input on bit 684 of port A: 1'0 + Constant input on bit 685 of port A: 1'0 + Constant input on bit 686 of port A: 1'0 + Constant input on bit 687 of port A: 1'0 + Constant input on bit 688 of port A: 1'0 + Constant input on bit 689 of port A: 1'0 + Constant input on bit 690 of port A: 1'0 + Constant input on bit 691 of port A: 1'0 + Constant input on bit 692 of port A: 1'0 + Constant input on bit 693 of port A: 1'0 + Constant input on bit 694 of port A: 1'0 + Constant input on bit 695 of port A: 1'0 + Constant input on bit 696 of port A: 1'0 + Constant input on bit 697 of port A: 1'0 + Constant input on bit 698 of port A: 1'0 + Constant input on bit 699 of port A: 1'0 + Constant input on bit 700 of port A: 1'0 + Constant input on bit 701 of port A: 1'0 + Constant input on bit 702 of port A: 1'0 + Constant input on bit 703 of port A: 1'0 + Constant input on bit 704 of port A: 1'0 + Constant input on bit 705 of port A: 1'0 + Constant input on bit 706 of port A: 1'0 + Constant input on bit 707 of port A: 1'0 + Constant input on bit 708 of port A: 1'0 + Constant input on bit 709 of port A: 1'0 + Constant input on bit 710 of port A: 1'0 + Constant input on bit 711 of port A: 1'0 + Constant input on bit 712 of port A: 1'0 + Constant input on bit 713 of port A: 1'0 + Constant input on bit 714 of port A: 1'0 + Constant input on bit 715 of port A: 1'0 + Constant input on bit 716 of port A: 1'0 + Constant input on bit 717 of port A: 1'0 + Constant input on bit 718 of port A: 1'0 + Constant input on bit 719 of port A: 1'0 + Constant input on bit 720 of port A: 1'0 + Constant input on bit 721 of port A: 1'0 + Constant input on bit 722 of port A: 1'0 + Constant input on bit 723 of port A: 1'0 + Constant input on bit 724 of port A: 1'0 + Constant input on bit 725 of port A: 1'0 + Constant input on bit 726 of port A: 1'0 + Constant input on bit 727 of port A: 1'0 + Constant input on bit 728 of port A: 1'0 + Constant input on bit 729 of port A: 1'0 + Constant input on bit 730 of port A: 1'0 + Constant input on bit 731 of port A: 1'0 + Constant input on bit 732 of port A: 1'0 + Constant input on bit 733 of port A: 1'0 + Constant input on bit 734 of port A: 1'0 + Constant input on bit 735 of port A: 1'0 + Constant input on bit 736 of port A: 1'0 + Constant input on bit 737 of port A: 1'0 + Constant input on bit 738 of port A: 1'0 + Constant input on bit 739 of port A: 1'0 + Constant input on bit 740 of port A: 1'0 + Constant input on bit 741 of port A: 1'0 + Constant input on bit 742 of port A: 1'0 + Constant input on bit 743 of port A: 1'0 + Constant input on bit 744 of port A: 1'0 + Constant input on bit 745 of port A: 1'0 + Constant input on bit 746 of port A: 1'0 + Constant input on bit 747 of port A: 1'0 + Constant input on bit 748 of port A: 1'0 + Constant input on bit 749 of port A: 1'0 + Constant input on bit 750 of port A: 1'0 + Constant input on bit 751 of port A: 1'0 + Constant input on bit 752 of port A: 1'0 + Constant input on bit 753 of port A: 1'0 + Constant input on bit 754 of port A: 1'0 + Constant input on bit 755 of port A: 1'0 + Constant input on bit 756 of port A: 1'0 + Constant input on bit 757 of port A: 1'0 + Constant input on bit 758 of port A: 1'0 + Constant input on bit 759 of port A: 1'0 + Constant input on bit 760 of port A: 1'0 + Constant input on bit 761 of port A: 1'0 + Constant input on bit 762 of port A: 1'0 + Constant input on bit 763 of port A: 1'0 + Constant input on bit 764 of port A: 1'0 + Constant input on bit 765 of port A: 1'0 + Constant input on bit 766 of port A: 1'0 + Constant input on bit 767 of port A: 1'0 + Constant input on bit 768 of port A: 1'0 + Constant input on bit 769 of port A: 1'0 + Constant input on bit 770 of port A: 1'0 + Constant input on bit 771 of port A: 1'0 + Constant input on bit 772 of port A: 1'0 + Constant input on bit 773 of port A: 1'0 + Constant input on bit 774 of port A: 1'0 + Constant input on bit 775 of port A: 1'0 + Constant input on bit 776 of port A: 1'0 + Constant input on bit 777 of port A: 1'0 + Constant input on bit 778 of port A: 1'0 + Constant input on bit 779 of port A: 1'0 + Constant input on bit 780 of port A: 1'0 + Constant input on bit 781 of port A: 1'0 + Constant input on bit 782 of port A: 1'0 + Constant input on bit 783 of port A: 1'0 + Constant input on bit 784 of port A: 1'0 + Constant input on bit 785 of port A: 1'0 + Constant input on bit 786 of port A: 1'0 + Constant input on bit 787 of port A: 1'0 + Constant input on bit 788 of port A: 1'0 + Constant input on bit 789 of port A: 1'0 + Constant input on bit 790 of port A: 1'0 + Constant input on bit 791 of port A: 1'0 + Constant input on bit 792 of port A: 1'0 + Constant input on bit 793 of port A: 1'0 + Constant input on bit 794 of port A: 1'0 + Constant input on bit 795 of port A: 1'0 + Constant input on bit 796 of port A: 1'0 + Constant input on bit 797 of port A: 1'0 + Constant input on bit 798 of port A: 1'0 + Constant input on bit 799 of port A: 1'0 + Constant input on bit 800 of port A: 1'0 + Constant input on bit 801 of port A: 1'0 + Constant input on bit 802 of port A: 1'0 + Constant input on bit 803 of port A: 1'0 + Constant input on bit 804 of port A: 1'0 + Constant input on bit 805 of port A: 1'0 + Constant input on bit 806 of port A: 1'0 + Constant input on bit 807 of port A: 1'0 + Constant input on bit 808 of port A: 1'0 + Constant input on bit 809 of port A: 1'0 + Constant input on bit 810 of port A: 1'0 + Constant input on bit 811 of port A: 1'0 + Constant input on bit 812 of port A: 1'0 + Constant input on bit 813 of port A: 1'0 + Constant input on bit 814 of port A: 1'0 + Constant input on bit 815 of port A: 1'0 + Constant input on bit 816 of port A: 1'0 + Constant input on bit 817 of port A: 1'0 + Constant input on bit 818 of port A: 1'0 + Constant input on bit 819 of port A: 1'0 + Constant input on bit 820 of port A: 1'0 + Constant input on bit 821 of port A: 1'0 + Constant input on bit 822 of port A: 1'0 + Constant input on bit 823 of port A: 1'0 + Constant input on bit 824 of port A: 1'0 + Constant input on bit 825 of port A: 1'0 + Constant input on bit 826 of port A: 1'0 + Constant input on bit 827 of port A: 1'0 + Constant input on bit 828 of port A: 1'0 + Constant input on bit 829 of port A: 1'0 + Constant input on bit 830 of port A: 1'0 + Constant input on bit 831 of port A: 1'0 + Constant input on bit 832 of port A: 1'0 + Constant input on bit 833 of port A: 1'0 + Constant input on bit 834 of port A: 1'0 + Constant input on bit 835 of port A: 1'0 + Constant input on bit 836 of port A: 1'0 + Constant input on bit 837 of port A: 1'0 + Constant input on bit 838 of port A: 1'0 + Constant input on bit 839 of port A: 1'0 + Constant input on bit 840 of port A: 1'0 + Constant input on bit 841 of port A: 1'0 + Constant input on bit 842 of port A: 1'0 + Constant input on bit 843 of port A: 1'0 + Constant input on bit 844 of port A: 1'0 + Constant input on bit 845 of port A: 1'0 + Constant input on bit 846 of port A: 1'0 + Constant input on bit 847 of port A: 1'0 + Constant input on bit 848 of port A: 1'0 + Constant input on bit 849 of port A: 1'0 + Constant input on bit 850 of port A: 1'0 + Constant input on bit 851 of port A: 1'0 + Constant input on bit 852 of port A: 1'0 + Constant input on bit 853 of port A: 1'0 + Constant input on bit 854 of port A: 1'0 + Constant input on bit 855 of port A: 1'0 + Constant input on bit 856 of port A: 1'0 + Constant input on bit 857 of port A: 1'0 + Constant input on bit 858 of port A: 1'0 + Constant input on bit 859 of port A: 1'0 + Constant input on bit 860 of port A: 1'0 + Constant input on bit 861 of port A: 1'0 + Constant input on bit 862 of port A: 1'0 + Constant input on bit 863 of port A: 1'0 + Constant input on bit 864 of port A: 1'0 + Constant input on bit 865 of port A: 1'0 + Constant input on bit 866 of port A: 1'0 + Constant input on bit 867 of port A: 1'0 + Constant input on bit 868 of port A: 1'0 + Constant input on bit 869 of port A: 1'0 + Constant input on bit 870 of port A: 1'0 + Constant input on bit 871 of port A: 1'0 + Constant input on bit 872 of port A: 1'0 + Constant input on bit 873 of port A: 1'0 + Constant input on bit 874 of port A: 1'0 + Constant input on bit 875 of port A: 1'0 + Constant input on bit 876 of port A: 1'0 + Constant input on bit 877 of port A: 1'0 + Constant input on bit 878 of port A: 1'0 + Constant input on bit 879 of port A: 1'0 + Constant input on bit 880 of port A: 1'0 + Constant input on bit 881 of port A: 1'0 + Constant input on bit 882 of port A: 1'0 + Constant input on bit 883 of port A: 1'0 + Constant input on bit 884 of port A: 1'0 + Constant input on bit 885 of port A: 1'0 + Constant input on bit 886 of port A: 1'0 + Constant input on bit 887 of port A: 1'0 + Constant input on bit 888 of port A: 1'0 + Constant input on bit 889 of port A: 1'0 + Constant input on bit 890 of port A: 1'0 + Constant input on bit 891 of port A: 1'0 + Constant input on bit 892 of port A: 1'0 + Constant input on bit 893 of port A: 1'0 + Constant input on bit 894 of port A: 1'0 + Constant input on bit 895 of port A: 1'0 + Constant input on bit 896 of port A: 1'0 + Constant input on bit 897 of port A: 1'0 + Constant input on bit 898 of port A: 1'0 + Constant input on bit 899 of port A: 1'0 + Constant input on bit 900 of port A: 1'0 + Constant input on bit 901 of port A: 1'0 + Constant input on bit 902 of port A: 1'0 + Constant input on bit 903 of port A: 1'0 + Constant input on bit 904 of port A: 1'0 + Constant input on bit 905 of port A: 1'0 + Constant input on bit 906 of port A: 1'0 + Constant input on bit 907 of port A: 1'0 + Constant input on bit 908 of port A: 1'0 + Constant input on bit 909 of port A: 1'0 + Constant input on bit 910 of port A: 1'0 + Constant input on bit 911 of port A: 1'0 + Constant input on bit 912 of port A: 1'0 + Constant input on bit 913 of port A: 1'0 + Constant input on bit 914 of port A: 1'0 + Constant input on bit 915 of port A: 1'0 + Constant input on bit 916 of port A: 1'0 + Constant input on bit 917 of port A: 1'0 + Constant input on bit 918 of port A: 1'0 + Constant input on bit 919 of port A: 1'0 + Constant input on bit 920 of port A: 1'0 + Constant input on bit 921 of port A: 1'0 + Constant input on bit 922 of port A: 1'0 + Constant input on bit 923 of port A: 1'0 + Constant input on bit 924 of port A: 1'0 + Constant input on bit 925 of port A: 1'0 + Constant input on bit 926 of port A: 1'0 + Constant input on bit 927 of port A: 1'0 + Constant input on bit 928 of port A: 1'0 + Constant input on bit 929 of port A: 1'0 + Constant input on bit 930 of port A: 1'0 + Constant input on bit 931 of port A: 1'0 + Constant input on bit 932 of port A: 1'0 + Constant input on bit 933 of port A: 1'0 + Constant input on bit 934 of port A: 1'0 + Constant input on bit 935 of port A: 1'0 + Constant input on bit 936 of port A: 1'0 + Constant input on bit 937 of port A: 1'0 + Constant input on bit 938 of port A: 1'0 + Constant input on bit 939 of port A: 1'0 + Constant input on bit 940 of port A: 1'0 + Constant input on bit 941 of port A: 1'0 + Constant input on bit 942 of port A: 1'0 + Constant input on bit 943 of port A: 1'0 + Constant input on bit 944 of port A: 1'0 + Constant input on bit 945 of port A: 1'0 + Constant input on bit 946 of port A: 1'0 + Constant input on bit 947 of port A: 1'0 + Constant input on bit 948 of port A: 1'0 + Constant input on bit 949 of port A: 1'0 + Constant input on bit 950 of port A: 1'0 + Constant input on bit 951 of port A: 1'0 + Constant input on bit 952 of port A: 1'0 + Constant input on bit 953 of port A: 1'0 + Constant input on bit 954 of port A: 1'0 + Constant input on bit 955 of port A: 1'0 + Constant input on bit 956 of port A: 1'0 + Constant input on bit 957 of port A: 1'0 + Constant input on bit 958 of port A: 1'0 + Constant input on bit 959 of port A: 1'0 + Constant input on bit 960 of port A: 1'0 + Constant input on bit 961 of port A: 1'0 + Constant input on bit 962 of port A: 1'0 + Constant input on bit 963 of port A: 1'0 + Constant input on bit 964 of port A: 1'0 + Constant input on bit 965 of port A: 1'0 + Constant input on bit 966 of port A: 1'0 + Constant input on bit 967 of port A: 1'0 + Constant input on bit 968 of port A: 1'0 + Constant input on bit 969 of port A: 1'0 + Constant input on bit 970 of port A: 1'0 + Constant input on bit 971 of port A: 1'0 + Constant input on bit 972 of port A: 1'0 + Constant input on bit 973 of port A: 1'0 + Constant input on bit 974 of port A: 1'0 + Constant input on bit 975 of port A: 1'0 + Constant input on bit 976 of port A: 1'0 + Constant input on bit 977 of port A: 1'0 + Constant input on bit 978 of port A: 1'0 + Constant input on bit 979 of port A: 1'0 + Constant input on bit 980 of port A: 1'0 + Constant input on bit 981 of port A: 1'0 + Constant input on bit 982 of port A: 1'0 + Constant input on bit 983 of port A: 1'0 + Constant input on bit 984 of port A: 1'0 + Constant input on bit 985 of port A: 1'0 + Constant input on bit 986 of port A: 1'0 + Constant input on bit 987 of port A: 1'0 + Constant input on bit 988 of port A: 1'0 + Constant input on bit 989 of port A: 1'0 + Constant input on bit 990 of port A: 1'0 + Constant input on bit 991 of port A: 1'0 + Constant input on bit 992 of port A: 1'0 + Constant input on bit 993 of port A: 1'0 + Constant input on bit 994 of port A: 1'0 + Constant input on bit 995 of port A: 1'0 + Constant input on bit 996 of port A: 1'0 + Constant input on bit 997 of port A: 1'0 + Constant input on bit 998 of port A: 1'0 + Constant input on bit 999 of port A: 1'0 + Constant input on bit 1000 of port A: 1'0 + Constant input on bit 1001 of port A: 1'0 + Constant input on bit 1002 of port A: 1'0 + Constant input on bit 1003 of port A: 1'0 + Constant input on bit 1004 of port A: 1'0 + Constant input on bit 1005 of port A: 1'0 + Constant input on bit 1006 of port A: 1'0 + Constant input on bit 1007 of port A: 1'0 + Constant input on bit 1008 of port A: 1'0 + Constant input on bit 1009 of port A: 1'0 + Constant input on bit 1010 of port A: 1'0 + Constant input on bit 1011 of port A: 1'0 + Constant input on bit 1012 of port A: 1'0 + Constant input on bit 1013 of port A: 1'0 + Constant input on bit 1014 of port A: 1'0 + Constant input on bit 1015 of port A: 1'0 + Constant input on bit 1016 of port A: 1'0 + Constant input on bit 1017 of port A: 1'0 + Constant input on bit 1018 of port A: 1'0 + Constant input on bit 1019 of port A: 1'0 + Constant input on bit 1020 of port A: 1'0 + Constant input on bit 1021 of port A: 1'0 + Constant input on bit 1022 of port A: 1'0 + Constant input on bit 1023 of port A: 1'0 + Constant input on bit 1024 of port A: 1'0 + Constant input on bit 1025 of port A: 1'0 + Constant input on bit 1026 of port A: 1'0 + Constant input on bit 1027 of port A: 1'0 + Constant input on bit 1028 of port A: 1'0 + Constant input on bit 1029 of port A: 1'0 + Constant input on bit 1030 of port A: 1'0 + Constant input on bit 1031 of port A: 1'0 + Constant input on bit 1032 of port A: 1'0 + Constant input on bit 1033 of port A: 1'0 + Constant input on bit 1034 of port A: 1'0 + Constant input on bit 1035 of port A: 1'0 + Constant input on bit 1036 of port A: 1'0 + Constant input on bit 1037 of port A: 1'0 + Constant input on bit 1038 of port A: 1'0 + Constant input on bit 1039 of port A: 1'0 + Constant input on bit 1040 of port A: 1'0 + Constant input on bit 1041 of port A: 1'0 + Constant input on bit 1042 of port A: 1'0 + Constant input on bit 1043 of port A: 1'0 + Constant input on bit 1044 of port A: 1'0 + Constant input on bit 1045 of port A: 1'0 + Constant input on bit 1046 of port A: 1'0 + Constant input on bit 1047 of port A: 1'0 + Constant input on bit 1048 of port A: 1'0 + Constant input on bit 1049 of port A: 1'0 + Constant input on bit 1050 of port A: 1'0 + Constant input on bit 1051 of port A: 1'0 + Constant input on bit 1052 of port A: 1'0 + Constant input on bit 1053 of port A: 1'0 + Constant input on bit 1054 of port A: 1'0 + Constant input on bit 1055 of port A: 1'0 + Constant input on bit 1056 of port A: 1'0 + Constant input on bit 1057 of port A: 1'0 + Constant input on bit 1058 of port A: 1'0 + Constant input on bit 1059 of port A: 1'0 + Constant input on bit 1060 of port A: 1'0 + Constant input on bit 1061 of port A: 1'0 + Constant input on bit 1062 of port A: 1'0 + Constant input on bit 1063 of port A: 1'0 + Constant input on bit 1064 of port A: 1'0 + Constant input on bit 1065 of port A: 1'0 + Constant input on bit 1066 of port A: 1'0 + Constant input on bit 1067 of port A: 1'0 + Constant input on bit 1068 of port A: 1'0 + Constant input on bit 1069 of port A: 1'0 + Constant input on bit 1070 of port A: 1'0 + Constant input on bit 1071 of port A: 1'0 + Constant input on bit 1072 of port A: 1'0 + Constant input on bit 1073 of port A: 1'0 + Constant input on bit 1074 of port A: 1'0 + Constant input on bit 1075 of port A: 1'0 + Constant input on bit 1076 of port A: 1'0 + Constant input on bit 1077 of port A: 1'0 + Constant input on bit 1078 of port A: 1'0 + Constant input on bit 1079 of port A: 1'0 + Constant input on bit 1080 of port A: 1'0 + Constant input on bit 1081 of port A: 1'0 + Constant input on bit 1082 of port A: 1'0 + Constant input on bit 1083 of port A: 1'0 + Constant input on bit 1084 of port A: 1'0 + Constant input on bit 1085 of port A: 1'0 + Constant input on bit 1086 of port A: 1'0 + Constant input on bit 1087 of port A: 1'0 + Constant input on bit 1088 of port A: 1'0 + Constant input on bit 1089 of port A: 1'0 + Constant input on bit 1090 of port A: 1'0 + Constant input on bit 1091 of port A: 1'0 + Constant input on bit 1092 of port A: 1'0 + Constant input on bit 1093 of port A: 1'0 + Constant input on bit 1094 of port A: 1'0 + Constant input on bit 1095 of port A: 1'0 + Constant input on bit 1096 of port A: 1'0 + Constant input on bit 1097 of port A: 1'0 + Constant input on bit 1098 of port A: 1'0 + Constant input on bit 1099 of port A: 1'0 + Constant input on bit 1100 of port A: 1'0 + Constant input on bit 1101 of port A: 1'0 + Constant input on bit 1102 of port A: 1'0 + Constant input on bit 1103 of port A: 1'0 + Constant input on bit 1104 of port A: 1'0 + Constant input on bit 1105 of port A: 1'0 + Constant input on bit 1106 of port A: 1'0 + Constant input on bit 1107 of port A: 1'0 + Constant input on bit 1108 of port A: 1'0 + Constant input on bit 1109 of port A: 1'0 + Constant input on bit 1110 of port A: 1'0 + Constant input on bit 1111 of port A: 1'0 + Constant input on bit 1112 of port A: 1'0 + Constant input on bit 1113 of port A: 1'0 + Constant input on bit 1114 of port A: 1'0 + Constant input on bit 1115 of port A: 1'0 + Constant input on bit 1116 of port A: 1'0 + Constant input on bit 1117 of port A: 1'0 + Constant input on bit 1118 of port A: 1'0 + Constant input on bit 1119 of port A: 1'0 + Constant input on bit 1120 of port A: 1'0 + Constant input on bit 1121 of port A: 1'0 + Constant input on bit 1122 of port A: 1'0 + Constant input on bit 1123 of port A: 1'0 + Constant input on bit 1124 of port A: 1'0 + Constant input on bit 1125 of port A: 1'0 + Constant input on bit 1126 of port A: 1'0 + Constant input on bit 1127 of port A: 1'0 + Constant input on bit 1128 of port A: 1'0 + Constant input on bit 1129 of port A: 1'0 + Constant input on bit 1130 of port A: 1'0 + Constant input on bit 1131 of port A: 1'0 + Constant input on bit 1132 of port A: 1'0 + Constant input on bit 1133 of port A: 1'0 + Constant input on bit 1134 of port A: 1'0 + Constant input on bit 1135 of port A: 1'0 + Constant input on bit 1136 of port A: 1'0 + Constant input on bit 1137 of port A: 1'0 + Constant input on bit 1138 of port A: 1'0 + Constant input on bit 1139 of port A: 1'0 + Constant input on bit 1140 of port A: 1'0 + Constant input on bit 1141 of port A: 1'0 + Constant input on bit 1142 of port A: 1'0 + Constant input on bit 1143 of port A: 1'0 + Constant input on bit 1144 of port A: 1'0 + Constant input on bit 1145 of port A: 1'0 + Constant input on bit 1146 of port A: 1'0 + Constant input on bit 1147 of port A: 1'0 + Constant input on bit 1148 of port A: 1'0 + Constant input on bit 1149 of port A: 1'0 + Constant input on bit 1150 of port A: 1'0 + Constant input on bit 1151 of port A: 1'0 + Constant input on bit 1152 of port A: 1'0 + Constant input on bit 1153 of port A: 1'0 + Constant input on bit 1154 of port A: 1'0 + Constant input on bit 1155 of port A: 1'0 + Constant input on bit 1156 of port A: 1'0 + Constant input on bit 1157 of port A: 1'0 + Constant input on bit 1158 of port A: 1'0 + Constant input on bit 1159 of port A: 1'0 + Constant input on bit 1160 of port A: 1'0 + Constant input on bit 1161 of port A: 1'0 + Constant input on bit 1162 of port A: 1'0 + Constant input on bit 1163 of port A: 1'0 + Constant input on bit 1164 of port A: 1'0 + Constant input on bit 1165 of port A: 1'0 + Constant input on bit 1166 of port A: 1'0 + Constant input on bit 1167 of port A: 1'0 + Constant input on bit 1168 of port A: 1'0 + Constant input on bit 1169 of port A: 1'0 + Constant input on bit 1170 of port A: 1'0 + Constant input on bit 1171 of port A: 1'0 + Constant input on bit 1172 of port A: 1'0 + Constant input on bit 1173 of port A: 1'0 + Constant input on bit 1174 of port A: 1'0 + Constant input on bit 1175 of port A: 1'0 + Constant input on bit 1176 of port A: 1'0 + Constant input on bit 1177 of port A: 1'0 + Constant input on bit 1178 of port A: 1'0 + Constant input on bit 1179 of port A: 1'0 + Constant input on bit 1180 of port A: 1'0 + Constant input on bit 1181 of port A: 1'0 + Constant input on bit 1182 of port A: 1'0 + Constant input on bit 1183 of port A: 1'0 + Constant input on bit 1184 of port A: 1'0 + Constant input on bit 1185 of port A: 1'0 + Constant input on bit 1186 of port A: 1'0 + Constant input on bit 1187 of port A: 1'0 + Constant input on bit 1188 of port A: 1'0 + Constant input on bit 1189 of port A: 1'0 + Constant input on bit 1190 of port A: 1'0 + Constant input on bit 1191 of port A: 1'0 + Constant input on bit 1192 of port A: 1'0 + Constant input on bit 1193 of port A: 1'0 + Constant input on bit 1194 of port A: 1'0 + Constant input on bit 1195 of port A: 1'0 + Constant input on bit 1196 of port A: 1'0 + Constant input on bit 1197 of port A: 1'0 + Constant input on bit 1198 of port A: 1'0 + Constant input on bit 1199 of port A: 1'0 + Constant input on bit 1200 of port A: 1'0 + Constant input on bit 1201 of port A: 1'0 + Constant input on bit 1202 of port A: 1'0 + Constant input on bit 1203 of port A: 1'0 + Constant input on bit 1204 of port A: 1'0 + Constant input on bit 1205 of port A: 1'0 + Constant input on bit 1206 of port A: 1'0 + Constant input on bit 1207 of port A: 1'0 + Constant input on bit 1208 of port A: 1'0 + Constant input on bit 1209 of port A: 1'0 + Constant input on bit 1210 of port A: 1'0 + Constant input on bit 1211 of port A: 1'0 + Constant input on bit 1212 of port A: 1'0 + Constant input on bit 1213 of port A: 1'0 + Constant input on bit 1214 of port A: 1'0 + Constant input on bit 1215 of port A: 1'0 + Constant input on bit 1216 of port A: 1'0 + Constant input on bit 1217 of port A: 1'0 + Constant input on bit 1218 of port A: 1'0 + Constant input on bit 1219 of port A: 1'0 + Constant input on bit 1220 of port A: 1'0 + Constant input on bit 1221 of port A: 1'0 + Constant input on bit 1222 of port A: 1'0 + Constant input on bit 1223 of port A: 1'0 + Constant input on bit 1224 of port A: 1'0 + Constant input on bit 1225 of port A: 1'0 + Constant input on bit 1226 of port A: 1'0 + Constant input on bit 1227 of port A: 1'0 + Constant input on bit 1228 of port A: 1'0 + Constant input on bit 1229 of port A: 1'0 + Constant input on bit 1230 of port A: 1'0 + Constant input on bit 1231 of port A: 1'0 + Constant input on bit 1232 of port A: 1'0 + Constant input on bit 1233 of port A: 1'0 + Constant input on bit 1234 of port A: 1'0 + Constant input on bit 1235 of port A: 1'0 + Constant input on bit 1236 of port A: 1'0 + Constant input on bit 1237 of port A: 1'0 + Constant input on bit 1238 of port A: 1'0 + Constant input on bit 1239 of port A: 1'0 + Constant input on bit 1240 of port A: 1'0 + Constant input on bit 1241 of port A: 1'0 + Constant input on bit 1242 of port A: 1'0 + Constant input on bit 1243 of port A: 1'0 + Constant input on bit 1244 of port A: 1'0 + Constant input on bit 1245 of port A: 1'0 + Constant input on bit 1246 of port A: 1'0 + Constant input on bit 1247 of port A: 1'0 + Constant input on bit 1248 of port A: 1'0 + Constant input on bit 1249 of port A: 1'0 + Constant input on bit 1250 of port A: 1'0 + Constant input on bit 1251 of port A: 1'0 + Constant input on bit 1252 of port A: 1'0 + Constant input on bit 1253 of port A: 1'0 + Constant input on bit 1254 of port A: 1'0 + Constant input on bit 1255 of port A: 1'0 + Constant input on bit 1256 of port A: 1'0 + Constant input on bit 1257 of port A: 1'0 + Constant input on bit 1258 of port A: 1'0 + Constant input on bit 1259 of port A: 1'0 + Constant input on bit 1260 of port A: 1'0 + Constant input on bit 1261 of port A: 1'0 + Constant input on bit 1262 of port A: 1'0 + Constant input on bit 1263 of port A: 1'0 + Constant input on bit 1264 of port A: 1'0 + Constant input on bit 1265 of port A: 1'0 + Constant input on bit 1266 of port A: 1'0 + Constant input on bit 1267 of port A: 1'0 + Constant input on bit 1268 of port A: 1'0 + Constant input on bit 1269 of port A: 1'0 + Constant input on bit 1270 of port A: 1'0 + Constant input on bit 1271 of port A: 1'0 + Constant input on bit 1272 of port A: 1'0 + Constant input on bit 1273 of port A: 1'0 + Constant input on bit 1274 of port A: 1'0 + Constant input on bit 1275 of port A: 1'0 + Constant input on bit 1276 of port A: 1'0 + Constant input on bit 1277 of port A: 1'0 + Constant input on bit 1278 of port A: 1'0 + Constant input on bit 1279 of port A: 1'0 + Constant input on bit 1280 of port A: 1'0 + Constant input on bit 1281 of port A: 1'0 + Constant input on bit 1282 of port A: 1'0 + Constant input on bit 1283 of port A: 1'0 + Constant input on bit 1284 of port A: 1'0 + Constant input on bit 1285 of port A: 1'0 + Constant input on bit 1286 of port A: 1'0 + Constant input on bit 1287 of port A: 1'0 + Constant input on bit 1288 of port A: 1'0 + Constant input on bit 1289 of port A: 1'0 + Constant input on bit 1290 of port A: 1'0 + Constant input on bit 1291 of port A: 1'0 + Constant input on bit 1292 of port A: 1'0 + Constant input on bit 1293 of port A: 1'0 + Constant input on bit 1294 of port A: 1'0 + Constant input on bit 1295 of port A: 1'0 + Constant input on bit 1296 of port A: 1'0 + Constant input on bit 1297 of port A: 1'0 + Constant input on bit 1298 of port A: 1'0 + Constant input on bit 1299 of port A: 1'0 + Constant input on bit 1300 of port A: 1'0 + Constant input on bit 1301 of port A: 1'0 + Constant input on bit 1302 of port A: 1'0 + Constant input on bit 1303 of port A: 1'0 + Constant input on bit 1304 of port A: 1'0 + Constant input on bit 1305 of port A: 1'0 + Constant input on bit 1306 of port A: 1'0 + Constant input on bit 1307 of port A: 1'0 + Constant input on bit 1308 of port A: 1'0 + Constant input on bit 1309 of port A: 1'0 + Constant input on bit 1310 of port A: 1'0 + Constant input on bit 1311 of port A: 1'0 + Constant input on bit 1312 of port A: 1'0 + Constant input on bit 1313 of port A: 1'0 + Constant input on bit 1314 of port A: 1'0 + Constant input on bit 1315 of port A: 1'0 + Constant input on bit 1316 of port A: 1'0 + Constant input on bit 1317 of port A: 1'0 + Constant input on bit 1318 of port A: 1'0 + Constant input on bit 1319 of port A: 1'0 + Constant input on bit 1320 of port A: 1'0 + Constant input on bit 1321 of port A: 1'0 + Constant input on bit 1322 of port A: 1'0 + Constant input on bit 1323 of port A: 1'0 + Constant input on bit 1324 of port A: 1'0 + Constant input on bit 1325 of port A: 1'0 + Constant input on bit 1326 of port A: 1'0 + Constant input on bit 1327 of port A: 1'0 + Constant input on bit 1328 of port A: 1'0 + Constant input on bit 1329 of port A: 1'0 + Constant input on bit 1330 of port A: 1'0 + Constant input on bit 1331 of port A: 1'0 + Constant input on bit 1332 of port A: 1'0 + Constant input on bit 1333 of port A: 1'0 + Constant input on bit 1334 of port A: 1'0 + Constant input on bit 1335 of port A: 1'0 + Constant input on bit 1336 of port A: 1'0 + Constant input on bit 1337 of port A: 1'0 + Constant input on bit 1338 of port A: 1'0 + Constant input on bit 1339 of port A: 1'0 + Constant input on bit 1340 of port A: 1'0 + Constant input on bit 1341 of port A: 1'0 + Constant input on bit 1342 of port A: 1'0 + Constant input on bit 1343 of port A: 1'0 + Constant input on bit 1344 of port A: 1'0 + Constant input on bit 1345 of port A: 1'0 + Constant input on bit 1346 of port A: 1'0 + Constant input on bit 1347 of port A: 1'0 + Constant input on bit 1348 of port A: 1'0 + Constant input on bit 1349 of port A: 1'0 + Constant input on bit 1350 of port A: 1'0 + Constant input on bit 1351 of port A: 1'0 + Constant input on bit 1352 of port A: 1'0 + Constant input on bit 1353 of port A: 1'0 + Constant input on bit 1354 of port A: 1'0 + Constant input on bit 1355 of port A: 1'0 + Constant input on bit 1356 of port A: 1'0 + Constant input on bit 1357 of port A: 1'0 + Constant input on bit 1358 of port A: 1'0 + Constant input on bit 1359 of port A: 1'0 + Constant input on bit 1360 of port A: 1'0 + Constant input on bit 1361 of port A: 1'0 + Constant input on bit 1362 of port A: 1'0 + Constant input on bit 1363 of port A: 1'0 + Constant input on bit 1364 of port A: 1'0 + Constant input on bit 1365 of port A: 1'0 + Constant input on bit 1366 of port A: 1'0 + Constant input on bit 1367 of port A: 1'0 + Constant input on bit 1368 of port A: 1'0 + Constant input on bit 1369 of port A: 1'0 + Constant input on bit 1370 of port A: 1'0 + Constant input on bit 1371 of port A: 1'0 + Constant input on bit 1372 of port A: 1'0 + Constant input on bit 1373 of port A: 1'0 + Constant input on bit 1374 of port A: 1'0 + Constant input on bit 1375 of port A: 1'0 + Constant input on bit 1376 of port A: 1'0 + Constant input on bit 1377 of port A: 1'0 + Constant input on bit 1378 of port A: 1'0 + Constant input on bit 1379 of port A: 1'0 + Constant input on bit 1380 of port A: 1'0 + Constant input on bit 1381 of port A: 1'0 + Constant input on bit 1382 of port A: 1'0 + Constant input on bit 1383 of port A: 1'0 + Constant input on bit 1384 of port A: 1'0 + Constant input on bit 1385 of port A: 1'0 + Constant input on bit 1386 of port A: 1'0 + Constant input on bit 1387 of port A: 1'0 + Constant input on bit 1388 of port A: 1'0 + Constant input on bit 1389 of port A: 1'0 + Constant input on bit 1390 of port A: 1'0 + Constant input on bit 1391 of port A: 1'0 + Constant input on bit 1392 of port A: 1'0 + Constant input on bit 1393 of port A: 1'0 + Constant input on bit 1394 of port A: 1'0 + Constant input on bit 1395 of port A: 1'0 + Constant input on bit 1396 of port A: 1'0 + Constant input on bit 1397 of port A: 1'0 + Constant input on bit 1398 of port A: 1'0 + Constant input on bit 1399 of port A: 1'0 + Constant input on bit 1400 of port A: 1'0 + Constant input on bit 1401 of port A: 1'0 + Constant input on bit 1402 of port A: 1'0 + Constant input on bit 1403 of port A: 1'0 + Constant input on bit 1404 of port A: 1'0 + Constant input on bit 1405 of port A: 1'0 + Constant input on bit 1406 of port A: 1'0 + Constant input on bit 1407 of port A: 1'0 + Constant input on bit 1408 of port A: 1'0 + Constant input on bit 1409 of port A: 1'0 + Constant input on bit 1410 of port A: 1'0 + Constant input on bit 1411 of port A: 1'0 + Constant input on bit 1412 of port A: 1'0 + Constant input on bit 1413 of port A: 1'0 + Constant input on bit 1414 of port A: 1'0 + Constant input on bit 1415 of port A: 1'0 + Constant input on bit 1416 of port A: 1'0 + Constant input on bit 1417 of port A: 1'0 + Constant input on bit 1418 of port A: 1'0 + Constant input on bit 1419 of port A: 1'0 + Constant input on bit 1420 of port A: 1'0 + Constant input on bit 1421 of port A: 1'0 + Constant input on bit 1422 of port A: 1'0 + Constant input on bit 1423 of port A: 1'0 + Constant input on bit 1424 of port A: 1'0 + Constant input on bit 1425 of port A: 1'0 + Constant input on bit 1426 of port A: 1'0 + Constant input on bit 1427 of port A: 1'0 + Constant input on bit 1428 of port A: 1'0 + Constant input on bit 1429 of port A: 1'0 + Constant input on bit 1430 of port A: 1'0 + Constant input on bit 1431 of port A: 1'0 + Constant input on bit 1432 of port A: 1'0 + Constant input on bit 1433 of port A: 1'0 + Constant input on bit 1434 of port A: 1'0 + Constant input on bit 1435 of port A: 1'0 + Constant input on bit 1436 of port A: 1'0 + Constant input on bit 1437 of port A: 1'0 + Constant input on bit 1438 of port A: 1'0 + Constant input on bit 1439 of port A: 1'0 + Constant input on bit 1440 of port A: 1'0 + Constant input on bit 1441 of port A: 1'0 + Constant input on bit 1442 of port A: 1'0 + Constant input on bit 1443 of port A: 1'0 + Constant input on bit 1444 of port A: 1'0 + Constant input on bit 1445 of port A: 1'0 + Constant input on bit 1446 of port A: 1'0 + Constant input on bit 1447 of port A: 1'0 + Constant input on bit 1448 of port A: 1'0 + Constant input on bit 1449 of port A: 1'0 + Constant input on bit 1450 of port A: 1'0 + Constant input on bit 1451 of port A: 1'0 + Constant input on bit 1452 of port A: 1'0 + Constant input on bit 1453 of port A: 1'0 + Constant input on bit 1454 of port A: 1'0 + Constant input on bit 1455 of port A: 1'0 + Constant input on bit 1456 of port A: 1'0 + Constant input on bit 1457 of port A: 1'0 + Constant input on bit 1458 of port A: 1'0 + Constant input on bit 1459 of port A: 1'0 + Constant input on bit 1460 of port A: 1'0 + Constant input on bit 1461 of port A: 1'0 + Constant input on bit 1462 of port A: 1'0 + Constant input on bit 1463 of port A: 1'0 + Constant input on bit 1464 of port A: 1'0 + Constant input on bit 1465 of port A: 1'0 + Constant input on bit 1466 of port A: 1'0 + Constant input on bit 1467 of port A: 1'0 + Constant input on bit 1468 of port A: 1'0 + Constant input on bit 1469 of port A: 1'0 + Constant input on bit 1470 of port A: 1'0 + Constant input on bit 1471 of port A: 1'0 + Constant input on bit 1472 of port A: 1'0 + Constant input on bit 1473 of port A: 1'0 + Constant input on bit 1474 of port A: 1'0 + Constant input on bit 1475 of port A: 1'0 + Constant input on bit 1476 of port A: 1'0 + Constant input on bit 1477 of port A: 1'0 + Constant input on bit 1478 of port A: 1'0 + Constant input on bit 1479 of port A: 1'0 + Constant input on bit 1480 of port A: 1'0 + Constant input on bit 1481 of port A: 1'0 + Constant input on bit 1482 of port A: 1'0 + Constant input on bit 1483 of port A: 1'0 + Constant input on bit 1484 of port A: 1'0 + Constant input on bit 1485 of port A: 1'0 + Constant input on bit 1486 of port A: 1'0 + Constant input on bit 1487 of port A: 1'0 + Constant input on bit 1488 of port A: 1'0 + Constant input on bit 1489 of port A: 1'0 + Constant input on bit 1490 of port A: 1'0 + Constant input on bit 1491 of port A: 1'0 + Constant input on bit 1492 of port A: 1'0 + Constant input on bit 1493 of port A: 1'0 + Constant input on bit 1494 of port A: 1'0 + Constant input on bit 1495 of port A: 1'0 + Constant input on bit 1496 of port A: 1'0 + Constant input on bit 1497 of port A: 1'0 + Constant input on bit 1498 of port A: 1'0 + Constant input on bit 1499 of port A: 1'0 + Constant input on bit 1500 of port A: 1'0 + Constant input on bit 1501 of port A: 1'0 + Constant input on bit 1502 of port A: 1'0 + Constant input on bit 1503 of port A: 1'0 + Constant input on bit 1504 of port A: 1'0 + Constant input on bit 1505 of port A: 1'0 + Constant input on bit 1506 of port A: 1'0 + Constant input on bit 1507 of port A: 1'0 + Constant input on bit 1508 of port A: 1'0 + Constant input on bit 1509 of port A: 1'0 + Constant input on bit 1510 of port A: 1'0 + Constant input on bit 1511 of port A: 1'0 + Constant input on bit 1512 of port A: 1'0 + Constant input on bit 1513 of port A: 1'0 + Constant input on bit 1514 of port A: 1'0 + Constant input on bit 1515 of port A: 1'0 + Constant input on bit 1516 of port A: 1'0 + Constant input on bit 1517 of port A: 1'0 + Constant input on bit 1518 of port A: 1'0 + Constant input on bit 1519 of port A: 1'0 + Constant input on bit 1520 of port A: 1'0 + Constant input on bit 1521 of port A: 1'0 + Constant input on bit 1522 of port A: 1'0 + Constant input on bit 1523 of port A: 1'0 + Constant input on bit 1524 of port A: 1'0 + Constant input on bit 1525 of port A: 1'0 + Constant input on bit 1526 of port A: 1'0 + Constant input on bit 1527 of port A: 1'0 + Constant input on bit 1528 of port A: 1'0 + Constant input on bit 1529 of port A: 1'0 + Constant input on bit 1530 of port A: 1'0 + Constant input on bit 1531 of port A: 1'0 + Constant input on bit 1532 of port A: 1'0 + Constant input on bit 1533 of port A: 1'0 + Constant input on bit 1534 of port A: 1'0 + Constant input on bit 1535 of port A: 1'0 + Constant input on bit 1536 of port A: 1'0 + Constant input on bit 1537 of port A: 1'0 + Constant input on bit 1538 of port A: 1'0 + Constant input on bit 1539 of port A: 1'0 + Constant input on bit 1540 of port A: 1'0 + Constant input on bit 1541 of port A: 1'0 + Constant input on bit 1542 of port A: 1'0 + Constant input on bit 1543 of port A: 1'0 + Constant input on bit 1544 of port A: 1'0 + Constant input on bit 1545 of port A: 1'0 + Constant input on bit 1546 of port A: 1'0 + Constant input on bit 1547 of port A: 1'0 + Constant input on bit 1548 of port A: 1'0 + Constant input on bit 1549 of port A: 1'0 + Constant input on bit 1550 of port A: 1'0 + Constant input on bit 1551 of port A: 1'0 + Constant input on bit 1552 of port A: 1'0 + Constant input on bit 1553 of port A: 1'0 + Constant input on bit 1554 of port A: 1'0 + Constant input on bit 1555 of port A: 1'0 + Constant input on bit 1556 of port A: 1'0 + Constant input on bit 1557 of port A: 1'0 + Constant input on bit 1558 of port A: 1'0 + Constant input on bit 1559 of port A: 1'0 + Constant input on bit 1560 of port A: 1'0 + Constant input on bit 1561 of port A: 1'0 + Constant input on bit 1562 of port A: 1'0 + Constant input on bit 1563 of port A: 1'0 + Constant input on bit 1564 of port A: 1'0 + Constant input on bit 1565 of port A: 1'0 + Constant input on bit 1566 of port A: 1'0 + Constant input on bit 1567 of port A: 1'0 + Constant input on bit 1568 of port A: 1'0 + Constant input on bit 1569 of port A: 1'0 + Constant input on bit 1570 of port A: 1'0 + Constant input on bit 1571 of port A: 1'0 + Constant input on bit 1572 of port A: 1'0 + Constant input on bit 1573 of port A: 1'0 + Constant input on bit 1574 of port A: 1'0 + Constant input on bit 1575 of port A: 1'0 + Constant input on bit 1576 of port A: 1'0 + Constant input on bit 1577 of port A: 1'0 + Constant input on bit 1578 of port A: 1'0 + Constant input on bit 1579 of port A: 1'0 + Constant input on bit 1580 of port A: 1'0 + Constant input on bit 1581 of port A: 1'0 + Constant input on bit 1582 of port A: 1'0 + Constant input on bit 1583 of port A: 1'0 + Constant input on bit 1584 of port A: 1'0 + Constant input on bit 1585 of port A: 1'0 + Constant input on bit 1586 of port A: 1'0 + Constant input on bit 1587 of port A: 1'0 + Constant input on bit 1588 of port A: 1'0 + Constant input on bit 1589 of port A: 1'0 + Constant input on bit 1590 of port A: 1'0 + Constant input on bit 1591 of port A: 1'0 + Constant input on bit 1592 of port A: 1'0 + Constant input on bit 1593 of port A: 1'0 + Constant input on bit 1594 of port A: 1'0 + Constant input on bit 1595 of port A: 1'0 + Constant input on bit 1596 of port A: 1'0 + Constant input on bit 1597 of port A: 1'0 + Constant input on bit 1598 of port A: 1'0 + Constant input on bit 1599 of port A: 1'0 + Constant input on bit 1600 of port A: 1'0 + Constant input on bit 1601 of port A: 1'0 + Constant input on bit 1602 of port A: 1'0 + Constant input on bit 1603 of port A: 1'0 + Constant input on bit 1604 of port A: 1'0 + Constant input on bit 1605 of port A: 1'0 + Constant input on bit 1606 of port A: 1'0 + Constant input on bit 1607 of port A: 1'0 + Constant input on bit 1608 of port A: 1'0 + Constant input on bit 1609 of port A: 1'0 + Constant input on bit 1610 of port A: 1'0 + Constant input on bit 1611 of port A: 1'0 + Constant input on bit 1612 of port A: 1'0 + Constant input on bit 1613 of port A: 1'0 + Constant input on bit 1614 of port A: 1'0 + Constant input on bit 1615 of port A: 1'0 + Constant input on bit 1616 of port A: 1'0 + Constant input on bit 1617 of port A: 1'0 + Constant input on bit 1618 of port A: 1'0 + Constant input on bit 1619 of port A: 1'0 + Constant input on bit 1620 of port A: 1'0 + Constant input on bit 1621 of port A: 1'0 + Constant input on bit 1622 of port A: 1'0 + Constant input on bit 1623 of port A: 1'0 + Constant input on bit 1624 of port A: 1'0 + Constant input on bit 1625 of port A: 1'0 + Constant input on bit 1626 of port A: 1'0 + Constant input on bit 1627 of port A: 1'0 + Constant input on bit 1628 of port A: 1'0 + Constant input on bit 1629 of port A: 1'0 + Constant input on bit 1630 of port A: 1'0 + Constant input on bit 1631 of port A: 1'0 + Constant input on bit 1632 of port A: 1'0 + Constant input on bit 1633 of port A: 1'0 + Constant input on bit 1634 of port A: 1'0 + Constant input on bit 1635 of port A: 1'0 + Constant input on bit 1636 of port A: 1'0 + Constant input on bit 1637 of port A: 1'0 + Constant input on bit 1638 of port A: 1'0 + Constant input on bit 1639 of port A: 1'0 + Constant input on bit 1640 of port A: 1'0 + Constant input on bit 1641 of port A: 1'0 + Constant input on bit 1642 of port A: 1'0 + Constant input on bit 1643 of port A: 1'0 + Constant input on bit 1644 of port A: 1'0 + Constant input on bit 1645 of port A: 1'0 + Constant input on bit 1646 of port A: 1'0 + Constant input on bit 1647 of port A: 1'0 + Constant input on bit 1648 of port A: 1'0 + Constant input on bit 1649 of port A: 1'0 + Constant input on bit 1650 of port A: 1'0 + Constant input on bit 1651 of port A: 1'0 + Constant input on bit 1652 of port A: 1'0 + Constant input on bit 1653 of port A: 1'0 + Constant input on bit 1654 of port A: 1'0 + Constant input on bit 1655 of port A: 1'0 + Constant input on bit 1656 of port A: 1'0 + Constant input on bit 1657 of port A: 1'0 + Constant input on bit 1658 of port A: 1'0 + Constant input on bit 1659 of port A: 1'0 + Constant input on bit 1660 of port A: 1'0 + Constant input on bit 1661 of port A: 1'0 + Constant input on bit 1662 of port A: 1'0 + Constant input on bit 1663 of port A: 1'0 + Constant input on bit 1664 of port A: 1'0 + Constant input on bit 1665 of port A: 1'0 + Constant input on bit 1666 of port A: 1'0 + Constant input on bit 1667 of port A: 1'0 + Constant input on bit 1668 of port A: 1'0 + Constant input on bit 1669 of port A: 1'0 + Constant input on bit 1670 of port A: 1'0 + Constant input on bit 1671 of port A: 1'0 + Constant input on bit 1672 of port A: 1'0 + Constant input on bit 1673 of port A: 1'0 + Constant input on bit 1674 of port A: 1'0 + Constant input on bit 1675 of port A: 1'0 + Constant input on bit 1676 of port A: 1'0 + Constant input on bit 1677 of port A: 1'0 + Constant input on bit 1678 of port A: 1'0 + Constant input on bit 1679 of port A: 1'0 + Constant input on bit 1680 of port A: 1'0 + Constant input on bit 1681 of port A: 1'0 + Constant input on bit 1682 of port A: 1'0 + Constant input on bit 1683 of port A: 1'0 + Constant input on bit 1684 of port A: 1'0 + Constant input on bit 1685 of port A: 1'0 + Constant input on bit 1686 of port A: 1'0 + Constant input on bit 1687 of port A: 1'0 + Constant input on bit 1688 of port A: 1'0 + Constant input on bit 1689 of port A: 1'0 + Constant input on bit 1690 of port A: 1'0 + Constant input on bit 1691 of port A: 1'0 + Constant input on bit 1692 of port A: 1'0 + Constant input on bit 1693 of port A: 1'0 + Constant input on bit 1694 of port A: 1'0 + Constant input on bit 1695 of port A: 1'0 + Constant input on bit 1696 of port A: 1'0 + Constant input on bit 1697 of port A: 1'0 + Constant input on bit 1698 of port A: 1'0 + Constant input on bit 1699 of port A: 1'0 + Constant input on bit 1700 of port A: 1'0 + Constant input on bit 1701 of port A: 1'0 + Constant input on bit 1702 of port A: 1'0 + Constant input on bit 1703 of port A: 1'0 + Constant input on bit 1704 of port A: 1'0 + Constant input on bit 1705 of port A: 1'0 + Constant input on bit 1706 of port A: 1'0 + Constant input on bit 1707 of port A: 1'0 + Constant input on bit 1708 of port A: 1'0 + Constant input on bit 1709 of port A: 1'0 + Constant input on bit 1710 of port A: 1'0 + Constant input on bit 1711 of port A: 1'0 + Constant input on bit 1712 of port A: 1'0 + Constant input on bit 1713 of port A: 1'0 + Constant input on bit 1714 of port A: 1'0 + Constant input on bit 1715 of port A: 1'0 + Constant input on bit 1716 of port A: 1'0 + Constant input on bit 1717 of port A: 1'0 + Constant input on bit 1718 of port A: 1'0 + Constant input on bit 1719 of port A: 1'0 + Constant input on bit 1720 of port A: 1'0 + Constant input on bit 1721 of port A: 1'0 + Constant input on bit 1722 of port A: 1'0 + Constant input on bit 1723 of port A: 1'0 + Constant input on bit 1724 of port A: 1'0 + Constant input on bit 1725 of port A: 1'0 + Constant input on bit 1726 of port A: 1'0 + Constant input on bit 1727 of port A: 1'0 + Constant input on bit 1728 of port A: 1'0 + Constant input on bit 1729 of port A: 1'0 + Constant input on bit 1730 of port A: 1'0 + Constant input on bit 1731 of port A: 1'0 + Constant input on bit 1732 of port A: 1'0 + Constant input on bit 1733 of port A: 1'0 + Constant input on bit 1734 of port A: 1'0 + Constant input on bit 1735 of port A: 1'0 + Constant input on bit 1736 of port A: 1'0 + Constant input on bit 1737 of port A: 1'0 + Constant input on bit 1738 of port A: 1'0 + Constant input on bit 1739 of port A: 1'0 + Constant input on bit 1740 of port A: 1'0 + Constant input on bit 1741 of port A: 1'0 + Constant input on bit 1742 of port A: 1'0 + Constant input on bit 1743 of port A: 1'0 + Constant input on bit 1744 of port A: 1'0 + Constant input on bit 1745 of port A: 1'0 + Constant input on bit 1746 of port A: 1'0 + Constant input on bit 1747 of port A: 1'0 + Constant input on bit 1748 of port A: 1'0 + Constant input on bit 1749 of port A: 1'0 + Constant input on bit 1750 of port A: 1'0 + Constant input on bit 1751 of port A: 1'0 + Constant input on bit 1752 of port A: 1'0 + Constant input on bit 1753 of port A: 1'0 + Constant input on bit 1754 of port A: 1'0 + Constant input on bit 1755 of port A: 1'0 + Constant input on bit 1756 of port A: 1'0 + Constant input on bit 1757 of port A: 1'0 + Constant input on bit 1758 of port A: 1'0 + Constant input on bit 1759 of port A: 1'0 + Constant input on bit 1760 of port A: 1'0 + Constant input on bit 1761 of port A: 1'0 + Constant input on bit 1762 of port A: 1'0 + Constant input on bit 1763 of port A: 1'0 + Constant input on bit 1764 of port A: 1'0 + Constant input on bit 1765 of port A: 1'0 + Constant input on bit 1766 of port A: 1'0 + Constant input on bit 1767 of port A: 1'0 + Constant input on bit 1768 of port A: 1'0 + Constant input on bit 1769 of port A: 1'0 + Constant input on bit 1770 of port A: 1'0 + Constant input on bit 1771 of port A: 1'0 + Constant input on bit 1772 of port A: 1'0 + Constant input on bit 1773 of port A: 1'0 + Constant input on bit 1774 of port A: 1'0 + Constant input on bit 1775 of port A: 1'0 + Constant input on bit 1776 of port A: 1'0 + Constant input on bit 1777 of port A: 1'0 + Constant input on bit 1778 of port A: 1'0 + Constant input on bit 1779 of port A: 1'0 + Constant input on bit 1780 of port A: 1'0 + Constant input on bit 1781 of port A: 1'0 + Constant input on bit 1782 of port A: 1'0 + Constant input on bit 1783 of port A: 1'0 + Constant input on bit 1784 of port A: 1'0 + Constant input on bit 1785 of port A: 1'0 + Constant input on bit 1786 of port A: 1'0 + Constant input on bit 1787 of port A: 1'0 + Constant input on bit 1788 of port A: 1'0 + Constant input on bit 1789 of port A: 1'0 + Constant input on bit 1790 of port A: 1'0 + Constant input on bit 1791 of port A: 1'0 + Constant input on bit 1792 of port A: 1'0 + Constant input on bit 1793 of port A: 1'0 + Constant input on bit 1794 of port A: 1'0 + Constant input on bit 1795 of port A: 1'0 + Constant input on bit 1796 of port A: 1'0 + Constant input on bit 1797 of port A: 1'0 + Constant input on bit 1798 of port A: 1'0 + Constant input on bit 1799 of port A: 1'0 + Constant input on bit 1800 of port A: 1'0 + Constant input on bit 1801 of port A: 1'0 + Constant input on bit 1802 of port A: 1'0 + Constant input on bit 1803 of port A: 1'0 + Constant input on bit 1804 of port A: 1'0 + Constant input on bit 1805 of port A: 1'0 + Constant input on bit 1806 of port A: 1'0 + Constant input on bit 1807 of port A: 1'0 + Constant input on bit 1808 of port A: 1'0 + Constant input on bit 1809 of port A: 1'0 + Constant input on bit 1810 of port A: 1'0 + Constant input on bit 1811 of port A: 1'0 + Constant input on bit 1812 of port A: 1'0 + Constant input on bit 1813 of port A: 1'0 + Constant input on bit 1814 of port A: 1'0 + Constant input on bit 1815 of port A: 1'0 + Constant input on bit 1816 of port A: 1'0 + Constant input on bit 1817 of port A: 1'0 + Constant input on bit 1818 of port A: 1'0 + Constant input on bit 1819 of port A: 1'0 + Constant input on bit 1820 of port A: 1'0 + Constant input on bit 1821 of port A: 1'0 + Constant input on bit 1822 of port A: 1'0 + Constant input on bit 1823 of port A: 1'0 + Constant input on bit 1824 of port A: 1'0 + Constant input on bit 1825 of port A: 1'0 + Constant input on bit 1826 of port A: 1'0 + Constant input on bit 1827 of port A: 1'0 + Constant input on bit 1828 of port A: 1'0 + Constant input on bit 1829 of port A: 1'0 + Constant input on bit 1830 of port A: 1'0 + Constant input on bit 1831 of port A: 1'0 + Constant input on bit 1832 of port A: 1'0 + Constant input on bit 1833 of port A: 1'0 + Constant input on bit 1834 of port A: 1'0 + Constant input on bit 1835 of port A: 1'0 + Constant input on bit 1836 of port A: 1'0 + Constant input on bit 1837 of port A: 1'0 + Constant input on bit 1838 of port A: 1'0 + Constant input on bit 1839 of port A: 1'0 + Constant input on bit 1840 of port A: 1'0 + Constant input on bit 1841 of port A: 1'0 + Constant input on bit 1842 of port A: 1'0 + Constant input on bit 1843 of port A: 1'0 + Constant input on bit 1844 of port A: 1'0 + Constant input on bit 1845 of port A: 1'0 + Constant input on bit 1846 of port A: 1'0 + Constant input on bit 1847 of port A: 1'0 + Constant input on bit 1848 of port A: 1'0 + Constant input on bit 1849 of port A: 1'0 + Constant input on bit 1850 of port A: 1'0 + Constant input on bit 1851 of port A: 1'0 + Constant input on bit 1852 of port A: 1'0 + Constant input on bit 1853 of port A: 1'0 + Constant input on bit 1854 of port A: 1'0 + Constant input on bit 1855 of port A: 1'0 + Constant input on bit 1856 of port A: 1'0 + Constant input on bit 1857 of port A: 1'0 + Constant input on bit 1858 of port A: 1'0 + Constant input on bit 1859 of port A: 1'0 + Constant input on bit 1860 of port A: 1'0 + Constant input on bit 1861 of port A: 1'0 + Constant input on bit 1862 of port A: 1'0 + Constant input on bit 1863 of port A: 1'0 + Constant input on bit 1864 of port A: 1'0 + Constant input on bit 1865 of port A: 1'0 + Constant input on bit 1866 of port A: 1'0 + Constant input on bit 1867 of port A: 1'0 + Constant input on bit 1868 of port A: 1'0 + Constant input on bit 1869 of port A: 1'0 + Constant input on bit 1870 of port A: 1'0 + Constant input on bit 1871 of port A: 1'0 + Constant input on bit 1872 of port A: 1'0 + Constant input on bit 1873 of port A: 1'0 + Constant input on bit 1874 of port A: 1'0 + Constant input on bit 1875 of port A: 1'0 + Constant input on bit 1876 of port A: 1'0 + Constant input on bit 1877 of port A: 1'0 + Constant input on bit 1878 of port A: 1'0 + Constant input on bit 1879 of port A: 1'0 + Constant input on bit 1880 of port A: 1'0 + Constant input on bit 1881 of port A: 1'0 + Constant input on bit 1882 of port A: 1'0 + Constant input on bit 1883 of port A: 1'0 + Constant input on bit 1884 of port A: 1'0 + Constant input on bit 1885 of port A: 1'0 + Constant input on bit 1886 of port A: 1'0 + Constant input on bit 1887 of port A: 1'0 + Constant input on bit 1888 of port A: 1'0 + Constant input on bit 1889 of port A: 1'0 + Constant input on bit 1890 of port A: 1'0 + Constant input on bit 1891 of port A: 1'0 + Constant input on bit 1892 of port A: 1'0 + Constant input on bit 1893 of port A: 1'0 + Constant input on bit 1894 of port A: 1'0 + Constant input on bit 1895 of port A: 1'0 + Constant input on bit 1896 of port A: 1'0 + Constant input on bit 1897 of port A: 1'0 + Constant input on bit 1898 of port A: 1'0 + Constant input on bit 1899 of port A: 1'0 + Constant input on bit 1900 of port A: 1'0 + Constant input on bit 1901 of port A: 1'0 + Constant input on bit 1902 of port A: 1'0 + Constant input on bit 1903 of port A: 1'0 + Constant input on bit 1904 of port A: 1'0 + Constant input on bit 1905 of port A: 1'0 + Constant input on bit 1906 of port A: 1'0 + Constant input on bit 1907 of port A: 1'0 + Constant input on bit 1908 of port A: 1'0 + Constant input on bit 1909 of port A: 1'0 + Constant input on bit 1910 of port A: 1'0 + Constant input on bit 1911 of port A: 1'0 + Constant input on bit 1912 of port A: 1'0 + Constant input on bit 1913 of port A: 1'0 + Constant input on bit 1914 of port A: 1'0 + Constant input on bit 1915 of port A: 1'0 + Constant input on bit 1916 of port A: 1'0 + Constant input on bit 1917 of port A: 1'0 + Constant input on bit 1918 of port A: 1'0 + Constant input on bit 1919 of port A: 1'0 + Constant input on bit 1920 of port A: 1'0 + Constant input on bit 1921 of port A: 1'0 + Constant input on bit 1922 of port A: 1'0 + Constant input on bit 1923 of port A: 1'0 + Constant input on bit 1924 of port A: 1'0 + Constant input on bit 1925 of port A: 1'0 + Constant input on bit 1926 of port A: 1'0 + Constant input on bit 1927 of port A: 1'0 + Constant input on bit 1928 of port A: 1'0 + Constant input on bit 1929 of port A: 1'0 + Constant input on bit 1930 of port A: 1'0 + Constant input on bit 1931 of port A: 1'0 + Constant input on bit 1932 of port A: 1'0 + Constant input on bit 1933 of port A: 1'0 + Constant input on bit 1934 of port A: 1'0 + Constant input on bit 1935 of port A: 1'0 + Constant input on bit 1936 of port A: 1'0 + Constant input on bit 1937 of port A: 1'0 + Constant input on bit 1938 of port A: 1'0 + Constant input on bit 1939 of port A: 1'0 + Constant input on bit 1940 of port A: 1'0 + Constant input on bit 1941 of port A: 1'0 + Constant input on bit 1942 of port A: 1'0 + Constant input on bit 1943 of port A: 1'0 + Constant input on bit 1944 of port A: 1'0 + Constant input on bit 1945 of port A: 1'0 + Constant input on bit 1946 of port A: 1'0 + Constant input on bit 1947 of port A: 1'0 + Constant input on bit 1948 of port A: 1'0 + Constant input on bit 1949 of port A: 1'0 + Constant input on bit 1950 of port A: 1'0 + Constant input on bit 1951 of port A: 1'0 + Constant input on bit 1952 of port A: 1'0 + Constant input on bit 1953 of port A: 1'0 + Constant input on bit 1954 of port A: 1'0 + Constant input on bit 1955 of port A: 1'0 + Constant input on bit 1956 of port A: 1'0 + Constant input on bit 1957 of port A: 1'0 + Constant input on bit 1958 of port A: 1'0 + Constant input on bit 1959 of port A: 1'0 + Constant input on bit 1960 of port A: 1'0 + Constant input on bit 1961 of port A: 1'0 + Constant input on bit 1962 of port A: 1'0 + Constant input on bit 1963 of port A: 1'0 + Constant input on bit 1964 of port A: 1'0 + Constant input on bit 1965 of port A: 1'0 + Constant input on bit 1966 of port A: 1'0 + Constant input on bit 1967 of port A: 1'0 + Constant input on bit 1968 of port A: 1'0 + Constant input on bit 1969 of port A: 1'0 + Constant input on bit 1970 of port A: 1'0 + Constant input on bit 1971 of port A: 1'0 + Constant input on bit 1972 of port A: 1'0 + Constant input on bit 1973 of port A: 1'0 + Constant input on bit 1974 of port A: 1'0 + Constant input on bit 1975 of port A: 1'0 + Constant input on bit 1976 of port A: 1'0 + Constant input on bit 1977 of port A: 1'0 + Constant input on bit 1978 of port A: 1'0 + Constant input on bit 1979 of port A: 1'0 + Constant input on bit 1980 of port A: 1'0 + Constant input on bit 1981 of port A: 1'0 + Constant input on bit 1982 of port A: 1'0 + Constant input on bit 1983 of port A: 1'0 + Constant input on bit 1984 of port A: 1'0 + Constant input on bit 1985 of port A: 1'0 + Constant input on bit 1986 of port A: 1'0 + Constant input on bit 1987 of port A: 1'0 + Constant input on bit 1988 of port A: 1'0 + Constant input on bit 1989 of port A: 1'0 + Constant input on bit 1990 of port A: 1'0 + Constant input on bit 1991 of port A: 1'0 + Constant input on bit 1992 of port A: 1'0 + Constant input on bit 1993 of port A: 1'0 + Constant input on bit 1994 of port A: 1'0 + Constant input on bit 1995 of port A: 1'0 + Constant input on bit 1996 of port A: 1'0 + Constant input on bit 1997 of port A: 1'0 + Constant input on bit 1998 of port A: 1'0 + Constant input on bit 1999 of port A: 1'0 + Constant input on bit 2000 of port A: 1'0 + Constant input on bit 2001 of port A: 1'0 + Constant input on bit 2002 of port A: 1'0 + Constant input on bit 2003 of port A: 1'0 + Constant input on bit 2004 of port A: 1'0 + Constant input on bit 2005 of port A: 1'0 + Constant input on bit 2006 of port A: 1'0 + Constant input on bit 2007 of port A: 1'0 + Constant input on bit 2008 of port A: 1'0 + Constant input on bit 2009 of port A: 1'0 + Constant input on bit 2010 of port A: 1'0 + Constant input on bit 2011 of port A: 1'0 + Constant input on bit 2012 of port A: 1'0 + Constant input on bit 2013 of port A: 1'0 + Constant input on bit 2014 of port A: 1'0 + Constant input on bit 2015 of port A: 1'0 + Constant input on bit 2016 of port A: 1'0 + Constant input on bit 2017 of port A: 1'0 + Constant input on bit 2018 of port A: 1'0 + Constant input on bit 2019 of port A: 1'0 + Constant input on bit 2020 of port A: 1'0 + Constant input on bit 2021 of port A: 1'0 + Constant input on bit 2022 of port A: 1'0 + Constant input on bit 2023 of port A: 1'0 + Constant input on bit 2024 of port A: 1'0 + Constant input on bit 2025 of port A: 1'0 + Constant input on bit 2026 of port A: 1'0 + Constant input on bit 2027 of port A: 1'0 + Constant input on bit 2028 of port A: 1'0 + Constant input on bit 2029 of port A: 1'0 + Constant input on bit 2030 of port A: 1'0 + Constant input on bit 2031 of port A: 1'0 + Constant input on bit 2032 of port A: 1'0 + Constant input on bit 2033 of port A: 1'0 + Constant input on bit 2034 of port A: 1'0 + Constant input on bit 2035 of port A: 1'0 + Constant input on bit 2036 of port A: 1'0 + Constant input on bit 2037 of port A: 1'0 + Constant input on bit 2038 of port A: 1'0 + Constant input on bit 2039 of port A: 1'0 + Constant input on bit 2040 of port A: 1'0 + Constant input on bit 2041 of port A: 1'0 + Constant input on bit 2042 of port A: 1'0 + Constant input on bit 2043 of port A: 1'0 + Constant input on bit 2044 of port A: 1'0 + Constant input on bit 2045 of port A: 1'0 + Constant input on bit 2046 of port A: 1'0 + Constant input on bit 2047 of port A: 1'0 +Creating constmapped module `$paramod$constmap:daa7ad788665cea58217042c64af55b4ea23971a$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx'. + +12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:daa7ad788665cea58217042c64af55b4ea23971a$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $procmux$817. + dead port 2/2 on $mux $procmux$817. + dead port 1/2 on $mux $procmux$820. + dead port 2/2 on $mux $procmux$823. + dead port 2/2 on $mux $procmux$829. + dead port 2/2 on $mux $procmux$835. + dead port 2/2 on $mux $procmux$841. + dead port 2/2 on $mux $procmux$847. + dead port 1/2 on $mux $procmux$853. + dead port 2/2 on $mux $procmux$853. + dead port 1/2 on $mux $procmux$856. + dead port 1/2 on $mux $procmux$859. + dead port 2/2 on $mux $procmux$859. + dead port 1/2 on $mux $procmux$862. + dead port 1/2 on $mux $procmux$865. + dead port 2/2 on $mux $procmux$865. + dead port 1/2 on $mux $procmux$868. + dead port 1/2 on $mux $procmux$871. + dead port 2/2 on $mux $procmux$871. + dead port 1/2 on $mux $procmux$874. + dead port 1/2 on $mux $procmux$877. + dead port 2/2 on $mux $procmux$877. + dead port 1/2 on $mux $procmux$880. + dead port 1/2 on $mux $procmux$883. + dead port 2/2 on $mux $procmux$883. + dead port 1/2 on $mux $procmux$886. +Removed 26 multiplexer ports. + + +12.25. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:daa7ad788665cea58217042c64af55b4ea23971a$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx. + +Removed 0 unused cells and 64 unused wires. +Using template $paramod$constmap:daa7ad788665cea58217042c64af55b4ea23971a$paramod$7d00db8a59728ec0e93a9e75d12a59371a9099d5\_90_shift_shiftx for cells of type $shiftx. +Using extmapper maccmap for cells of type $macc_v2. + add \u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus [7:0] * \u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus [7:0] (8x8 bits, signed) + add \u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus [15:8] * \u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus [15:8] (8x8 bits, signed) + add \u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus [23:16] * \u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus [23:16] (8x8 bits, signed) + add \u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus [31:24] * \u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus [31:24] (8x8 bits, signed) + add \u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus [39:32] * \u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus [39:32] (8x8 bits, signed) + add \u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus [47:40] * \u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus [47:40] (8x8 bits, signed) + add \u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus [55:48] * \u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus [55:48] (8x8 bits, signed) + add \u_layer.GEN_NEURON[0].u_neuron.u_mac8.x_bus [63:56] * \u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus [63:56] (8x8 bits, signed) +Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_90_alu for cells of type $alu. +Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $or. + add \u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus [7:0] * \u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus [7:0] (8x8 bits, signed) + add \u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus [15:8] * \u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus [15:8] (8x8 bits, signed) + add \u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus [23:16] * \u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus [23:16] (8x8 bits, signed) + add \u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus [31:24] * \u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus [31:24] (8x8 bits, signed) + add \u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus [39:32] * \u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus [39:32] (8x8 bits, signed) + add \u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus [47:40] * \u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus [47:40] (8x8 bits, signed) + add \u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus [55:48] * \u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus [55:48] (8x8 bits, signed) + add \u_layer.GEN_NEURON[1].u_neuron.u_mac8.x_bus [63:56] * \u_layer.GEN_NEURON[1].u_neuron.u_mac8.w_bus [63:56] (8x8 bits, signed) + add \u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus [7:0] * \u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus [7:0] (8x8 bits, signed) + add \u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus [15:8] * \u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus [15:8] (8x8 bits, signed) + add \u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus [23:16] * \u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus [23:16] (8x8 bits, signed) + add \u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus [31:24] * \u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus [31:24] (8x8 bits, signed) + add \u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus [39:32] * \u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus [39:32] (8x8 bits, signed) + add \u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus [47:40] * \u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus [47:40] (8x8 bits, signed) + add \u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus [55:48] * \u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus [55:48] (8x8 bits, signed) + add \u_layer.GEN_NEURON[2].u_neuron.u_mac8.x_bus [63:56] * \u_layer.GEN_NEURON[2].u_neuron.u_mac8.w_bus [63:56] (8x8 bits, signed) + add \u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus [7:0] * \u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus [7:0] (8x8 bits, signed) + add \u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus [15:8] * \u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus [15:8] (8x8 bits, signed) + add \u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus [23:16] * \u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus [23:16] (8x8 bits, signed) + add \u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus [31:24] * \u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus [31:24] (8x8 bits, signed) + add \u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus [39:32] * \u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus [39:32] (8x8 bits, signed) + add \u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus [47:40] * \u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus [47:40] (8x8 bits, signed) + add \u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus [55:48] * \u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus [55:48] (8x8 bits, signed) + add \u_layer.GEN_NEURON[3].u_neuron.u_mac8.x_bus [63:56] * \u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus [63:56] (8x8 bits, signed) +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010000 for cells of type $fa. +Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000100000 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000100000 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000101 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000101 for cells of type $lcu. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu. +No more expansions possible. + + +13. Executing OPT pass (performing simple optimizations). + +13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 32267 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 29422 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 25167 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 18960 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 10807 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 2707 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 2690 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 2676 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 2672 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 2668 cells of `\top'. +Finding duplicate cells in `\top'. + +Removed a total of 29599 cells. + +13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 2668 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +13.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $auto$ff.cc:337:slice$640 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [31], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [31]). +Adding EN signal on $auto$ff.cc:337:slice$610 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [1], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [1]). +Adding EN signal on $auto$ff.cc:337:slice$611 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [2], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [2]). +Adding EN signal on $auto$ff.cc:337:slice$612 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [3], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [3]). +Adding EN signal on $auto$ff.cc:337:slice$613 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [4], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [4]). +Adding EN signal on $auto$ff.cc:337:slice$614 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [5], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [5]). +Adding EN signal on $auto$ff.cc:337:slice$615 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [6], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [6]). +Adding EN signal on $auto$ff.cc:337:slice$616 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [7], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [7]). +Adding EN signal on $auto$ff.cc:337:slice$617 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [8], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [8]). +Adding EN signal on $auto$ff.cc:337:slice$618 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [9], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [9]). +Adding EN signal on $auto$ff.cc:337:slice$619 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [10], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [10]). +Adding EN signal on $auto$ff.cc:337:slice$620 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [11], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [11]). +Adding EN signal on $auto$ff.cc:337:slice$621 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [12], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [12]). +Adding EN signal on $auto$ff.cc:337:slice$622 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [13], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [13]). +Adding EN signal on $auto$ff.cc:337:slice$623 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [14], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [14]). +Adding EN signal on $auto$ff.cc:337:slice$624 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [15], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [15]). +Adding EN signal on $auto$ff.cc:337:slice$625 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [16], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [16]). +Adding EN signal on $auto$ff.cc:337:slice$626 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [17], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [17]). +Adding EN signal on $auto$ff.cc:337:slice$627 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [18], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [18]). +Adding EN signal on $auto$ff.cc:337:slice$628 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [19], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [19]). +Adding EN signal on $auto$ff.cc:337:slice$629 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [20], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [20]). +Adding EN signal on $auto$ff.cc:337:slice$630 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [21], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [21]). +Adding EN signal on $auto$ff.cc:337:slice$631 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [22], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [22]). +Adding EN signal on $auto$ff.cc:337:slice$632 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [23], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [23]). +Adding EN signal on $auto$ff.cc:337:slice$633 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [24], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [24]). +Adding EN signal on $auto$ff.cc:337:slice$634 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [25], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [25]). +Adding EN signal on $auto$ff.cc:337:slice$635 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [26], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [26]). +Adding EN signal on $auto$ff.cc:337:slice$636 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [27], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [27]). +Adding EN signal on $auto$ff.cc:337:slice$637 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [28], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [28]). +Adding EN signal on $auto$ff.cc:337:slice$638 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [29], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [29]). +Adding EN signal on $auto$ff.cc:337:slice$639 ($_SDFFE_PP0P_) from module top (D = $flatten\u_layer.\GEN_NEURON[1].u_neuron.$procmux$312_Y [30], Q = \u_layer.GEN_NEURON[1].u_neuron.acc [30]). + +13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 1095 unused cells and 13319 unused wires. + + +13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +13.9. Rerunning OPT passes. (Maybe there is more to do..) + +13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 1557 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 1524 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 1494 cells of `\top'. +Finding duplicate cells in `\top'. + +Removed a total of 63 cells. + +13.13. Executing OPT_DFF pass (perform DFF optimizations). +Handling D = Q on $auto$ff.cc:337:slice$609 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$671 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$672 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$673 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$733 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$734 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$734 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$733 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$673 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$672 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$671 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$609 ($_DFFE_PP_) from module top. + +13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 1 unused cells and 129 unused wires. + + +13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +13.16. Rerunning OPT passes. (Maybe there is more to do..) + +13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +13.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 1449 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 1446 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 1443 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 1440 cells of `\top'. +Finding duplicate cells in `\top'. + +Removed a total of 9 cells. + +13.20. Executing OPT_DFF pass (perform DFF optimizations). +Handling D = Q on $auto$ff.cc:337:slice$547 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$548 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$549 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$735 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$736 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Handling D = Q on $auto$ff.cc:337:slice$737 ($_SDFFE_PP0P_) from module top (conecting SRST instead). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$737 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$736 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$735 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$549 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$548 ($_DFFE_PP_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$547 ($_DFFE_PP_) from module top. + +13.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 8 unused cells and 9 unused wires. + + +13.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +13.23. Rerunning OPT passes. (Maybe there is more to do..) + +13.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +13.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +13.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 1396 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 1391 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 1386 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 1381 cells of `\top'. +Finding duplicate cells in `\top'. + +Removed a total of 15 cells. + +13.27. Executing OPT_DFF pass (perform DFF optimizations). + +13.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 2 unused cells and 11 unused wires. + + +13.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +13.30. Rerunning OPT passes. (Maybe there is more to do..) + +13.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +13.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +13.33. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 1379 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +13.34. Executing OPT_DFF pass (perform DFF optimizations). + +13.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +13.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +13.37. Finished fast OPT passes. (There is nothing left to do.) + +14. Executing ABC pass (technology mapping using ABC). + +14.1. Extracting gate netlist of module `\top' to `/input.blif'.. +Replacing 31 occurrences of constant undef bits with constant zero bits + +14.1.1. Executed ABC. +Extracted 1170 gates and 1319 wires to a netlist network with 146 inputs and 187 outputs. +Running ABC script: /abc.script +ABC: ======== ABC command line "source /abc.script" +ABC: + read_blif /input.blif +ABC: + read_library /stdcells.genlib +ABC: + strash +ABC: + &get -n +ABC: + &fraig -x +ABC: + &put +ABC: + scorr +ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). +ABC: + dc2 +ABC: + dretime +ABC: + strash +ABC: + &get -n +ABC: + &dch -f +ABC: + &nf +ABC: + &put +ABC: + write_blif /output.blif + +14.1.2. Re-integrating ABC results. +ABC RESULTS: AND cells: 165 +ABC RESULTS: MUX cells: 4 +ABC RESULTS: NOT cells: 85 +ABC RESULTS: OR cells: 164 +ABC RESULTS: XOR cells: 130 +ABC RESULTS: ZERO cells: 4 +ABC RESULTS: internal signals: 986 +ABC RESULTS: input signals: 146 +ABC RESULTS: output signals: 187 +Removing temp directory. +Removing global temp directory. +Removed 0 unused cells and 838 unused wires. + +15. Executing SYNTH_LATTICE pass. + +15.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +15.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +15.3. Executing HIERARCHY pass (managing design hierarchy). + +15.3.1. Analyzing design hierarchy.. +Top module: \top + +15.3.2. Analyzing design hierarchy.. +Top module: \top +Removed 0 unused modules. + +15.4. Executing PROC pass (convert processes to netlists). + +15.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +15.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +15.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +15.4.4. Executing PROC_INIT pass (extract init attributes). + +15.4.5. Executing PROC_ARST pass (detect async resets in processes). + +15.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +15.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +15.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +15.4.9. Executing PROC_DFF pass (convert process syncs to FFs). + +15.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +15.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +15.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.5. Executing CHECK pass (checking for obvious problems). +Checking module top... +Found and reported 0 problems. + +15.6. Executing FLATTEN pass (flatten design). + +15.7. Executing TRIBUF pass. + +15.8. Executing DEMINOUT pass (demote inout ports to input or output). + +15.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.11. Executing CHECK pass (checking for obvious problems). +Checking module top... +Found and reported 0 problems. + +15.12. Executing OPT pass (performing simple optimizations). + +15.12.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 757 cells of `\top'. +Finding duplicate cells in `\top'. +Computing hashes of 756 cells of `\top'. +Finding duplicate cells in `\top'. + +Removed a total of 1 cells. + +15.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +15.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +15.12.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 756 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.12.6. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$670 ($_SDFFE_PP0P_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$732 ($_SDFFE_PP0P_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$608 ($_SDFFE_PP0P_) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$794 ($_SDFFE_PP0P_) from module top. + +15.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 0 unused cells and 1 unused wires. + + +15.12.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.12.9. Rerunning OPT passes. (Maybe there is more to do..) + +15.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +15.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +15.12.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.12.13. Executing OPT_DFF pass (perform DFF optimizations). + +15.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.12.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.12.16. Finished fast OPT passes. (There is nothing left to do.) + +15.13. Executing FSM pass (extract and optimize FSM). + +15.13.1. Executing FSM_DETECT pass (finding FSMs in design). + +15.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +15.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +15.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +15.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +15.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +15.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +15.14. Executing OPT pass (performing simple optimizations). + +15.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +15.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +15.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.14.6. Executing OPT_DFF pass (perform DFF optimizations). + +15.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.14.9. Finished fast OPT passes. (There is nothing left to do.) + +15.15. Executing WREDUCE pass (reducing word size of cells). + +15.16. Executing PEEPOPT pass (run peephole optimizers). + +15.17. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.18. Executing SHARE pass (SAT-based resource sharing). + +15.19. Executing TECHMAP pass (map to technology primitives). + +15.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +15.19.2. Continuing TECHMAP pass. +No more expansions possible. + + +15.20. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.22. Executing TECHMAP pass (map to technology primitives). + +15.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +15.22.2. Continuing TECHMAP pass. +No more expansions possible. + + +15.23. Executing TECHMAP pass (map to technology primitives). + +15.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +15.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +15.24. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module top: + created 0 $alu and 0 $macc cells. + +15.25. Executing OPT pass (performing simple optimizations). + +15.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +15.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +15.25.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.25.6. Executing OPT_DFF pass (perform DFF optimizations). + +15.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.25.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.25.9. Finished fast OPT passes. (There is nothing left to do.) + +15.26. Executing MEMORY pass. + +15.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +15.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +15.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +15.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +15.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +15.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +15.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +15.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +15.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +15.29. Executing TECHMAP pass (map to technology primitives). + +15.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +15.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +15.29.3. Continuing TECHMAP pass. +No more expansions possible. + + +15.30. Executing OPT pass (performing simple optimizations). + +15.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +15.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.30.3. Executing OPT_DFF pass (perform DFF optimizations). + +15.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.30.5. Finished fast OPT passes. + +15.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +15.32. Executing OPT pass (performing simple optimizations). + +15.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +15.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +15.32.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.32.6. Executing OPT_DFF pass (perform DFF optimizations). + +15.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.32.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.32.9. Finished fast OPT passes. (There is nothing left to do.) + +15.33. Executing TECHMAP pass (map to technology primitives). + +15.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +15.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +15.33.3. Continuing TECHMAP pass. +No more expansions possible. + + +15.34. Executing OPT pass (performing simple optimizations). + +15.34.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.34.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.34.3. Executing OPT_DFF pass (perform DFF optimizations). + +15.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.34.5. Finished fast OPT passes. + +15.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +15.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +15.37. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Computing hashes of 752 cells of `\top'. +Finding duplicate cells in `\top'. +Removed a total of 0 cells. + +15.38. Executing TECHMAP pass (map to technology primitives). + +15.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +15.38.2. Continuing TECHMAP pass. +Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. +Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. +No more expansions possible. + + +15.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +15.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +15.41. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in top. + +15.42. Executing ATTRMVCP pass (move or copy attributes). + +15.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 0 unused cells and 976 unused wires. + + +15.44. Executing CHECK pass (checking for obvious problems). +Checking module top... +Found and reported 0 problems. + +15.45. Executing TECHMAP pass (map to technology primitives). + +15.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +15.45.2. Continuing TECHMAP pass. +No more expansions possible. + + +15.46. Executing ABC9 pass. + +15.46.1. Executing ABC9_OPS pass (helper functions for ABC9). + +15.46.2. Executing ABC9_OPS pass (helper functions for ABC9). + +15.46.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module top. +Found 0 SCCs. + +15.46.4. Executing ABC9_OPS pass (helper functions for ABC9). + +15.46.5. Executing TECHMAP pass (map to technology primitives). + +15.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +15.46.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +15.46.6. Executing OPT pass (performing simple optimizations). + +15.46.6.1. Executing OPT_EXPR pass (perform const folding). + +15.46.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +15.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +15.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +15.46.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +15.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +15.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +15.46.6.8. Executing OPT_EXPR pass (perform const folding). + +15.46.6.9. Finished fast OPT passes. (There is nothing left to do.) + +15.46.7. Executing TECHMAP pass (map to technology primitives). + +15.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +15.46.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +15.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +15.46.9. Executing ABC9_OPS pass (helper functions for ABC9). + +15.46.10. Executing ABC9_OPS pass (helper functions for ABC9). + +15.46.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +15.46.12. Executing AIGMAP pass (map logic to AIG). +Module top: replaced 298 cells with 1594 new cells, skipped 454 cells. + replaced 3 cell types: + 4 $_MUX_ + 164 $_OR_ + 130 $_XOR_ + not replaced 4 cell types: + 164 $_AND_ + 85 $_NOT_ + 41 $scopeinfo + 164 TRELLIS_FF + +15.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9). + +15.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9). + +15.46.12.3. Executing XAIGER backend. + +Extracted 730 AND gates and 2121 wires from module `top' to a netlist network with 167 inputs and 217 outputs. + +15.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +15.46.12.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 167/ 217 and = 624 lev = 34 (12.67) mem = 0.01 MB box = 0 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 167/ 217 and = 733 lev = 34 (12.57) mem = 0.02 MB ch = 49 box = 0 bb = 0 +ABC: cst = 0 cls = 43 lit = 49 unused = 808 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 733. Ch = 43. Total mem = 0.18 MB. Peak cut mem = 0.08 MB. +ABC: P: Del = 3531.00. Ar = 1669.0. Edge = 1803. Cut = 12025. T = 0.00 sec +ABC: P: Del = 3531.00. Ar = 1716.0. Edge = 1848. Cut = 12051. T = 0.00 sec +ABC: P: Del = 3531.00. Ar = 1097.0. Edge = 1483. Cut = 16365. T = 0.00 sec +ABC: F: Del = 3531.00. Ar = 820.0. Edge = 1267. Cut = 8137. T = 0.00 sec +ABC: A: Del = 3531.00. Ar = 750.0. Edge = 1142. Cut = 8275. T = 0.00 sec +ABC: A: Del = 3531.00. Ar = 732.0. Edge = 1118. Cut = 7846. T = 0.00 sec +ABC: Total time = 0.01 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: Timing manager is given but there is no GIA of boxes. +ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. +ABC: + &ps -l +ABC: /input : i/o = 167/ 217 and = 1337 lev = 34 (12.51) mem = 0.02 MB box = 0 bb = 0 +ABC: Mapping (K=7) : lut = 289 edge = 1118 lev = 7 (3.34) mem = 0.01 MB +ABC: LUT = 289 : 2=93 32.2 % 3=59 20.4 % 4=56 19.4 % 5=10 3.5 % 6=16 5.5 % 7=55 19.0 % Ave = 3.87 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.01 sec +ABC: + time +ABC: elapse: 0.05 seconds, total: 0.05 seconds + +15.46.12.6. Executing AIGER frontend. + +Removed 1928 unused cells and 2278 unused wires. + +15.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 294 +ABC RESULTS: input signals: 14 +ABC RESULTS: output signals: 92 + +Removing temp directory. + +15.46.13. Executing TECHMAP pass (map to technology primitives). + +15.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +15.46.13.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 51 unused cells and 2412 unused wires. + +15.47. Executing TECHMAP pass (map to technology primitives). + +15.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +15.47.2. Continuing TECHMAP pass. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. +Using template $paramod$4f6126006518c39bfac08f438b457e3d24583766$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. +Using template $paramod$87a3f9dd58445c4c87061835e06c5719144e5fa3$lut for cells of type $lut. +Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8$lut for cells of type $lut. +Using template $paramod$11d98a734fddb972e4bcf061987d6c0007a7bbfa$lut for cells of type $lut. +Using template $paramod$e84578f0d0b31a1cf6b5b92fd4d2d62363343068$lut for cells of type $lut. +Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut. +Using template $paramod$b0f853446cd2ecaf153c5e9151da6a7dfc2ccc12$lut for cells of type $lut. +Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5$lut for cells of type $lut. +Using template $paramod$f6a254741739837c46c846c386d311104245dc32$lut for cells of type $lut. +Using template $paramod$daeec2ebb6099778303a5846c403e782b51893a0$lut for cells of type $lut. +Using template $paramod$309d78bd868a71083561540426189b92ecc4d503$lut for cells of type $lut. +Using template $paramod$46d981b5eabc08c1691f743d7a017e4435316de4$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. +Using template $paramod$fedc9dd49dc77948bb3b96048b3e9c4cb551096b$lut for cells of type $lut. +Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011010 for cells of type $lut. +Using template $paramod$cbb2dfe31d344d3326d567c2ed5a4b2a29f63219$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. +Using template $paramod$d2dcae2582364eb8e76bc67aa9dc9d4f47dbb8cb$lut for cells of type $lut. +Using template $paramod$c441dbd41fa7b52ce609b1fb3e8a706905598601$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut. +Using template $paramod$e743b1221f52335455dbba74da7fed1f19a8436e$lut for cells of type $lut. +Using template $paramod$14d0091694152ad6752206b32b402642db76b525$lut for cells of type $lut. +Using template $paramod$330516732c2e8503f8dba5c7129f06e0b2a290ac$lut for cells of type $lut. +Using template $paramod$54a853cac0e65b945d96d7dd0e9cca8bb9f3a21e$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. +Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5$lut for cells of type $lut. +Using template $paramod$5a3828e1c7b846466ebe403becfcf1b450236796$lut for cells of type $lut. +Using template $paramod$301321002cb28483434a813b17302088bf27b78e$lut for cells of type $lut. +Using template $paramod$da41738bd25cb72668eab9ab46ebb830f6ddbc36$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101001 for cells of type $lut. +Using template $paramod$7bcf5f70986487920c848507d659d29b9546545c$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. +Using template $paramod$872def176acf0af46aee1a4df67a9291309e3c01$lut for cells of type $lut. +Using template $paramod$dedb9b90ecc905c9c538f1bb6856026f0a218fc3$lut for cells of type $lut. +Using template $paramod$a50fbd3eb9c4f570e0cbd5722aaaebd24b8d0425$lut for cells of type $lut. +Using template $paramod$049cc17901d0cb8ba29380e71db66a16bae61970$lut for cells of type $lut. +Using template $paramod$f5fa3d8363b434d79f262bd97e5ff17e8b013e00$lut for cells of type $lut. +Using template $paramod$71528c3b736bcda40283e54d8ce275fa0a3f31d1$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. +Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. +Using template $paramod$842d4b2fe22949669eac276c9bebad3774bb02a1$lut for cells of type $lut. +Using template $paramod$368ece0cbe0dd8813956f5c0ea41432c34a980c2$lut for cells of type $lut. +Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. +Using template $paramod$63dfb5d507c3c0842cdb02014ffa50dbe5770b84$lut for cells of type $lut. +Using template $paramod$e09907a521c34a79564e47a8ea074ecd03d539ab$lut for cells of type $lut. +Using template $paramod$6e98fea82e288eb70fa7833e8442d9b57c9d67e7$lut for cells of type $lut. +Using template $paramod$5d7fe76446451765edc3b360a65ded87ffbd0e8a$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. +Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut. +Using template $paramod$0d4b80ebb319c981973dcdd07eaa64bd2b0cb02b$lut for cells of type $lut. +Using template $paramod$0eac84a66cafdae694c197ae6a8350c46d7648b8$lut for cells of type $lut. +Using template $paramod$cb3f712517d81c64d8d5d99dd66f1e5efd49ab9b$lut for cells of type $lut. +Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. +Using template $paramod$79cc145864c59d5b269e01117e91dcd4eab8d7c8$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod$ba3cfc743540fa49da88f4b975f1f5c2bd23f7a1$lut for cells of type $lut. +Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. +Using template $paramod$64716900ddc889cf84105954219190c9eae14055$lut for cells of type $lut. +Using template $paramod$26df0e9406d3c99c42a387b999da9c74acdd4e96$lut for cells of type $lut. +Using template $paramod$3460dbea3cefc4ef9ac987b81b4b66298b1e4e5d$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. +Using template $paramod$210c3ee6c991e0b85178f32b0533af3eb92e961e$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. +Using template $paramod$df7ebd40fffb92f265e82f6d35ddcf309e75bc6b$lut for cells of type $lut. +Using template $paramod$2f17e1be43f3ac07ddcc5afec3b8e6a34320bd15$lut for cells of type $lut. +Using template $paramod$e80f6f2725cc9420cd22a4fc9327e020a107b9cc$lut for cells of type $lut. +Using template $paramod$52acd744af558b1acd7f06b0e1d721506b042b9b$lut for cells of type $lut. +No more expansions possible. + + +15.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in top. + Optimizing lut $abc$299741$lut$aiger$o31.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o31.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o31.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o31.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o31.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o11.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o11.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o11.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o11.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o51.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$299741$lut$aiger$o51.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$299741$lut$aiger299740$1220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o9.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o9.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o9.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o9.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o9.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o8.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o8.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o8.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o8.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o7.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o7.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o7.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o7.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$299741$lut$aiger299740$492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o59.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$299741$lut$aiger$o59.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$299741$lut$aiger$o49.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o49.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$1177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$1177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$1177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$1177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$1203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$1151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$299741$lut$aiger299740$199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$983.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$1134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$1203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o59.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o59.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o7.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o7.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$1163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o49.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o8.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o8.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o9.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o25.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$299741$lut$aiger299740$297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$1220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger$o51.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o51.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o11.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o11.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$1007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$1013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger$o180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o31.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o31.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$299751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger299740$1177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$299741$lut$aiger$o179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$299741$lut$aiger299740$492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$299741$lut$aiger299740$644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$299741$lut$aiger299740$506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) +Removed 0 unused cells and 612 unused wires. + +15.49. Executing AUTONAME pass. +Renamed 2401 objects in module top. + + +15.50. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `top'. Setting top module to top. + +15.50.1. Analyzing design hierarchy.. +Top module: \top + +15.50.2. Analyzing design hierarchy.. +Top module: \top +Removed 0 unused modules. + +15.51. Printing statistics. + +=== top === + + +----------Local Count, excluding submodules. + | + 1442 wires + 47457 wire bits + 1442 public wires + 47457 public wire bits + 6 ports + 37 port bits + 41 cells + 41 $scopeinfo + 1344 submodules + 181 L6MUX21 + 737 LUT4 + 262 PFUMX + 164 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 41 top + + +----------Count including submodules. + | + 1442 wires + 47457 wire bits + 1442 public wires + 47457 public wire bits + 6 ports + 37 port bits + - memories + - memory bits + - processes + 41 cells + 41 $scopeinfo + 1344 submodules + 181 L6MUX21 + 737 LUT4 + 262 PFUMX + 164 TRELLIS_FF + +15.52. Executing CHECK pass (checking for obvious problems). +Checking module top... +Found and reported 0 problems. + +15.53. Executing JSON backend. + +End of script. Logfile hash: a4010fd38d, time: 3.39s, user: 3.47s, system: 0.10s, MEM: 642.16 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 27% 42x opt_expr (0 sec), 16% 12x techmap (0 sec), ... diff --git a/synth/ecp5/top.v b/synth/ecp5/top.v index f6b20d9..06100db 100644 --- a/synth/ecp5/top.v +++ b/synth/ecp5/top.v @@ -1,78 +1,120 @@ -module top ( - input clk, - input rst, - input start, +module top #( + parameter DATA_WIDTH = 8, + parameter N_INPUTS = 256, + parameter N_NEURONS = 4, + parameter PARALLEL = 8, + parameter ACC_WIDTH = 32 +)( + input wire clk, + input wire rst, + input wire start, - output signed [31:0] y_bus, - output busy, - output done + output wire signed [DATA_WIDTH*N_NEURONS-1:0] y_bus, + output wire busy, + output wire done ); - localparam DATA_WIDTH = 8; - localparam N_INPUTS = 256; - localparam N_NEURONS = 4; - localparam PARALLEL = 2; - localparam ACC_WIDTH = 32; + localparam X_BITS = DATA_WIDTH * N_INPUTS; + localparam W_BITS = DATA_WIDTH * N_INPUTS * N_NEURONS; + localparam B_BITS = DATA_WIDTH * N_NEURONS; - reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus; - reg signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0] weights_bus; - reg signed [DATA_WIDTH*N_NEURONS-1:0] bias_bus; + /* + * Deterministic benchmark vectors. + * + * These are INTERNAL signals. + * They are deliberately marked keep so that Yosys does not + * constant-fold the complete neural datapath away. + */ - integer i; + (* keep = "true" *) + wire signed [X_BITS-1:0] x_bus; - initial begin - x_bus = 0; - weights_bus = 0; - bias_bus = 0; + (* keep = "true" *) + wire signed [W_BITS-1:0] weights_bus; - // x[i] = 1 - for (i = 0; i < N_INPUTS; i = i + 1) - x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1; + (* keep = "true" *) + wire signed [B_BITS-1:0] bias_bus; - // Neurone 0: primi 32 pesi = +1 - for (i = 0; i < 32; i = i + 1) - weights_bus[ - 0*N_INPUTS*DATA_WIDTH + - i*DATA_WIDTH +: - DATA_WIDTH - ] = 8'sd1; - // Neurone 1: tutti i pesi = 0, bias = 10 - bias_bus[1*DATA_WIDTH +: DATA_WIDTH] = 8'sd10; + /* + * Generate deterministic non-zero INT8 data. + * + * Each byte is a different constant. The buses remain internal, + * so nextpnr sees only the 37 real top-level I/Os. + */ - // Neurone 2: tutti i pesi = -1 - for (i = 0; i < N_INPUTS; i = i + 1) - weights_bus[ - 2*N_INPUTS*DATA_WIDTH + - i*DATA_WIDTH +: - DATA_WIDTH - ] = -8'sd1; + genvar i; + genvar n; - // Neurone 3: primi 32 pesi = +4 - for (i = 0; i < 32; i = i + 1) - weights_bus[ - 3*N_INPUTS*DATA_WIDTH + - i*DATA_WIDTH +: - DATA_WIDTH - ] = 8'sd4; - end + generate + for (i = 0; i < N_INPUTS; i = i + 1) begin : GEN_X + + localparam integer XV = + ((i * 17 + 3) % 31) - 15; + + assign x_bus[ + i*DATA_WIDTH +: DATA_WIDTH + ] = XV; + + end + + + for (n = 0; n < N_NEURONS; n = n + 1) begin : GEN_WN + + for (i = 0; i < N_INPUTS; i = i + 1) begin : GEN_WI + + localparam integer WV = + ((n * 29 + i * 13 + 5) % 31) - 15; + + assign weights_bus[ + (n*N_INPUTS+i)*DATA_WIDTH + +: DATA_WIDTH + ] = WV; + + end + + end + + + for (n = 0; n < N_NEURONS; n = n + 1) begin : GEN_B + + localparam integer BV = + ((n * 7 + 1) % 9) - 4; + + assign bias_bus[ + n*DATA_WIDTH + +: DATA_WIDTH + ] = BV; + + end + + endgenerate + + + /* + * Real neural-network layer. + */ + + (* keep_hierarchy = "true" *) layer #( .DATA_WIDTH(DATA_WIDTH), .N_INPUTS(N_INPUTS), .N_NEURONS(N_NEURONS), .PARALLEL(PARALLEL), .ACC_WIDTH(ACC_WIDTH) - ) u_layer ( + ) dut ( .clk(clk), .rst(rst), .start(start), + .x_bus(x_bus), .weights_bus(weights_bus), .bias_bus(bias_bus), + .y_bus(y_bus), .busy(busy), .done(done) ); -endmodule +endmodule \ No newline at end of file diff --git a/tools/fpga_benchmark.py b/tools/fpga_benchmark.py new file mode 100755 index 0000000..30b3375 --- /dev/null +++ b/tools/fpga_benchmark.py @@ -0,0 +1,1101 @@ +#!/usr/bin/env python3 + +import csv +import json +import re +import subprocess +import sys +from pathlib import Path + + +# ============================================================ +# PATHS +# ============================================================ + +ROOT = Path(__file__).resolve().parents[1] + +RTL_DIR = ROOT / "rtl" +SYNTH_ROOT = ROOT / "synth" / "ecp5" +RESULT_ROOT = ROOT / "benchmark_results" + +YOSYS = "/opt/homebrew/bin/yosys" +NEXTPNR = "/tmp/nextpnr/build/nextpnr-ecp5" + + +# ============================================================ +# FPGA +# ============================================================ + +DEVICE = "LFE5U-45F-8BG381" +NEXT_PNR_DEVICE = "45k" +PACKAGE = "CABGA381" +SPEED_GRADE = "8" + +TARGET_FREQ_MHZ = 80.0 + + +# ============================================================ +# NEURAL NETWORK +# ============================================================ + +DATA_WIDTH = 8 +ACC_WIDTH = 32 + +N_INPUTS = 256 +N_NEURONS = 4 + +PARALLELS = [8, 4, 2] + + +# ============================================================ +# RTL +# +# Same source list as the validated ECP5 synthesis flow. +# ============================================================ + +RTL_FILES = [ + RTL_DIR / "mac_unit.v", + RTL_DIR / "mac8.v", + RTL_DIR / "neuron_parallel.v", + RTL_DIR / "layer.v", +] + + +# ============================================================ +# COMMAND +# ============================================================ + +def run_command(cmd, cwd=None, log_file=None): + print() + print("-" * 80) + print("COMMAND:") + print(" ".join(str(x) for x in cmd)) + print("-" * 80) + + result = subprocess.run( + [str(x) for x in cmd], + cwd=str(cwd) if cwd else None, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + text=True, + ) + + output = result.stdout + + if log_file is not None: + log_file.parent.mkdir(parents=True, exist_ok=True) + log_file.write_text(output) + + print(output) + + if result.returncode != 0: + raise RuntimeError( + f"Command failed with exit code {result.returncode}" + ) + + return output + + +# ============================================================ +# CHECK TOOLS +# ============================================================ + +def check_tools(): + if not Path(YOSYS).exists(): + raise RuntimeError(f"Yosys not found: {YOSYS}") + + if not Path(NEXTPNR).exists(): + raise RuntimeError(f"nextpnr-ecp5 not found: {NEXTPNR}") + + for path in RTL_FILES: + if not path.exists(): + raise RuntimeError(f"RTL file not found: {path}") + + +# ============================================================ +# GENERATE TOP +# ============================================================ + +def generate_top(parallel, top_v): + """ + Benchmark wrapper. + + IMPORTANT: + - Do NOT expose x_bus / weights_bus / bias_bus as top-level I/O. + - The ECP5 has only 245 physical I/O. + - The neural-network vectors are generated internally. + - clk/reset/start remain real inputs so the sequential datapath + cannot be reduced to constants. + - y_bus is a real output so the result remains observable. + """ + + x_bits = DATA_WIDTH * N_INPUTS + w_bits = DATA_WIDTH * N_INPUTS * N_NEURONS + b_bits = DATA_WIDTH * N_NEURONS + y_bits = DATA_WIDTH * N_NEURONS + + text = f""" +module top #( + parameter DATA_WIDTH = {DATA_WIDTH}, + parameter N_INPUTS = {N_INPUTS}, + parameter N_NEURONS = {N_NEURONS}, + parameter PARALLEL = {parallel}, + parameter ACC_WIDTH = {ACC_WIDTH} +)( + input wire clk, + input wire rst, + input wire start, + + output wire signed [{y_bits - 1}:0] y_bus, + output wire busy, + output wire done +); + + localparam X_BITS = DATA_WIDTH * N_INPUTS; + localparam W_BITS = DATA_WIDTH * N_INPUTS * N_NEURONS; + localparam B_BITS = DATA_WIDTH * N_NEURONS; + + /* + * Internal neural-network data. + * + * These are deliberately registers, not parameters/constants. + * This prevents the complete datapath from disappearing during + * synthesis. + */ + + reg signed [X_BITS-1:0] x_bus; + reg signed [W_BITS-1:0] weights_bus; + reg signed [B_BITS-1:0] bias_bus; + + integer i; + integer n; + + /* + * Deterministic initialization. + * + * The actual datapath remains present because the vectors are + * stored in registers and loaded through the clocked process. + */ + + always @(posedge clk) begin + if (rst) begin + + x_bus <= '0; + weights_bus <= '0; + bias_bus <= '0; + + end + else if (start) begin + + /* + * INT8 input vector. + * + * Pattern: + * -16 ... +15 + */ + + for (i = 0; i < N_INPUTS; i = i + 1) begin + x_bus[i*DATA_WIDTH +: DATA_WIDTH] + <= ((i * 17 + 3) % 31) - 15; + end + + /* + * INT8 weights. + */ + + for (n = 0; n < N_NEURONS; n = n + 1) begin + + for (i = 0; i < N_INPUTS; i = i + 1) begin + + weights_bus[ + (n*N_INPUTS+i)*DATA_WIDTH + +: DATA_WIDTH + ] + <= ((n * 29 + i * 13 + 5) % 31) - 15; + + end + + end + + /* + * INT8 biases. + */ + + for (n = 0; n < N_NEURONS; n = n + 1) begin + + bias_bus[ + n*DATA_WIDTH + +: DATA_WIDTH + ] + <= ((n * 7 + 1) % 9) - 4; + + end + + end + end + + + /* + * Real neural-network layer. + */ + + layer #( + .DATA_WIDTH(DATA_WIDTH), + .N_INPUTS(N_INPUTS), + .N_NEURONS(N_NEURONS), + .PARALLEL(PARALLEL), + .ACC_WIDTH(ACC_WIDTH) + ) dut ( + .clk(clk), + .rst(rst), + .start(start), + + .x_bus(x_bus), + .weights_bus(weights_bus), + .bias_bus(bias_bus), + + .y_bus(y_bus), + .busy(busy), + .done(done) + ); + +endmodule +""" + + top_v.parent.mkdir(parents=True, exist_ok=True) + top_v.write_text(text.strip() + "\n") + + +# ============================================================ +# SYNTHESIS SCRIPT +# ============================================================ + +def generate_synth_script(top_v, synth_ys, top_json): + + rtl_paths = [ + str(path) + for path in RTL_FILES + ] + + lines = [] + + lines.append("read_verilog -sv \\") + + for index, rtl in enumerate(rtl_paths): + lines.append(f"{rtl} \\") + + lines.append(str(top_v)) + lines.append("") + lines.append("hierarchy -top top") + lines.append("") + lines.append("proc") + lines.append("flatten") + lines.append("opt") + lines.append("memory") + lines.append("opt") + lines.append("techmap") + lines.append("opt") + lines.append("abc -g simple") + lines.append("clean") + lines.append("") + lines.append( + f'synth_ecp5 -top top -json {top_json}' + ) + + synth_ys.parent.mkdir( + parents=True, + exist_ok=True + ) + + synth_ys.write_text( + "\n".join(lines) + "\n" + ) + + +# ============================================================ +# LPF +# ============================================================ + +def generate_lpf(lpf): + """ + No physical pin constraints. + + nextpnr will automatically place the small number of + top-level I/Os. + """ + + lpf.parent.mkdir( + parents=True, + exist_ok=True + ) + + lpf.write_text("") + + +# ============================================================ +# NEXTPNR +# ============================================================ + +def run_nextpnr( + top_json, + lpf, + config, + log +): + + cmd = [ + NEXTPNR, + f"--{NEXT_PNR_DEVICE}", + "--package", + PACKAGE, + "--speed", + SPEED_GRADE, + "--json", + str(top_json), + "--lpf", + str(lpf), + "--lpf-allow-unconstrained", + "--freq", + str(TARGET_FREQ_MHZ), + "--textcfg", + str(config), + ] + + return run_command( + cmd, + cwd=ROOT, + log_file=log + ) + + +# ============================================================ +# PARSER +# ============================================================ + +def parse_nextpnr_report(text): + + # -------------------------------------------------------- + # LUT4 + # -------------------------------------------------------- + + lut_matches = re.findall( + r"Total LUT4s:\s*([0-9]+)\s*/", + text + ) + + lut4 = ( + int(lut_matches[-1]) + if lut_matches + else None + ) + + # -------------------------------------------------------- + # DFF + # -------------------------------------------------------- + + ff_matches = re.findall( + r"Total DFFs:\s*([0-9]+)\s*/", + text + ) + + dff = ( + int(ff_matches[-1]) + if ff_matches + else None + ) + + # -------------------------------------------------------- + # DSP + # -------------------------------------------------------- + + dsp_matches = re.findall( + r"MULT18X18D:\s*([0-9]+)\s*/", + text + ) + + dsp = ( + int(dsp_matches[-1]) + if dsp_matches + else None + ) + + # -------------------------------------------------------- + # RAM + # -------------------------------------------------------- + + ram_matches = re.findall( + r"DP16KD:\s*([0-9]+)\s*/", + text + ) + + dp16kd = ( + int(ram_matches[-1]) + if ram_matches + else None + ) + + # -------------------------------------------------------- + # IO + # -------------------------------------------------------- + + io_matches = re.findall( + r"TRELLIS_IO:\s*([0-9]+)\s*/", + text + ) + + io = ( + int(io_matches[-1]) + if io_matches + else None + ) + + # -------------------------------------------------------- + # TRELLIS FF + # -------------------------------------------------------- + + trellis_ff_matches = re.findall( + r"TRELLIS_FF:\s*([0-9]+)\s*/", + text + ) + + trellis_ff = ( + int(trellis_ff_matches[-1]) + if trellis_ff_matches + else None + ) + + # -------------------------------------------------------- + # TRELLIS COMB + # -------------------------------------------------------- + + trellis_comb_matches = re.findall( + r"TRELLIS_COMB:\s*([0-9]+)\s*/", + text + ) + + trellis_comb = ( + int(trellis_comb_matches[-1]) + if trellis_comb_matches + else None + ) + + # -------------------------------------------------------- + # FMAX + # + # nextpnr can print more than one Fmax. + # The LAST one is the final post-route result. + # -------------------------------------------------------- + + freq_matches = re.findall( + r"Max frequency for clock .*?:\s*" + r"([0-9]+(?:\.[0-9]+)?)\s*MHz", + text + ) + + fmax = ( + float(freq_matches[-1]) + if freq_matches + else None + ) + + # -------------------------------------------------------- + # LOGIC / ROUTING + # + # Again use the final occurrence. + # -------------------------------------------------------- + + timing_matches = re.findall( + r"([0-9]+(?:\.[0-9]+)?)\s*ns\s+logic,\s*" + r"([0-9]+(?:\.[0-9]+)?)\s*ns\s+routing", + text + ) + + if timing_matches: + + logic_ns = float( + timing_matches[-1][0] + ) + + routing_ns = float( + timing_matches[-1][1] + ) + + else: + + logic_ns = None + routing_ns = None + + # -------------------------------------------------------- + # TCRIT + # -------------------------------------------------------- + + if ( + logic_ns is not None + and routing_ns is not None + ): + + tcrit_ns = ( + logic_ns + + routing_ns + ) + + elif fmax is not None and fmax > 0: + + tcrit_ns = 1000.0 / fmax + + else: + + tcrit_ns = None + + return { + "lut4": lut4, + "ff": dff, + "dsp": dsp, + "dp16kd": dp16kd, + "io": io, + "trellis_ff": trellis_ff, + "trellis_comb": trellis_comb, + + "fmax_mhz": fmax, + + "logic_ns": logic_ns, + "routing_ns": routing_ns, + "tcrit_ns": tcrit_ns, + } + + +# ============================================================ +# BENCHMARK ONE PARALLEL +# ============================================================ + +def benchmark_parallel(parallel): + + print() + print("=" * 80) + print(f"BENCHMARK P = {parallel}") + print("=" * 80) + + out_dir = ( + SYNTH_ROOT / + f"p{parallel}" + ) + + out_dir.mkdir( + parents=True, + exist_ok=True + ) + + top_v = out_dir / "top.v" + synth_ys = out_dir / "synth.ys" + top_json = out_dir / "top.json" + lpf = out_dir / "top.lpf" + config = out_dir / "top.config" + + yosys_log = out_dir / "yosys.log" + nextpnr_log = out_dir / "nextpnr.log" + + # -------------------------------------------------------- + # TOP + # -------------------------------------------------------- + + generate_top( + parallel, + top_v + ) + + # -------------------------------------------------------- + # SYNTH SCRIPT + # -------------------------------------------------------- + + generate_synth_script( + top_v, + synth_ys, + top_json + ) + + # -------------------------------------------------------- + # LPF + # -------------------------------------------------------- + + generate_lpf(lpf) + + # -------------------------------------------------------- + # YOSYS + # -------------------------------------------------------- + + run_command( + [ + YOSYS, + "-s", + str(synth_ys) + ], + cwd=ROOT, + log_file=yosys_log + ) + + if not top_json.exists(): + + raise RuntimeError( + f"Yosys did not generate {top_json}" + ) + + # -------------------------------------------------------- + # NEXTPNR + # -------------------------------------------------------- + + output = run_nextpnr( + top_json, + lpf, + config, + nextpnr_log + ) + + # -------------------------------------------------------- + # PARSE + # -------------------------------------------------------- + + metrics = parse_nextpnr_report( + output + ) + + # -------------------------------------------------------- + # VALIDATION + # -------------------------------------------------------- + + required = [ + "fmax_mhz", + "lut4", + "ff", + "dsp", + ] + + for key in required: + + if metrics[key] is None: + + raise RuntimeError( + f"Unable to parse {key} " + f"for P={parallel}" + ) + + # -------------------------------------------------------- + # MAC COUNT + # -------------------------------------------------------- + + mac_total = ( + N_NEURONS * + parallel + ) + + # -------------------------------------------------------- + # THROUGHPUT + # -------------------------------------------------------- + + mac_per_sec = ( + mac_total * + metrics["fmax_mhz"] * + 1_000_000.0 + ) + + mac_per_sec_m = ( + mac_per_sec / + 1_000_000.0 + ) + + mac_per_sec_g = ( + mac_per_sec / + 1_000_000_000.0 + ) + + # -------------------------------------------------------- + # TARGET + # -------------------------------------------------------- + + pass_80 = ( + metrics["fmax_mhz"] >= + TARGET_FREQ_MHZ + ) + + # -------------------------------------------------------- + # RESULT + # -------------------------------------------------------- + + result = { + + "fpga": DEVICE, + "package": PACKAGE, + "speed_grade": SPEED_GRADE, + + "n_inputs": N_INPUTS, + "n_neurons": N_NEURONS, + + "data_width": DATA_WIDTH, + "acc_width": ACC_WIDTH, + + "parallel": parallel, + + "mac": mac_total, + + "fmax_mhz": + metrics["fmax_mhz"], + + "lut4": + metrics["lut4"], + + "ff": + metrics["ff"], + + "dsp": + metrics["dsp"], + + "dp16kd": + metrics["dp16kd"], + + "io": + metrics["io"], + + "trellis_ff": + metrics["trellis_ff"], + + "trellis_comb": + metrics["trellis_comb"], + + "logic_ns": + metrics["logic_ns"], + + "routing_ns": + metrics["routing_ns"], + + "tcrit_ns": + metrics["tcrit_ns"], + + "mac_per_sec_m": + mac_per_sec_m, + + "mac_per_sec_g": + mac_per_sec_g, + + "pass_80mhz": + pass_80, + } + + # -------------------------------------------------------- + # PRINT + # -------------------------------------------------------- + + print() + print("RESULT") + print("-" * 50) + + print( + f"PARALLEL : {parallel}" + ) + + print( + f"MAC : {mac_total}" + ) + + print( + f"Fmax : " + f"{metrics['fmax_mhz']:.2f} MHz" + ) + + print( + f"LUT4 : " + f"{metrics['lut4']}" + ) + + print( + f"DFF : " + f"{metrics['ff']}" + ) + + print( + f"DSP : " + f"{metrics['dsp']}" + ) + + if metrics["logic_ns"] is not None: + + print( + f"Logic : " + f"{metrics['logic_ns']:.2f} ns" + ) + + if metrics["routing_ns"] is not None: + + print( + f"Routing : " + f"{metrics['routing_ns']:.2f} ns" + ) + + if metrics["tcrit_ns"] is not None: + + print( + f"Tcrit : " + f"{metrics['tcrit_ns']:.2f} ns" + ) + + print( + f"Throughput : " + f"{mac_per_sec_g:.3f} GMAC/s" + ) + + print( + f"80 MHz : " + f"{'PASS' if pass_80 else 'FAIL'}" + ) + + return result + + +# ============================================================ +# WRITE RESULTS +# ============================================================ + +def write_results(results): + + RESULT_ROOT.mkdir( + parents=True, + exist_ok=True + ) + + json_path = ( + RESULT_ROOT / + "fpga_benchmark.json" + ) + + csv_path = ( + RESULT_ROOT / + "fpga_benchmark.csv" + ) + + data = { + + "benchmark": { + + "fpga": DEVICE, + "package": PACKAGE, + "speed_grade": SPEED_GRADE, + + "n_inputs": N_INPUTS, + "n_neurons": N_NEURONS, + + "data_width": DATA_WIDTH, + "acc_width": ACC_WIDTH, + + "target_freq_mhz": + TARGET_FREQ_MHZ, + + "parallel_values": + PARALLELS, + }, + + "results": results, + } + + json_path.write_text( + json.dumps( + data, + indent=2 + ) + ) + + fieldnames = list( + results[0].keys() + ) + + with csv_path.open( + "w", + newline="" + ) as f: + + writer = csv.DictWriter( + f, + fieldnames=fieldnames + ) + + writer.writeheader() + writer.writerows(results) + + return ( + json_path, + csv_path + ) + + +# ============================================================ +# SUMMARY +# ============================================================ + +def print_summary(results): + + print() + print() + print("=" * 105) + print("FPGA-NEURAL BENCHMARK RESULTS") + print("=" * 105) + + print( + f"{'FPGA':24}" + f"{'P':>4}" + f"{'MAC':>7}" + f"{'Fmax':>10}" + f"{'LUT':>8}" + f"{'FF':>8}" + f"{'DSP':>8}" + f"{'MAC/s':>14}" + f"{'80MHz':>9}" + ) + + print("-" * 105) + + for r in results: + + print( + f"{r['fpga']:24}" + f"{r['parallel']:>4}" + f"{r['mac']:>7}" + f"{r['fmax_mhz']:>9.2f}" + f"{r['lut4']:>8}" + f"{r['ff']:>8}" + f"{r['dsp']:>8}" + f"{r['mac_per_sec_g']:>12.3f}G" + f"{'PASS' if r['pass_80mhz'] else 'FAIL':>9}" + ) + + print("-" * 105) + + best_fmax = max( + results, + key=lambda r: + r["fmax_mhz"] + ) + + best_throughput = max( + results, + key=lambda r: + r["mac_per_sec_g"] + ) + + print() + + print( + "BEST FMAX: " + f"P={best_fmax['parallel']} " + f"-> " + f"{best_fmax['fmax_mhz']:.2f} MHz" + ) + + print( + "BEST THROUGHPUT: " + f"P={best_throughput['parallel']} " + f"-> " + f"{best_throughput['mac_per_sec_g']:.3f} GMAC/s" + ) + + print() + + +# ============================================================ +# MAIN +# ============================================================ + +def main(): + + print() + print("=" * 80) + print("FPGA-NEURAL ECP5 PARAMETRIC BENCHMARK") + print("=" * 80) + + print( + f"FPGA : {DEVICE}" + ) + + print( + f"Package : {PACKAGE}" + ) + + print( + f"Speed : -{SPEED_GRADE}" + ) + + print( + f"N_INPUTS : {N_INPUTS}" + ) + + print( + f"N_NEURONS : {N_NEURONS}" + ) + + print( + f"DATA_WIDTH : {DATA_WIDTH}" + ) + + print( + f"ACC_WIDTH : {ACC_WIDTH}" + ) + + print( + f"PARALLEL : {PARALLELS}" + ) + + print( + f"TARGET : " + f"{TARGET_FREQ_MHZ:.0f} MHz" + ) + + check_tools() + + results = [] + + for parallel in PARALLELS: + + result = benchmark_parallel( + parallel + ) + + results.append(result) + + json_path, csv_path = ( + write_results(results) + ) + + print_summary(results) + + print( + f"JSON: {json_path}" + ) + + print( + f"CSV : {csv_path}" + ) + + +# ============================================================ +# ENTRY POINT +# ============================================================ + +if __name__ == "__main__": + + try: + + main() + + except KeyboardInterrupt: + + print( + "\nInterrupted." + ) + + sys.exit(130) + + except Exception as e: + + print() + print("=" * 80) + print("ERROR") + print("=" * 80) + print(str(e)) + + sys.exit(1) \ No newline at end of file