feat: real result-writeback engine, removes the last hard N-scaling pin blocker (EXP-0088)

Adds result_writeback.v, one instance per packed_slot.v, writing each
completed job's result directly into DDR3 at the job's own
result_addr_a/b instead of driving literal top-level pins -- the same
architectural shape as the weight-fetch path, in reverse. job_done now
means "durably in DDR3", not "captured in a register only a pin could
see". n2_system_ddr3_top.v's own s0_result_data_a/b, s1_result_data_a/b
top-level package pins are removed (and the now-dangling XDC constraint
for them), closing the real, hard scaling blocker docs/ARCHITECTURE_
ANALYSIS.md flagged since EXP-0074/0079 (8 bits x 2 lanes x N cores ->
256 pins at N=16).

Addressing reuses the exact same JOB_ADDR_WIDTH->ctrl-bus-word
truncation x_base_a/w_base already use (verified against act_tile_
fetch.v's/layer_prefetch_ctrl.v's own real code, not guessed). The host
reads results back via the already-existing READ_MEM (0x02) SPI opcode
-- no new protocol. A real EXP-0066-class bug (issuing ctrl_req before
mem_grant) was caught and fixed before ever compiling, by re-deriving
the design against act_tile_fetch.v's own proven S_MEMWAIT/S_GAP
sequencing.

Verified two ways: tb_packed_slot.v extended with a real DDR3
read-after-write check (9/9 PASS, confirms the write actually landed,
not just that job_done pulsed); tb_n2_system_ddr3.v re-run via real
xsim to confirm correct behavior under real 2-slot shared-bus
arbitration (8/8 PASS, 0 errors, consistent timing with EXP-0087's own
baseline for this workload).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

hardware/v3/constraints/n2_system_ddr3_top.xdc

@@ -52,17 +52,20 @@ set_property IOSTANDARD LVCMOS33 [get_ports flash_cs_n]
 set_property PROHIBIT true [get_sites -of_objects [get_package_pins {L16 R16 V15}]]
 
 # ---- EXP-0084: remaining top-level ports with no fixed board LOC yet
-# (result-data debug pins, status signals) default to LVCMOS18 with no
-# explicit IOSTANDARD set -- real place_design found this real,
-# concrete: banks 14/15/34/35 are ALL already committed to other real
-# voltages (2.5V/3.3V/1.5V/1.5V), leaving only bank 16's spare pins as
-# LVCMOS18-compatible, and there aren't enough of them (40 ports vs 10
-# pins). Assign these explicitly to LVCMOS33 so they place in bank
-# 15's own real spare capacity (46 free pins) instead -- a real,
+# (status signals) default to LVCMOS18 with no explicit IOSTANDARD set
+# -- real place_design found this real, concrete: banks 14/15/34/35 are
+# ALL already committed to other real voltages (2.5V/3.3V/1.5V/1.5V),
+# leaving only bank 16's spare pins as LVCMOS18-compatible, and there
+# aren't enough of them. Assign these explicitly to LVCMOS33 so they
+# place in bank 15's own real spare capacity instead -- a real,
 # necessary fix, not a workaround; a permanent board LOC for each
 # should still be assigned once the rest of the board layout is
 # decided (S7 of docs/PHYSICAL_REALIZATION.md).
-set_property IOSTANDARD LVCMOS33 [get_ports {s0_result_data_a[*] s0_result_data_b[*] s1_result_data_a[*] s1_result_data_b[*]}]
+# EXP-0088: the s0_result_data_a/b, s1_result_data_a/b ports this
+# constraint used to also cover no longer exist as top-level ports --
+# each slot now writes its own result directly into DDR3 via its own
+# internal result_writeback.v (see packed_slot.v's own header) instead
+# of exposing literal, N-scaled result pins.
 set_property IOSTANDARD LVCMOS33 [get_ports {job_out_slot[*] job_out_done init_calib_complete ui_clk_o}]
 
 # ---- neural-processor management SPI (-> spi_host_bridge_v3.v):