feat: real result-writeback engine, removes the last hard N-scaling pin blocker (EXP-0088)

Adds result_writeback.v, one instance per packed_slot.v, writing each
completed job's result directly into DDR3 at the job's own
result_addr_a/b instead of driving literal top-level pins -- the same
architectural shape as the weight-fetch path, in reverse. job_done now
means "durably in DDR3", not "captured in a register only a pin could
see". n2_system_ddr3_top.v's own s0_result_data_a/b, s1_result_data_a/b
top-level package pins are removed (and the now-dangling XDC constraint
for them), closing the real, hard scaling blocker docs/ARCHITECTURE_
ANALYSIS.md flagged since EXP-0074/0079 (8 bits x 2 lanes x N cores ->
256 pins at N=16).

Addressing reuses the exact same JOB_ADDR_WIDTH->ctrl-bus-word
truncation x_base_a/w_base already use (verified against act_tile_
fetch.v's/layer_prefetch_ctrl.v's own real code, not guessed). The host
reads results back via the already-existing READ_MEM (0x02) SPI opcode
-- no new protocol. A real EXP-0066-class bug (issuing ctrl_req before
mem_grant) was caught and fixed before ever compiling, by re-deriving
the design against act_tile_fetch.v's own proven S_MEMWAIT/S_GAP
sequencing.

Verified two ways: tb_packed_slot.v extended with a real DDR3
read-after-write check (9/9 PASS, confirms the write actually landed,
not just that job_done pulsed); tb_n2_system_ddr3.v re-run via real
xsim to confirm correct behavior under real 2-slot shared-bus
arbitration (8/8 PASS, 0 errors, consistent timing with EXP-0087's own
baseline for this workload).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

docs/PHYSICAL_REALIZATION.md

@@ -363,10 +363,11 @@ when it actually fires, instead of polling every loop iteration.
 ## 7. Known-open items (honestly disclosed, not hidden)
 
 - Scaling past N=2 compute cores (silicon budget allows up to ~30 per the
-  DSP48E1 count) is not yet built or timing-verified. A result-writeback
-  engine (currently `result_data_a/b` are literal top-level pins, fine at
-  N=2 but a real pin-budget blocker beyond that) must land first — see
-  `docs/ARCHITECTURE_ANALYSIS.md` §5.3.
+  DSP48E1 count) is not yet built or timing-verified. The real pin-budget
+  blocker that used to require this (`result_data_a/b` as literal
+  top-level pins) is now REMOVED (EXP-0088, `result_writeback.v` — see
+  `docs/ARCHITECTURE_ANALYSIS.md` §4.6/§5.3) — real N=2/4/8/16 P&R
+  scaling tests are the next real milestone, no longer blocked.
 - `sys_rst` has only a *tentative* real pin (G13, bank 15, EXP-0084 —
   chosen just to unblock real P&R, not a final board decision) — assign
   its real, permanent location once the rest of the board layout (reset
@@ -388,7 +389,8 @@ when it actually fires, instead of polling every loop iteration.
   `tb_spi_host_bridge_v3.v`), AND real P&R-verified at the closed EXP-0086
   signoff (D14/LVCMOS33, confirmed via a direct query on the routed
   checkpoint) — see §6.
-- Scaling past N=2 real core count and the result-writeback engine (both
-  listed above) remain the real next milestones now that the 32-bit
-  channel's own timing is closed — see
-  `hardware/v2/logs/experiments.log` EXP-0086's `next_action`.
+- `result_writeback.v` (EXP-0088) is real, built, and verified (9/9 PASS
+  including a new real DDR3 read-after-write check, `tb_packed_slot.v`).
+  Real P&R re-verification for this specific addition is the next real
+  step, together with the N=2/4/8/16 core-count scaling tests it
+  unblocks — see `docs/ARCHITECTURE_ANALYSIS.md` §5.3/§5.5.