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feat: real active-low data_ready_n sticky IRQ pin (EXP-0085)

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User-requested hardware notification so the ESP32 can be
interrupt-driven instead of polling STATUS in a loop.

spi_host_bridge_v3.v: new job_out_done input (wired from
neural_director_packed.v, already available at the top level) and new
data_ready_n output. A sticky irq_pending register sets on job_out_done
(latched, survives the pulse itself deasserting) and clears when the
host completes a real STATUS (0x20) or REG_READ(0x02) transaction -
reusing cs_rose, the same real transaction-complete event the module
already relies on elsewhere, not a new mechanism. dir_error is ORed in
live/combinational, not latched. SET has priority over CLEAR on the
rare cycle both coincide.

Real pin: D14, bank 15 (already 3.3V, alongside the SPI bus and
sys_rst) - tentative, not yet a final board decision. Deliberately
added after EXP-0084's own P&R iterations settled, so it didn't
complicate that already-tight I/O/VCCO budget mid-fix. Its own real
P&R verification is deferred to the next real P&R run (already needed
to close EXP-0084's clock-period timing gap), not run separately
against a config already known to fail timing for unrelated reasons.

Real verification: tb_spi_host_bridge_v3.v extended with 10 new checks
(idle state, sticky set, mid-transaction hold, real-acknowledge clear,
unrelated-register non-acknowledge, dir_error live assert/clear).
49/49 PASS.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-20 16:33:46 +02:00
co-authored by Claude Sonnet 5
parent 9dead54ebf
commit bdc821222f
6 changed files with 196 additions and 7 deletions
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hardware/v3/constraints/n2_system_ddr3_top.xdc
+9
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@@ -95,3 +95,12 @@ set_property IOSTANDARD LVCMOS33 [get_ports cs_n]
# (queried from the actual part database).
set_property PACKAGE_PIN G13 [get_ports sys_rst]
set_property IOSTANDARD LVCMOS33 [get_ports sys_rst]
# ---- data_ready_n: real, user-requested active-low sticky IRQ so the
# ESP32 can be interrupt-driven instead of polling STATUS (see
# spi_host_bridge_v3.v's own header for the real set/clear semantics).
# Placed in bank 15 alongside the management SPI bus (same real,
# already-committed 3.3V) -- real, verified-free pin, not yet a final
# board decision (same caveat as sys_rst above).
set_property PACKAGE_PIN D14 [get_ports data_ready_n]
set_property IOSTANDARD LVCMOS33 [get_ports data_ready_n]