feat: real active-low data_ready_n sticky IRQ pin (EXP-0085)

User-requested hardware notification so the ESP32 can be
interrupt-driven instead of polling STATUS in a loop.

spi_host_bridge_v3.v: new job_out_done input (wired from
neural_director_packed.v, already available at the top level) and new
data_ready_n output. A sticky irq_pending register sets on job_out_done
(latched, survives the pulse itself deasserting) and clears when the
host completes a real STATUS (0x20) or REG_READ(0x02) transaction -
reusing cs_rose, the same real transaction-complete event the module
already relies on elsewhere, not a new mechanism. dir_error is ORed in
live/combinational, not latched. SET has priority over CLEAR on the
rare cycle both coincide.

Real pin: D14, bank 15 (already 3.3V, alongside the SPI bus and
sys_rst) - tentative, not yet a final board decision. Deliberately
added after EXP-0084's own P&R iterations settled, so it didn't
complicate that already-tight I/O/VCCO budget mid-fix. Its own real
P&R verification is deferred to the next real P&R run (already needed
to close EXP-0084's clock-period timing gap), not run separately
against a config already known to fail timing for unrelated reasons.

Real verification: tb_spi_host_bridge_v3.v extended with 10 new checks
(idle state, sticky set, mid-transaction hold, real-acknowledge clear,
unrelated-register non-acknowledge, dir_error live assert/clear).
49/49 PASS.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

hardware/v2/logs/experiments.log

@@ -5559,3 +5559,61 @@ neural_processor_packed.v's own packed-MAC accumulation tree (the
 real bottleneck identified above, unchanged since EXP-0059) would need
 real re-pipelining -- a genuinely separate, disclosed, not-yet-
 attempted optimization.
+
+EXP-0085 -- real active-low data_ready_n IRQ pin, user-requested
+(2026-09-20, same autonomous continuation: "magari attivo basso" after
+"mi aggiungi anche un pin data_ready quando ha finito la elaborazione
+o semplicemente FPGA ha qualcosa da dire a processore centrale")
+
+CONTEXT: the ESP32 host currently has no way to know a job (or job
+pair) completed, or that a real director error occurred, without
+polling the STATUS register (REG_READ 0x02) in a loop. User asked for
+a real hardware notification pin instead, explicitly active-low.
+
+DESIGN: spi_host_bridge_v3.v gained a new input (job_out_done, wired
+from neural_director_packed.v's own existing output, already available
+at n2_system_ddr3_top.v) and a new output (data_ready_n). A single
+`irq_pending` register is SET on job_out_done (a real job/pair
+completion, latched -- stays set even after job_out_done itself drops
+back to 0 the next cycle) and CLEARED when the host actually completes
+a STATUS-carrying transaction (STATUS opcode 0x20, or REG_READ of
+register 0x02) -- reusing `cs_rose`, the SAME real "response actually
+delivered" event this module's own FSM already relies on elsewhere, not
+a new mechanism. SET has priority over CLEAR on the rare cycle both
+coincide, so a real completion is never silently dropped by a
+coincidental acknowledge. dir_error is ORed in combinationally (not
+latched -- neural_director_packed.v already owns that error state's own
+lifetime), so data_ready_n also tracks it directly, live.
+
+REAL, DELIBERATE SEQUENCING: added AFTER EXP-0084's real P&R attempts
+finished (even though that P&R's own timing doesn't close yet, for
+reasons unrelated to this pin) rather than interleaved with them --
+EXP-0084 spent several real iterations fighting a very tight I/O/VCCO
+budget on this package; adding another top-level port mid-fight would
+have made root-causing harder. Real pin assigned now: D14 (bank 15,
+already-committed 3.3V, alongside the management SPI bus and sys_rst)
+-- a real, verified-free pin, not yet a final board decision.
+
+VERIFICATION: tb_spi_host_bridge_v3.v extended with a new Test O (10
+real checks): idle-high with no job/error; job_out_done sets it low and
+it's sticky (survives job_out_done itself deasserting); still low
+mid-transaction, only clears when CS actually rises on a real STATUS
+or REG_READ(0x02) transaction; a REG_READ of an UNRELATED register does
+NOT acknowledge it; dir_error alone (no job_out_done) also asserts it,
+combinationally, live, clearing the moment dir_error itself clears.
+**49/49 PASS** (39 pre-existing + 10 new), real iverilog run.
+
+DECISION: keep. Real, verified, low-risk (one new register, one new
+top-level port, no change to any existing timing-critical path). Real
+P&R verification for this specific addition is deferred to the SAME
+next real P&R run already needed to close EXP-0084's own real timing
+gap (reverting Input Clock Period) -- no point spending a separate real
+P&R cycle on an unrelated port addition against a config already known
+to fail timing for other reasons.
+
+next_action: include in the next real P&R run (after the user's own
+clock-period-revert MIG wizard session) and confirm it doesn't disturb
+the tight I/O/VCCO budget further. Document the real ESP32-side
+GPIO/interrupt wiring implication once the board's own reset-circuit
+pin planning (S7, still open) is decided, since data_ready_n and
+sys_rst now share bank 15's own real, tentative pin choices.