feat: real Director extension for group dispatch + systolic_group.v P&R sanity check (EXP-0090)

Adds neural_director_grouped.v, a direct extension of neural_director_
packed.v's own already-proven 2-position pairing discipline to 8-position
octets (matching systolic_group.v's fixed 4 PEs x 2 lanes). Real,
deliberate finding: the host-facing SPI/WRITE_JOB submission protocol
needs zero changes -- the host just submits 8 jobs sharing a weight base
instead of 2, the same real pattern already required today.

Real out-of-context synthesis of one systolic_group.v: 32 DSP48E1
(13.3%), confirming the original brainstorm's own DSP projection exactly.

Found and fixed two real bugs: (1) a wraparound-arithmetic width bug in
the octet index computation (same class already flagged for address
math elsewhere in this project -- needs N+1 bits before the mod-reduce
compare, not N); (2) a real, generalizable testbench race -- driving
stimulus on the same clock edge the DUT samples on works fine with a
natural gap between pulses (every prior testbench in this project has
one) but silently double-registers data when called back-to-back with
zero gap, confirmed via real signal tracing. Fixed with @(negedge clk)
stimulus; CLAUDE.md's existing blocking/nonblocking testbench-race
lesson extended to cover this new trigger.

Verified via tb_neural_director_grouped.v: 4/4 PASS (octet dispatch +
per-PE addressing, stall-not-mis-dispatch on a mismatched octet, queue
wraparound).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

docs/ARCHITECTURE_ANALYSIS.md

@@ -659,18 +659,35 @@ specifically to document where/how it breaks rather than to succeed):
 
 ---
 
-### 5.6 [First step DONE, EXP-0089] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains
+### 5.6 [Steps 1–2 DONE, EXP-0089/0090] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains
 
 Captured from a 2026-09-20 brainstorming session as a purely exploratory
 idea; the same day, per the user's own explicit reprioritization, the real
 open design question below (shared-weight broadcast vs. a literal PE-to-PE
-systolic shift register) was resolved with the user directly (not guessed),
-and the **first real, isolated step is now built and verified**:
-`systolic_group.v` + `packed_pe.v` (EXP-0089) — one real group of 4 PEs
-sharing a single broadcast weight fetch, real barrier-synchronized, real
-xsim-verified (8/8 PASS across 2 consecutive group jobs). **Not yet done**:
-Director/SPI-level job dispatch for group jobs, a real N=16 (4-group)
-top-level, and any real P&R for this — see EXP-0089's own `next_action`.
+systolic shift register) was resolved with the user directly (not guessed).
+**Real progress so far**:
+- `systolic_group.v` + `packed_pe.v` (EXP-0089) — one real group of 4 PEs
+  sharing a single broadcast weight fetch, real barrier-synchronized, real
+  xsim-verified (8/8 PASS across 2 consecutive group jobs).
+- Real out-of-context synthesis of one group (EXP-0090): **32 DSP48E1**
+  (13.3%), confirming the original brainstorm's own quantified DSP
+  projection exactly (8 DSP/PE × 4 PEs = 32; scaled to 4 groups, 128/240 =
+  53%, matching the doc's own earlier estimate).
+- `neural_director_grouped.v` (EXP-0090) — real Director extension
+  dispatching 8-position octets to free groups, a direct extension of
+  `neural_director_packed.v`'s own already-proven 2-position pairing
+  discipline. Real, deliberate finding: the host-facing SPI/`WRITE_JOB`
+  submission protocol needs **zero changes** — the host just submits 8
+  jobs sharing a weight base instead of 2. Real xsim-verified (4/4 PASS:
+  correct octet dispatch + per-PE addressing, correct stall-not-mis-
+  dispatch on a mismatched octet, correct queue wraparound). Also
+  surfaced a real, generalizable testbench-race lesson (tight back-to-
+  back stimulus pulses on the same edge the DUT samples on — fixed with
+  `@(negedge clk)` stimulus — see CLAUDE.md).
+
+**Not yet done**: a real N=16 (4-group) top-level module + a real,
+appropriately-sized arbiter, and real in-context P&R for the whole system
+— see EXP-0090's own `next_action`.
 
 **The problem it targets**: plain N=16 independent cores (§5.5's own
 "documentary, expected to break" framing) means 16 independent DDR3