michele/FPGA-Neural
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix: make flash SPI bus electrically independent, drop USRMCLK/CCLK reuse (Phase F7)

Browse Source 
The flash subsystem's SCLK previously reused the boot config-SPI's CCLK
pad via the ECP5 USRMCLK primitive to save one pin. This made the
"exclusive flash bus" claim misleading (SCLK still depended on the
config engine's own pad electrically) and carried an unresolved
verification gap (USRMCLKTS pad-enable timing never checked against
the primary Lattice sysCONFIG Usage Guide).

flash_sclk is now a genuine 4th ordinary GPIO pin (E3, bank 7), added
purely additively to the real .lpf (git diff: one new line, no existing
ball moved). The flash bus is now 4 fully independent wires
(sclk/mosi/miso/cs_n), zero pins shared with any ECP5 config primitive
-- confirmed by the full-system synthesis reporting USRMCLK 0/1 (0%)
utilisation.

All 33 project testbenches re-run clean after the port rename (no
functional change, only sclk_sim -> sclk). Full-system real synthesis
re-verified: 0 constraint errors, Fmax 67.91MHz (up slightly from
66.68MHz, same critical path, not a regression).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-04 10:16:31 +02:00
co-authored by Claude Sonnet 5
parent 97a21be240
commit b029e3d95a
27 changed files with 421230 additions and 418334 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tools/pinout/gen_lpf.py
+16 -12
View File
@@ -77,19 +77,23 @@ def assign(rows):
# Application SPI + reset + host attention pins (irq_n/data_ready_n,
# added 2026-09-03), all in bank 7 alongside clk -- kept away from
# the PSRAM bus (banks 2+3) per the same "opposite edges" rationale
# as the SPI signals. flash_mosi/flash_miso/flash_cs_n (added
# 2026-09-04, flash-subsystem F5) join the same pool for the same
# reason -- this is the APPLICATION-side master toward the
# boot/persistence flash (rtl/spi_flash_master.v), physically
# distinct pins from both the host SPI above and the dedicated
# config-SPI pins (never touched by user logic, see
# docs/FPGA-Neural-Hardware-Design.md §6). No flash_sclk pin here:
# that clock is generated internally via the USRMCLK primitive
# (see rtl/spi_flash_master.v's header for the full ECP5
# rationale), not a normal constrainable I/O.
# as the SPI signals. flash_sclk/flash_mosi/flash_miso/flash_cs_n
# (added 2026-09-04, revised same day to drop the USRMCLK/CCLK
# coupling -- see rtl/spi_flash_master.v's header) join the same
# pool for the same reason -- this is a fully independent,
# ordinary-GPIO SPI bus toward the boot/persistence flash
# (rtl/spi_flash_master.v), physically distinct from both the host
# SPI above and the dedicated config-SPI pins (never touched by
# user logic, see docs/FPGA-Neural-Hardware-Design.md §6). No pin
# is shared with any ECP5 config primitive.
# flash_sclk appended LAST (not inserted among the other flash
# signals) so this regeneration stays additive: flash_mosi/
# flash_miso/flash_cs_n keep the exact balls already committed to
# the datasheet/schematic notes, only one genuinely new ball is
# allocated for flash_sclk.
spi_names = ["sclk", "mosi", "miso", "cs_n", "rst", "irq_n", "data_ready_n",
"flash_mosi", "flash_miso", "flash_cs_n"]
for name, (ball, _) in zip(spi_names, ctrl_pool[0:10]):
"flash_mosi", "flash_miso", "flash_cs_n", "flash_sclk"]
for name, (ball, _) in zip(spi_names, ctrl_pool[0:11]):
a[name] = ball
a["clk"] = CLK_BALL
return a