fix: make flash SPI bus electrically independent, drop USRMCLK/CCLK reuse (Phase F7)

The flash subsystem's SCLK previously reused the boot config-SPI's CCLK
pad via the ECP5 USRMCLK primitive to save one pin. This made the
"exclusive flash bus" claim misleading (SCLK still depended on the
config engine's own pad electrically) and carried an unresolved
verification gap (USRMCLKTS pad-enable timing never checked against
the primary Lattice sysCONFIG Usage Guide).

flash_sclk is now a genuine 4th ordinary GPIO pin (E3, bank 7), added
purely additively to the real .lpf (git diff: one new line, no existing
ball moved). The flash bus is now 4 fully independent wires
(sclk/mosi/miso/cs_n), zero pins shared with any ECP5 config primitive
-- confirmed by the full-system synthesis reporting USRMCLK 0/1 (0%)
utilisation.

All 33 project testbenches re-run clean after the port rename (no
functional change, only sclk_sim -> sclk). Full-system real synthesis
re-verified: 0 constraint errors, Fmax 67.91MHz (up slightly from
66.68MHz, same critical path, not a regression).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

docs/FPGA-NeuralNetwork-Engine.md

@@ -556,9 +556,18 @@ flash sector (sector 0) — no dynamic allocation, no garbage collection.
 
 **Layering** (each level reusable/testable on its own):
 - `rtl/spi_flash_master.v` — raw SPI master toward the flash chip
-  (RDID/READ/WREN/PP/SE/RDSR-1), owns the ECP5 `USRMCLK` primitive
-  internally (the flash's SCLK is not a normal I/O pin post-configuration
-  — see that file's own header for the full citation trail).
+  (RDID/READ/WREN/PP/SE/RDSR-1). All 4 pins (`sclk`/`mosi`/`miso`/`cs_n`)
+  are ordinary GPIO (`flash_sclk`/`flash_mosi`/`flash_miso`/`flash_cs_n`
+  at the top level) — a **fully independent** SPI bus, no pin shared
+  with the dedicated boot config-SPI path, no ECP5 config-primitive
+  involved. **Revised 2026-09-04**: an earlier version reused the
+  boot `CCLK` pad via the `USRMCLK` primitive to save one pin — dropped
+  because it made the "exclusive flash bus" claim electrically
+  misleading (SCLK depended on the same pad as the config engine) and
+  carried an unresolved verification gap (`USRMCLKTS` pad-enable timing
+  was never checked against the primary Lattice sysCONFIG Usage Guide,
+  FPGA-TN-02039, not present in this project's local document set).
+  See `WORKLOG.md`'s Phase F7 entry.
 - `rtl/flash_copy_engine.v` — block-streaming engine on top: flash→PSRAM
   (`DIR_LOAD`), PSRAM→flash with internal erase-before-write + ≤256B
   Page Program loop + WIP polling (`DIR_SAVE`), standalone sector erase