fix: make flash SPI bus electrically independent, drop USRMCLK/CCLK reuse (Phase F7)
The flash subsystem's SCLK previously reused the boot config-SPI's CCLK pad via the ECP5 USRMCLK primitive to save one pin. This made the "exclusive flash bus" claim misleading (SCLK still depended on the config engine's own pad electrically) and carried an unresolved verification gap (USRMCLKTS pad-enable timing never checked against the primary Lattice sysCONFIG Usage Guide). flash_sclk is now a genuine 4th ordinary GPIO pin (E3, bank 7), added purely additively to the real .lpf (git diff: one new line, no existing ball moved). The flash bus is now 4 fully independent wires (sclk/mosi/miso/cs_n), zero pins shared with any ECP5 config primitive -- confirmed by the full-system synthesis reporting USRMCLK 0/1 (0%) utilisation. All 33 project testbenches re-run clean after the port rename (no functional change, only sclk_sim -> sclk). Full-system real synthesis re-verified: 0 constraint errors, Fmax 67.91MHz (up slightly from 66.68MHz, same critical path, not a regression). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
@@ -15,8 +15,9 @@ Yosys+nextpnr-ecp5), test avversari oltre al caso positivo, tracciabilità delle
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## `rtl/spi_flash_master.v` — master SPI verso la flash (F1)
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**Cosa è coperto**: RDID, READ, WREN, PP (incl. la regola "solo AND, mai OR" del datasheet),
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SE, RDSR-1; gestione USRMCLK per CCLK post-configurazione; opcode non implementato non causa
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hang.
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SE, RDSR-1; opcode non implementato non causa hang. **Revisionato in Fase F7 (2026-09-04)**:
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`sclk` è ora GPIO ordinaria sempre presente (non più dietro `USRMCLK`/CCLK-reuse — vedi
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`WORKLOG.md` Fase F7 per il perché), bus a 4 fili genuinamente indipendente.
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**Come**: `sim/spi_flash_master_tb.v`, 5 test contro `sim/flash_model.v`.
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@@ -31,13 +32,15 @@ ingenuo che passerebbe un test più debole.
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nessun hang, il master shifta un numero fisso di bit indipendentemente dalla semantica.
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**Sintesi reale**: `yosys synth_ecp5` (0 problemi) + `nextpnr-ecp5` reale, modulo isolato:
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Fmax 181.72 MHz (PASS a 80MHz), `USRMCLK` 1/1 piazzata.
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Fmax 181.36 MHz (PASS a 80MHz, ri-misurato in Fase F7 dopo la rimozione di `USRMCLK` —
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181.72 MHz il numero precedente, differenza nel rumore di piazzamento), `USRMCLK` **0/1
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(0%)** — conferma diretta che la primitiva non è più usata.
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**NON coperto (§A.6)**: nessun test di power-loss (arriva a livello catalogo, F4); nessun
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timeout RDSR a questo livello (responsabilità del chiamante, F3); nessuna verifica
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elettrica/analogica reale (setup/hold, rise/fall) — solo comportamentale; polarità di
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`USRMCLKTS` basata sulla convenzione open-source comune, non verificata contro la Technical
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Note Lattice primaria (non presente nel set documentale locale).
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elettrica/analogica reale (setup/hold, rise/fall) — solo comportamentale. Il gap di
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verifica su `USRMCLKTS` (mai verificato contro la Technical Note Lattice primaria) è stato
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**chiuso rimuovendo la dipendenza stessa** in Fase F7, non colmando la verifica mancante.
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---
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@@ -226,6 +229,20 @@ Occupazione (sistema completo): `TRELLIS_IO` 56/245 (22%), `TRELLIS_FF` 4855/438
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`TRELLIS_COMB` 9060/43848 (20%), `DP16KD` 2/108, `MULT18X18D` 16/72, `USRMCLK` 1/1 (100%) —
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nessuna pressione sulle risorse del dispositivo.
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**Fase F7 (2026-09-04, stesso giorno): bus flash reso indipendente, ri-sintetizzato.**
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Rimosso `USRMCLK`/riuso di CCLK per SCLK (richiesta esplicita dell'utente: il bus deve essere
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esclusivo anche elettricamente, non solo di controllo — vedi `WORKLOG.md` Fase F7 per il
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razionale completo). `flash_sclk` è ora una 4ª ball GPIO ordinaria (`E3`, banco 7), aggiunta
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in modo puramente additivo (`git diff` sul `.lpf`: solo 1 riga in più, nessuna ball esistente
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spostata). Ri-sintesi completa del sistema: **0 errori di vincolo**, `TRELLIS_IO` 57/245
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(23%), **`USRMCLK` 0/1 (0%)** — conferma diretta che la primitiva non è più usata affatto.
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Fmax **67.91 MHz** (leggermente meglio dei 66.68MHz precedenti, rumore di piazzamento, non
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regressione), percorso critico confermato ancora identico (nessun modulo flash coinvolto).
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Regressione completa dei 33 testbench del progetto ripetuta da zero dopo il fix: tutti PASS,
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incluso il test end-to-end mandatorio con lo stesso output atteso (126) e le stesse latenze
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misurate (ERASE≈400.003ms, SAVE≈403.004ms, LOAD=1.743ms — invariate, la rinomina del pin non
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tocca la temporizzazione).
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---
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## Scoperta trasversale: limite reale di `WRITE_RAM`/`READ_RAM` (non specifica alla flash)
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@@ -72,11 +72,11 @@ Signal budget this design actually needs:
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| Application SPI (`sclk/mosi/miso/cs_n`) | 4 |
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| `clk`, `rst` | 2 |
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| Host attention (`irq_n`, `data_ready_n`, added 2026-09-03 — §7) | 2 |
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| Config SPI (to onboard FLASH) | 3 (`flash_mosi`/`flash_miso`/`flash_cs_n` — SCLK shared via `USRMCLK`, no dedicated pin, confirmed against yosys's own `cells_bb.v` blackbox; implemented Phases F1-F6) |
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| Flash runtime SPI bus (`flash_sclk`/`flash_mosi`/`flash_miso`/`flash_cs_n` — fully independent, all ordinary GPIO, no config-primitive shared; implemented Phases F1-F7) | 4 |
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| JTAG (recommended, for bring-up/debug) | 4 |
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| **Total** | **~59** |
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| **Total** | **~60** |
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~59 of ~232 usable I/O used (56 actually placed and place&route-verified
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~60 of ~232 usable I/O used (57 actually placed and place&route-verified
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in the flash-subsystem synthesis, `synth/ecp5/spi_neuron_top_flash/
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nextpnr.log`) — **plenty of headroom** (~170+ spare
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pins) for LEDs, buttons, a debug PMOD-style header, or a second SPI
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@@ -280,16 +280,28 @@ usage: 53/245 (21%) — still confirms the §2 headroom estimate.
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`WORKLOG.md`) added 3 real pins (`flash_mosi`, `flash_miso`, `flash_cs_n`
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— bank 7, generated additively by `tools/pinout/gen_lpf.py`, confirmed via
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`git diff` on `synth/ecp5/spi_neuron_top.lpf` to leave every existing ball
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unchanged; no dedicated flash SCLK pin — it reuses the same `USRMCLK`
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primitive already driving the application-SPI/config path, per §7):
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full-system real Yosys+nextpnr-ecp5 synthesis (`synth/ecp5/
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unchanged). Full-system real Yosys+nextpnr-ecp5 synthesis (`synth/ecp5/
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spi_neuron_top_flash/nextpnr.log`), **0 constraint errors**, full route
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completes, Fmax **66.68 MHz**. The critical path is confirmed
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unchanged from the pre-existing `neuron_parallel` accumulator carry chain
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(no flash-subsystem module appears in the reported critical path) — the
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66.68 vs 73.88 MHz difference is attributed to placement/routing
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noise from the added I/O and logic, not a new bottleneck. TRELLIS_IO
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usage: 56/245 (23%).
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completes, Fmax **66.68 MHz**. TRELLIS_IO usage: 56/245 (23%).
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**Superseded again the same day (Phase F7)**: the flash bus's SCLK
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originally reused the boot `CCLK` pad via the ECP5 `USRMCLK` primitive
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(no dedicated pin) — dropped after the user pointed out this made the
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"exclusive flash bus" claim electrically misleading (SCLK still
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depended on the same pad as the config engine) and it carried an
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unresolved verification gap (`USRMCLKTS` pad-enable timing never
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checked against the primary Lattice sysCONFIG Usage Guide,
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FPGA-TN-02039, absent from this project's document set). `flash_sclk`
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is now a 4th ordinary GPIO ball (`E3`, bank 7), added purely additively
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(`git diff` confirms only the new line, no existing ball moved) — the
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flash bus is now 4 independent wires (`sclk`/`mosi`/`miso`/`cs_n`), zero
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pins shared with any ECP5 config primitive. Re-verified with a fresh
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full-system synthesis: **0 constraint errors**, Fmax **67.91 MHz**
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(slightly better than 66.68, placement noise, not a regression),
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critical path confirmed unchanged (`neuron_parallel` accumulator carry
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chain, no flash module involved), `USRMCLK` utilisation now **0/1
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(0%)** — direct confirmation the primitive is no longer used at all.
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TRELLIS_IO usage: 57/245 (23%). See `WORKLOG.md`'s Phase F7 entry.
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**Cross-checked against the real Lattice datasheet (2026-09-03, user-
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provided `FPGA-DS-02012-3-4-ECP5-ECP5G-Family-Data-Sheet.pdf`)**: its §4.3.2
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@@ -374,9 +386,10 @@ the exact rationale):
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| `irq_n` | C4 | 7 | low while `graph_engine`'s load-time guard has tripped (mirrors STATUS.bit2 / §7 of the network-engine spec); clears only on RESET or a fresh graph `run_start`, NOT on a plain STATUS read |
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**Flash subsystem — runtime SPI to the onboard W25Q128JV** (added
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2026-09-04, Phases F1-F6 — `rtl/spi_flash_master.v`, `WORKLOG.md`; ordinary
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GPIO, generated the same additive way as every other row here, confirmed
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by `git diff` against the pre-flash `.lpf` to leave every existing ball
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2026-09-04, Phases F1-F6, made fully independent in Phase F7 same day —
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`rtl/spi_flash_master.v`, `WORKLOG.md`; all 4 signals ordinary GPIO,
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generated the same additive way as every other row here, confirmed by
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`git diff` against the pre-flash `.lpf` to leave every existing ball
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unchanged):
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| Signal | Ball | Bank | Note |
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@@ -384,12 +397,23 @@ unchanged):
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| `flash_cs_n` | E4 | 7 | |
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| `flash_miso` | D5 | 7 | |
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| `flash_mosi` | D3 | 7 | |
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| `flash_sclk` | E3 | 7 | added Phase F7 — see below |
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No `flash_sclk` ball: SCLK is driven through the `USRMCLK` primitive,
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reclaiming the same physical CCLK net already used for bitstream boot —
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see §6/§9 for the board-level wiring implication (the flash chip's
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DI/DO/CS pins must be dual-wired to both the dedicated sysCONFIG pins and
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these 3 ordinary balls).
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**Phase F7 (2026-09-04): `flash_sclk` is now a real, independent GPIO
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ball, not a CCLK/`USRMCLK` reuse.** An earlier version drove SCLK
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through the ECP5 `USRMCLK` primitive, reclaiming the same physical CCLK
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net already used for bitstream boot, to save one pin. Dropped: it made
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the "exclusive flash bus" claim electrically misleading (SCLK still
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depended on the config engine's own pad) and carried an unresolved
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verification gap (`USRMCLKTS` pad-enable timing never checked against
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the primary Lattice sysCONFIG Usage Guide, FPGA-TN-02039, absent from
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this project's document set). Re-synthesized full system: `USRMCLK`
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utilisation now 0/1 (0%), directly confirming the primitive is no
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longer used at all. See §6/§9 for the board-level wiring implication
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(the flash chip's DI/DO/CS/CLK pins must be dual-wired to both the
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dedicated sysCONFIG pins and these 4 ordinary balls — a board-level
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duplication inherent to using one physical chip for both boot and
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runtime persistence, not something Phase F7 changed).
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**PSRAM address:**
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@@ -485,9 +509,10 @@ sizes are decided.
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real Lattice datasheet (§7, matches on 6/7 banks exactly). Fmax
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54.58 MHz when this pinout was first verified, 75.30 MHz
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after the `neuron_parallel` timing-closure work, 73.88 MHz
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after adding the host-attention pins, and **66.68 MHz** for
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the current full system including the flash subsystem (§7,
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2026-09-04) — see §7 for the full history and why each change is
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after adding the host-attention pins, 66.68 MHz after adding
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the flash subsystem, and **67.91 MHz** for the current full
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system after making the flash SPI bus fully independent (Phase F7,
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§7, 2026-09-04) — see §7 for the full history and why each change is
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pin-placement noise, not a regression.
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**Config-SPI and JTAG ball numbers are still not pinned down**
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(§7) — confirmed by reading the full real datasheet that it has
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@@ -504,21 +529,21 @@ sizes are decided.
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in-progress KiCad work, not something this repo's synthesis
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flow needs to resolve.
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**Distinct from this open item** (do not conflate the two): the
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flash subsystem's own runtime SPI pins (`flash_mosi`, `flash_miso`,
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`flash_cs_n` — Phases F1-F6, `WORKLOG.md`) **are** real, pinned,
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place&route-verified ordinary GPIO on bank 7 (`flash_mosi`=D3,
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flash subsystem's own runtime SPI pins (`flash_sclk`, `flash_mosi`,
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`flash_miso`, `flash_cs_n` — Phases F1-F6, made fully independent
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in Phase F7, `WORKLOG.md`) **are** real, pinned, place&route-
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verified ordinary GPIO on bank 7 (`flash_sclk`=E3, `flash_mosi`=D3,
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`flash_miso`=D5, `flash_cs_n`=E4), generated the same way as every
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other signal in this table. Only SCLK is shared with the dedicated
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config-boot clock, reclaimed post-configuration via the `USRMCLK`
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primitive (confirmed against yosys's own `cells_bb.v` blackbox) —
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it needs no `.lpf` entry of its own, same reasoning as the
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dedicated pins discussed above. §5's PCB-level implication: the
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W25Q128JV's DI/DO/CS pins must be wired to *both* the dedicated
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sysCONFIG pins (for boot) *and* these 3 ordinary GPIO balls (for
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other signal in this table — **no pin shared with any ECP5 config
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primitive** (Phase F7 removed the earlier `USRMCLK`/CCLK reuse for
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SCLK; `USRMCLK` utilisation in the current full-system synthesis
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is 0/1, confirming it). §5's PCB-level implication: the
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W25Q128JV's DI/DO/CS/CLK pins must be wired to *both* the dedicated
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sysCONFIG pins (for boot) *and* these 4 ordinary GPIO balls (for
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runtime access after configuration completes) — a board-level
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dual-wiring the same shape as the CCLK-reuse workaround already
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noted above, not yet reflected in a schematic since none exists
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yet (see the KiCad item below).
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duplication inherent to using one physical chip for both roles,
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not yet reflected in a schematic since none exists yet (see the
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KiCad item below).
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- [ ] Confirm PSRAM/SPI signal integrity at whatever clock is
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actually fitted (§4) — no signal integrity analysis done yet
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- [ ] JTAG header footprint choice (blocked on the JTAG ball question
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@@ -556,9 +556,18 @@ flash sector (sector 0) — no dynamic allocation, no garbage collection.
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**Layering** (each level reusable/testable on its own):
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- `rtl/spi_flash_master.v` — raw SPI master toward the flash chip
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(RDID/READ/WREN/PP/SE/RDSR-1), owns the ECP5 `USRMCLK` primitive
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internally (the flash's SCLK is not a normal I/O pin post-configuration
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— see that file's own header for the full citation trail).
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(RDID/READ/WREN/PP/SE/RDSR-1). All 4 pins (`sclk`/`mosi`/`miso`/`cs_n`)
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are ordinary GPIO (`flash_sclk`/`flash_mosi`/`flash_miso`/`flash_cs_n`
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at the top level) — a **fully independent** SPI bus, no pin shared
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with the dedicated boot config-SPI path, no ECP5 config-primitive
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involved. **Revised 2026-09-04**: an earlier version reused the
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boot `CCLK` pad via the `USRMCLK` primitive to save one pin — dropped
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because it made the "exclusive flash bus" claim electrically
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misleading (SCLK depended on the same pad as the config engine) and
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carried an unresolved verification gap (`USRMCLKTS` pad-enable timing
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was never checked against the primary Lattice sysCONFIG Usage Guide,
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FPGA-TN-02039, not present in this project's local document set).
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See `WORKLOG.md`'s Phase F7 entry.
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- `rtl/flash_copy_engine.v` — block-streaming engine on top: flash→PSRAM
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(`DIR_LOAD`), PSRAM→flash with internal erase-before-write + ≤256B
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Page Program loop + WIP polling (`DIR_SAVE`), standalone sector erase
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