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test: fix tb_sdram_arbiter_n.v hang, root-caused as testbench bug (EXP-0069)

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TEST2 fired all 3 simulated requesters' one-shot req pulse
unconditionally, not waiting for each one's own grant -- an
unrealistic stimulus that doesn't match packed_slot.v's real
S_MEMWAIT usage (wait for grant, then fire). Rewrote with parallel
fork branches, each waiting for its own req_grant first, still
exercising the real simultaneous-activation contention case.

7/7 PASS, 0 errors. sdram_arbiter_n.v is now genuinely verified, not
just written.

Full writeup in hardware/v2/logs/experiments.log EXP-0069.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-17 08:44:46 +02:00
co-authored by Claude Sonnet 5
parent e25e4a1506
commit afff0c4f02
2 changed files with 65 additions and 17 deletions
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hardware/v2/logs/experiments.log
+33
View File
@@ -4261,3 +4261,36 @@ that is resolved); (3) swap mig_native_adapter.v into packed_slot.v's
memory path, replacing the SDR SDRAM placeholder, and re-verify the
N=2 system against real DDR3; (4) real (not out-of-context) P&R with
the actual generated MIG XDC constraints for genuine timing signoff.
EXP-0069 -- sdram_arbiter_n.v hang root-caused: testbench bug, not
arbiter bug (2026-09-17, same autonomous continuation)
CONTEXT: EXP-0068's own next_action flagged tb_sdram_arbiter_n.v as
hanging, arbiter not yet trusted.
ROOT CAUSE: TEST2 asserted req_req for all 3 simulated requesters on
the SAME cycle as req_active, then dropped req_req one cycle later
UNCONDITIONALLY -- but the arbiter only grants ONE requester (lowest
index) at a time; slots 1 and 2's one-shot req pulse was long gone by
the time their own turn actually arrived, so they never issued a real
ctrl_req and the test's own `while (!req_ready[1])` waited forever.
This is a testbench-stimulus bug, not an arbiter bug: it modeled an
UNREALISTIC requester (fire-and-forget regardless of grant status)
that does not match how packed_slot.v's own real S_MEMWAIT state
behaves (wait for mem_grant, THEN fire the one-shot pulse) -- the
exact pattern EXP-0066 already established as required and correct.
FIX: rewrote TEST2 with 3 parallel fork branches, each waiting for its
OWN req_grant before pulsing its OWN req_req -- matching packed_slot.v's
real usage exactly, still exercising the real simultaneous-activation
contention case (all 3 raise `active` on the same cycle).
RESULT: 7/7 tests, 0 errors. sdram_arbiter_n.v is now genuinely
verified, including the real simultaneous-multi-requester contention
case with one-shot-pulse requesters (the EXP-0066 risk class).
DECISION: sdram_arbiter_n.v is trusted for integration.
next_action: same as EXP-0068's (3)/(4) -- swap mig_native_adapter.v
into packed_slot.v, re-verify N=2 against real DDR3, then real P&R
with the generated MIG XDC.
hardware/v3/sim/tb_sdram_arbiter_n.v
+32 -17
View File
@@ -131,37 +131,52 @@ module tb;
check_slot(1, 25'd8, 16'hB000);
check_slot(2, 25'd16, 16'hC000);
$display("=== TEST 2: simultaneous multi-requester activation (the real EXP-0066 risk case) ===");
$display("=== TEST 2: simultaneous multi-requester ACTIVATION (the real EXP-0066 risk case) -- each requester fires its OWN one-shot req only once IT sees its OWN grant, exactly matching packed_slot.v's real S_MEMWAIT usage, not a blind simultaneous fire ===");
begin : test2
reg [16*BURST_LEN-1:0] g0, g1, g2, w0, w1, w2;
reg [16*BURST_LEN-1:0] w0, w1, w2;
integer kk;
for (kk = 0; kk < BURST_LEN; kk = kk + 1) begin
w0[kk*16 +: 16] = 16'hD000 + kk[15:0];
w1[kk*16 +: 16] = 16'hE000 + kk[15:0];
w2[kk*16 +: 16] = 16'hF000 + kk[15:0];
end
// all three assert `active`+`req` on the SAME cycle --
// exactly the scenario a registered/late grant loses.
@(posedge clk);
req_active = 3'b111; req_req = 3'b111;
req_wr[0] = 1'b1; req_wr[1] = 1'b1; req_wr[2] = 1'b1;
req_addr[0*ADDR_WIDTH +: ADDR_WIDTH] = 25'd100;
req_addr[1*ADDR_WIDTH +: ADDR_WIDTH] = 25'd108;
req_addr[2*ADDR_WIDTH +: ADDR_WIDTH] = 25'd116;
req_wdata[0*16*BURST_LEN +: 16*BURST_LEN] = w0;
req_wdata[1*16*BURST_LEN +: 16*BURST_LEN] = w1;
req_wdata[2*16*BURST_LEN +: 16*BURST_LEN] = w2;
@(posedge clk);
req_req = 3'b000;
req_wr[0] = 1'b1; req_wr[1] = 1'b1; req_wr[2] = 1'b1;
// slot 0 (lowest index) must win first; 1 and 2 must NOT
// silently lose their request -- wait for each in turn.
while (!req_ready[0]) @(posedge clk);
req_active[0] = 1'b0;
while (!req_ready[1]) @(posedge clk);
req_active[1] = 1'b0;
while (!req_ready[2]) @(posedge clk);
req_active[2] = 1'b0;
// all three raise `active` on the SAME cycle (the real
// contention case) -- but each only pulses its own `req`
// once its own `grant` is observed, exactly like
// packed_slot.v's S_MEMWAIT -> pf_start sequencing.
@(posedge clk);
req_active = 3'b111;
fork
begin
while (!req_grant[0]) @(posedge clk);
@(posedge clk); req_req[0] = 1'b1;
@(posedge clk); req_req[0] = 1'b0;
while (!req_ready[0]) @(posedge clk);
req_active[0] = 1'b0;
end
begin
while (!req_grant[1]) @(posedge clk);
@(posedge clk); req_req[1] = 1'b1;
@(posedge clk); req_req[1] = 1'b0;
while (!req_ready[1]) @(posedge clk);
req_active[1] = 1'b0;
end
begin
while (!req_grant[2]) @(posedge clk);
@(posedge clk); req_req[2] = 1'b1;
@(posedge clk); req_req[2] = 1'b0;
while (!req_ready[2]) @(posedge clk);
req_active[2] = 1'b0;
end
join
tests = tests + 1;
$display("PASS TEST2: all 3 simultaneous requests completed (none silently lost)");