feat: config-flash passthrough bridge via STARTUPE2, real board-exclusive flash access (EXP-0077)

Implements the user's board architecture: config flash wired
exclusively to the FPGA, host (ESP32) reaches it only through the
FPGA. flash_spi_master.v is a plain byte-wide SPI master using
STARTUPE2 to reclaim CCLK after configuration (the real, Xilinx-
documented "indirect SPI flash programming" technique, UG470 p94-96).
New opcode 0x40 FLASH_XFER in spi_host_bridge_v3.v relays bytes
byte-for-byte between host and the physical flash bus -- the host
decides the exact SPI NOR command sequence (verified against the real
W25Q32JV datasheet), this RTL knows nothing about flash semantics.

Found and fixed two real bugs during verification: a byte-assembly
off-by-one in flash_spi_master.v, and a genuine protocol-latency bug
in the FLASH_XFER opcode's response timing (needed 2 trailing margin
bytes, not 1 -- the internal flash transfer doesn't start until the
triggering byte finishes, so 1 byte of margin isn't enough). 39/39
tests pass end to end (host SPI -> bridge -> flash_spi_master ->
behavioral flash model).

Wired into n2_system_ddr3_top.v with real pin constraints (flash_mosi
=K17/flash_miso=K18/flash_cs_n=L13, the same pins reserved-but-unused
in EXP-0075) and BITSTREAM.CONFIG.PERSIST=FALSE made explicit.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

hardware/v3/rtl/n2_system_ddr3_top.v

@@ -70,6 +70,17 @@ module n2_system_ddr3_top #(
     output wire miso,
     input  wire cs_n,
 
+    // ---- config-flash passthrough physical pins (this project's own
+    // board pins D00_MOSI=K17/D01_DIN=K18/FCS_B=L13, reclaimed as
+    // ordinary fabric I/O post-configuration -- see flash_spi_master.v's
+    // own header for the real Xilinx PERSIST/STARTUPE2 requirements
+    // this depends on). CCLK is NOT a port here -- flash_spi_master.v
+    // drives it internally via STARTUPE2, a dedicated pin that can
+    // never be an ordinary top-level port. ----
+    output wire flash_cs_n,
+    output wire flash_mosi,
+    input  wire flash_miso,
+
     // ---- results (small enough to keep as real top-level pins for
     // observation; NOT part of the activation-interface pin-count
     // problem described below) ----
@@ -201,6 +212,9 @@ module n2_system_ddr3_top #(
     wire [15:0] mem_wdata, mem_rdata;
     wire soft_rst_pulse;
 
+    wire       flash_xfer_active, flash_byte_req, flash_byte_done;
+    wire [7:0] flash_byte_wdata, flash_byte_rdata;
+
     spi_host_bridge_v3 #(
         .JOB_ADDR_WIDTH(JOB_ADDR_WIDTH), .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH), .N_SLOTS(N_SLOTS)
     ) u_spi (
@@ -214,9 +228,19 @@ module n2_system_ddr3_top #(
         .mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr),
         .mem_wdata(mem_wdata), .mem_lb_n(mem_lb_n), .mem_ub_n(mem_ub_n),
         .mem_rdata(mem_rdata), .mem_ready(mem_ready),
+        .flash_xfer_active(flash_xfer_active), .flash_byte_req(flash_byte_req),
+        .flash_byte_wdata(flash_byte_wdata), .flash_byte_rdata(flash_byte_rdata),
+        .flash_byte_done(flash_byte_done),
         .soft_rst_pulse(soft_rst_pulse)
     );
 
+    flash_spi_master u_flash (
+        .clk(ui_clk), .rst(ui_clk_sync_rst),
+        .xfer_active(flash_xfer_active), .byte_req(flash_byte_req),
+        .byte_wdata(flash_byte_wdata), .byte_rdata(flash_byte_rdata), .byte_done(flash_byte_done), .busy(),
+        .flash_cs_n(flash_cs_n), .flash_mosi(flash_mosi), .flash_miso(flash_miso)
+    );
+
     host_mem_bridge #(
         .BURST_LEN(BURST_LEN), .ADDR_WIDTH(MEM_ADDR_WIDTH)
     ) u_host_bridge (