feat: complete Phase 4 SPI RTL (engine, arbiter, top) + real-RAM e2e test
Implements the rest of the SPI interface (docs §8.1) on top of spi_slave.v from the previous commit: - rtl/spi_engine.v: opcode FSM + register bank, all 8 opcodes (NOP, WRITE_RAM, READ_RAM, RESET, SET_BASE, START, STATUS, READ_OUTPUT, READ_CONFIG). tx_byte is driven combinationally from live state (not reactively on tx_byte_req), applying the prefetch-vs-consume contract documented on spi_slave.v. STATUS.done is a sticky, clear-on-read latch. RAM master port uses the same byte-level convention as neuron_memory.v's external mem_* port. - rtl/mem_arbiter.v: fixed-priority (neuron_memory > spi_engine) grant-and-forward arbiter sharing one byte-level memory port between spi_engine's WRITE_RAM/READ_RAM and neuron_memory's own X/W/bias reads during a run. - rtl/spi_neuron_top.v: full integration -- spi_slave -> spi_engine -> mem_arbiter -> a single shared int8_memory_access -> memory_interface -> psram_controller -> PSRAM pins. neuron_memory's rst is global rst OR'd with the RESET opcode's soft-reset pulse. The host has no direct electrical path to the RAM, only through this chain. Testing: - sim/spi_engine_tb.v: 10 tests (one per opcode + WRITE_RAM/READ_RAM, START idle-vs-busy, STATUS sticky/clear-on-read, extra-MOSI-bytes- ignored, back-to-back transactions) against a synthetic 2-cycle- latency RAM model, isolating the opcode FSM from PSRAM timing. Found and fixed two testbench-only bugs (RTL needed no change): the same delta-zero clock-edge race as spi_slave_tb.v (blocking `nm_done=1` landing on the same sim time as a posedge -- fixed via negedge-based pulsing) and a missing RAM sentinel initialization. - sim/spi_neuron_top_tb.v: end-to-end test against the **real** psram_model.v (not a mock) -- RESET/READ_CONFIG/WRITE_RAM/ READ_RAM/SET_BASE/START/STATUS/READ_OUTPUT all driven purely over simulated SPI. 3/3 scenarios (sum, saturation, ReLU) pass on the first attempt; confirms the arbiter and shared byte<->word bridge are correct against real PSRAM timing, not just a synthetic mock. Real-toolchain verification (Yosys + nextpnr-ecp5 + ecppack): spi_slave.v and spi_engine.v synthesize clean and comfortably clear 80 MHz in isolation (403 MHz / 191 MHz, no DSP usage). The full spi_neuron_top.v integration, however, does NOT meet 80 MHz (~52-56 MHz depending on PARALLEL) -- the critical path is entirely inside neuron_parallel.v's existing saturation comparator (no contribution from the new SPI/arbiter logic), but its routed delay is ~57% worse than in the isolated benchmark due to placement/ routing congestion once SPI + PSRAM logic shares the fabric with it, not resource exhaustion (2% DSP usage). Documented as a Phase 4/7 finding in docs/FPGA-NeuralNetwork-Engine.md -- a floorplanning/ pipelining problem for Phase 7, not a functional-correctness issue (verified independently in simulation against real PSRAM timing). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
This commit is contained in:
Claude Sonnet 5
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`timescale 1ns/1ps
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// ================================================================
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// SPI_NEURON_TOP
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//
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// Full Phase 3 + Phase 4 integration: SPI host interface (spi_slave
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// + spi_engine, docs §8.1) driving neuron_memory.v (Phase 3,
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// N_NEURONS>=1) through a shared PSRAM (memory_interface +
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// psram_controller), arbitrated between spi_engine's own RAM access
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// (WRITE_RAM/READ_RAM opcodes) and neuron_memory's own X/W/bias
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// reads during a run.
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//
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// neuron_memory's own `rst` is the global reset OR'd with the
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// RESET opcode's soft-reset pulse from spi_engine, so a host can
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// recover the compute engine over SPI without a physical reset
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// (RAM contents are untouched either way).
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// ================================================================
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module spi_neuron_top #(
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parameter ADDR_WIDTH = 22,
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parameter DATA_WIDTH = 8,
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parameter N_INPUTS = 32,
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parameter N_NEURONS = 1,
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parameter PARALLEL = 8,
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parameter ACC_WIDTH = 32,
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parameter MEM_DATA_WIDTH = 16,
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parameter CLK_FREQ_MHZ = 80
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)(
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input wire clk,
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input wire rst,
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// ------------------------------------------------------------
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// SPI host interface
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// ------------------------------------------------------------
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input wire sclk,
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input wire mosi,
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output wire miso,
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input wire cs_n,
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// ------------------------------------------------------------
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// PSRAM physical interface
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// ------------------------------------------------------------
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output wire [ADDR_WIDTH-1:0] psram_a,
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inout wire [MEM_DATA_WIDTH-1:0] psram_dq,
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output wire psram_ce_n,
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output wire psram_oe_n,
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output wire psram_we_n,
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output wire psram_lb_n,
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output wire psram_ub_n,
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output wire psram_zz_n
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);
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// ============================================================
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// SPI PHYSICAL LAYER
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// ============================================================
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wire [7:0] rx_byte;
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wire rx_valid;
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wire cs_start;
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wire cs_end;
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wire [7:0] tx_byte;
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wire tx_byte_req;
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spi_slave u_spi_slave (
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.clk(clk), .rst(rst),
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.sclk(sclk), .mosi(mosi), .miso(miso), .cs_n(cs_n),
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.rx_byte(rx_byte), .rx_valid(rx_valid),
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.tx_byte(tx_byte), .tx_byte_req(tx_byte_req),
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.cs_active(), .cs_start(cs_start), .cs_end(cs_end)
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);
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// ============================================================
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// SPI PROTOCOL ENGINE
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// ============================================================
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wire spi_ram_req;
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wire spi_ram_wr;
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wire [ADDR_WIDTH-1:0] spi_ram_addr;
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wire signed [7:0] spi_ram_wdata;
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wire signed [7:0] spi_ram_rdata;
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wire spi_ram_ready;
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wire [ADDR_WIDTH-1:0] x_base;
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wire [ADDR_WIDTH-1:0] w_base;
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wire [ADDR_WIDTH-1:0] bias_addr;
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wire nm_start;
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wire nm_busy;
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wire nm_done;
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wire signed [DATA_WIDTH*N_NEURONS-1:0] y_bus;
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wire nm_soft_rst;
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spi_engine #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.N_INPUTS(N_INPUTS),
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.N_NEURONS(N_NEURONS),
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.PARALLEL(PARALLEL)
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) u_spi_engine (
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.clk(clk), .rst(rst),
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.rx_byte(rx_byte), .rx_valid(rx_valid),
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.cs_start(cs_start), .cs_end(cs_end),
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.tx_byte(tx_byte), .tx_byte_req(tx_byte_req),
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.ram_req(spi_ram_req), .ram_wr(spi_ram_wr),
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.ram_addr(spi_ram_addr), .ram_wdata(spi_ram_wdata),
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.ram_rdata(spi_ram_rdata), .ram_ready(spi_ram_ready),
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.x_base(x_base), .w_base(w_base), .bias_addr(bias_addr),
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.nm_start(nm_start), .nm_busy(nm_busy), .nm_done(nm_done),
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.y_bus(y_bus),
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.nm_soft_rst(nm_soft_rst)
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);
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// ============================================================
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// NEURON MEMORY
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//
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// rst is the global reset OR'd with the SPI RESET opcode pulse.
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// ============================================================
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wire nm_rst = rst | nm_soft_rst;
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wire nm_ram_req;
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wire nm_ram_wr;
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wire [ADDR_WIDTH-1:0] nm_ram_addr;
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wire signed [7:0] nm_ram_wdata;
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wire signed [7:0] nm_ram_rdata;
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wire nm_ram_ready;
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neuron_memory #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.N_INPUTS(N_INPUTS),
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.N_NEURONS(N_NEURONS),
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.PARALLEL(PARALLEL),
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.ACC_WIDTH(ACC_WIDTH)
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) u_neuron_memory (
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.clk(clk), .rst(nm_rst),
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.start(nm_start),
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.mem_req(nm_ram_req), .mem_wr(nm_ram_wr),
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.mem_addr(nm_ram_addr), .mem_wdata(nm_ram_wdata),
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.mem_rdata(nm_ram_rdata), .mem_ready(nm_ram_ready),
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.x_base(x_base), .w_base(w_base), .bias_addr(bias_addr),
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.y_bus(y_bus), .busy(nm_busy), .done(nm_done)
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);
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// ============================================================
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// SHARED MEMORY ARBITER
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// ============================================================
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wire arb_req;
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wire arb_wr;
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wire [ADDR_WIDTH-1:0] arb_addr;
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wire signed [7:0] arb_wdata;
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wire signed [7:0] arb_rdata;
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wire arb_ready;
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mem_arbiter #(
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.ADDR_WIDTH(ADDR_WIDTH)
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) u_arbiter (
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.clk(clk), .rst(rst),
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.a_req(spi_ram_req), .a_wr(spi_ram_wr),
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.a_addr(spi_ram_addr), .a_wdata(spi_ram_wdata),
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.a_rdata(spi_ram_rdata), .a_ready(spi_ram_ready),
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.b_req(nm_ram_req), .b_wr(nm_ram_wr),
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.b_addr(nm_ram_addr), .b_wdata(nm_ram_wdata),
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.b_rdata(nm_ram_rdata), .b_ready(nm_ram_ready),
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.m_req(arb_req), .m_wr(arb_wr),
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.m_addr(arb_addr), .m_wdata(arb_wdata),
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.m_rdata(arb_rdata), .m_ready(arb_ready)
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);
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// ============================================================
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// BYTE <-> WORD BRIDGE (shared, single instance)
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// ============================================================
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wire i8_mem_req;
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wire i8_mem_wr;
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wire [ADDR_WIDTH-1:0] i8_mem_addr;
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wire [MEM_DATA_WIDTH-1:0] i8_mem_wdata;
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wire i8_mem_lb_n;
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wire i8_mem_ub_n;
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wire [MEM_DATA_WIDTH-1:0] i8_mem_rdata;
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wire i8_mem_ready;
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int8_memory_access #(
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.ADDR_WIDTH(ADDR_WIDTH)
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) u_int8_access (
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.clk(clk), .rst(rst),
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.req(arb_req), .wr(arb_wr), .addr(arb_addr), .wdata(arb_wdata),
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.rdata(arb_rdata), .ready(arb_ready),
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.mem_req(i8_mem_req), .mem_wr(i8_mem_wr),
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.mem_addr(i8_mem_addr), .mem_wdata(i8_mem_wdata),
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.mem_lb_n(i8_mem_lb_n), .mem_ub_n(i8_mem_ub_n),
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.mem_rdata(i8_mem_rdata), .mem_ready(i8_mem_ready)
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);
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// ============================================================
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// MEMORY INTERFACE / PSRAM CONTROLLER
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// ============================================================
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wire [MEM_DATA_WIDTH-1:0] psram_mem_rdata;
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wire psram_mem_ready;
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wire psram_mem_req;
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wire psram_mem_wr;
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wire [ADDR_WIDTH-1:0] psram_mem_addr;
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wire [MEM_DATA_WIDTH-1:0] psram_mem_wdata;
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wire psram_mem_lb_n;
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wire psram_mem_ub_n;
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memory_interface #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(MEM_DATA_WIDTH)
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) u_memory_if (
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.clk(clk), .rst(rst),
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.req(i8_mem_req), .wr(i8_mem_wr), .addr(i8_mem_addr), .wdata(i8_mem_wdata),
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.lb_n(i8_mem_lb_n), .ub_n(i8_mem_ub_n),
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.rdata(i8_mem_rdata), .ready(i8_mem_ready),
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.mem_req(psram_mem_req), .mem_wr(psram_mem_wr),
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.mem_addr(psram_mem_addr), .mem_wdata(psram_mem_wdata),
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.mem_lb_n(psram_mem_lb_n), .mem_ub_n(psram_mem_ub_n),
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.mem_rdata(psram_mem_rdata), .mem_ready(psram_mem_ready)
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);
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psram_controller #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(MEM_DATA_WIDTH),
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ)
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) u_psram_ctrl (
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.clk(clk), .rst(rst),
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.mem_req(psram_mem_req), .mem_wr(psram_mem_wr),
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.mem_addr(psram_mem_addr), .mem_wdata(psram_mem_wdata),
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.mem_lb_n(psram_mem_lb_n), .mem_ub_n(psram_mem_ub_n),
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.mem_rdata(psram_mem_rdata), .mem_ready(psram_mem_ready),
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.psram_a(psram_a), .psram_dq(psram_dq),
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.psram_ce_n(psram_ce_n), .psram_oe_n(psram_oe_n), .psram_we_n(psram_we_n),
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.psram_lb_n(psram_lb_n), .psram_ub_n(psram_ub_n), .psram_zz_n(psram_zz_n)
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);
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endmodule
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