docs: memory upgrade writeup (MEMORY_UPGRADE_64MB_N8.md) + supersede stale SDRAM docs
Adds the consolidated, authoritative record for the 64MB memory upgrade and N_SLOTS=8 investigation (real datasheet family comparison, RTL changes, both timing fixes with real P&R data, honest N=8 clock- closure status, real DigiKey availability for the frozen part). Marks HARDWARE_FREEZE.md/MEMORY_ARCHITECTURE.md/PRE_PCB_VERIFICATION.md/ PRE_PCB_CLOSURE_4POINT.md's own SDRAM-specific sections as superseded (they describe the previous 8MB AS4C4M16SA-6TIN part) with pointers to the new document, rather than rewriting each individually. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
@@ -2161,3 +2161,72 @@ STATUS).
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This REVISES CHIP_READINESS.md/OPEN_ITEMS.md's own prior "SDRAM
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datasheet-parameter cross-check: OPEN (sim-level only)" status to
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CLOSED.
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DEC-0039
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DATE: 2026-09-07
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DECISION:
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The single external SDRAM is UPGRADED from Alliance Memory
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AS4C4M16SA-6TIN (64Mbit/8MB, 4 banks x 4096 rows x 256 cols, 12 address
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pins A0-A11) to Alliance Memory AS4C32M16SB-7BIN (54-ball TFBGA
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package, per the user's own explicit package choice -- the TSOP-II
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sibling AS4C32M16SB-7TIN is the same die/organization/timing and was
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also confirmed real/in-stock, should package choice be reconsidered
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during layout) (512Mbit/64MB, 4 banks
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x 8192 rows x 1024 cols, 13 address pins A0-A12 -- one new pin,
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sdram_a[12], real ball F1/bank6, added to v2_board_top.lpf). This
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followed a real, from-datasheet investigation of the whole Alliance
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Memory SDR SDRAM family (AS4C4M16SA/AS4C8M16SA/AS4C16M16SA/
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AS4C32M16SA, all confirmed same package/pinout family via their own
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real datasheets) at the user's own explicit request, after establishing
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that 8MB was not a hard capacity ceiling for this accelerator's actual
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compute throughput (D-Stress: 32,768 weights takes 49,771 cycles/
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777us at 64MHz -- a 24MB weight budget at the same rate would take
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~580ms/inference, already compute-bound long before memory-bound).
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"SA" vs "SB" in the part number is a die-shrink revision (Alliance's
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own standard practice, confirmed via their own datasheet revision
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history), NOT a functional/pinout difference -- "SB" is the currently
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orderable die at real distributors (DigiKey: 568 units in stock,
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$31.12/unit for the frozen BGA package as of this session; "SA" did
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not surface as a current distributor listing for this exact
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package/temp-grade combination).
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Real -7-grade AC timing (144MHz max, `far above our 64MHz target):
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tRCD=15ns, tRP=15ns (both BETTER than the previous part's 18ns), tRAS=
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45ns/100000ns, tRC=65ns, tMRD=2 CLK (fixed, explicit units, no
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ambiguity), tREFI=7.8125us (HALF the previous part's 15.625us, since
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8192 rows must refresh in the same 64ms window).
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This REQUIRED a real SPI protocol change (spi_host_bridge.v): the
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26-bit byte address (up from 23 bits) no longer fits in 3 bytes (24
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bits) with a spare reserved bit -- every address field (x_base/w_base/
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result_addr in WRITE_JOB, addr in WRITE_MEM/READ_MEM) widened from 3
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to 4 bytes. WRITE_JOB grew from 15 to 18 payload bytes; the WRITE_MEM/
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READ_MEM header grew from 5 to 6 bytes.
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This ALSO exposed two real, pre-existing timing-scaling issues, found
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via real nextpnr-ecp5 P&R re-verification (not assumed): see errors.log
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ERR-0027 (neural_director.v's own runtime-indexed demux write, fixed,
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N_SLOTS=4 now fully reliable at 64MHz across all 8 tested seeds) and
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ERR-0028 (nms_activation_fill_ctrl_v3.v's own linear N_SLOTS-wide max
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scan, fixed, N_SLOTS=8 significantly improved but not yet fully
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reliable -- 5/8 seeds close timing at 64MHz).
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Full regression re-verified against BOTH the memory upgrade and both
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RTL fixes with zero functional regression: sdram_controller (461/461,
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18 configs), tb_sdram_boundary (21/21, real+cross-checked 64/166MHz),
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D-Stress N=2/N=4/N=8 (bit-exact, identical cycle counts to the
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pre-upgrade baseline), tb_spi_host_bridge (18/18), board-level SPI
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smoke test (11/11, real 64MHz clk_sys), tb_sdram_unified_backend
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(40/40).
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STATUS: Memory upgrade CLOSED and verified. N_SLOTS=4 clock closure
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CLOSED (64MHz, all seeds). N_SLOTS=8 clock closure OPEN (64MHz, 5/8
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seeds) -- a real, disclosed, not-yet-fully-resolved finding, not
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silently claimed complete. 80MHz (the user's own stretch preference)
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is NOT achievable with the current architecture at either N_SLOTS
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value -- confirmed via a real 80MHz-targeted PLL regeneration and
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P&R re-run, all seeds failing -- consistent with this project's own
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prior documented conclusion (ecp5_pll_sys_clk.v's own header: "64MHz
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was chosen... the highest frequency at which ALL measured seeds close
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timing with real margin").
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@@ -1288,3 +1288,90 @@ VERIFICATION (all via Verilator, the trusted tool per DEC-0004):
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- tb_fpga_neural_v2_top_smoke.v: 11/11 PASS, unaffected.
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STATUS: RESOLVED. Files changed: hardware/v2/nms/rtl/sdram_
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controller.v (single localparam, plus explanatory comment).
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ERR-0027 -- neural_director.v: runtime-indexed demux write regressed
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timing after the ADDR_WIDTH memory-upgrade widening
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DATE: 2026-09-07
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FOUND DURING: memory-capacity upgrade investigation (AS4C4M16SA-6TIN
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8MB -> AS4C32M16SA/SB-7TIN 64MB), real nextpnr-ecp5 P&R re-verification
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after ADDR_WIDTH grew from 23 to 26 bits.
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ROOT CAUSE: neural_director.v's own per-slot job dispatch
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(`slot_x_base[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= ...`, and the
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same pattern for w_base/n_tiles/result_addr/node_id) writes into a wide
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PACKED output register using a RUNTIME-COMPUTED bit-select index
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(`free_slot_idx*ADDR_WIDTH`). Yosys/synth_ecp5 synthesized this
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multiply-by-a-non-power-of-two-constant as an actual MULT18X18D hard
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multiplier feeding a wide demux/crossbar into the destination slot.
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This was already present before the memory upgrade (confirmed: N=4
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synthesis before the fix showed 33 MULT18X18D, one more than the
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expected 32 = 4 processors x 8-wide MAC), but its contribution to the
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critical path grew directly with ADDR_WIDTH (more bits through the
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demux) and became DOMINANT once ADDR_WIDTH grew from 23 to 26: real
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nextpnr-ecp5 P&R showed worst-seed Fmax collapsing from the previously-
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verified 68.51MHz (ADDR_WIDTH=23, PRE_PCB_VERIFICATION.md section 5)
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to 40.27MHz (ADDR_WIDTH=26), FAILING the 64MHz target across all 8
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seeds tested.
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FIX: replaced the wide packed `output reg` + runtime-indexed write with
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N_SLOTS unpacked per-slot registers (`slot_x_base_r[0:N_SLOTS-1]` etc.)
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written via N_SLOTS parallel CONSTANT-indexed compares
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(`fi==free_slot_idx`, cheap, no multiply), wired out to the SAME packed
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external ports via a generate block using constant genvar indices
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(zero-cost wiring, resolved at elaboration). External port widths/
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semantics are UNCHANGED -- bit-exact same behavior, confirmed by
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re-running the full N=2/4/8 D-Stress regression (identical cycle
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counts: 49961/49927/49909, matching the pre-fix baseline exactly).
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VERIFICATION: real Yosys synthesis confirmed the spurious 33rd
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MULT18X18D is gone (32 for N=4, 64 for N=8, exactly 8 per processor).
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Real nextpnr-ecp5 P&R, N=4, 8 seeds: ALL PASS at 64MHz (65.02-72.01MHz,
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mean ~68.8MHz) -- back to approximately the pre-upgrade baseline range.
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STATUS: RESOLVED for N=4. File changed: hardware/v2/rtl/neural_director.v.
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ERR-0028 -- nms_activation_fill_ctrl_v3.v: linear N_SLOTS-wide max-scan
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became the dominant critical path at N_SLOTS=8
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DATE: 2026-09-07
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FOUND DURING: same investigation as ERR-0027, after fixing ERR-0027 and
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re-running P&R at N_SLOTS=8 (the user's own preferred processor count):
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real nextpnr-ecp5 P&R showed Fmax collapsing to ~38-40MHz across 4
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seeds, FAILING 64MHz, with the critical path now routing through
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nms_activation_fill_ctrl_v3.v's own `max_n_tiles_comb` computation --
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a flat, sequential N_SLOTS-wide scan (`for (j=0;j<N_SLOTS;j=j+1) if
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(n_tiles_masked[j] > max_n_tiles_comb) max_n_tiles_comb =
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n_tiles_masked[j];`), already flagged as "an N_SLOTS-wide sequential
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chain" by this file's OWN prior header comment -- a pre-existing,
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known characteristic (not newly introduced), but one whose carry-chain
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critical path scales linearly with N_SLOTS and became dominant at
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N_SLOTS=8 (twice the comparison depth of N_SLOTS=4, where it was not
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the bottleneck).
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FIX: replaced the flat scan with an explicit, hand-written balanced
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binary max-tree (log2(N_SLOTS) comparison levels instead of N_SLOTS),
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using distinctly-named per-level wires (NOT a multi-dimensional
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generate-indexed array -- a first attempt using a shared 2D array
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triggered a real simulator UNOPTFLAT "circular combinational logic"
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false-positive, since that tool's array-flattening circularity check
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could not prove the (acyclic) per-level dependency safe for a shared
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array). Explicit cases for N_SLOTS=1/2/4/8 (the only real
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configurations this project uses), with a safe (unoptimized) fallback
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for any other value. SAME single-cycle latency as the scan it replaces
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(max_n_tiles_reg is still registered exactly one cycle behind
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n_tiles_masked) -- no FSM timing change, purely a combinational-depth
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reduction. Confirmed bit-exact via the same N=2/4/8 D-Stress regression
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re-run (identical cycle counts, zero regression).
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VERIFICATION: real nextpnr-ecp5 P&R, N=8, 8 seeds: 5/8 PASS at 64MHz
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(65.27-70.78MHz), 3/8 FAIL narrowly (55.84/61.00/63.42MHz) -- a large
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improvement over the pre-fix ~38-40MHz, but NOT yet fully reliable
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across every placement seed at N_SLOTS=8 (unlike N_SLOTS=4, which
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passes all 8 tested seeds). The remaining bottleneck (confirmed via a
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fresh critical-path trace on a failing seed) is sdram_unified_backend.
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v's own weight-cache hit-index scan -- the SAME pre-existing critical-
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path class already documented in PRE_PCB_VERIFICATION.md section 5
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("alternates... between dependency_manager.v's own priority-encoder
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scan and sdram_unified_backend.v's own weight-cache hit-index logic"),
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not a new defect, but not further optimized this session (time/scope
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boundary -- a similar tree-based fix is the clear next step, not
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attempted here to avoid rushing an unverified third change).
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STATUS: PARTIALLY RESOLVED. N_SLOTS=4 fully reliable at 64MHz (8/8
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seeds). N_SLOTS=8 significantly improved but OPEN -- 5/8 seeds close
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timing at 64MHz, 3/8 do not. File changed: hardware/v2/nms/rtl/
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nms_activation_fill_ctrl_v3.v.
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