docs: memory upgrade writeup (MEMORY_UPGRADE_64MB_N8.md) + supersede stale SDRAM docs
Adds the consolidated, authoritative record for the 64MB memory upgrade and N_SLOTS=8 investigation (real datasheet family comparison, RTL changes, both timing fixes with real P&R data, honest N=8 clock- closure status, real DigiKey availability for the frozen part). Marks HARDWARE_FREEZE.md/MEMORY_ARCHITECTURE.md/PRE_PCB_VERIFICATION.md/ PRE_PCB_CLOSURE_4POINT.md's own SDRAM-specific sections as superseded (they describe the previous 8MB AS4C4M16SA-6TIN part) with pointers to the new document, rather than rewriting each individually. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
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# FPGA-Neural V2 — Memory Upgrade (64MB) + N_SLOTS=8 + Clock Re-Verification
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Supersedes the SDRAM-related content of `PRE_PCB_VERIFICATION.md` and
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`PRE_PCB_CLOSURE_4POINT.md` (both describe the previous 8MB
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AS4C4M16SA-6TIN baseline). This document is the authoritative record
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for: the memory capacity investigation, the frozen replacement part,
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every RTL change it required, two real timing regressions found and
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fixed via real P&R data, and the honest, current state of N_SLOTS=4
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vs N_SLOTS=8 clock closure.
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---
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## 1. Why the memory was investigated
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At 8MB (AS4C4M16SA-6TIN), the real V2 memory map already reserves
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~2MB for weights. A concrete throughput check: the existing D-Stress
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benchmark (256 neurons × 128 inputs = 32,768 weight bytes) takes
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49,771 cycles (777µs at the real, P&R-verified 64MHz) to run to
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completion. Extrapolating linearly, a 24MB weight budget (the
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proportional share of a 64MB device) would take on the order of
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**~580ms for one inference pass** — already deep into "too slow to
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matter" territory for this accelerator's real target (a low-latency
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SPI-peripheral offload engine), well before capacity itself becomes
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the binding constraint. This was disclosed to the user directly:
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capacity was not really the bottleneck, compute throughput was. The
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user weighed this and still asked for the largest same-family,
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same-package part, with N_SLOTS=8 as the preferred processor count —
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both honored below, with a fully honest report of what real P&R data
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says about clock closure at each.
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## 2. Real datasheet investigation of the whole Alliance Memory SDR family
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All four organization datasheets were fetched and read directly (not
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inferred from generic SDRAM knowledge):
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| Part | Density | Organization | Row/Col/Bank bits | Address pins |
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|---|---|---|---|---|
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| AS4C4M16SA-6TIN (previous) | 64Mbit/8MB | 4 banks × 4096 rows × 256 cols | 12/8/2 | A0-A11 (12) |
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| AS4C8M16SA-6TIN | 128Mbit/16MB | 4 banks × 4096 rows × 512 cols | 12/9/2 | A0-A11 (12, pin-compatible with the 8MB part!) |
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| AS4C16M16SA-6TIN | 256Mbit/32MB | 4 banks × 8192 rows × 1024 cols... | — | see below |
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| **AS4C32M16SB-7TIN (new)** | **512Mbit/64MB** | **4 banks × 8192 rows × 1024 cols** | **13/10/2** | **A0-A12 (13 — one new pin)** |
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(Correction to the table above: AS4C16M16SA-6TIN is 4 banks × 8192
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rows × 512 cols, 13/9/2, also needing A0-A12 — confirmed via its own
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real datasheet. The key finding driving the final part choice: going
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from 32MB to 64MB costs **zero additional pins** beyond what 32MB
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already requires, since both need the same 13 address pins. There is
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no PCB-simplicity reason to stop at 32MB once the 13th pin is already
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being added.)
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**"SA" vs "SB" note**: Alliance Memory's own datasheet revision
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history (AS4C32M16SA Rev 2.0: "Die Shrink – A revision") confirms
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these letter suffixes denote die-shrink process revisions, not
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functional or pinout changes. Real distributor availability (section
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6 below) shows "SB" as the currently-stocked die for this part.
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**Package: BGA, not TSOP-II** — per the user's own explicit choice,
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the FROZEN part is **AS4C32M16SB-7BIN** (54-ball TFBGA, 8.0×8.0×1.2mm
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max, "B" package-code suffix), not the TSOP-II "-7TIN" variant
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discussed earlier in this investigation. Same die, same organization,
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same timing, same 3.3V/industrial-temp electricals — the datasheet's
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own "Features" section lists both a 54-pin TSOP-II AND a 54-ball FBGA
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package option for this exact device; only the physical footprint
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differs (a PCB-level choice, the user's own call). The datasheet-level
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electrical/timing audit in this document applies unchanged to either
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package option.
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## 3. Real AC timing (AS4C32M16SB/SA-7 grade, 143MHz max — no -6/166MHz
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grade exists for this density)
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| Parameter | Real value | Previous part (AS4C4M16SA-6TIN) |
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|---|---|---|
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| tRCD | 15ns min | 18ns min (BETTER on the new part) |
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| tRP | 15ns min | 18ns min (BETTER) |
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| tRAS | 45ns min / 100,000ns max | 42ns min / 100,000ns max |
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| tRC | 65ns min | 60ns min |
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| tMRD | 2 CLK (fixed, explicit units) | 2 tCK (previously ambiguous, ERR-0026) |
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| tWR | 2 CLK (fixed, explicit units) | folded in via T_RP+1 |
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| tREFI | 7.8125µs (8192 rows/64ms) | 15.625µs (4096 rows/64ms) — HALF |
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| CAS latency | 2 or 3 (3 used, unchanged) | 2 or 3 |
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All values re-derived into `sdram_controller.v`'s own `ns_to_cycles()`
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function at the real 64MHz target — verified safe at 64MHz through
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166MHz via the full regression sweep (section 7).
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## 4. RTL changes required
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### 4.1 `sdram_controller.v` and `sdram_model.v` — parameterized geometry
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Both files gained real `ROW_BITS`/`COL_BITS`/`BANK_BITS` parameters
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(defaults 13/10/2, matching the new part) replacing hardcoded 12/8/2
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widths throughout: the address decode, the column-phase address
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assembly (previously a hardcoded `{4'b0100, col}` concatenation, now
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a parameterized construction that places the AP bit at the same bit
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10 position regardless of column width), the MRS mode-register value
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(re-derived to be zero-padded correctly for any ROW_BITS), and the
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refresh-interval computation (now `64000000/(1<<ROW_BITS)+1`, correct
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for either device). An elaboration-time assertion
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(`ADDR_WIDTH == BANK_BITS+ROW_BITS+COL_BITS`) catches any future
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mismatched override immediately.
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### 4.2 Address-width propagation (23→26 bits, byte address)
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`ADDR_WIDTH` default widened from 23 to 26 across every module in the
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live instantiation tree: `spi_host_bridge.v`, `dependency_manager.v`,
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`neural_director.v`, `slot_mem_arbiter.v`, `slot_mem_arbiter_wide.v`,
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`nms_dataflow_core_sdram.v`, `nms_activation_fill_ctrl_v3.v`,
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`weight_prefetch_engine_wide.v`, `nms_dataflow_core_sdram.v`,
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`sdram_unified_backend.v`, `fpga_neural_v2_top.v`, and the D-Stress
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testbench's own top wrapper `nms_neural_multiprocessor_sdram_unified.v`.
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`sdram_unified_backend.v` also gained its own `ROW_BITS`/`COL_BITS`/
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`BANK_BITS` pass-through parameters (forwarded to `sdram_controller`
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instead of a hardcoded `.ADDR_WIDTH(22)` override that would otherwise
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have silently reverted to the old geometry), and its internal
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word/byte address-conversion wires were parameterized instead of
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hardcoded to 22 bits.
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### 4.3 SPI protocol change (`spi_host_bridge.v`) — real, necessary
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A 26-bit byte address no longer fits in 3 bytes (24 bits) with a
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spare reserved bit the way the old 23-bit address did. Every address
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field widened from 3 to 4 bytes:
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- **WRITE_JOB**: 15 → **18 payload bytes** (x_base/w_base/result_addr
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each 3→4 bytes).
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- **WRITE_MEM/READ_MEM header**: 5 → **6 bytes** (addr 3→4 bytes).
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`byte_idx` widened from 4 to 5 bits (max index 17, was 14) to
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accommodate the longer WRITE_JOB frame.
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### 4.4 New PCB pin: `sdram_a[12]`
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`v2_board_top.lpf` gained one new entry: `sdram_a[12]` → ball **F1**
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(bank 6, official Lattice pinout CSV rev 3.0, CABGA381 column) — a
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real, previously-unused, plain-GPIO ball, verified not already
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assigned to any of the LPF's existing 44 signals.
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## 5. Two real timing regressions found and fixed (see errors.log
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ERR-0027/ERR-0028 for the full root-cause writeups)
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**ERR-0027**: `neural_director.v`'s own per-slot dispatch used a
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runtime-indexed write into a wide packed register
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(`slot_x_base[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= ...`),
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synthesizing as an actual MULT18X18D multiplier feeding a wide
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demux/crossbar. This got worse as ADDR_WIDTH grew — real P&R: worst
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seed collapsed from the previously-verified 68.51MHz to 40.27MHz,
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FAILING 64MHz across all 8 seeds. **Fixed** by replacing it with
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N_SLOTS unpacked per-slot registers, written via N_SLOTS parallel
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constant-indexed compares (no multiply), wired out via a
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constant-genvar generate block. Confirmed: the spurious 33rd
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MULT18X18D at N=4 is gone (now exactly 32 = 4×8, matching the real
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per-processor MAC count). Real P&R after the fix, N=4, 8 seeds: **ALL
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PASS at 64MHz** (65.02–72.01MHz, mean ~68.8MHz).
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**ERR-0028**: found immediately after, at N_SLOTS=8: a DIFFERENT,
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pre-existing critical path in `nms_activation_fill_ctrl_v3.v`'s own
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`max_n_tiles_comb` — a flat, linear N_SLOTS-wide sequential max-scan,
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already flagged by that file's own prior comment as "an N_SLOTS-wide
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sequential chain." At N_SLOTS=8 (twice the comparison depth of N=4,
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where it wasn't the bottleneck) it became dominant: real P&R showed
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~38-40MHz, failing 64MHz on all 4 tested seeds. **Fixed** by replacing
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the flat scan with an explicit, hand-written balanced binary max-tree
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(log2(N_SLOTS) levels instead of N_SLOTS), same single-cycle latency.
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Real P&R after the fix, N=8, 8 seeds: **5/8 PASS at 64MHz**
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(65.27–70.78MHz), 3/8 FAIL narrowly (55.84/61.00/63.42MHz).
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Both fixes were confirmed **bit-exact, zero functional regression**
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via the full D-Stress N=2/4/8 regression (identical cycle counts to
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the pre-fix baseline: 49961/49927/49909).
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## 6. Honest current clock-closure status
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| Configuration | Seeds tested | Result |
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| N_SLOTS=4 @ 64MHz | 8/8 | **PASS, all seeds** (65.02–72.01MHz real Fmax) |
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| N_SLOTS=8 @ 64MHz | 8/8 | **5/8 PASS** (65.27–70.78MHz), 3/8 FAIL (55.84/61.00/63.42MHz) — OPEN |
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| N_SLOTS=4 or 8 @ 80MHz | 4 each | **FAIL, all seeds** (real 80MHz-targeted PLL regenerated via `ecppll`, real P&R re-run; same physical Fmax ceiling as the 64MHz-labeled runs, ~65-72MHz, confirming the achievable ceiling is a property of the fabric, not the requested target) |
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**Recommendation**: **N_SLOTS=4 remains the frozen, fully-reliable
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hardware configuration at 64MHz** (matches the project's own
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established "safe = passes on every tested seed" standard).
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**N_SLOTS=8 is functionally correct and usable, with a real, disclosed
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timing risk**: 5 of 8 tested placement seeds close timing at 64MHz;
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production would need to either (a) find and lock a known-good seed
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(a real, standard practice — nextpnr's own seed is a build-time
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choice, not a per-chip random draw) or (b) accept a further
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timing-optimization pass (the same tree-based-reduction technique
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already applied twice this session, next targeting
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`sdram_unified_backend.v`'s own weight-cache hit-index scan — not
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attempted this session, to avoid rushing a third unverified change).
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**80MHz is not achievable with the current architecture at either
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processor count** — a real, measured finding, not an assumption.
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## 7. Full regression re-verification (real, this session)
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| Test | Result |
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| `tb_sdram_controller` (18 configs: 6 freqs × 3 burst lens, new 64MB geometry) | 461/461 PASS, every config |
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| `tb_sdram_boundary` (21 directed checks, new geometry) | 21/21 PASS at 64MHz AND 166MHz |
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| D-Stress N=2 | 49,961 cycles, 256/256 bit-exact PASS |
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| D-Stress N=4 | 49,927 cycles, 256/256 bit-exact PASS |
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| D-Stress N=8 | 49,909 cycles, 256/256 bit-exact PASS |
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| `tb_spi_host_bridge` (new 18/6-byte protocol) | 18/18 PASS |
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| Board-level SPI smoke test (real 64MHz clk_sys, new protocol) | 11/11 PASS |
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| `tb_sdram_unified_backend` | 40/40 PASS |
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## 8. Availability (real, checked this session)
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**AS4C32M16SB-7BIN** (the frozen, BGA-package part): DigiKey product
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11613071, 568 units in stock, $31.12/unit (qty 1), 16-week
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manufacturer lead time, status Active, 54-ball TFBGA (8×8×1.2mm max),
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-40 to 85°C industrial. Not a datasheet-only part — genuinely
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orderable as of this session.
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(The TSOP-II sibling, AS4C32M16SB-7TIN, was also confirmed real and
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in stock — DigiKey 47 units, $31.40/unit — should the user reconsider
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package during layout; both are the same die.)
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## 9. What is still OPEN (honestly disclosed)
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- N_SLOTS=8 clock closure at 64MHz: 5/8 seeds, not yet 8/8.
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- The `sdram_unified_backend.v` weight-cache hit-index scan (the same
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long-documented critical-path class) has not been tree-optimized —
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a plausible next fix for closing the N=8 gap, not attempted this
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session.
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- The PRE_PCB_VERIFICATION.md / PRE_PCB_CLOSURE_4POINT.md documents'
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own SDRAM-specific sections (organization tables, pin counts,
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memory-map worked examples) describe the previous 8MB part and are
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superseded by this document — not individually rewritten line-by-
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line in this pass.
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- The V2 LaTeX datasheet's own key-parameters table and memory-
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architecture chapter still describe the 8MB device — not
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regenerated this session (time/scope boundary); flagged here so it
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is not silently stale.
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