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docs: memory upgrade writeup (MEMORY_UPGRADE_64MB_N8.md) + supersede stale SDRAM docs

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Adds the consolidated, authoritative record for the 64MB memory
upgrade and N_SLOTS=8 investigation (real datasheet family comparison,
RTL changes, both timing fixes with real P&R data, honest N=8 clock-
closure status, real DigiKey availability for the frozen part).

Marks HARDWARE_FREEZE.md/MEMORY_ARCHITECTURE.md/PRE_PCB_VERIFICATION.md/
PRE_PCB_CLOSURE_4POINT.md's own SDRAM-specific sections as superseded
(they describe the previous 8MB AS4C4M16SA-6TIN part) with pointers to
the new document, rather than rewriting each individually.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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michele
2026-09-07 00:21:05 +02:00
co-authored by Claude Sonnet 5
parent 8d83d97bde
commit a20f1ecd73
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hardware/v2/docs/MEMORY_ARCHITECTURE.md
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# FPGA-Neural V2 — MEMORY ARCHITECTURE (single SDRAM)
**PART NUMBER SUPERSEDED (DEC-0039).** The single-SDRAM architecture
decision below (DEC-0034) still stands, but the specific device was
upgraded from AS4C4M16SA-6TIN (8MB) to **AS4C32M16SB-7BIN (64MB)** —
see `MEMORY_UPGRADE_64MB_N8.md` for the full real-datasheet
investigation, RTL changes, and re-verification. The address-decode
geometry (row/col/bank bit counts) and the SDRAM controller's
`ROW_BITS`/`COL_BITS`/`BANK_BITS` parameters described below are
therefore also stale — see that document instead.
## Decision (DEC-0034)
**ONE external memory device: Alliance Memory AS4C4M16SA-6TIN SDR