feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084)
Real 32-bit DDR3 widening (2x MT41J128M16JT-125:K chips ganged in parallel, user's own MIG wizard session). Full RTL adaptation across the shared ctrl bus (16-bit word -> 32-bit word, BURST_LEN=8 unchanged, burst payload 128->256 bits): - mig_native_adapter.v: app_wdf_data/app_rd_data 64->128 bits (real, confirmed against the regenerated MIG wrapper), beat count unchanged. - act_tile_fetch.v: real logic change - burst now holds 4 tiles instead of 2 (sel_lat extended to 2 registered bits, 4-way case mux instead of 2-way ternary, same request-time-registered-select discipline as EXP-0081). Not a further bytes/MAC reduction, just what's needed to keep 100% packing utilization at the larger burst. - host_mem_bridge.v: real addressing redesign - host-facing 16-bit-word contract kept unchanged (ESP32 firmware unaffected), internally translated onto the new 32-bit-native ctrl bus. - sdram_arbiter_n.v, layer_prefetch_ctrl.v, packed_slot.v, ddr_prefetch_mgr.v, n2_system_ddr3_top.v: mechanical width bump plus doubled ddr3_dq/dqs/dm pins and the real differential sys_clk/clk_ref top-level ports the regenerated MIG now requires. New burst_mem_model32.v: explicitly synthetic 32-bit test-only burst memory (the real 16-bit SDR model is genuinely fixed-width, shared by 20+ other tests, correctly not touched). Found and fixed a real address-aliasing bug in it during bring-up (MEM_ADDR_BITS=16 silently wrapped a real 0x10000 test address to 0). Real verification: all isolated testbenches re-verified (10/10, 33/33, 32/32, 7/7, 9/9 PASS), plus real xsim against the real 2-chip DDR3 model (tb_mig_native_adapter.v 12/12 PASS, tb_n2_system_ddr3.v 8/8 PASS, both chips visibly returning different real data). Real P&R: 5 real bugs found and fixed across iterations (stale single-ended MIG clock ports, a real VCCO conflict between the flash SPI bus and the differential reference clock in bank 14 - fixed by moving flash to bank 16, a stale imported XDC - same bug class as EXP-0078 but for constraints this time, missing IOSTANDARDs, and two previously-silently-broken XDC property bugs). Route completes 100%, but real timing does NOT close: WNS -0.618ns, 213 failing endpoints. Honest root cause: the violation is inside neural_processor_packed.v's own packed-MAC accumulation tree, unchanged since EXP-0059 - it has real margin at the old 155.039MHz ui_clk but not at the new 172.414MHz the paired clock-period change produced. This is NOT caused by the 32-bit width change itself. Width alone, even at the old clock, already delivers the full intended 2x bandwidth gain (1.24 -> ~2.48 GB/s) - width and clock rate are separable levers. Current trustworthy timing signoff remains EXP-0083 (16-bit, +0.073ns) until the clock period is reverted toward 3225ps (keeping Data Width=32) in one more real, user-gated MIG wizard session. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
Claude Sonnet 5
@@ -4,26 +4,31 @@
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// Isolated correctness test for host_mem_bridge.v: the word<->burst
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// translator that closes the "no host raw-memory-access path" gap
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// found re-auditing spi_host_bridge.v against V3 (EXP-0068's audit).
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// Uses the cheap SDR SDRAM placeholder backend (sdram_controller.v +
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// sdram_model.v), same precedent as tb_sdram_arbiter_n.v: verify new
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// glue logic against the fast backend first, real DDR3 integration
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// is a separate, later step once this is trusted standalone.
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//
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// Checks: (a) single-word write only touches its OWN word inside the
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// burst (byte masking correctness, lb_n/ub_n both individually and
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// together) without corrupting neighboring words in the same burst;
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// (b) single-word read extracts the correct word regardless of its
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// offset within the burst (all BURST_LEN=8 offsets exercised);
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// (c) mem_ready pulses exactly once per transaction.
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// EXP-0084: re-run against the new 32-bit ctrl bus / burst_mem_
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// model32.v backend (real DDR3 channel widening -- was 16-bit-word-
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// native before, now 32-bit-word-native, see host_mem_bridge.v's own
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// header for the real addressing redesign this required: mem_addr
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// stays a 16-bit-word address for the host's own unchanged protocol,
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// but now mem_addr[0] additionally selects which half of the
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// underlying 32-bit ctrl-bus word to target). One burst now spans
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// 2*BURST_LEN=16 host-side 16-bit-word offsets (was BURST_LEN=8) --
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// this test now exercises all 16, not just 8, to cover the new
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// half-select logic across the WHOLE burst, not half of it.
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//
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// Checks: (a) single-word write only touches its OWN half-word inside
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// the burst (byte masking correctness, lb_n/ub_n both individually and
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// together) without corrupting neighboring half-words in the same
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// burst; (b) single-word read extracts the correct half-word
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// regardless of its offset within the burst (all 16 offsets
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// exercised); (c) mem_ready pulses exactly once per transaction.
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// ============================================================
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module tb;
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localparam BURST_LEN = 8;
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localparam ROW_BITS = 13;
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localparam COL_BITS = 10;
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localparam BANK_BITS = 2;
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localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
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localparam ADDR_WIDTH = 25;
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localparam CLK_FREQ_MHZ = 64;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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localparam BURST_SPAN = 2*BURST_LEN; // 16-bit-word positions per burst, host-side addressing
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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@@ -31,30 +36,16 @@ module tb;
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wire ctrl_req, ctrl_wr;
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wire [ADDR_WIDTH-1:0] ctrl_addr;
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wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
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wire [2*BURST_LEN-1:0] ctrl_wmask;
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wire [32*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
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wire [4*BURST_LEN-1:0] ctrl_wmask;
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wire ctrl_ready, ctrl_busy;
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wire cke, cs_n, ras_n, cas_n, we_n;
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wire [BANK_BITS-1:0] ba;
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wire [ROW_BITS-1:0] a;
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wire [15:0] dq;
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wire [1:0] dqm;
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sdram_controller #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_ctrl (
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burst_mem_model32 #(
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.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
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) u_mem (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
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.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
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);
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sdram_model #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_mem (
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.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
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.ba(ba), .a(a), .dq(dq), .dqm(dqm)
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy)
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);
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// single requester -> arbiter isn't even needed for an isolated
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@@ -112,7 +103,7 @@ module tb;
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reg [15:0] got;
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integer i;
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localparam [ADDR_WIDTH-1:0] BASE = 25'd200; // burst-aligned base (200 % 8 == 0)
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localparam [ADDR_WIDTH-1:0] BASE = 25'd256; // burst-aligned base (256 % 16 == 0)
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initial begin
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errors = 0; tests = 0;
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@@ -121,11 +112,11 @@ module tb;
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rst = 0;
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@(posedge clk);
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$display("=== TEST 1: write+read every word offset within one burst, verify no cross-word corruption ===");
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for (i = 0; i < BURST_LEN; i = i + 1) begin
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$display("=== TEST 1: write+read every half-word offset within one burst (0..%0d), verify no cross-word corruption ===", BURST_SPAN-1);
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for (i = 0; i < BURST_SPAN; i = i + 1) begin
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host_write(BASE + i[ADDR_WIDTH-1:0], 16'hA000 + i[15:0], 1'b0, 1'b0);
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end
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for (i = 0; i < BURST_LEN; i = i + 1) begin
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for (i = 0; i < BURST_SPAN; i = i + 1) begin
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host_read(BASE + i[ADDR_WIDTH-1:0], got);
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tests = tests + 1;
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if (got !== (16'hA000 + i[15:0])) begin
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@@ -136,9 +127,9 @@ module tb;
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end
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end
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$display("=== TEST 2: re-write word 3 only, confirm neighbors (0,1,2,4..7) untouched ===");
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$display("=== TEST 2: re-write offset 3 only, confirm neighbors (0..%0d except 3) untouched ===", BURST_SPAN-1);
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host_write(BASE + 25'd3, 16'hBEEF, 1'b0, 1'b0);
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for (i = 0; i < BURST_LEN; i = i + 1) begin
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for (i = 0; i < BURST_SPAN; i = i + 1) begin
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host_read(BASE + i[ADDR_WIDTH-1:0], got);
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tests = tests + 1;
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if (i == 3) begin
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