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feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084)

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Real 32-bit DDR3 widening (2x MT41J128M16JT-125:K chips ganged in
parallel, user's own MIG wizard session). Full RTL adaptation across
the shared ctrl bus (16-bit word -> 32-bit word, BURST_LEN=8 unchanged,
burst payload 128->256 bits):

- mig_native_adapter.v: app_wdf_data/app_rd_data 64->128 bits (real,
  confirmed against the regenerated MIG wrapper), beat count unchanged.
- act_tile_fetch.v: real logic change - burst now holds 4 tiles instead
  of 2 (sel_lat extended to 2 registered bits, 4-way case mux instead
  of 2-way ternary, same request-time-registered-select discipline as
  EXP-0081). Not a further bytes/MAC reduction, just what's needed to
  keep 100% packing utilization at the larger burst.
- host_mem_bridge.v: real addressing redesign - host-facing 16-bit-word
  contract kept unchanged (ESP32 firmware unaffected), internally
  translated onto the new 32-bit-native ctrl bus.
- sdram_arbiter_n.v, layer_prefetch_ctrl.v, packed_slot.v,
  ddr_prefetch_mgr.v, n2_system_ddr3_top.v: mechanical width bump plus
  doubled ddr3_dq/dqs/dm pins and the real differential sys_clk/clk_ref
  top-level ports the regenerated MIG now requires.

New burst_mem_model32.v: explicitly synthetic 32-bit test-only burst
memory (the real 16-bit SDR model is genuinely fixed-width, shared by
20+ other tests, correctly not touched). Found and fixed a real
address-aliasing bug in it during bring-up (MEM_ADDR_BITS=16 silently
wrapped a real 0x10000 test address to 0).

Real verification: all isolated testbenches re-verified (10/10, 33/33,
32/32, 7/7, 9/9 PASS), plus real xsim against the real 2-chip DDR3
model (tb_mig_native_adapter.v 12/12 PASS, tb_n2_system_ddr3.v 8/8
PASS, both chips visibly returning different real data).

Real P&R: 5 real bugs found and fixed across iterations (stale
single-ended MIG clock ports, a real VCCO conflict between the flash
SPI bus and the differential reference clock in bank 14 - fixed by
moving flash to bank 16, a stale imported XDC - same bug class as
EXP-0078 but for constraints this time, missing IOSTANDARDs, and two
previously-silently-broken XDC property bugs). Route completes 100%,
but real timing does NOT close: WNS -0.618ns, 213 failing endpoints.

Honest root cause: the violation is inside neural_processor_packed.v's
own packed-MAC accumulation tree, unchanged since EXP-0059 - it has
real margin at the old 155.039MHz ui_clk but not at the new 172.414MHz
the paired clock-period change produced. This is NOT caused by the
32-bit width change itself. Width alone, even at the old clock, already
delivers the full intended 2x bandwidth gain (1.24 -> ~2.48 GB/s) -
width and clock rate are separable levers. Current trustworthy timing
signoff remains EXP-0083 (16-bit, +0.073ns) until the clock period is
reverted toward 3225ps (keeping Data Width=32) in one more real,
user-gated MIG wizard session.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-20 16:28:44 +02:00
co-authored by Claude Sonnet 5
parent 376ccb6ee2
commit 9dead54ebf
21 changed files with 1302 additions and 754 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v3/sim/tb_ddr_prefetch_mgr.v
+51 -125
View File
@@ -1,40 +1,33 @@
`timescale 1ns/1ps
// ============================================================
// EXP-0083: (1) isolated correctness test for ddr_prefetch_mgr.v --
// same real SDR SDRAM placeholder backend precedent as
// tb_act_tile_fetch.v -- and (2) a real, measured, honest A/B cycle-
// count comparison against the OLD per-tile req/wait/consume loop
// packed_slot.v used before EXP-0083, to get a REAL number for the
// look-ahead prefetch's benefit instead of asserting one.
// EXP-0084: re-run of the EXP-0083 ddr_prefetch_mgr.v isolated
// correctness + A/B cycle-count test against the new 32-bit ctrl bus
// (real DDR3 channel widening). Backend switched to burst_mem_
// model32.v (see its own header -- explicitly synthetic, fixed
// latency, not claiming real DDR3 row/bank AC timing) since the real
// AS4C32M16SA x16 SDR model this test used before is genuinely fixed
// at 16-bit and can't represent the new bus width.
//
// Both the "baseline" (direct act_tile_fetch.v, one requester per
// tile, old packed_slot.v sequencing) and the "prefetch" (ddr_
// prefetch_mgr.v, EXP-0083) loops are run against the SAME shared
// backend and the SAME preloaded data, back to back, muxed the same
// way tb_act_tile_fetch.v's own pre_active mux works -- so the
// comparison is apples to apples, not two different simulated
// environments.
//
// Both loops apply the SAME 2-cycle "simulated compute overhead" per
// tile (matching packed_slot.v's own real S_TILEREQ + S_OPERAND
// single-cycle costs) between a tile becoming available and the next
// step being taken -- the honest question this answers is: does
// removing the OLD design's serialization of that overhead with the
// NEXT tile's DDR3 fetch produce a real, measurable improvement, and
// how much.
// EXP-0083's own PART 3 (same-row vs row-switch-heavy A/B, exploiting
// the old SDR model's own real row/bank timing distinction) is
// DROPPED here -- burst_mem_model32.v has a single fixed latency
// regardless of address pattern, so that comparison would no longer
// carry real meaning on this backend. The trustworthy, real number
// for that effect already comes from EXP-0083's own real-DDR3-backend
// measurement (tb_n2_system_ddr3.v, 2.86% real reduction) -- this
// isolated test's own job is correctness + a basic sanity check that
// prefetch is still not slower than the old per-tile loop, not to
// re-derive that headline number.
// ============================================================
module tb;
localparam BURST_LEN = 8;
localparam ROW_BITS = 13;
localparam COL_BITS = 10;
localparam BANK_BITS = 2;
localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS; // 25
localparam ADDR_WIDTH = 25;
localparam CLK_FREQ_MHZ = 64;
localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
localparam DATA_WIDTH = 8;
localparam P_IN = 8;
localparam N_TILES = 6; // 3 burst-pairs/lane -- enough to see steady-state behavior
localparam N_TILES = 8; // 2 bursts/lane at 4 tiles/burst -- enough to see steady-state behavior
reg clk = 0;
always #(CLK_PERIOD_NS/2.0) clk = ~clk;
@@ -42,30 +35,16 @@ module tb;
wire ctrl_req, ctrl_wr;
wire [ADDR_WIDTH-1:0] ctrl_addr;
wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
wire [2*BURST_LEN-1:0] ctrl_wmask;
wire [32*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
wire [4*BURST_LEN-1:0] ctrl_wmask;
wire ctrl_ready, ctrl_busy;
wire cke, cs_n, ras_n, cas_n, we_n;
wire [BANK_BITS-1:0] ba;
wire [ROW_BITS-1:0] a;
wire [15:0] dq;
wire [1:0] dqm;
sdram_controller #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_ctrl (
burst_mem_model32 #(
.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
) u_mem (
.clk(clk), .rst(rst),
.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
);
sdram_model #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_mem (
.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
.ba(ba), .a(a), .dq(dq), .dqm(dqm)
.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy)
);
// ---- 3-way mux on the shared backend: preload / baseline DUT / prefetch DUT ----
@@ -74,7 +53,7 @@ module tb;
reg pre_req, pre_wr;
reg [ADDR_WIDTH-1:0] pre_addr;
reg [16*BURST_LEN-1:0] pre_wdata;
reg [32*BURST_LEN-1:0] pre_wdata;
// ---- baseline DUT: plain act_tile_fetch.v, driven by a per-tile
// req/wait/consume loop replicating OLD packed_slot.v sequencing ----
@@ -86,8 +65,8 @@ module tb;
wire base_mem_active;
wire base_ctrl_req, base_ctrl_wr;
wire [ADDR_WIDTH-1:0] base_ctrl_addr;
wire [16*BURST_LEN-1:0] base_ctrl_wdata;
wire [2*BURST_LEN-1:0] base_ctrl_wmask;
wire [32*BURST_LEN-1:0] base_ctrl_wdata;
wire [4*BURST_LEN-1:0] base_ctrl_wmask;
act_tile_fetch #(
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
@@ -111,8 +90,8 @@ module tb;
wire pf_mem_active;
wire pf_ctrl_req, pf_ctrl_wr;
wire [ADDR_WIDTH-1:0] pf_ctrl_addr;
wire [16*BURST_LEN-1:0] pf_ctrl_wdata;
wire [2*BURST_LEN-1:0] pf_ctrl_wmask;
wire [32*BURST_LEN-1:0] pf_ctrl_wdata;
wire [4*BURST_LEN-1:0] pf_ctrl_wmask;
ddr_prefetch_mgr #(
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
@@ -130,9 +109,9 @@ module tb;
assign ctrl_wr = (sel==SEL_PRELOAD) ? pre_wr : (sel==SEL_BASE) ? base_ctrl_wr : pf_ctrl_wr;
assign ctrl_addr = (sel==SEL_PRELOAD) ? pre_addr : (sel==SEL_BASE) ? base_ctrl_addr : pf_ctrl_addr;
assign ctrl_wdata = (sel==SEL_PRELOAD) ? pre_wdata : (sel==SEL_BASE) ? base_ctrl_wdata : pf_ctrl_wdata;
assign ctrl_wmask = (sel==SEL_BASE) ? base_ctrl_wmask : (sel==SEL_PF) ? pf_ctrl_wmask : {(2*BURST_LEN){1'b0}};
assign ctrl_wmask = (sel==SEL_BASE) ? base_ctrl_wmask : (sel==SEL_PF) ? pf_ctrl_wmask : {(4*BURST_LEN){1'b0}};
task automatic sdram_write_burst(input [ADDR_WIDTH-1:0] word_addr, input [16*BURST_LEN-1:0] data);
task automatic mem_write_burst(input [ADDR_WIDTH-1:0] word_addr, input [32*BURST_LEN-1:0] data);
begin
@(posedge clk); while (ctrl_busy) @(posedge clk);
pre_req = 1'b1; pre_wr = 1'b1; pre_addr = word_addr; pre_wdata = data;
@@ -155,8 +134,8 @@ module tb;
endtask
reg signed [DATA_WIDTH*P_IN-1:0] exp_a, exp_b;
integer k, wi, cyc;
reg [16*BURST_LEN-1:0] burst;
integer k, wi, qi;
reg [32*BURST_LEN-1:0] burst;
integer t_start, t_end, base_cycles, pf_cycles;
initial begin
@@ -169,24 +148,22 @@ module tb;
rst = 0;
@(posedge clk); while (ctrl_busy) @(posedge clk);
$display("=== preload lane A base=0, lane B base=200, %0d tiles (EXP-0081 2-tiles/burst layout) ===", N_TILES);
for (wi = 0; wi < N_TILES/2; wi = wi + 1) begin
for (k = 0; k < P_IN/2; k = k + 1)
burst[k*16 +: 16] = {act_byte(0, 2*wi, 2*k+1), act_byte(0, 2*wi, 2*k)};
for (k = 0; k < P_IN/2; k = k + 1)
burst[(P_IN/2+k)*16 +: 16] = {act_byte(0, 2*wi+1, 2*k+1), act_byte(0, 2*wi+1, 2*k)};
sdram_write_burst(0 + wi*BURST_LEN, burst);
$display("=== preload lane A base=0, lane B base=200, %0d tiles (EXP-0084 4-tiles/burst layout) ===", N_TILES);
for (wi = 0; wi < N_TILES/4; wi = wi + 1) begin
for (qi = 0; qi < 4; qi = qi + 1)
burst[qi*64 +: 64] = {act_byte(0, 4*wi+qi, 7), act_byte(0, 4*wi+qi, 6), act_byte(0, 4*wi+qi, 5), act_byte(0, 4*wi+qi, 4),
act_byte(0, 4*wi+qi, 3), act_byte(0, 4*wi+qi, 2), act_byte(0, 4*wi+qi, 1), act_byte(0, 4*wi+qi, 0)};
mem_write_burst(0 + wi*BURST_LEN, burst);
for (k = 0; k < P_IN/2; k = k + 1)
burst[k*16 +: 16] = {act_byte(200, 2*wi, 2*k+1), act_byte(200, 2*wi, 2*k)};
for (k = 0; k < P_IN/2; k = k + 1)
burst[(P_IN/2+k)*16 +: 16] = {act_byte(200, 2*wi+1, 2*k+1), act_byte(200, 2*wi+1, 2*k)};
sdram_write_burst(200 + wi*BURST_LEN, burst);
for (qi = 0; qi < 4; qi = qi + 1)
burst[qi*64 +: 64] = {act_byte(200, 4*wi+qi, 7), act_byte(200, 4*wi+qi, 6), act_byte(200, 4*wi+qi, 5), act_byte(200, 4*wi+qi, 4),
act_byte(200, 4*wi+qi, 3), act_byte(200, 4*wi+qi, 2), act_byte(200, 4*wi+qi, 1), act_byte(200, 4*wi+qi, 0)};
mem_write_burst(200 + wi*BURST_LEN, burst);
end
@(posedge clk);
// ============================================================
// PART 1: baseline correctness + real cycle count, OLD-style
// PART 1: baseline correctness + cycle count, OLD-style
// per-tile req -> wait valid -> 2-cycle simulated compute -> next req
// ============================================================
$display("=== PART 1: baseline (direct act_tile_fetch.v, old packed_slot.v loop) ===");
@@ -213,10 +190,10 @@ module tb;
$display("baseline: %0d tiles in %0d cycles (%0.2f cycles/tile)", N_TILES, base_cycles, base_cycles*1.0/N_TILES);
// ============================================================
// PART 2: prefetch correctness + real cycle count, EXP-0083
// job-level start, poll tile_valid, 2-cycle simulated compute, consume
// PART 2: prefetch correctness + cycle count, EXP-0083 job-level
// start, poll tile_valid, 2-cycle simulated compute, consume
// ============================================================
$display("=== PART 2: prefetch (ddr_prefetch_mgr.v, EXP-0083) ===");
$display("=== PART 2: prefetch (ddr_prefetch_mgr.v, EXP-0083/0084) ===");
sel = SEL_PF;
@(posedge clk);
pf_base_a <= 0; pf_base_b <= 200; pf_n_tiles <= N_TILES[15:0];
@@ -230,11 +207,7 @@ module tb;
// pulse being sampled by the DUT (both triggered off the same
// @(posedge clk)), reading pf_tile_valid/bank_valid BEFORE the
// DUT's own nonblocking update for that consume has been
// applied -- a real testbench race, not an RTL bug (found via
// an iteration-tagged trace: k=1 was reading k=0's still-
// unconsumed bank). #1 (real time, 1ns << the 15.625ns clock
// period) forces this poll to always run strictly after that
// update has settled.
// applied -- a real testbench race, not an RTL bug (EXP-0083).
#1;
while (!pf_tile_valid) @(posedge clk);
for (wi = 0; wi < P_IN; wi = wi + 1) begin
@@ -252,56 +225,9 @@ module tb;
pf_cycles = (t_end - t_start) / CLK_PERIOD_NS;
$display("prefetch: %0d tiles in %0d cycles (%0.2f cycles/tile)", N_TILES, pf_cycles, pf_cycles*1.0/N_TILES);
$display("=== REAL MEASURED COMPARISON (row-switch-heavy, 3 different burst pairs): baseline=%0d cycles, prefetch=%0d cycles, reduction=%0.1f%% ===",
base_cycles, pf_cycles, 100.0*(base_cycles-pf_cycles)/base_cycles);
check(pf_cycles < base_cycles, "prefetch is real, measurably faster than baseline (row-switch-heavy)");
// ============================================================
// PART 3 (EXP-0083 addendum): best-case, SAME-ROW comparison --
// only tiles 0/1 (both already resident in the FIRST preloaded
// burst pair, no row activation needed for either), isolating
// the look-ahead benefit from row-switch cost entirely. Answers
// honestly whether the small PART-1/2 result is because the
// benefit is inherently small, or because row-switch cost
// dominates and masks it in that scenario.
// ============================================================
$display("=== PART 3: same-row best case (2 tiles, single burst pair, no row switch) ===");
sel = SEL_BASE;
@(posedge clk);
t_start = $time;
for (k = 0; k < 2; k = k + 1) begin
@(posedge clk);
base_base_a <= 0; base_base_b <= 200; base_tcnt <= k[15:0];
base_req <= 1'b1;
@(posedge clk);
base_req <= 1'b0;
while (!base_valid) @(posedge clk);
repeat(2) @(posedge clk);
end
t_end = $time;
base_cycles = (t_end - t_start) / CLK_PERIOD_NS;
$display("same-row baseline: 2 tiles in %0d cycles", base_cycles);
sel = SEL_PF;
@(posedge clk);
pf_base_a <= 0; pf_base_b <= 200; pf_n_tiles <= 16'd2;
pf_job_start <= 1'b1;
t_start = $time;
@(posedge clk);
pf_job_start <= 1'b0;
for (k = 0; k < 2; k = k + 1) begin
#1;
while (!pf_tile_valid) @(posedge clk);
repeat(2) @(posedge clk);
pf_tile_consume <= 1'b1;
@(posedge clk);
pf_tile_consume <= 1'b0;
end
t_end = $time;
pf_cycles = (t_end - t_start) / CLK_PERIOD_NS;
$display("same-row prefetch: 2 tiles in %0d cycles", pf_cycles);
$display("=== REAL MEASURED COMPARISON (same-row, best case): baseline=%0d cycles, prefetch=%0d cycles, reduction=%0.1f%% ===",
$display("=== cycle comparison on this fixed-latency synthetic backend: baseline=%0d cycles, prefetch=%0d cycles, reduction=%0.1f%% (sanity check only -- the real, trustworthy number is EXP-0083's real-DDR3-backend measurement, 2.86%%) ===",
base_cycles, pf_cycles, 100.0*(base_cycles-pf_cycles)/base_cycles);
check(pf_cycles <= base_cycles, "prefetch is not slower than baseline (sanity check)");
$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
if (errors == 0) $display("ALL TESTS PASSED (tb_ddr_prefetch_mgr)");