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feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084)

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Real 32-bit DDR3 widening (2x MT41J128M16JT-125:K chips ganged in
parallel, user's own MIG wizard session). Full RTL adaptation across
the shared ctrl bus (16-bit word -> 32-bit word, BURST_LEN=8 unchanged,
burst payload 128->256 bits):

- mig_native_adapter.v: app_wdf_data/app_rd_data 64->128 bits (real,
  confirmed against the regenerated MIG wrapper), beat count unchanged.
- act_tile_fetch.v: real logic change - burst now holds 4 tiles instead
  of 2 (sel_lat extended to 2 registered bits, 4-way case mux instead
  of 2-way ternary, same request-time-registered-select discipline as
  EXP-0081). Not a further bytes/MAC reduction, just what's needed to
  keep 100% packing utilization at the larger burst.
- host_mem_bridge.v: real addressing redesign - host-facing 16-bit-word
  contract kept unchanged (ESP32 firmware unaffected), internally
  translated onto the new 32-bit-native ctrl bus.
- sdram_arbiter_n.v, layer_prefetch_ctrl.v, packed_slot.v,
  ddr_prefetch_mgr.v, n2_system_ddr3_top.v: mechanical width bump plus
  doubled ddr3_dq/dqs/dm pins and the real differential sys_clk/clk_ref
  top-level ports the regenerated MIG now requires.

New burst_mem_model32.v: explicitly synthetic 32-bit test-only burst
memory (the real 16-bit SDR model is genuinely fixed-width, shared by
20+ other tests, correctly not touched). Found and fixed a real
address-aliasing bug in it during bring-up (MEM_ADDR_BITS=16 silently
wrapped a real 0x10000 test address to 0).

Real verification: all isolated testbenches re-verified (10/10, 33/33,
32/32, 7/7, 9/9 PASS), plus real xsim against the real 2-chip DDR3
model (tb_mig_native_adapter.v 12/12 PASS, tb_n2_system_ddr3.v 8/8
PASS, both chips visibly returning different real data).

Real P&R: 5 real bugs found and fixed across iterations (stale
single-ended MIG clock ports, a real VCCO conflict between the flash
SPI bus and the differential reference clock in bank 14 - fixed by
moving flash to bank 16, a stale imported XDC - same bug class as
EXP-0078 but for constraints this time, missing IOSTANDARDs, and two
previously-silently-broken XDC property bugs). Route completes 100%,
but real timing does NOT close: WNS -0.618ns, 213 failing endpoints.

Honest root cause: the violation is inside neural_processor_packed.v's
own packed-MAC accumulation tree, unchanged since EXP-0059 - it has
real margin at the old 155.039MHz ui_clk but not at the new 172.414MHz
the paired clock-period change produced. This is NOT caused by the
32-bit width change itself. Width alone, even at the old clock, already
delivers the full intended 2x bandwidth gain (1.24 -> ~2.48 GB/s) -
width and clock rate are separable levers. Current trustworthy timing
signoff remains EXP-0083 (16-bit, +0.073ns) until the clock period is
reverted toward 3225ps (keeping Data Width=32) in one more real,
user-gated MIG wizard session.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-20 16:28:44 +02:00
co-authored by Claude Sonnet 5
parent 376ccb6ee2
commit 9dead54ebf
21 changed files with 1302 additions and 754 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v3/sim/tb_act_tile_fetch.v
+62 -72
View File
@@ -1,21 +1,23 @@
`timescale 1ns/1ps
// ============================================================
// Isolated correctness test for act_tile_fetch.v -- real SDR SDRAM
// placeholder backend (same precedent as tb_host_mem_bridge.v/
// tb_sdram_arbiter_n.v: verify new glue logic against the fast
// backend first). Checks: (1) both lanes read back bit-exact from
// their own burst-aligned tile slot; (2) different tile indices
// correctly compute different burst addresses (tile_offset =
// tcnt*BURST_LEN); (3) back-to-back requests (multiple tiles in a
// row) all stay correct, exercising the S_GAP busy-wait logic.
// Isolated correctness test for act_tile_fetch.v -- EXP-0084: re-run
// against the new 32-bit-wide ctrl bus / 4-tiles-per-burst layout
// (real 32-bit DDR3 channel widening). Backend switched from the real
// AS4C32M16SA x16 SDR model (sdram_controller.v/sdram_model.v -- a
// REAL chip, genuinely fixed at 16-bit, not reusable here) to
// burst_mem_model32.v, an explicitly synthetic 32-bit test-only
// burst memory built for exactly this purpose (see its own header).
// Checks: (1) all four lanes of a burst read back bit-exact from
// their own quarter-slot; (2) different tile indices correctly
// compute different burst addresses (tile_offset = (tcnt>>2)*
// BURST_LEN); (3) back-to-back requests (multiple tiles in a row,
// including crossing a burst boundary) all stay correct, exercising
// the S_GAP busy-wait logic.
// ============================================================
module tb;
localparam BURST_LEN = 8;
localparam ROW_BITS = 13;
localparam COL_BITS = 10;
localparam BANK_BITS = 2;
localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS; // 25
localparam ADDR_WIDTH = 25;
localparam CLK_FREQ_MHZ = 64;
localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
localparam DATA_WIDTH = 8;
@@ -27,30 +29,16 @@ module tb;
wire ctrl_req, ctrl_wr;
wire [ADDR_WIDTH-1:0] ctrl_addr;
wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
wire [2*BURST_LEN-1:0] ctrl_wmask;
wire [32*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
wire [4*BURST_LEN-1:0] ctrl_wmask;
wire ctrl_ready, ctrl_busy;
wire cke, cs_n, ras_n, cas_n, we_n;
wire [BANK_BITS-1:0] ba;
wire [ROW_BITS-1:0] a;
wire [15:0] dq;
wire [1:0] dqm;
sdram_controller #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_ctrl (
burst_mem_model32 #(
.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
) u_mem (
.clk(clk), .rst(rst),
.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
);
sdram_model #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_mem (
.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
.ba(ba), .a(a), .dq(dq), .dqm(dqm)
.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy)
);
// single requester -> tie grant = active, same precedent as
@@ -66,8 +54,8 @@ module tb;
wire dut_ctrl_req, dut_ctrl_wr;
wire [ADDR_WIDTH-1:0] dut_ctrl_addr;
wire [16*BURST_LEN-1:0] dut_ctrl_wdata;
wire [2*BURST_LEN-1:0] dut_ctrl_wmask;
wire [32*BURST_LEN-1:0] dut_ctrl_wdata;
wire [4*BURST_LEN-1:0] dut_ctrl_wmask;
act_tile_fetch #(
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
@@ -81,27 +69,21 @@ module tb;
.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
);
// ---- preload path: direct access to the SDRAM controller,
// bypassing act_tile_fetch.v entirely, same "pre_active" mux
// pattern as every other testbench in this project ----
// ---- preload path: direct access to the memory model, bypassing
// act_tile_fetch.v entirely, same "pre_active" mux pattern as
// every other testbench in this project ----
reg pre_active;
reg pre_req, pre_wr;
reg [ADDR_WIDTH-1:0] pre_addr;
reg [16*BURST_LEN-1:0] pre_wdata;
reg [32*BURST_LEN-1:0] pre_wdata;
// reroute: real DUT ctrl_* wires go through a mux so the testbench
// can preload memory directly before act_tile_fetch.v ever runs.
// (Re-declare the connection: DUT was wired directly above for
// simplicity of the DUT instantiation; use force-free approach by
// instead having the DUT's own ctrl_req/wr/addr/wdata feed the mux
// inputs below and the mux feed the real controller.)
assign ctrl_req = pre_active ? pre_req : dut_ctrl_req;
assign ctrl_wr = pre_active ? pre_wr : dut_ctrl_wr;
assign ctrl_addr = pre_active ? pre_addr : dut_ctrl_addr;
assign ctrl_wdata = pre_active ? pre_wdata : dut_ctrl_wdata;
assign ctrl_wmask = pre_active ? {(2*BURST_LEN){1'b0}} : dut_ctrl_wmask;
assign ctrl_wmask = pre_active ? {(4*BURST_LEN){1'b0}} : dut_ctrl_wmask;
task automatic sdram_write_burst(input [ADDR_WIDTH-1:0] word_addr, input [16*BURST_LEN-1:0] data);
task automatic mem_write_burst(input [ADDR_WIDTH-1:0] word_addr, input [32*BURST_LEN-1:0] data);
begin
@(posedge clk); while (ctrl_busy) @(posedge clk);
pre_req = 1'b1; pre_wr = 1'b1; pre_addr = word_addr; pre_wdata = data;
@@ -137,7 +119,7 @@ module tb;
reg signed [DATA_WIDTH*P_IN-1:0] exp_a, exp_b;
integer k, wi;
reg [16*BURST_LEN-1:0] burst;
reg [32*BURST_LEN-1:0] burst;
initial begin
errors = 0; tests = 0;
@@ -147,54 +129,62 @@ module tb;
rst = 0;
@(posedge clk); while (ctrl_busy) @(posedge clk);
$display("=== preload 2 bursts/lane, 2 tiles packed per burst (EXP-0081 layout) ===");
$display("=== preload 2 bursts/lane, 4 tiles packed per burst (EXP-0084 layout) ===");
// lane A base = 0, lane B base = 100 (arbitrary, word-address units).
// burst pair p holds tile 2p (low 64 bits) and tile 2p+1 (high 64 bits).
for (wi = 0; wi < 2; wi = wi + 1) begin // wi = burst-pair index (0 -> tiles 0/1, 1 -> tiles 2/3)
for (k = 0; k < P_IN/2; k = k + 1)
burst[k*16 +: 16] = {act_byte(0, 2*wi, 2*k+1), act_byte(0, 2*wi, 2*k)};
for (k = 0; k < P_IN/2; k = k + 1)
burst[(P_IN/2+k)*16 +: 16] = {act_byte(0, 2*wi+1, 2*k+1), act_byte(0, 2*wi+1, 2*k)};
sdram_write_burst(0 + wi*BURST_LEN, burst);
// burst pair p holds tiles 4p, 4p+1, 4p+2, 4p+3 in quarters 0..3.
for (wi = 0; wi < 2; wi = wi + 1) begin // wi = burst index (0 -> tiles 0-3, 1 -> tiles 4-7)
for (k = 0; k < 4; k = k + 1)
burst[k*64 +: 64] = {act_byte(0, 4*wi+k, 7), act_byte(0, 4*wi+k, 6), act_byte(0, 4*wi+k, 5), act_byte(0, 4*wi+k, 4),
act_byte(0, 4*wi+k, 3), act_byte(0, 4*wi+k, 2), act_byte(0, 4*wi+k, 1), act_byte(0, 4*wi+k, 0)};
mem_write_burst(0 + wi*BURST_LEN, burst);
for (k = 0; k < P_IN/2; k = k + 1)
burst[k*16 +: 16] = {act_byte(100, 2*wi, 2*k+1), act_byte(100, 2*wi, 2*k)};
for (k = 0; k < P_IN/2; k = k + 1)
burst[(P_IN/2+k)*16 +: 16] = {act_byte(100, 2*wi+1, 2*k+1), act_byte(100, 2*wi+1, 2*k)};
sdram_write_burst(100 + wi*BURST_LEN, burst);
for (k = 0; k < 4; k = k + 1)
burst[k*64 +: 64] = {act_byte(100, 4*wi+k, 7), act_byte(100, 4*wi+k, 6), act_byte(100, 4*wi+k, 5), act_byte(100, 4*wi+k, 4),
act_byte(100, 4*wi+k, 3), act_byte(100, 4*wi+k, 2), act_byte(100, 4*wi+k, 1), act_byte(100, 4*wi+k, 0)};
mem_write_burst(100 + wi*BURST_LEN, burst);
end
@(posedge clk);
pre_active = 1'b0;
$display("=== TEST 1: fetch tile 0 (even -> low half), both lanes ===");
$display("=== TEST 1: fetch tile 0 (quarter 0), both lanes ===");
do_fetch(25'd0, 25'd100, 16'd0);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 0, k);
for (k = 0; k < P_IN; k = k + 1) exp_b[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(100, 0, k);
check(data_a === exp_a, "T1: lane A tile 0 bit-exact");
check(data_b === exp_b, "T1: lane B tile 0 bit-exact");
$display("=== TEST 2: fetch tile 1 (odd -> high half, SAME burst address as tile 0) ===");
$display("=== TEST 2: fetch tile 1 (quarter 1, SAME burst address as tile 0) ===");
do_fetch(25'd0, 25'd100, 16'd1);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 1, k);
for (k = 0; k < P_IN; k = k + 1) exp_b[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(100, 1, k);
check(data_a === exp_a, "T2: lane A tile 1 bit-exact");
check(data_b === exp_b, "T2: lane B tile 1 bit-exact");
$display("=== TEST 3: fetch tile 2 (even -> low half, NEW burst address) ===");
$display("=== TEST 2b: fetch tile 2 (quarter 2, SAME burst) ===");
do_fetch(25'd0, 25'd100, 16'd2);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 2, k);
check(data_a === exp_a, "T3: lane A tile 2 bit-exact (new burst)");
check(data_a === exp_a, "T2b: lane A tile 2 bit-exact");
$display("=== TEST 4: back-to-back fetches, alternating even/odd tiles ===");
do_fetch(25'd0, 25'd100, 16'd0);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 0, k);
check(data_a === exp_a, "T4a: back-to-back fetch 1 (tile 0, even), lane A correct");
do_fetch(25'd0, 25'd100, 16'd1);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 1, k);
check(data_a === exp_a, "T4b: back-to-back fetch 2 (tile 1, odd), lane A correct");
$display("=== TEST 2c: fetch tile 3 (quarter 3, SAME burst) ===");
do_fetch(25'd0, 25'd100, 16'd3);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 3, k);
check(data_a === exp_a, "T4c: back-to-back fetch 3 (tile 3, odd, new burst), lane A correct");
check(data_a === exp_a, "T2c: lane A tile 3 bit-exact");
$display("=== TEST 3: fetch tile 4 (quarter 0, NEW burst address) ===");
do_fetch(25'd0, 25'd100, 16'd4);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 4, k);
check(data_a === exp_a, "T3: lane A tile 4 bit-exact (new burst)");
$display("=== TEST 4: back-to-back fetches, cycling through all 4 quarters ===");
do_fetch(25'd0, 25'd100, 16'd0);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 0, k);
check(data_a === exp_a, "T4a: back-to-back fetch 1 (tile 0, quarter 0), lane A correct");
do_fetch(25'd0, 25'd100, 16'd2);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 2, k);
check(data_a === exp_a, "T4b: back-to-back fetch 2 (tile 2, quarter 2), lane A correct");
do_fetch(25'd0, 25'd100, 16'd7);
for (k = 0; k < P_IN; k = k + 1) exp_a[k*DATA_WIDTH +: DATA_WIDTH] = act_byte(0, 7, k);
check(data_a === exp_a, "T4c: back-to-back fetch 3 (tile 7, quarter 3, new burst), lane A correct");
$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
if (errors == 0) $display("ALL TESTS PASSED (tb_act_tile_fetch)");