feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084)
Real 32-bit DDR3 widening (2x MT41J128M16JT-125:K chips ganged in parallel, user's own MIG wizard session). Full RTL adaptation across the shared ctrl bus (16-bit word -> 32-bit word, BURST_LEN=8 unchanged, burst payload 128->256 bits): - mig_native_adapter.v: app_wdf_data/app_rd_data 64->128 bits (real, confirmed against the regenerated MIG wrapper), beat count unchanged. - act_tile_fetch.v: real logic change - burst now holds 4 tiles instead of 2 (sel_lat extended to 2 registered bits, 4-way case mux instead of 2-way ternary, same request-time-registered-select discipline as EXP-0081). Not a further bytes/MAC reduction, just what's needed to keep 100% packing utilization at the larger burst. - host_mem_bridge.v: real addressing redesign - host-facing 16-bit-word contract kept unchanged (ESP32 firmware unaffected), internally translated onto the new 32-bit-native ctrl bus. - sdram_arbiter_n.v, layer_prefetch_ctrl.v, packed_slot.v, ddr_prefetch_mgr.v, n2_system_ddr3_top.v: mechanical width bump plus doubled ddr3_dq/dqs/dm pins and the real differential sys_clk/clk_ref top-level ports the regenerated MIG now requires. New burst_mem_model32.v: explicitly synthetic 32-bit test-only burst memory (the real 16-bit SDR model is genuinely fixed-width, shared by 20+ other tests, correctly not touched). Found and fixed a real address-aliasing bug in it during bring-up (MEM_ADDR_BITS=16 silently wrapped a real 0x10000 test address to 0). Real verification: all isolated testbenches re-verified (10/10, 33/33, 32/32, 7/7, 9/9 PASS), plus real xsim against the real 2-chip DDR3 model (tb_mig_native_adapter.v 12/12 PASS, tb_n2_system_ddr3.v 8/8 PASS, both chips visibly returning different real data). Real P&R: 5 real bugs found and fixed across iterations (stale single-ended MIG clock ports, a real VCCO conflict between the flash SPI bus and the differential reference clock in bank 14 - fixed by moving flash to bank 16, a stale imported XDC - same bug class as EXP-0078 but for constraints this time, missing IOSTANDARDs, and two previously-silently-broken XDC property bugs). Route completes 100%, but real timing does NOT close: WNS -0.618ns, 213 failing endpoints. Honest root cause: the violation is inside neural_processor_packed.v's own packed-MAC accumulation tree, unchanged since EXP-0059 - it has real margin at the old 155.039MHz ui_clk but not at the new 172.414MHz the paired clock-period change produced. This is NOT caused by the 32-bit width change itself. Width alone, even at the old clock, already delivers the full intended 2x bandwidth gain (1.24 -> ~2.48 GB/s) - width and clock rate are separable levers. Current trustworthy timing signoff remains EXP-0083 (16-bit, +0.073ns) until the clock period is reverted toward 3225ps (keeping Data Width=32) in one more real, user-gated MIG wizard session. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
Claude Sonnet 5
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`timescale 1ns/1ps
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// ============================================================
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// EXP-0084 -- minimal, EXPLICITLY SYNTHETIC 32-bit-wide burst-memory
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// test model. NOT a real chip model (unlike sdram_controller.v/
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// sdram_model.v, which genuinely represent the real AS4C32M16SA x16
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// SDR part this project also uses) -- that real model is inherently
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// fixed at 16-bit words (a real hardware fact, not a parameter choice)
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// and is shared by 20+ other testbenches across v2 and v3, so it is
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// deliberately NOT modified here. This file exists purely so the
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// isolated, fast (iverilog) testbenches for modules that now speak
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// this project's real 32-bit ctrl bus convention (EXP-0084's DDR3
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// widening) have a same-shape, functionally-correct backend to run
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// against WITHOUT needing the full real MIG IP + ddr3_model.sv (real
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// xsim, much slower) for every isolated glue-logic check -- matching
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// this project's own established "verify new glue logic against a
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// fast backend first" precedent (tb_act_tile_fetch.v's own header),
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// just re-pointed at a backend that actually matches the current real
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// bus width. The REAL, trustworthy, board-accurate verification still
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// comes from tb_n2_system_ddr3.v against the real ddr3_model.sv, same
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// as always -- this model's own fixed latency is a plausible, but NOT
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// claimed-real, stand-in.
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//
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// Small DENSE backing store (2^MEM_ADDR_BITS entries), not a full
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// 2^ADDR_WIDTH array -- ADDR_WIDTH=25 would need ~1GB densely
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// allocated for no reason; every real test in this project only ever
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// touches small, low addresses. MEM_ADDR_BITS=20 (~1M entries, ~32MB
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// of simulation memory) comfortably covers any realistic test address
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// -- including tb_packed_slot.v's own ACT_MEM_BASE=0x10000 region,
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// which a first version of this model sized at 16 bits (65536
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// entries) silently WRAPPED to address 0, aliasing weight and
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// activation data and producing real, confusing wrong-answer failures
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// (found via real simulation, not by inspection -- see EXP-0084's
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// log for the full root-cause trace). Staying portable (Icarus's
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// associative-array support for a packed-vector key type turned out
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// not to work for this purpose -- found via a real elaboration
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// error, not assumed).
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// ============================================================
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module burst_mem_model32 #(
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parameter BURST_LEN = 8,
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parameter ADDR_WIDTH = 25,
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parameter MEM_ADDR_BITS = 20,
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parameter LATENCY = 6 // fixed req->ready cycles, a plausible stand-in, not claimed real
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)(
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input wire clk,
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input wire rst,
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input wire req,
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input wire wr,
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input wire [ADDR_WIDTH-1:0] addr,
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input wire [32*BURST_LEN-1:0] wdata,
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input wire [4*BURST_LEN-1:0] wmask,
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output reg [32*BURST_LEN-1:0] rdata,
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output reg ready,
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output wire busy
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);
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reg [32*BURST_LEN-1:0] mem [0:(1<<MEM_ADDR_BITS)-1];
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localparam S_IDLE = 2'd0, S_BUSY = 2'd1, S_DONE = 2'd2;
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reg [1:0] state;
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reg [7:0] cnt;
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reg [ADDR_WIDTH-1:0] addr_lat;
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reg wr_lat;
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reg [32*BURST_LEN-1:0] wdata_lat;
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reg [4*BURST_LEN-1:0] wmask_lat;
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integer bi;
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assign busy = (state != S_IDLE);
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always @(posedge clk) begin
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if (rst) begin
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state <= S_IDLE;
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ready <= 1'b0;
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cnt <= 8'd0;
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end else begin
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ready <= 1'b0;
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case (state)
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S_IDLE: begin
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if (req) begin
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addr_lat <= addr;
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wr_lat <= wr;
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wdata_lat <= wdata;
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wmask_lat <= wmask;
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cnt <= LATENCY[7:0];
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state <= S_BUSY;
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end
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end
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S_BUSY: begin
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if (cnt == 8'd1) state <= S_DONE;
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else cnt <= cnt - 8'd1;
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end
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S_DONE: begin
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if (wr_lat) begin
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// real DQM polarity (matches sdram_controller.v's
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// own convention): 0=write that byte, 1=masked.
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for (bi = 0; bi < 4*BURST_LEN; bi = bi + 1)
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if (!wmask_lat[bi])
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mem[addr_lat[MEM_ADDR_BITS-1:0]][bi*8 +: 8] <= wdata_lat[bi*8 +: 8];
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end else begin
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rdata <= mem[addr_lat[MEM_ADDR_BITS-1:0]];
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end
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ready <= 1'b1;
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state <= S_IDLE;
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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endmodule
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