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feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084)

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Real 32-bit DDR3 widening (2x MT41J128M16JT-125:K chips ganged in
parallel, user's own MIG wizard session). Full RTL adaptation across
the shared ctrl bus (16-bit word -> 32-bit word, BURST_LEN=8 unchanged,
burst payload 128->256 bits):

- mig_native_adapter.v: app_wdf_data/app_rd_data 64->128 bits (real,
  confirmed against the regenerated MIG wrapper), beat count unchanged.
- act_tile_fetch.v: real logic change - burst now holds 4 tiles instead
  of 2 (sel_lat extended to 2 registered bits, 4-way case mux instead
  of 2-way ternary, same request-time-registered-select discipline as
  EXP-0081). Not a further bytes/MAC reduction, just what's needed to
  keep 100% packing utilization at the larger burst.
- host_mem_bridge.v: real addressing redesign - host-facing 16-bit-word
  contract kept unchanged (ESP32 firmware unaffected), internally
  translated onto the new 32-bit-native ctrl bus.
- sdram_arbiter_n.v, layer_prefetch_ctrl.v, packed_slot.v,
  ddr_prefetch_mgr.v, n2_system_ddr3_top.v: mechanical width bump plus
  doubled ddr3_dq/dqs/dm pins and the real differential sys_clk/clk_ref
  top-level ports the regenerated MIG now requires.

New burst_mem_model32.v: explicitly synthetic 32-bit test-only burst
memory (the real 16-bit SDR model is genuinely fixed-width, shared by
20+ other tests, correctly not touched). Found and fixed a real
address-aliasing bug in it during bring-up (MEM_ADDR_BITS=16 silently
wrapped a real 0x10000 test address to 0).

Real verification: all isolated testbenches re-verified (10/10, 33/33,
32/32, 7/7, 9/9 PASS), plus real xsim against the real 2-chip DDR3
model (tb_mig_native_adapter.v 12/12 PASS, tb_n2_system_ddr3.v 8/8
PASS, both chips visibly returning different real data).

Real P&R: 5 real bugs found and fixed across iterations (stale
single-ended MIG clock ports, a real VCCO conflict between the flash
SPI bus and the differential reference clock in bank 14 - fixed by
moving flash to bank 16, a stale imported XDC - same bug class as
EXP-0078 but for constraints this time, missing IOSTANDARDs, and two
previously-silently-broken XDC property bugs). Route completes 100%,
but real timing does NOT close: WNS -0.618ns, 213 failing endpoints.

Honest root cause: the violation is inside neural_processor_packed.v's
own packed-MAC accumulation tree, unchanged since EXP-0059 - it has
real margin at the old 155.039MHz ui_clk but not at the new 172.414MHz
the paired clock-period change produced. This is NOT caused by the
32-bit width change itself. Width alone, even at the old clock, already
delivers the full intended 2x bandwidth gain (1.24 -> ~2.48 GB/s) -
width and clock rate are separable levers. Current trustworthy timing
signoff remains EXP-0083 (16-bit, +0.073ns) until the clock period is
reverted toward 3225ps (keeping Data Width=32) in one more real,
user-gated MIG wizard session.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-20 16:28:44 +02:00
co-authored by Claude Sonnet 5
parent 376ccb6ee2
commit 9dead54ebf
21 changed files with 1302 additions and 754 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v3/rtl/n2_system_ddr3_top.v
+51 -34
View File
@@ -14,9 +14,16 @@
// packed_slot instances, and the SPI bridge itself) runs in the
// ui_clk domain, per this project's own standing convention
// (mig_native_adapter.v's header) -- ui_clk is generated BY the MIG
// from sys_clk_i, so this module only takes sys_clk_i/clk_ref_i/
// from sys_clk_p/n, so this module only takes sys_clk_p/n/clk_ref_p/n/
// sys_rst as clock/reset inputs, not a separate system clock.
//
// EXP-0084: sys_clk and clk_ref are now real DIFFERENTIAL pairs (the
// user's own wizard choice, confirmed against the real regenerated
// public mig_7series_0.v wrapper, which expects sys_clk_p/n and
// clk_ref_p/n directly as raw top-level differential pins -- not a
// single-ended sys_clk_i/clk_ref_i pair any more). Real board
// implication: a differential oscillator, not a single-ended one.
//
// This is the first REAL (in-context, not out-of-context) P&R target
// for V3: previous P&R runs (EXP-0059/63/67) were all out-of-context
// synthesis of a sub-block, without the real MIG-generated pin/timing
@@ -42,15 +49,25 @@ module n2_system_ddr3_top #(
parameter N_SLOTS = 2,
parameter QUEUE_DEPTH = 8
)(
// ---- MIG clock/reset ----
input wire sys_clk_i,
// ---- MIG clock/reset (EXP-0084: real differential pairs, both
// the user's own wizard choice -- confirmed against the real
// regenerated public mig_7series_0.v wrapper, which now expects
// sys_clk_p/n and clk_ref_p/n directly as raw top-level
// differential pins, not a single-ended sys_clk_i/clk_ref_i pair
// any more) ----
input wire sys_clk_p,
input wire sys_clk_n,
input wire sys_rst,
input wire clk_ref_i,
input wire clk_ref_p,
input wire clk_ref_n,
// ---- real DDR3 pins (matches mig_7series_0.xdc's own port names) ----
inout wire [15:0] ddr3_dq,
inout wire [1:0] ddr3_dqs_n,
inout wire [1:0] ddr3_dqs_p,
// ---- real DDR3 pins (matches mig_7series_0.xdc's own port names;
// dq/dqs/dm widths doubled since EXP-0084's real 32-bit widening --
// two MT41J128M16 chips ganged in parallel, confirmed against the
// real regenerated mig_7series_0.v wrapper, not assumed) ----
inout wire [31:0] ddr3_dq,
inout wire [3:0] ddr3_dqs_n,
inout wire [3:0] ddr3_dqs_p,
output wire [13:0] ddr3_addr,
output wire [2:0] ddr3_ba,
output wire ddr3_ras_n,
@@ -61,7 +78,7 @@ module n2_system_ddr3_top #(
output wire [0:0] ddr3_ck_n,
output wire [0:0] ddr3_cke,
output wire [0:0] ddr3_cs_n,
output wire [1:0] ddr3_dm,
output wire [3:0] ddr3_dm,
output wire [0:0] ddr3_odt,
// ---- physical SPI host interface (-> spi_host_bridge_v3.v) ----
@@ -95,15 +112,15 @@ module n2_system_ddr3_top #(
output wire job_out_done,
output wire [$clog2(N_SLOTS)-1:0] job_out_slot
);
wire [27:0] app_addr;
wire [2:0] app_cmd;
wire app_en, app_rdy;
wire [63:0] app_wdf_data;
wire app_wdf_end;
wire [7:0] app_wdf_mask;
wire app_wdf_wren, app_wdf_rdy;
wire [63:0] app_rd_data;
wire app_rd_data_end, app_rd_data_valid;
wire [27:0] app_addr;
wire [2:0] app_cmd;
wire app_en, app_rdy;
wire [127:0] app_wdf_data;
wire app_wdf_end;
wire [15:0] app_wdf_mask;
wire app_wdf_wren, app_wdf_rdy;
wire [127:0] app_rd_data;
wire app_rd_data_end, app_rd_data_valid;
wire ui_clk, ui_clk_sync_rst;
assign ui_clk_o = ui_clk;
@@ -120,7 +137,7 @@ module n2_system_ddr3_top #(
.ddr3_ck_p(ddr3_ck_p), .ddr3_ck_n(ddr3_ck_n),
.ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n),
.ddr3_dm(ddr3_dm), .ddr3_odt(ddr3_odt),
.sys_clk_i(sys_clk_i), .clk_ref_i(clk_ref_i),
.sys_clk_p(sys_clk_p), .sys_clk_n(sys_clk_n), .clk_ref_p(clk_ref_p), .clk_ref_n(clk_ref_n),
.app_addr(app_addr), .app_cmd(app_cmd), .app_en(app_en),
.app_wdf_data(app_wdf_data), .app_wdf_end(app_wdf_end),
.app_wdf_mask(app_wdf_mask), .app_wdf_wren(app_wdf_wren),
@@ -136,9 +153,9 @@ module n2_system_ddr3_top #(
wire adp_req, adp_wr;
wire [MEM_ADDR_WIDTH-1:0] adp_addr;
wire [16*BURST_LEN-1:0] adp_wdata;
wire [2*BURST_LEN-1:0] adp_wmask;
wire [16*BURST_LEN-1:0] adp_rdata;
wire [32*BURST_LEN-1:0] adp_wdata;
wire [4*BURST_LEN-1:0] adp_wmask;
wire [32*BURST_LEN-1:0] adp_rdata;
wire adp_ready, adp_busy;
mig_native_adapter #(.BURST_LEN(BURST_LEN), .ADDR_WIDTH(MEM_ADDR_WIDTH)) u_adapter (
@@ -156,9 +173,9 @@ module n2_system_ddr3_top #(
wire [NUM_REQ-1:0] req_active, req_grant, req_req, req_wr;
wire [NUM_REQ-1:0] req_ready, req_busy;
wire [NUM_REQ*MEM_ADDR_WIDTH-1:0] req_addr;
wire [NUM_REQ*16*BURST_LEN-1:0] req_wdata;
wire [NUM_REQ*2*BURST_LEN-1:0] req_wmask;
wire [NUM_REQ*16*BURST_LEN-1:0] req_rdata;
wire [NUM_REQ*32*BURST_LEN-1:0] req_wdata;
wire [NUM_REQ*4*BURST_LEN-1:0] req_wmask;
wire [NUM_REQ*32*BURST_LEN-1:0] req_rdata;
sdram_arbiter_n #(
.NUM_REQ(NUM_REQ), .ADDR_WIDTH(MEM_ADDR_WIDTH), .BURST_LEN(BURST_LEN)
@@ -251,9 +268,9 @@ module n2_system_ddr3_top #(
.req_active(req_active[2]), .req_grant(req_grant[2]),
.req_req(req_req[2]), .req_wr(req_wr[2]),
.req_addr(req_addr[2*MEM_ADDR_WIDTH +: MEM_ADDR_WIDTH]),
.req_wdata(req_wdata[2*16*BURST_LEN +: 16*BURST_LEN]),
.req_wmask(req_wmask[2*2*BURST_LEN +: 2*BURST_LEN]),
.req_rdata(req_rdata[2*16*BURST_LEN +: 16*BURST_LEN]),
.req_wdata(req_wdata[2*32*BURST_LEN +: 32*BURST_LEN]),
.req_wmask(req_wmask[2*4*BURST_LEN +: 4*BURST_LEN]),
.req_rdata(req_rdata[2*32*BURST_LEN +: 32*BURST_LEN]),
.req_ready(req_ready[2]), .req_busy(req_busy[2])
);
@@ -288,9 +305,9 @@ module n2_system_ddr3_top #(
.mem_active(req_active[0]), .mem_grant(req_grant[0]),
.ctrl_req(req_req[0]), .ctrl_wr(req_wr[0]),
.ctrl_addr(req_addr[0*MEM_ADDR_WIDTH +: MEM_ADDR_WIDTH]),
.ctrl_wdata(req_wdata[0*16*BURST_LEN +: 16*BURST_LEN]),
.ctrl_wmask(req_wmask[0*2*BURST_LEN +: 2*BURST_LEN]),
.ctrl_rdata(req_rdata[0*16*BURST_LEN +: 16*BURST_LEN]),
.ctrl_wdata(req_wdata[0*32*BURST_LEN +: 32*BURST_LEN]),
.ctrl_wmask(req_wmask[0*4*BURST_LEN +: 4*BURST_LEN]),
.ctrl_rdata(req_rdata[0*32*BURST_LEN +: 32*BURST_LEN]),
.ctrl_ready(req_ready[0]), .ctrl_busy(req_busy[0])
);
@@ -314,9 +331,9 @@ module n2_system_ddr3_top #(
.mem_active(req_active[1]), .mem_grant(req_grant[1]),
.ctrl_req(req_req[1]), .ctrl_wr(req_wr[1]),
.ctrl_addr(req_addr[1*MEM_ADDR_WIDTH +: MEM_ADDR_WIDTH]),
.ctrl_wdata(req_wdata[1*16*BURST_LEN +: 16*BURST_LEN]),
.ctrl_wmask(req_wmask[1*2*BURST_LEN +: 2*BURST_LEN]),
.ctrl_rdata(req_rdata[1*16*BURST_LEN +: 16*BURST_LEN]),
.ctrl_wdata(req_wdata[1*32*BURST_LEN +: 32*BURST_LEN]),
.ctrl_wmask(req_wmask[1*4*BURST_LEN +: 4*BURST_LEN]),
.ctrl_rdata(req_rdata[1*32*BURST_LEN +: 32*BURST_LEN]),
.ctrl_ready(req_ready[1]), .ctrl_busy(req_busy[1])
);
endmodule