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feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084)

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Real 32-bit DDR3 widening (2x MT41J128M16JT-125:K chips ganged in
parallel, user's own MIG wizard session). Full RTL adaptation across
the shared ctrl bus (16-bit word -> 32-bit word, BURST_LEN=8 unchanged,
burst payload 128->256 bits):

- mig_native_adapter.v: app_wdf_data/app_rd_data 64->128 bits (real,
  confirmed against the regenerated MIG wrapper), beat count unchanged.
- act_tile_fetch.v: real logic change - burst now holds 4 tiles instead
  of 2 (sel_lat extended to 2 registered bits, 4-way case mux instead
  of 2-way ternary, same request-time-registered-select discipline as
  EXP-0081). Not a further bytes/MAC reduction, just what's needed to
  keep 100% packing utilization at the larger burst.
- host_mem_bridge.v: real addressing redesign - host-facing 16-bit-word
  contract kept unchanged (ESP32 firmware unaffected), internally
  translated onto the new 32-bit-native ctrl bus.
- sdram_arbiter_n.v, layer_prefetch_ctrl.v, packed_slot.v,
  ddr_prefetch_mgr.v, n2_system_ddr3_top.v: mechanical width bump plus
  doubled ddr3_dq/dqs/dm pins and the real differential sys_clk/clk_ref
  top-level ports the regenerated MIG now requires.

New burst_mem_model32.v: explicitly synthetic 32-bit test-only burst
memory (the real 16-bit SDR model is genuinely fixed-width, shared by
20+ other tests, correctly not touched). Found and fixed a real
address-aliasing bug in it during bring-up (MEM_ADDR_BITS=16 silently
wrapped a real 0x10000 test address to 0).

Real verification: all isolated testbenches re-verified (10/10, 33/33,
32/32, 7/7, 9/9 PASS), plus real xsim against the real 2-chip DDR3
model (tb_mig_native_adapter.v 12/12 PASS, tb_n2_system_ddr3.v 8/8
PASS, both chips visibly returning different real data).

Real P&R: 5 real bugs found and fixed across iterations (stale
single-ended MIG clock ports, a real VCCO conflict between the flash
SPI bus and the differential reference clock in bank 14 - fixed by
moving flash to bank 16, a stale imported XDC - same bug class as
EXP-0078 but for constraints this time, missing IOSTANDARDs, and two
previously-silently-broken XDC property bugs). Route completes 100%,
but real timing does NOT close: WNS -0.618ns, 213 failing endpoints.

Honest root cause: the violation is inside neural_processor_packed.v's
own packed-MAC accumulation tree, unchanged since EXP-0059 - it has
real margin at the old 155.039MHz ui_clk but not at the new 172.414MHz
the paired clock-period change produced. This is NOT caused by the
32-bit width change itself. Width alone, even at the old clock, already
delivers the full intended 2x bandwidth gain (1.24 -> ~2.48 GB/s) -
width and clock rate are separable levers. Current trustworthy timing
signoff remains EXP-0083 (16-bit, +0.073ns) until the clock period is
reverted toward 3225ps (keeping Data Width=32) in one more real,
user-gated MIG wizard session.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-20 16:28:44 +02:00
co-authored by Claude Sonnet 5
parent 376ccb6ee2
commit 9dead54ebf
21 changed files with 1302 additions and 754 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v3/rtl/mig_native_adapter.v
+43 -37
View File
@@ -3,12 +3,12 @@
// ============================================================
// V3 -- adapter between this project's own established memory-
// controller contract (req/wr/addr/wdata/wmask -> rdata/ready/busy,
// BURST_LEN=8 16-bit words = 128 bits/transaction, the SAME shape
// sdram_controller.v has presented everywhere in this project since
// STEP16) and the REAL Xilinx MIG 7-series native "app" user
// interface (PG063), generated for this project's actual DDR3 target
// (mig_7series_0, XC7A100T, MT41J128M16JT-125:K, PHY:Controller
// ratio 2:1).
// BURST_LEN=8 32-bit words = 256 bits/transaction since EXP-0084's
// real 32-bit DDR3 channel widening -- was 16-bit/128 bits before)
// and the REAL Xilinx MIG 7-series native "app" user interface
// (PG063), generated for this project's actual DDR3 target
// (mig_7series_0, XC7A100T, 2x MT41J128M16JT-125:K ganged to 32-bit,
// PHY:Controller ratio 2:1, 2900ps/344.827MHz, EXP-0084).
//
// Runs entirely in the ui_clk domain -- MIG's own generated clock is
// this design's new system clock (the standard way MIG-based designs
@@ -17,14 +17,20 @@
// synchronized to ui_clk by the caller.
//
// ADDRESSING (real, derived from THIS project's actual generated MIG
// config, not assumed): Data Width=16, Phy:Controller ratio 2:1 =>
// nCK_PER_CLK=2 => app data width = 16*8/2 = 64 bits, matching the
// real generated mig_7series_0.v port widths exactly (app_wdf_data
// [63:0], app_rd_data[63:0]). One app_addr/app_cmd issuance moves a
// FULL BURST_LEN=8 (128-bit) DDR3 burst, delivered as TWO 64-bit
// beats on the app data bus -- so app_addr increments in the SAME
// unit as this project's own existing ctrl_addr (one BURST_LEN=8
// chunk per increment), no address scaling needed at this boundary.
// config, not assumed, re-verified after EXP-0084's 32-bit
// regeneration): Data Width=32, Phy:Controller ratio 2:1 =>
// nCK_PER_CLK=2 => app data width = 32*8/2 = 128 bits, matching the
// real regenerated mig_7series_0.v port widths exactly (app_wdf_data
// [127:0], app_rd_data[127:0], app_wdf_mask[15:0] -- confirmed by
// directly reading the real generated wrapper, not assumed from the
// old 16-bit numbers). app_addr itself stayed 28 bits (confirmed same
// real generated width as before the widening) -- one app_addr/
// app_cmd issuance still moves a FULL BURST_LEN=8 chunk per increment,
// same as before, just each chunk is now 256 bits (32-bit words) not
// 128 bits (16-bit words), delivered as TWO 128-bit beats instead of
// two 64-bit beats -- so app_addr increments in the SAME unit as this
// project's own existing ctrl_addr, no address scaling needed at this
// boundary, same as before.
//
// Sequencing is deliberately fully sequential, not pipelined
// (correctness first): the command is issued and accepted (app_en/
@@ -52,9 +58,9 @@ module mig_native_adapter #(
input wire req,
input wire wr,
input wire [ADDR_WIDTH-1:0] addr,
input wire [16*BURST_LEN-1:0] wdata,
input wire [2*BURST_LEN-1:0] wmask,
output reg [16*BURST_LEN-1:0] rdata,
input wire [32*BURST_LEN-1:0] wdata,
input wire [4*BURST_LEN-1:0] wmask,
output reg [32*BURST_LEN-1:0] rdata,
output reg ready,
output wire busy,
@@ -64,15 +70,15 @@ module mig_native_adapter #(
output reg app_en,
input wire app_rdy,
output reg [63:0] app_wdf_data,
output reg app_wdf_end,
output reg [7:0] app_wdf_mask,
output reg app_wdf_wren,
input wire app_wdf_rdy,
output reg [127:0] app_wdf_data,
output reg app_wdf_end,
output reg [15:0] app_wdf_mask,
output reg app_wdf_wren,
input wire app_wdf_rdy,
input wire [63:0] app_rd_data,
input wire app_rd_data_end,
input wire app_rd_data_valid
input wire [127:0] app_rd_data,
input wire app_rd_data_end,
input wire app_rd_data_valid
);
localparam CMD_WRITE = 3'b000;
localparam CMD_READ = 3'b001;
@@ -86,8 +92,8 @@ module mig_native_adapter #(
reg [2:0] state;
reg wr_lat;
reg [16*BURST_LEN-1:0] wdata_lat;
reg [2*BURST_LEN-1:0] wmask_lat;
reg [32*BURST_LEN-1:0] wdata_lat;
reg [4*BURST_LEN-1:0] wmask_lat;
assign busy = (state != S_IDLE);
@@ -98,11 +104,11 @@ module mig_native_adapter #(
app_wdf_wren <= 1'b0;
app_wdf_end <= 1'b0;
ready <= 1'b0;
rdata <= {(16*BURST_LEN){1'b0}};
rdata <= {(32*BURST_LEN){1'b0}};
app_addr <= 28'h0;
app_cmd <= CMD_READ;
app_wdf_data <= 64'h0;
app_wdf_mask <= 8'h0;
app_wdf_data <= 128'h0;
app_wdf_mask <= 16'h0;
end else begin
ready <= 1'b0;
@@ -123,8 +129,8 @@ module mig_native_adapter #(
if (app_rdy) begin
app_en <= 1'b0;
if (wr_lat) begin
app_wdf_data <= wdata_lat[63:0];
app_wdf_mask <= wmask_lat[7:0];
app_wdf_data <= wdata_lat[127:0];
app_wdf_mask <= wmask_lat[15:0];
app_wdf_end <= 1'b0;
app_wdf_wren <= 1'b1;
state <= S_WDF0;
@@ -136,8 +142,8 @@ module mig_native_adapter #(
S_WDF0: begin
if (app_wdf_rdy) begin
app_wdf_data <= wdata_lat[127:64];
app_wdf_mask <= wmask_lat[15:8];
app_wdf_data <= wdata_lat[255:128];
app_wdf_mask <= wmask_lat[31:16];
app_wdf_end <= 1'b1;
app_wdf_wren <= 1'b1;
state <= S_WDF1;
@@ -155,10 +161,10 @@ module mig_native_adapter #(
S_RD_WAIT: begin
if (app_rd_data_valid) begin
if (!app_rd_data_end) begin
rdata[63:0] <= app_rd_data;
rdata[127:0] <= app_rd_data;
end else begin
rdata[127:64] <= app_rd_data;
state <= S_DONE;
rdata[255:128] <= app_rd_data;
state <= S_DONE;
end
end
end