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feat(v2): M10 Optimization - data-driven findings, completes the V2 roadmap

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Final milestone of docs/v2-description.md's §33 roadmap, scoped
exactly to its own mandate: optimize only on data already gathered in
M1-M9, across the pipeline/P_IN/processor-count/scheduling/memory
axes - no speculative new features.

Three concrete, data-driven results:

1. N_SLOTS=8 (numero processor axis): real synthesis + nextpnr-ecp5
   P&R for dataflow_core at N_SLOTS=8, extending M7's N_SLOTS=2/4
   sweep to the real DSP ceiling DEC-0005 predicted. 92.63 MHz
   POST-P&R, PASS at 80MHz, DSP 64/72 (88.9%). DEC-0012 recommends
   N_SLOTS=8 as the practical ceiling for P_IN=8 on the
   LFE5U-45F-8BG381.

2. ACC_WIDTH 24 vs 32 (pipeline axis): a real 6-seed nextpnr-ecp5
   placement sweep (reusing already-synthesized netlists, no new
   synthesis needed) resolves EXP-0002's single-seed
   inconclusiveness. ACC_WIDTH=24 wins on both mean Fmax (+6.2%,
   180.71 vs 170.12 MHz) and seed-to-seed variance (~3.4x tighter),
   on top of its already-known resource advantage. DEC-0013
   recommends ACC_WIDTH=24 as the new default.

3. Stall %/utilization (scheduling/memory axes): testbench-only cycle
   counters added to tb_neural_multiprocessor.v (no RTL touched)
   close DEC-0011's deferred measurement gap with real data - shared
   PSRAM port 81.7% utilized, slot 0 95.2%, slot 1 65.2%, no
   conclusive evidence of harmful fixed-priority starvation at this
   scale.

The 10-milestone V2 roadmap (docs/v2-description.md §33) is now
complete end-to-end: real Verilator simulation, real Yosys synthesis,
real nextpnr-ecp5 place & route for every milestone, fully logged
(EXP-0001..EXP-0013, DEC-0001..DEC-0013, ERR-0001..ERR-0008) with no
invented results (§30) and V1 kept frozen and untouched throughout
(§1/§34).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 18:58:10 +02:00
co-authored by Claude Sonnet 5
parent 84794a3d25
commit 91bbbe2fe5
9 changed files with 367 additions and 1 deletions
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@@ -95,3 +95,26 @@ PASS/FAIL: 4/4 PASS after fixing a real dropped-request bug in the
regression: hardware/v2/sim/tb_memory_manager.v (M4) re-run unchanged
(no M4 file touched) -- still 3/3 PASS, identical cycle counts
(446/166/728), confirming slot_mem_arbiter.v is purely additive.
[2026-09-05] EXP-0013 -- hardware/v2/sim/tb_neural_multiprocessor.v,
M10 cycle-accounting instrumentation (closes decisions.log DEC-0011's
deferred stall %/utilization gap with real data, testbench-only
addition, no RTL touched)
test: same EXP-0009 scenario (3-node DAG, N_SLOTS=2, real V1 PSRAM
chain, real slot_mem_arbiter contention), instrumented with cycle
counters (shared PSRAM port busy cycles via
u_nmp.u_arbiter.owner!=0, each slot's memory_manager busy cycles via
its own state!=MM_IDLE), measured from the first node registration
to test completion.
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 4/4 PASS (unchanged from EXP-0009), plus real measured
data: 684 total cycles measured; shared PSRAM port busy 559/684
(81.7% utilization, 18.3% idle); slot 0 (memory_manager) busy
651/684 (95.2%); slot 1 (memory_manager) busy 446/684 (65.2%).
note: slot 0's higher utilization is at least partly explained by it
serving TWO sequential jobs in this run (node0, then whichever slot
frees first serves node2 -- likely slot 0, first-free/lowest-index)
while slot 1 only ever serves node1 -- NOT conclusive evidence of
harmful priority starvation on its own; see decisions.log DEC-0010's
original fairness deferral, now informed by this real (if small)
data point.