michele/FPGA-Neural
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

feat(v2): M10 Optimization - data-driven findings, completes the V2 roadmap

Browse Source 
Final milestone of docs/v2-description.md's §33 roadmap, scoped
exactly to its own mandate: optimize only on data already gathered in
M1-M9, across the pipeline/P_IN/processor-count/scheduling/memory
axes - no speculative new features.

Three concrete, data-driven results:

1. N_SLOTS=8 (numero processor axis): real synthesis + nextpnr-ecp5
   P&R for dataflow_core at N_SLOTS=8, extending M7's N_SLOTS=2/4
   sweep to the real DSP ceiling DEC-0005 predicted. 92.63 MHz
   POST-P&R, PASS at 80MHz, DSP 64/72 (88.9%). DEC-0012 recommends
   N_SLOTS=8 as the practical ceiling for P_IN=8 on the
   LFE5U-45F-8BG381.

2. ACC_WIDTH 24 vs 32 (pipeline axis): a real 6-seed nextpnr-ecp5
   placement sweep (reusing already-synthesized netlists, no new
   synthesis needed) resolves EXP-0002's single-seed
   inconclusiveness. ACC_WIDTH=24 wins on both mean Fmax (+6.2%,
   180.71 vs 170.12 MHz) and seed-to-seed variance (~3.4x tighter),
   on top of its already-known resource advantage. DEC-0013
   recommends ACC_WIDTH=24 as the new default.

3. Stall %/utilization (scheduling/memory axes): testbench-only cycle
   counters added to tb_neural_multiprocessor.v (no RTL touched)
   close DEC-0011's deferred measurement gap with real data - shared
   PSRAM port 81.7% utilized, slot 0 95.2%, slot 1 65.2%, no
   conclusive evidence of harmful fixed-priority starvation at this
   scale.

The 10-milestone V2 roadmap (docs/v2-description.md §33) is now
complete end-to-end: real Verilator simulation, real Yosys synthesis,
real nextpnr-ecp5 place & route for every milestone, fully logged
(EXP-0001..EXP-0013, DEC-0001..DEC-0013, ERR-0001..ERR-0008) with no
invented results (§30) and V1 kept frozen and untouched throughout
(§1/§34).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 18:58:10 +02:00
co-authored by Claude Sonnet 5
parent 84794a3d25
commit 91bbbe2fe5
9 changed files with 367 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v2/logs/development.log
+32
View File
@@ -252,3 +252,35 @@ decision: vedi decisions.log DEC-0011 (stall %/utilization non
rimandata a M10 dove diventa direttamente utile).
next_action: M10 -- Optimization, sulla base dei dati reali raccolti
in M1-M9.
[2026-09-05] M10 -- Optimization (finale della roadmap V2, §33)
reason: roadmap M10 -- ottimizzare SOLO sulla base dei dati reali
raccolti in M1-M9, sugli assi: pipeline, P_IN, numero processor,
buffer, FIFO, scheduling, prefetch, routing, memoria.
result: tre azioni concrete, tutte basate su dati reali gia' raccolti
o su nuove misure reali mirate a colmare lacune gia' documentate:
(1) N_SLOTS=8 sintetizzato e P&R reale (92.63 MHz, PASS @80MHz,
DSP 64/72=88.9%) -- conferma e completa il limite gia' previsto da
DEC-0005, formalizzato come DEC-0012 (N_SLOTS=8 tetto pratico per
P_IN=8 su questo chip). (2) Sweep reale a 6 seed di piazzamento per
ACC_WIDTH 24 vs 32 (riusando i netlist gia' sintetizzati) -- risolve
l'inconcludenza a singolo seed di EXP-0002: ACC_WIDTH=24 vince sia
in Fmax medio (+6.2%) che in varianza (~3.4x piu' stretta),
formalizzato come DEC-0013 (ACC_WIDTH=24 nuovo default
raccomandato). (3) Strumentazione di conteggio cicli aggiunta al
testbench M8 (nessun RTL toccato) -- chiude la lacuna di
DEC-0011 con dati reali SIMULATED: porta PSRAM condivisa
utilizzata all'81.7%, slot0 al 95.2%, slot1 al 65.2% (nessuna prova
conclusiva di starvation dannosa su un test cosi' piccolo).
errors: nessuno.
decision: vedi decisions.log DEC-0012 e DEC-0013.
next_action: nessuna prevista dal mandato (§33 termina a M10) -- la
roadmap V2 a 10 milestone e' ora completa end-to-end, da M1 (singolo
neural_processor) a M9 (benchmark completo V1 vs V2) a M10 (risultati
di ottimizzazione basati sui dati). Elementi ancora aperti restano
tutti esplicitamente rimandati dalle proprie DEC entry (non
dimenticanze): riuso slot in dependency_manager (DEC-0008),
fairness dell'arbitro sotto contesa piu' estesa (DEC-0010), sweep
P_IN<8 per N_SLOTS ancora piu' alto (DEC-0012 alternativa #2), riuso
dei buffer M3 come cache condivisa (DEC-0009), strumentazione
stall%/utilization anche lato V1 (DEC-0011).