V2.0.0 hardware freeze - single SDRAM
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
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`timescale 1ns/1ps
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// ================================================================
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// FPGA-Neural V2 -- Slot Memory Arbiter (M8, docs/v2-description.md §15)
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//
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// Generic N_PORTS-way arbiter for dataflow_core.v's per-slot Memory
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// Backend Interface ports (docs/v2-description.md §15's "Memory
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// Manager -> Memory Backend Interface -> PSRAM Controller" layering),
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// funneling N_SLOTS independent memory_manager backend ports down to
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// the ONE physical PSRAM port a real chip actually has.
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//
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// WORD-level (16-bit, + lb_n/ub_n) post-M10 (decisions.log DEC-0015):
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// arbitrates hardware/v1/rtl/memory_interface.v's own port shape
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// directly (int8_memory_access.v is no longer in this datapath -- see
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// memory_manager.v/prefetch_engine.v's own headers for why).
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//
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// Inspired by (NOT copied from -- see hardware/v2/logs/decisions.log
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// DEC-0006's own note) hardware/v1/rtl/mem_arbiter.v: same
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// single-owner-until-ready-pulse discipline (a port, once granted,
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// holds the shared master port until ITS OWN transaction's m_ready
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// pulse, then releases -- no queuing/pipelining needed, since every
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// requester already issues a clean one-cycle req pulse matching
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// memory_interface's own contract). Generalized from V1's fixed
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// 4 named ports (A/B/C/D) to a parametric N_PORTS array, since
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// dataflow_core.v's N_SLOTS is itself a parameter.
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//
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// Priority: fixed, lowest port index wins on a cycle where more than
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// one port requests simultaneously while the arbiter is idle -- same
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// "first-found, lowest index" convention already used by
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// neural_director's free-slot scan and dependency_manager's
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// first-ready scan (not fairness-balanced; see decisions.log DEC-0010
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// for why that is an acceptable starting point, same rationale as
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// neural_director's own "first-free, not load-balanced" choice).
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//
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// IMPORTANT (found via real concurrent-slot simulation, see
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// hardware/v2/logs/errors.log ERR-0008): each port's own s_req is a
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// FIRE-AND-FORGET single-cycle pulse (prefetch_engine.v/
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// memory_manager.v's own backend protocol -- M4 verified it only
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// against a DIRECT 1:1 connection to the backend, which is always
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// free to accept it since there is exactly one requester). A naive
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// "grant only while req is live" arbiter silently DROPS a pulse that
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// arrives while the shared bus is owned by another port, hanging that
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// slot's prefetch/writeback forever. Every incoming s_req is therefore
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// LATCHED into a per-port `pending` register (capturing wr/addr/wdata/
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// lb_n/ub_n the same cycle) regardless of arbiter state -- the same
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// single-entry "queue, don't drop the request" idiom already used by
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// memory_manager's own pf_pending register (ERR-0006 fix #1). Grants
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// are drawn from `pending`, never from a live s_req directly, which
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// adds a uniform minimum 1-cycle latency to every transaction (a real,
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// measured cost of sharing one PSRAM port -- see timing.log/
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// benchmark.log EXP-0009) but never drops a request.
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// ================================================================
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module slot_mem_arbiter_wide #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 23,
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parameter N_PORTS = 4
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)(
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input wire clk,
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input wire rst,
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// ---- N_PORTS requester side (one per dataflow_core slot) ----
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input wire [N_PORTS-1:0] s_req,
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input wire [N_PORTS-1:0] s_wr,
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input wire [ADDR_WIDTH*N_PORTS-1:0] s_addr, // WORD address
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input wire [DATA_WIDTH*N_PORTS-1:0] s_wdata,
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input wire [N_PORTS-1:0] s_lb_n,
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input wire [N_PORTS-1:0] s_ub_n,
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output reg [DATA_WIDTH*N_PORTS-1:0] s_rdata,
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output reg [N_PORTS-1:0] s_ready,
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// ---- single shared master port (-> memory_interface.v) ----
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output reg m_req,
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output reg m_wr,
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output reg [ADDR_WIDTH-1:0] m_addr,
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output reg [DATA_WIDTH-1:0] m_wdata,
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output reg m_lb_n,
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output reg m_ub_n,
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input wire [DATA_WIDTH-1:0] m_rdata,
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input wire m_ready
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);
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localparam PIDXW = $clog2(N_PORTS+1);
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localparam OWNER_NONE = {PIDXW{1'b0}}; // 0 = no owner; port i owned = i+1
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reg [PIDXW-1:0] owner;
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// Per-port pending-request latch (see file header/ERR-0008): every
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// s_req pulse is captured here, regardless of arbiter state, so it
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// is never silently dropped while the bus is owned by another port.
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reg [N_PORTS-1:0] pending;
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reg [ADDR_WIDTH*N_PORTS-1:0] pending_addr;
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reg [DATA_WIDTH*N_PORTS-1:0] pending_wdata;
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reg [N_PORTS-1:0] pending_wr;
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reg [N_PORTS-1:0] pending_lb_n;
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reg [N_PORTS-1:0] pending_ub_n;
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// Fixed lowest-index-wins priority scan over PENDING requests (not
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// raw s_req -- see file header).
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reg [PIDXW-1:0] grant_idx;
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reg any_pending;
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integer ri;
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always @(*) begin
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grant_idx = {PIDXW{1'b0}};
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any_pending = 1'b0;
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for (ri = N_PORTS-1; ri >= 0; ri = ri - 1) begin
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if (pending[ri]) begin
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grant_idx = ri[PIDXW-1:0];
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any_pending = 1'b1;
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end
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end
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end
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integer pi;
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always @(posedge clk) begin
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if (rst) begin
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owner <= OWNER_NONE;
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pending <= {N_PORTS{1'b0}};
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pending_addr <= {(ADDR_WIDTH*N_PORTS){1'b0}};
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pending_wdata <= {(16*N_PORTS){1'b0}};
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pending_wr <= {N_PORTS{1'b0}};
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pending_lb_n <= {N_PORTS{1'b1}};
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pending_ub_n <= {N_PORTS{1'b1}};
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m_req <= 1'b0;
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m_wr <= 1'b0;
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m_addr <= {ADDR_WIDTH{1'b0}};
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m_wdata <= {DATA_WIDTH{1'b0}};
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m_lb_n <= 1'b1;
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m_ub_n <= 1'b1;
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s_rdata <= {(16*N_PORTS){1'b0}};
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s_ready <= {N_PORTS{1'b0}};
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end else begin
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m_req <= 1'b0;
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s_ready <= {N_PORTS{1'b0}};
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// Latch every incoming request pulse. Safe against a
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// same-cycle collision with the grant-clear write below:
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// a port only ever becomes grant_idx while its OWN pending
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// bit is already 1 (latched on an earlier cycle), and its
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// requester (memory_manager/prefetch_engine) never issues
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// a NEW s_req for that port until THIS transaction's
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// s_ready arrives -- so s_req[grant_idx] is guaranteed low
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// the cycle it is granted.
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for (pi = 0; pi < N_PORTS; pi = pi + 1) begin
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if (s_req[pi]) begin
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pending[pi] <= 1'b1;
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pending_wr[pi] <= s_wr[pi];
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pending_lb_n[pi] <= s_lb_n[pi];
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pending_ub_n[pi] <= s_ub_n[pi];
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pending_addr[pi*ADDR_WIDTH +: ADDR_WIDTH] <= s_addr[pi*ADDR_WIDTH +: ADDR_WIDTH];
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pending_wdata[pi*DATA_WIDTH +: DATA_WIDTH] <= s_wdata[pi*DATA_WIDTH +: DATA_WIDTH];
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end
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end
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if (owner == OWNER_NONE) begin
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if (any_pending) begin
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owner <= grant_idx + 1'b1;
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m_req <= 1'b1;
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m_wr <= pending_wr[grant_idx];
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m_lb_n <= pending_lb_n[grant_idx];
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m_ub_n <= pending_ub_n[grant_idx];
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m_addr <= pending_addr[grant_idx*ADDR_WIDTH +: ADDR_WIDTH];
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m_wdata <= pending_wdata[grant_idx*DATA_WIDTH +: DATA_WIDTH];
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pending[grant_idx] <= 1'b0;
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end
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end else begin
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if (m_ready) begin
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// owner is (port_index+1); vectorized single-write
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// so exactly one s_rdata/s_ready lane updates (no
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// per-bit loop last-write-wins hazard -- same class
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// of bug already hit/fixed at ERR-0006/M2/M6).
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for (pi = 0; pi < N_PORTS; pi = pi + 1) begin
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if (owner == pi[PIDXW-1:0] + 1'b1) begin
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s_rdata[pi*DATA_WIDTH +: DATA_WIDTH] <= m_rdata;
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s_ready[pi] <= 1'b1;
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end
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end
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owner <= OWNER_NONE;
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end
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end
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end
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end
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endmodule
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