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V2.0.0 hardware freeze - single SDRAM

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FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-06 13:39:55 +02:00
co-authored by Claude Sonnet 5
parent 5c9ec618d3
commit 8e014d8d49
208 changed files with 3000390 additions and 0 deletions
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hardware/v2/reports/step18_resources.csv
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config,n_slots,trellis_io,trellis_ff,trellis_comb,mult18x18d,dp16kd,trellis_ramw,classification
baseline,4,194,6215,5516,32,0,173,POST-P&R
pack128,4,194,6483,6106,32,0,189,POST-P&R
baseline,2,194,3724,3783,16,0,109,POST-SYNTHESIS (yosys pre-map, N=2 not separately P&R'd with full util report in STEP17)
pack128,2,194,not_captured,not_captured,16,0,not_captured,POST-SYNTHESIS (yosys ran; single-seed P&R for Fmax only)
1 config,n_slots,trellis_io,trellis_ff,trellis_comb,mult18x18d,dp16kd,trellis_ramw,classification
2 baseline,4,194,6215,5516,32,0,173,POST-P&R
3 pack128,4,194,6483,6106,32,0,189,POST-P&R
4 baseline,2,194,3724,3783,16,0,109,POST-SYNTHESIS (yosys pre-map, N=2 not separately P&R'd with full util report in STEP17)
5 pack128,2,194,not_captured,not_captured,16,0,not_captured,POST-SYNTHESIS (yosys ran; single-seed P&R for Fmax only)