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V2.0.0 hardware freeze - single SDRAM

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FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-06 13:39:55 +02:00
co-authored by Claude Sonnet 5
parent 5c9ec618d3
commit 8e014d8d49
208 changed files with 3000390 additions and 0 deletions
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hardware/v2/nms/synthesis/wt_packed_n8_t16/nextpnr.log
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Info: Logic utilisation before packing:
Info: Total LUT4s: 136/43848 0%
Info: logic LUTs: 40/43848 0%
Info: carry LUTs: 0/43848 0%
Info: RAM LUTs: 64/ 5481 1%
Info: RAMW LUTs: 32/10962 0%
Info: Total DFFs: 104/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 72 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x9978010a
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 104/ 43848 0%
Info: TRELLIS_COMB: 138/ 43848 0%
Info: TRELLIS_RAMW: 16/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 81 cells, random placement wirelen = 10077.
Info: at initial placer iter 0, wirelen = 1550
Info: at initial placer iter 1, wirelen = 1160
Info: at initial placer iter 2, wirelen = 1079
Info: at initial placer iter 3, wirelen = 1019
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info: at iteration #1, type ALL: wirelen solved = 1028, spread = 1264, legal = 1320; time = 0.00s
Info: at iteration #2, type ALL: wirelen solved = 1039, spread = 1256, legal = 1297; time = 0.00s
Info: HeAP Placer Time: 0.02s
Info: of which solving equations: 0.01s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 27, wirelen = 1297
Info: at iteration #5: temp = 0.000000, timing cost = 22, wirelen = 982
Info: at iteration #10: temp = 0.000000, timing cost = 20, wirelen = 982
Info: at iteration #12: temp = 0.000000, timing cost = 13, wirelen = 993
Info: SA placement time 0.03s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 363.37 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.33 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.05 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9748, 9848) |*+
Info: [ 9848, 9948) |*+
Info: [ 9948, 10048) |*+
Info: [ 10048, 10148) |+
Info: [ 10148, 10248) |+
Info: [ 10248, 10348) |
Info: [ 10348, 10448) |+
Info: [ 10448, 10548) |******+
Info: [ 10548, 10648) |************+
Info: [ 10648, 10748) |***************************+
Info: [ 10748, 10848) |********+
Info: [ 10848, 10948) |********************************+
Info: [ 10948, 11048) |***********************************************+
Info: [ 11048, 11148) |************************************************************
Info: [ 11148, 11248) |***********************************+
Info: [ 11248, 11348) |****+
Info: [ 11348, 11448) |******************+
Info: [ 11448, 11548) |***+
Info: [ 11548, 11648) |******+
Info: [ 11648, 11748) |**+
Info: Checksum: 0x74c6e3b4
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 932 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 116 875 | 116 875 | 73| 0.04 0.04|
Info: 1074 | 118 948 | 2 73 | 0| 0.02 0.06|
Info: Routing complete.
Info: Router1 time 0.06s
Info: Checksum: 0xc1b54c25
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source dut.GEN_SLOT[6].GEN_LANE[0].rd_data_reg_TRELLIS_FF_Q_6.Q
Info: routing 0.80 1.19 Net rd_data_flat[390] (24,31) -> (25,30)
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0_LUT4_Z_1.A
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_weight_packed.v:30.50-30.62
Info: logic 0.18 1.37 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0_LUT4_Z_1.F
Info: routing 0.77 2.14 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0[4] (25,30) -> (22,32)
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 2.34 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_BLUT_LUT4_Z.OFX
Info: routing 0.27 2.61 Net chk_TRELLIS_FF_Q_DI[6] (22,32) -> (22,32)
Info: Sink chk_TRELLIS_FF_Q_6.M
Info: setup 0.00 2.61 Source chk_TRELLIS_FF_Q_6.M
Info: 0.77 ns logic, 1.84 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source seed[4]$tr_io.O
Info: routing 3.23 3.23 Net seed[4]$TRELLIS_IO_IN (90,32) -> (24,29)
Info: Sink seed_LUT4_B_Z_LUT4_Z_2.B
Info: Defined in:
Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:14.23-14.27
Info: logic 0.18 3.41 Source seed_LUT4_B_Z_LUT4_Z_2.F
Info: routing 0.12 3.53 Net seed_LUT4_B_Z[4] (24,29) -> (24,29)
Info: Sink lfsr_TRELLIS_FF_Q_5.DI
Info: setup 0.00 3.53 Source lfsr_TRELLIS_FF_Q_5.DI
Info: 0.18 ns logic, 3.35 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_2.Q
Info: routing 2.92 3.31 Net checksum[2]$TRELLIS_IO_OUT (27,32) -> (90,32)
Info: Sink checksum[2]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 2.92 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 383.73 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.53 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.31 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9894, 9989) |+
Info: [ 9989, 10084) |*+
Info: [ 10084, 10179) |+
Info: [ 10179, 10274) |**+
Info: [ 10274, 10369) |
Info: [ 10369, 10464) |
Info: [ 10464, 10559) |
Info: [ 10559, 10654) |***********+
Info: [ 10654, 10749) |*****************+
Info: [ 10749, 10844) |************+
Info: [ 10844, 10939) |***************+
Info: [ 10939, 11034) |*******************************+
Info: [ 11034, 11129) |***********************************+
Info: [ 11129, 11224) |****************************************************+
Info: [ 11224, 11319) |************************************+
Info: [ 11319, 11414) |************************************************************
Info: [ 11414, 11509) |******************+
Info: [ 11509, 11604) |**************+
Info: [ 11604, 11699) |****+
Info: [ 11699, 11794) |***+
Info: Program finished normally.