V2.0.0 hardware freeze - single SDRAM
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 42/43848 0%
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Info: logic LUTs: 42/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 56/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 16 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0xb4abc577
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 4/ 108 3%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 56/ 43848 0%
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Info: TRELLIS_COMB: 44/ 43848 0%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 75 cells, random placement wirelen = 7922.
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Info: at initial placer iter 0, wirelen = 1177
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Info: at initial placer iter 1, wirelen = 1085
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Info: at initial placer iter 2, wirelen = 1038
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Info: at initial placer iter 3, wirelen = 1014
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Info: Running main analytical placer, max placement attempts per cell = 10000.
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Info: at iteration #1, type ALL: wirelen solved = 1012, spread = 1503, legal = 2089; time = 0.00s
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Info: at iteration #2, type ALL: wirelen solved = 1002, spread = 1408, legal = 2121; time = 0.00s
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Info: at iteration #3, type ALL: wirelen solved = 1045, spread = 1417, legal = 2123; time = 0.00s
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Info: at iteration #4, type ALL: wirelen solved = 998, spread = 1452, legal = 2320; time = 0.00s
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Info: at iteration #5, type ALL: wirelen solved = 1010, spread = 1419, legal = 2320; time = 0.00s
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Info: at iteration #6, type ALL: wirelen solved = 1012, spread = 1464, legal = 2353; time = 0.00s
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Info: HeAP Placer Time: 0.03s
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Info: of which solving equations: 0.00s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 31, wirelen = 2089
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Info: at iteration #5: temp = 0.000000, timing cost = 31, wirelen = 1310
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Info: at iteration #10: temp = 0.000000, timing cost = 31, wirelen = 1292
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Info: at iteration #15: temp = 0.000000, timing cost = 28, wirelen = 1285
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Info: at iteration #20: temp = 0.000000, timing cost = 27, wirelen = 1236
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Info: at iteration #20: temp = 0.000000, timing cost = 27, wirelen = 1236
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Info: SA placement time 0.02s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 159.67 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.95 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.35 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 6237, 6512) |******
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Info: [ 6512, 6787) |
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Info: [ 6787, 7062) |*
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Info: [ 7062, 7337) |*
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Info: [ 7337, 7612) |
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Info: [ 7612, 7887) |
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Info: [ 7887, 8162) |*
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Info: [ 8162, 8437) |
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Info: [ 8437, 8712) |
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Info: [ 8712, 8987) |
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Info: [ 8987, 9262) |
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Info: [ 9262, 9537) |
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Info: [ 9537, 9812) |
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Info: [ 9812, 10087) |**
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Info: [ 10087, 10362) |****
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Info: [ 10362, 10637) |*************
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Info: [ 10637, 10912) |**************************
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Info: [ 10912, 11187) |**********************
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Info: [ 11187, 11462) |********************************
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Info: [ 11462, 11737) |*******************************
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Info: Checksum: 0x22f96075
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 317 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 440 | 117 316 | 117 316 | 0| 0.07 0.07|
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Info: Routing complete.
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Info: Router1 time 0.07s
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Info: Checksum: 0xcc51a16f
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 4.10 4.10 Source dut.GEN_SLOT[1].GEN_LANE[0].mem.0.0.DOA0
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Info: routing 1.43 5.53 Net rd_data_flat[64] (13,34) -> (9,25)
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Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C.A
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Info: Defined in:
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Info: hardware/v2/nms/rtl/nms_weight_packed.v:30.50-30.62
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Info: logic 0.18 5.71 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C.F
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Info: routing 0.32 6.03 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z[2] (9,25) -> (9,25)
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Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z_LUT4_D.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 6.21 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z_LUT4_D.F
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Info: routing 0.12 6.33 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z_LUT4_D_Z[0] (9,25) -> (9,25)
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Info: Sink chk_TRELLIS_FF_Q_2.DI
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Info: setup 0.00 6.33 Source chk_TRELLIS_FF_Q_2.DI
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Info: 4.46 ns logic, 1.87 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source seed[7]$tr_io.O
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Info: routing 3.88 3.88 Net seed[7]$TRELLIS_IO_IN (90,35) -> (12,33)
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Info: Sink seed_LUT4_B_Z_LUT4_Z.B
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:14.23-14.27
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Info: logic 0.18 4.06 Source seed_LUT4_B_Z_LUT4_Z.F
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Info: routing 0.12 4.18 Net seed_LUT4_B_Z[7] (12,33) -> (12,33)
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Info: Sink lfsr_TRELLIS_FF_Q_8.DI
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Info: setup 0.00 4.18 Source lfsr_TRELLIS_FF_Q_8.DI
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Info: 0.18 ns logic, 4.00 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_7.Q
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Info: routing 3.72 4.11 Net checksum[5]$TRELLIS_IO_OUT (8,33) -> (90,32)
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Info: Sink checksum[5]$tr_io.I
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: 0.40 ns logic, 3.72 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 157.98 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.18 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.11 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 6170, 6455) |***
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Info: [ 6455, 6740) |*****
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Info: [ 6740, 7025) |
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Info: [ 7025, 7310) |
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Info: [ 7310, 7595) |
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Info: [ 7595, 7880) |
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Info: [ 7880, 8165) |
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Info: [ 8165, 8450) |
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Info: [ 8450, 8735) |
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Info: [ 8735, 9020) |
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Info: [ 9020, 9305) |*
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Info: [ 9305, 9590) |
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Info: [ 9590, 9875) |
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Info: [ 9875, 10160) |
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Info: [ 10160, 10445) |*
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Info: [ 10445, 10730) |********
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Info: [ 10730, 11015) |********************************
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Info: [ 11015, 11300) |**********************************************
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Info: [ 11300, 11585) |**********************
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Info: [ 11585, 11870) |*********************
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Info: Program finished normally.
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