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V2.0.0 hardware freeze - single SDRAM

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FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-06 13:39:55 +02:00
co-authored by Claude Sonnet 5
parent 5c9ec618d3
commit 8e014d8d49
208 changed files with 3000390 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v2/nms/synthesis/nms_multiproc_n2/nextpnr.log
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Info: Logic utilisation before packing:
Info: Total LUT4s: 3134/43848 7%
Info: logic LUTs: 1948/43848 4%
Info: carry LUTs: 532/43848 1%
Info: RAM LUTs: 436/ 5481 7%
Info: RAMW LUTs: 218/10962 1%
Info: Total DFFs: 3522/43848 8%
Info: Packing IOs..
Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 1574 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x402d222a
Info: Device utilisation:
Info: TRELLIS_IO: 157/ 245 64%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 16/ 72 22%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 3522/ 43848 8%
Info: TRELLIS_COMB: 3268/ 43848 7%
Info: TRELLIS_RAMW: 109/ 5481 1%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 3884 cells, random placement wirelen = 321215.
Info: at initial placer iter 0, wirelen = 17565
Info: at initial placer iter 1, wirelen = 14264
Info: at initial placer iter 2, wirelen = 13173
Info: at initial placer iter 3, wirelen = 12611
Info: Running main analytical placer, max placement attempts per cell = 6253416.
Info: at iteration #1, type ALL: wirelen solved = 12338, spread = 45332, legal = 50715; time = 0.07s
Info: at iteration #2, type ALL: wirelen solved = 15231, spread = 37486, legal = 42468; time = 0.06s
Info: at iteration #3, type ALL: wirelen solved = 16968, spread = 32224, legal = 37720; time = 0.05s
Info: at iteration #4, type ALL: wirelen solved = 17739, spread = 30435, legal = 35388; time = 0.05s
Info: at iteration #5, type ALL: wirelen solved = 18593, spread = 29680, legal = 35283; time = 0.05s
Info: at iteration #6, type ALL: wirelen solved = 19532, spread = 28805, legal = 34860; time = 0.05s
Info: at iteration #7, type ALL: wirelen solved = 20152, spread = 28933, legal = 33241; time = 0.04s
Info: at iteration #8, type ALL: wirelen solved = 20744, spread = 28754, legal = 34006; time = 0.05s
Info: at iteration #9, type ALL: wirelen solved = 20768, spread = 28888, legal = 34571; time = 0.05s
Info: at iteration #10, type ALL: wirelen solved = 20842, spread = 29598, legal = 34991; time = 0.05s
Info: at iteration #11, type ALL: wirelen solved = 21269, spread = 32317, legal = 35678; time = 0.04s
Info: at iteration #12, type ALL: wirelen solved = 21827, spread = 32505, legal = 36242; time = 0.04s
Info: HeAP Placer Time: 0.90s
Info: of which solving equations: 0.51s
Info: of which spreading cells: 0.08s
Info: of which strict legalisation: 0.15s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 194, wirelen = 33241
Info: at iteration #5: temp = 0.000000, timing cost = 238, wirelen = 30937
Info: at iteration #10: temp = 0.000000, timing cost = 253, wirelen = 30039
Info: at iteration #15: temp = 0.000000, timing cost = 264, wirelen = 29759
Info: at iteration #20: temp = 0.000000, timing cost = 235, wirelen = 29657
Info: at iteration #21: temp = 0.000000, timing cost = 251, wirelen = 29652
Info: SA placement time 1.76s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 89.09 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> <async> : 16.31 ns
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 16.90 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.63 ns
Info: Slack histogram:
Info: legend: * represents 23 endpoint(s)
Info: + represents [1,23) endpoint(s)
Info: [ 1276, 1809) |*+
Info: [ 1809, 2342) |**+
Info: [ 2342, 2875) |****+
Info: [ 2875, 3408) |***********+
Info: [ 3408, 3941) |**+
Info: [ 3941, 4474) |**+
Info: [ 4474, 5007) |**+
Info: [ 5007, 5540) |*****+
Info: [ 5540, 6073) |*****+
Info: [ 6073, 6606) |****+
Info: [ 6606, 7139) |*****+
Info: [ 7139, 7672) |************+
Info: [ 7672, 8205) |****************+
Info: [ 8205, 8738) |***************************+
Info: [ 8738, 9271) |***********************************+
Info: [ 9271, 9804) |***************************************+
Info: [ 9804, 10337) |************************************************************
Info: [ 10337, 10870) |***************************************+
Info: [ 10870, 11403) |***************************************+
Info: [ 11403, 11936) |******************************+
Info: Checksum: 0x7631c1a6
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 18985 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 88 911 | 88 911 | 18087| 0.24 0.24|
Info: 2000 | 148 1851 | 60 940 | 17194| 0.13 0.38|
Info: 3000 | 201 2798 | 53 947 | 16254| 0.10 0.47|
Info: 4000 | 268 3731 | 67 933 | 15338| 0.08 0.55|
Info: 5000 | 393 4606 | 125 875 | 14481| 0.09 0.64|
Info: 6000 | 469 5513 | 76 907 | 13559| 0.08 0.72|
Info: 7000 | 607 6368 | 138 855 | 12713| 0.09 0.81|
Info: 8000 | 696 7260 | 89 892 | 11813| 0.08 0.89|
Info: 9000 | 858 8083 | 162 823 | 10987| 0.10 1.00|
Info: 10000 | 973 8955 | 115 872 | 10113| 0.06 1.06|
Info: 11000 | 1062 9840 | 89 885 | 9204| 0.07 1.13|
Info: 12000 | 1119 10737 | 57 897 | 8261| 0.07 1.21|
Info: 13000 | 1169 11607 | 50 870 | 7312| 0.06 1.27|
Info: 14000 | 1215 12483 | 46 876 | 6366| 0.08 1.35|
Info: 15000 | 1259 13384 | 44 901 | 5417| 0.07 1.42|
Info: 16000 | 1318 14284 | 59 900 | 4487| 0.07 1.49|
Info: 17000 | 1386 15213 | 68 929 | 3645| 0.08 1.57|
Info: 18000 | 1499 16100 | 113 887 | 2793| 0.10 1.67|
Info: 19000 | 1578 16990 | 79 890 | 1876| 0.20 1.87|
Info: 20000 | 1645 17891 | 67 901 | 959| 0.20 2.07|
Info: 21000 | 1773 18730 | 128 839 | 136| 0.36 2.42|
Info: 21172 | 1806 18861 | 33 131 | 0| 0.08 2.50|
Info: Routing complete.
Info: Router1 time 2.50s
Info: Checksum: 0x82e9e49c
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_act_fill.resident_tag_TRELLIS_FF_Q_15.Q
Info: routing 0.67 1.06 Net u_dataflow_core.act_resident_tag[15] (26,37) -> (26,36)
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.24 Source u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z.F
Info: routing 0.54 1.78 Net u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_SD[6] (26,36) -> (26,35)
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 1.98 Source u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.62 2.59 Net u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D[2] (26,35) -> (26,37)
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.77 Source u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z.F
Info: routing 0.55 3.32 Net u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D[3] (26,37) -> (22,37)
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.50 Source u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z.F
Info: routing 0.80 4.30 Net u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z[4] (22,37) -> (24,40)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.48 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info: routing 0.31 4.79 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_D[1] (24,40) -> (24,40)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.97 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z.F
Info: routing 0.84 5.82 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C[1] (24,40) -> (24,38)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 6.17 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
Info: routing 0.00 6.17 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (24,38) -> (24,38)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
Info: logic 0.00 6.17 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
Info: routing 0.00 6.17 Net $nextpnr_CCU2C_43$CIN (24,38) -> (24,38)
Info: Sink $nextpnr_CCU2C_43$CCU2_COMB0.FCI
Info: logic 0.33 6.50 Source $nextpnr_CCU2C_43$CCU2_COMB0.F
Info: routing 0.73 7.22 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B0[4] (24,38) -> (23,40)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 7.42 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.81 8.23 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (23,40) -> (23,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: logic 0.35 8.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 8.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (23,39) -> (23,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 8.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 8.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (23,39) -> (24,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 8.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 8.64 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (24,39) -> (24,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 8.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 8.64 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (24,39) -> (24,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 8.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 8.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (24,39) -> (24,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 8.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 8.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (24,39) -> (24,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 8.75 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 8.75 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (24,39) -> (24,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 8.75 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 8.75 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (24,39) -> (24,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 8.81 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 8.81 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (24,39) -> (24,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 8.81 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 8.81 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN (24,39) -> (25,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 8.86 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 8.86 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (25,39) -> (25,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 8.86 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 8.86 Net $nextpnr_CCU2C_37$CIN (25,39) -> (25,39)
Info: Sink $nextpnr_CCU2C_37$CCU2_COMB0.FCI
Info: logic 0.33 9.19 Source $nextpnr_CCU2C_37$CCU2_COMB0.F
Info: routing 0.78 9.97 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR[2] (25,39) -> (24,35)
Info: Sink u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 10.15 Source u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.F
Info: routing 0.59 10.74 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B_Z (24,35) -> (25,36)
Info: Sink u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_21.CE
Info: setup 0.00 10.74 Source u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_21.CE
Info: 3.51 ns logic, 7.23 ns routing
Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: type curr total name
Info: source 0.00 0.00 Source reg_node_id[0]$tr_io.O
Info: routing 4.57 4.57 Net reg_node_id[0]$TRELLIS_IO_IN (90,50) -> (5,37)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_LUT4_Z_1.D
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
Info: logic 0.18 4.75 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_LUT4_Z_1.F
Info: routing 1.17 5.92 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C[2] (5,37) -> (5,38)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.10 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
Info: routing 0.75 6.86 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[2] (5,38) -> (7,37)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.04 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
Info: routing 0.38 7.42 Net reg_ready_PFUMX_Z_C0[2] (7,37) -> (7,37)
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.31 7.72 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 3.95 11.67 Net reg_ready$TRELLIS_IO_OUT (7,37) -> (90,35)
Info: Sink reg_ready$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
Info: 0.85 ns logic, 10.83 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source reg_node_id[0]$tr_io.O
Info: routing 4.57 4.57 Net reg_node_id[0]$TRELLIS_IO_IN (90,50) -> (5,37)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_LUT4_Z_1.D
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
Info: logic 0.18 4.75 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_LUT4_Z_1.F
Info: routing 1.17 5.92 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C[2] (5,37) -> (5,38)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.10 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
Info: routing 0.75 6.86 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[2] (5,38) -> (7,37)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.04 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
Info: routing 0.38 7.42 Net reg_ready_PFUMX_Z_C0[2] (7,37) -> (7,37)
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.31 7.72 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.79 8.52 Net reg_ready$TRELLIS_IO_OUT (7,37) -> (15,35)
Info: Sink reg_valid_LUT4_B.D
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
Info: logic 0.18 8.69 Source reg_valid_LUT4_B.F
Info: routing 1.02 9.72 Net reg_valid_LUT4_B_Z[2] (15,35) -> (5,33)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.90 Source u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.F
Info: routing 0.58 10.48 Net u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D[2] (5,33) -> (5,31)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_D_2.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 10.66 Source u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_D_2.F
Info: routing 0.20 10.86 Net u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_D_2_Z[1] (5,31) -> (5,31)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[47]_LUT4_A_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.04 Source u_dataflow_core.u_dep_mgr.node_producer_ids[47]_LUT4_A_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z.F
Info: routing 0.71 11.75 Net u_dataflow_core.u_dep_mgr.node_producer_ids[47]_LUT4_A_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] (5,31) -> (6,33)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q_CE_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 11.94 Source u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q_CE_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.54 12.48 Net u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q_CE (6,33) -> (5,35)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q.CE
Info: setup 0.00 12.48 Source u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q.CE
Info: 1.76 ns logic, 10.72 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_dep_mgr.node_state[7]_TRELLIS_FF_Q.Q
Info: routing 0.50 0.89 Net u_dataflow_core.u_dep_mgr.first_ready_idx_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_C0_PFUMX_Z_C0_PFUMX_Z_C0[3] (4,39) -> (4,39)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_C0_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.07 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_C0_LUT4_Z.F
Info: routing 0.61 1.68 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_C0[4] (4,39) -> (8,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 1.87 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.48 2.35 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C[4] (8,40) -> (6,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 2.55 Source reg_ready_PFUMX_Z_C0_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.55 3.10 Net reg_ready_PFUMX_Z_C0_LUT4_Z_2_D[2] (6,40) -> (6,37)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_2.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.28 Source reg_ready_PFUMX_Z_C0_LUT4_Z_2.F
Info: routing 0.34 3.62 Net reg_ready_PFUMX_Z_C0[4] (6,37) -> (7,37)
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 3.82 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 3.95 7.76 Net reg_ready$TRELLIS_IO_OUT (7,37) -> (90,35)
Info: Sink reg_ready$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
Info: 1.33 ns logic, 6.43 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 93.10 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> <async> : 11.67 ns
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.48 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.76 ns
Info: Slack histogram:
Info: legend: * represents 25 endpoint(s)
Info: + represents [1,25) endpoint(s)
Info: [ 1759, 2261) |+
Info: [ 2261, 2763) |+
Info: [ 2763, 3265) |
Info: [ 3265, 3767) |
Info: [ 3767, 4269) |*+
Info: [ 4269, 4771) |*****+
Info: [ 4771, 5273) |*******+
Info: [ 5273, 5775) |******+
Info: [ 5775, 6277) |*******+
Info: [ 6277, 6779) |*********+
Info: [ 6779, 7281) |*****+
Info: [ 7281, 7783) |***+
Info: [ 7783, 8285) |*******+
Info: [ 8285, 8787) |********************+
Info: [ 8787, 9289) |**************************+
Info: [ 9289, 9791) |*******************************+
Info: [ 9791, 10293) |************************************+
Info: [ 10293, 10795) |****************************************************+
Info: [ 10795, 11297) |************************************************************
Info: [ 11297, 11799) |*******************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n2/top.config
+99019
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hardware/v2/nms/synthesis/nms_multiproc_n2/top.json
+213283
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hardware/v2/nms/synthesis/nms_multiproc_n2/yosys.log
+13498
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