V2.0.0 hardware freeze - single SDRAM

FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/nms/synthesis/harness_nms_weight_packed.v

@@ -0,0 +1,53 @@
+// ================================================================
+// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
+// Same pattern as harness_nms_weight_direct.v, for nms_weight_packed.v.
+// ================================================================
+module harness_nms_weight_packed #(
+    parameter DATA_WIDTH = 8,
+    parameter P_IN       = 8,
+    parameter N_SLOTS    = 4,
+    parameter MAX_TILES  = 16,
+    parameter TIW        = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES)
+)(
+    input  wire clk,
+    input  wire rst,
+    input  wire [7:0] seed,
+    output wire [7:0] checksum
+);
+
+    reg [31:0] lfsr;
+    always @(posedge clk) begin
+        if (rst) lfsr <= {24'h0, seed} | 32'h1;
+        else     lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
+    end
+
+    wire [N_SLOTS-1:0] fill_we = lfsr[N_SLOTS-1:0];
+    wire [N_SLOTS*TIW-1:0] fill_addr_flat = {(N_SLOTS*TIW/32+1){lfsr}};
+    wire [N_SLOTS*DATA_WIDTH*P_IN-1:0] fill_data_flat = {(N_SLOTS*DATA_WIDTH*P_IN/32+1){lfsr}};
+    wire [N_SLOTS-1:0] rd_en = lfsr[N_SLOTS-1:0];
+    wire [N_SLOTS*TIW-1:0] rd_addr_flat = {(N_SLOTS*TIW/32+1){lfsr}};
+    wire [N_SLOTS*DATA_WIDTH*P_IN-1:0] rd_data_flat;
+
+    nms_weight_packed #(
+        .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .N_SLOTS(N_SLOTS), .MAX_TILES(MAX_TILES)
+    ) dut (
+        .clk(clk), .rst(rst),
+        .fill_we(fill_we), .fill_addr_flat(fill_addr_flat), .fill_data_flat(fill_data_flat),
+        .rd_en(rd_en), .rd_addr_flat(rd_addr_flat), .rd_data_flat(rd_data_flat)
+    );
+
+    integer k;
+    reg [7:0] chk, chk_next;
+    always @(posedge clk) begin
+        if (rst) begin
+            chk <= 8'h0;
+        end else begin
+            chk_next = chk;
+            for (k = 0; k < N_SLOTS; k = k + 1)
+                chk_next = chk_next ^ rd_data_flat[k*DATA_WIDTH*P_IN +: 8];
+            chk <= chk_next;
+        end
+    end
+    assign checksum = chk;
+
+endmodule