V2.0.0 hardware freeze - single SDRAM
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 72/43848 0%
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Info: logic LUTs: 24/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 32/ 5481 0%
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Info: RAMW LUTs: 16/10962 0%
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Info: Total DFFs: 72/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 40 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x12571da3
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 72/ 43848 0%
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Info: TRELLIS_COMB: 74/ 43848 0%
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Info: TRELLIS_RAMW: 8/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 57 cells, random placement wirelen = 5943.
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Info: at initial placer iter 0, wirelen = 1261
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Info: at initial placer iter 1, wirelen = 997
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Info: at initial placer iter 2, wirelen = 970
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Info: at initial placer iter 3, wirelen = 960
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Info: Running main analytical placer, max placement attempts per cell = 10000.
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Info: at iteration #1, type ALL: wirelen solved = 945, spread = 1040, legal = 1090; time = 0.00s
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Info: HeAP Placer Time: 0.02s
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Info: of which solving equations: 0.00s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 24, wirelen = 1090
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Info: at iteration #5: temp = 0.000000, timing cost = 19, wirelen = 869
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Info: at iteration #10: temp = 0.000000, timing cost = 18, wirelen = 859
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Info: at iteration #12: temp = 0.000000, timing cost = 15, wirelen = 849
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Info: SA placement time 0.02s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 410.34 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.84 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.67 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10063, 10147) |*
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Info: [ 10147, 10231) |**
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Info: [ 10231, 10315) |***
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Info: [ 10315, 10399) |
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Info: [ 10399, 10483) |**
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Info: [ 10483, 10567) |
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Info: [ 10567, 10651) |*****
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Info: [ 10651, 10735) |
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Info: [ 10735, 10819) |****
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Info: [ 10819, 10903) |******************************
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Info: [ 10903, 10987) |************
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Info: [ 10987, 11071) |*************************
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Info: [ 11071, 11155) |********************************************************
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Info: [ 11155, 11239) |***************************************************
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Info: [ 11239, 11323) |*****
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Info: [ 11323, 11407) |***************
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Info: [ 11407, 11491) |*************************
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Info: [ 11491, 11575) |*
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Info: [ 11575, 11659) |************
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Info: [ 11659, 11743) |***********
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Info: Checksum: 0x1eb2f5c5
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 531 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 621 | 86 527 | 86 527 | 0| 0.06 0.06|
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Info: Routing complete.
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Info: Router1 time 0.06s
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Info: Checksum: 0xb377ad17
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source dut.GEN_COPY[3].rd_data_reg_TRELLIS_FF_Q_1.Q
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Info: routing 0.92 1.32 Net rd_data_flat[199] (35,36) -> (36,38)
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Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.A
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Info: Defined in:
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Info: hardware/v2/nms/rtl/nms_activation_replicated.v:34.50-34.62
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Info: logic 0.31 1.62 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.OFX
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Info: routing 0.35 1.98 Net chk_TRELLIS_FF_Q_DI[7] (36,38) -> (36,38)
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Info: Sink chk_TRELLIS_FF_Q_7.M
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Info: setup 0.00 1.98 Source chk_TRELLIS_FF_Q_7.M
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Info: 0.70 ns logic, 1.28 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source seed[6]$tr_io.O
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Info: routing 2.78 2.78 Net seed[6]$TRELLIS_IO_IN (42,0) -> (36,37)
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Info: Sink seed_LUT4_B_Z_LUT4_Z_3.B
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:23.23-23.27
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Info: logic 0.18 2.96 Source seed_LUT4_B_Z_LUT4_Z_3.F
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Info: routing 0.12 3.07 Net seed_LUT4_B_Z[6] (36,37) -> (36,37)
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Info: Sink lfsr_TRELLIS_FF_Q_1.DI
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Info: setup 0.00 3.07 Source lfsr_TRELLIS_FF_Q_1.DI
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Info: 0.18 ns logic, 2.89 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_4.Q
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Info: routing 2.83 3.22 Net checksum[4]$TRELLIS_IO_OUT (34,37) -> (90,38)
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Info: Sink checksum[4]$tr_io.I
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:50.15-50.18
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Info: 0.40 ns logic, 2.83 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 505.82 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.07 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.22 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10523, 10587) |*
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Info: [ 10587, 10651) |******
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Info: [ 10651, 10715) |***********
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Info: [ 10715, 10779) |*******
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Info: [ 10779, 10843) |*********
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Info: [ 10843, 10907) |************
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Info: [ 10907, 10971) |******
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Info: [ 10971, 11035) |*******************
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Info: [ 11035, 11099) |**
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Info: [ 11099, 11163) |**************
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Info: [ 11163, 11227) |**************************************************
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Info: [ 11227, 11291) |***********************
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Info: [ 11291, 11355) |***************************************
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Info: [ 11355, 11419) |*********
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Info: [ 11419, 11483) |***
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Info: [ 11483, 11547) |****************
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Info: [ 11547, 11611) |****************
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Info: [ 11611, 11675) |**
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Info: [ 11675, 11739) |*******
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Info: [ 11739, 11803) |********
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Info: Program finished normally.
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