V2.0.0 hardware freeze - single SDRAM
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 1666/43848 3%
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Info: logic LUTs: 1618/43848 3%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 32/ 5481 0%
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Info: RAMW LUTs: 16/10962 0%
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Info: Total DFFs: 102/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 59 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0xee0ee104
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 102/ 43848 0%
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Info: TRELLIS_COMB: 1667/ 43848 3%
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Info: TRELLIS_RAMW: 8/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 1097 cells, random placement wirelen = 78612.
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Info: at initial placer iter 0, wirelen = 1786
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Info: at initial placer iter 1, wirelen = 1138
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Info: at initial placer iter 2, wirelen = 1117
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Info: at initial placer iter 3, wirelen = 1091
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Info: Running main analytical placer, max placement attempts per cell = 403202.
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Info: at iteration #1, type ALL: wirelen solved = 1023, spread = 6894, legal = 6975; time = 0.01s
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Info: at iteration #2, type ALL: wirelen solved = 1803, spread = 5497, legal = 5610; time = 0.01s
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Info: at iteration #3, type ALL: wirelen solved = 2036, spread = 5487, legal = 5600; time = 0.01s
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Info: at iteration #4, type ALL: wirelen solved = 2159, spread = 5011, legal = 5100; time = 0.01s
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Info: at iteration #5, type ALL: wirelen solved = 2451, spread = 4995, legal = 5256; time = 0.01s
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Info: at iteration #6, type ALL: wirelen solved = 2448, spread = 4778, legal = 4923; time = 0.01s
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Info: at iteration #7, type ALL: wirelen solved = 2634, spread = 4937, legal = 5040; time = 0.01s
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Info: at iteration #8, type ALL: wirelen solved = 2796, spread = 4945, legal = 5024; time = 0.01s
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Info: at iteration #9, type ALL: wirelen solved = 2886, spread = 4809, legal = 4849; time = 0.01s
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Info: at iteration #10, type ALL: wirelen solved = 2882, spread = 5015, legal = 5171; time = 0.01s
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Info: at iteration #11, type ALL: wirelen solved = 3179, spread = 4938, legal = 5108; time = 0.01s
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Info: at iteration #12, type ALL: wirelen solved = 3245, spread = 5203, legal = 5304; time = 0.01s
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Info: at iteration #13, type ALL: wirelen solved = 3413, spread = 5138, legal = 5319; time = 0.01s
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Info: at iteration #14, type ALL: wirelen solved = 3518, spread = 4959, legal = 5121; time = 0.01s
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Info: HeAP Placer Time: 0.24s
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Info: of which solving equations: 0.16s
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Info: of which spreading cells: 0.03s
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Info: of which strict legalisation: 0.01s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 810, wirelen = 4849
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Info: at iteration #5: temp = 0.000000, timing cost = 521, wirelen = 4141
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Info: at iteration #10: temp = 0.000000, timing cost = 596, wirelen = 4004
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Info: at iteration #15: temp = 0.000000, timing cost = 497, wirelen = 3865
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Info: at iteration #18: temp = 0.000000, timing cost = 461, wirelen = 3826
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Info: SA placement time 0.42s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 92.60 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.95 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.16 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 1701, 2197) |*+
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Info: [ 2197, 2693) |**+
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Info: [ 2693, 3189) |+
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Info: [ 3189, 3685) |**+
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Info: [ 3685, 4181) |******+
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Info: [ 4181, 4677) |***+
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Info: [ 4677, 5173) |*+
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Info: [ 5173, 5669) |*+
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Info: [ 5669, 6165) |*+
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Info: [ 6165, 6661) |*+
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Info: [ 6661, 7157) |*+
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Info: [ 7157, 7653) |*+
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Info: [ 7653, 8149) |*+
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Info: [ 8149, 8645) |
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Info: [ 8645, 9141) |
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Info: [ 9141, 9637) |
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Info: [ 9637, 10133) |******+
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Info: [ 10133, 10629) |************************************************************
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Info: [ 10629, 11125) |*******************************************************+
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Info: [ 11125, 11621) |********+
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Info: Checksum: 0x23829f4c
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 6315 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 189 810 | 189 810 | 5529| 0.08 0.08|
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Info: 2000 | 472 1527 | 283 717 | 4856| 0.08 0.15|
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Info: 3000 | 838 2161 | 366 634 | 4315| 0.08 0.24|
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Info: 4000 | 1186 2813 | 348 652 | 3831| 0.08 0.32|
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Info: 5000 | 1568 3431 | 382 618 | 3324| 0.08 0.39|
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Info: 6000 | 1956 4043 | 388 612 | 2835| 0.08 0.47|
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Info: 7000 | 2224 4661 | 268 618 | 2150| 0.05 0.52|
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Info: 8000 | 2593 5211 | 369 550 | 1542| 0.06 0.58|
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Info: 9000 | 2889 5887 | 296 676 | 866| 0.06 0.63|
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Info: 9961 | 2984 6557 | 95 670 | 0| 0.08 0.72|
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Info: Routing complete.
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Info: Router1 time 0.72s
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Info: Checksum: 0xf9e6caa1
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source dut.rr_ptr[1]_TRELLIS_FF_Q_2.Q
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Info: routing 0.88 1.27 Net dut.rr_ptr[1][2] (7,16) -> (5,15)
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Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_2_C_LUT4_Z.B
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 1.46 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_2_C_LUT4_Z.F
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Info: routing 0.75 2.21 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_1_D_LUT4_D_Z_LUT4_D_Z_PFUMX_BLUT_Z_PFUMX_Z_C0[1] (5,15) -> (5,12)
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Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_1_D_PFUMX_C0_Z_L6MUX21_D1_Z_LUT4_Z.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 2.39 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_1_D_PFUMX_C0_Z_L6MUX21_D1_Z_LUT4_Z.F
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Info: routing 0.47 2.86 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_1_D_PFUMX_C0_Z_L6MUX21_D1_Z[3] (5,12) -> (5,12)
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Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_ALUT_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 3.04 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_ALUT_LUT4_Z.F
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Info: routing 0.00 3.04 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_ALUT (5,12) -> (5,12)
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Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_BLUT_LUT4_Z.F1
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
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Info: logic 0.13 3.16 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_BLUT_LUT4_Z.OFX
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Info: routing 0.82 3.99 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D[2] (5,12) -> (4,14)
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Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 4.17 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1.F
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Info: routing 0.53 4.70 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z[4] (4,14) -> (4,16)
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Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 4.89 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
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Info: routing 0.00 4.89 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1 (4,16) -> (4,16)
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Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
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Info: logic 0.18 5.07 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
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Info: routing 0.50 5.57 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z[0] (4,16) -> (4,18)
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Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 5.75 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z.F
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Info: routing 0.33 6.07 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] (4,18) -> (4,18)
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Info: Sink dut.win_valid[1]_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 6.25 Source dut.win_valid[1]_LUT4_Z.F
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Info: routing 0.56 6.81 Net dut.win_valid[1] (4,18) -> (3,17)
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Info: Sink dut.win_valid[1]_LUT4_A.A
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 6.99 Source dut.win_valid[1]_LUT4_A.F
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Info: routing 0.00 6.99 Net dut.win_valid[1]_LUT4_A_Z (3,17) -> (3,17)
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Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_BLUT_LUT4_Z.F1
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
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Info: logic 0.13 7.12 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
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Info: routing 0.00 7.12 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z (3,17) -> (3,17)
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Info: Sink dut.win_valid[1]_LUT4_A.FXB
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
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Info: logic 0.18 7.30 Source dut.win_valid[1]_LUT4_A.OFX
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Info: routing 0.53 7.83 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[5] (3,17) -> (2,18)
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Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 8.02 Source dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
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Info: routing 0.00 8.02 Net dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1 (2,18) -> (2,18)
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Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
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Info: logic 0.18 8.20 Source dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
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Info: routing 0.92 9.12 Net dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI[2] (2,18) -> (7,16)
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Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_2.M
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Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_banked.v:141.48-141.67
|
||||
Info: /opt/homebrew/bin/../share/yosys/techmap.v:270.26-270.27
|
||||
Info: setup 0.00 9.12 Source dut.rr_ptr[1]_TRELLIS_FF_Q_2.M
|
||||
Info: 2.83 ns logic, 6.29 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[5]$tr_io.O
|
||||
Info: routing 3.69 3.69 Net seed[5]$TRELLIS_IO_IN (90,20) -> (8,20)
|
||||
Info: Sink seed_LUT4_B.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:19.23-19.27
|
||||
Info: logic 0.18 3.87 Source seed_LUT4_B.F
|
||||
Info: routing 0.12 3.99 Net seed_LUT4_B_Z[5] (8,20) -> (8,20)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_11.DI
|
||||
Info: setup 0.00 3.99 Source lfsr_TRELLIS_FF_Q_11.DI
|
||||
Info: 0.18 ns logic, 3.81 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_1.Q
|
||||
Info: routing 3.63 4.03 Net ack_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_3_D_LUT4_Z_2_D[0] (13,16) -> (90,17)
|
||||
Info: Sink checksum[1]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:48.15-48.18
|
||||
Info: 0.40 ns logic, 3.63 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 109.61 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.99 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.03 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 3377, 3787) |*+
|
||||
Info: [ 3787, 4197) |**+
|
||||
Info: [ 4197, 4607) |****+
|
||||
Info: [ 4607, 5017) |****+
|
||||
Info: [ 5017, 5427) |*****+
|
||||
Info: [ 5427, 5837) |***+
|
||||
Info: [ 5837, 6247) |***+
|
||||
Info: [ 6247, 6657) |+
|
||||
Info: [ 6657, 7067) |
|
||||
Info: [ 7067, 7477) |+
|
||||
Info: [ 7477, 7887) |*+
|
||||
Info: [ 7887, 8297) |**+
|
||||
Info: [ 8297, 8707) |+
|
||||
Info: [ 8707, 9117) |
|
||||
Info: [ 9117, 9527) |
|
||||
Info: [ 9527, 9937) |
|
||||
Info: [ 9937, 10347) |*****+
|
||||
Info: [ 10347, 10757) |***************************************+
|
||||
Info: [ 10757, 11167) |************************************************************
|
||||
Info: [ 11167, 11577) |*******************************************+
|
||||
|
||||
Info: Program finished normally.
|
||||
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Load Diff
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Load Diff
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Reference in New Issue
Block a user