V2.0.0 hardware freeze - single SDRAM
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 436/43848 0%
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Info: logic LUTs: 388/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 32/ 5481 0%
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Info: RAMW LUTs: 16/10962 0%
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Info: Total DFFs: 98/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 54 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x16d4eaf3
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 98/ 43848 0%
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Info: TRELLIS_COMB: 437/ 43848 0%
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Info: TRELLIS_RAMW: 8/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 312 cells, random placement wirelen = 26489.
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Info: at initial placer iter 0, wirelen = 1407
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Info: at initial placer iter 1, wirelen = 971
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Info: at initial placer iter 2, wirelen = 890
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Info: at initial placer iter 3, wirelen = 903
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Info: Running main analytical placer, max placement attempts per cell = 39480.
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Info: at iteration #1, type ALL: wirelen solved = 883, spread = 2048, legal = 2107; time = 0.01s
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Info: at iteration #2, type ALL: wirelen solved = 1056, spread = 1913, legal = 1949; time = 0.01s
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Info: at iteration #3, type ALL: wirelen solved = 1092, spread = 1800, legal = 1830; time = 0.01s
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Info: at iteration #4, type ALL: wirelen solved = 1133, spread = 1919, legal = 1962; time = 0.01s
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Info: at iteration #5, type ALL: wirelen solved = 1216, spread = 1852, legal = 1915; time = 0.01s
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Info: at iteration #6, type ALL: wirelen solved = 1274, spread = 1780, legal = 1812; time = 0.01s
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Info: at iteration #7, type ALL: wirelen solved = 1290, spread = 1862, legal = 1892; time = 0.01s
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Info: at iteration #8, type ALL: wirelen solved = 1366, spread = 1947, legal = 1972; time = 0.01s
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Info: at iteration #9, type ALL: wirelen solved = 1412, spread = 1883, legal = 1892; time = 0.01s
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Info: at iteration #10, type ALL: wirelen solved = 1446, spread = 1968, legal = 1972; time = 0.01s
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Info: at iteration #11, type ALL: wirelen solved = 1496, spread = 1878, legal = 1913; time = 0.01s
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Info: HeAP Placer Time: 0.09s
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Info: of which solving equations: 0.06s
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Info: of which spreading cells: 0.01s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 78, wirelen = 1812
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Info: at iteration #5: temp = 0.000000, timing cost = 81, wirelen = 1563
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Info: at iteration #10: temp = 0.000000, timing cost = 77, wirelen = 1523
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Info: at iteration #11: temp = 0.000000, timing cost = 81, wirelen = 1515
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Info: SA placement time 0.08s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 142.96 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.88 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.66 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 5505, 5817) |*
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Info: [ 5817, 6129) |
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Info: [ 6129, 6441) |
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Info: [ 6441, 6753) |*
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Info: [ 6753, 7065) |*****
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Info: [ 7065, 7377) |**
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Info: [ 7377, 7689) |**********
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Info: [ 7689, 8001) |*********
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Info: [ 8001, 8313) |*****
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Info: [ 8313, 8625) |*
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Info: [ 8625, 8937) |
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Info: [ 8937, 9249) |*
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Info: [ 9249, 9561) |*
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Info: [ 9561, 9873) |********
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Info: [ 9873, 10185) |*************************
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Info: [ 10185, 10497) |*****************
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Info: [ 10497, 10809) |****************************************************
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Info: [ 10809, 11121) |**************************************************
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Info: [ 11121, 11433) |**************************
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Info: [ 11433, 11745) |************************************
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Info: Checksum: 0x99bbbc03
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 1929 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 271 728 | 271 728 | 1233| 0.06 0.06|
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Info: 2000 | 551 1361 | 280 633 | 532| 0.05 0.11|
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Info: 2579 | 599 1866 | 48 505 | 0| 0.03 0.15|
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Info: Routing complete.
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Info: Router1 time 0.15s
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Info: Checksum: 0x518249c2
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_5.Q
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Info: routing 0.87 1.26 Net fill_data[1] (9,38) -> (12,37)
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Info: Sink dut.GEN_BANK[3].this_bank_we_LUT4_Z.C
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:33.24-33.33
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Info: logic 0.18 1.44 Source dut.GEN_BANK[3].this_bank_we_LUT4_Z.F
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Info: routing 0.59 2.04 Net dut.GEN_BANK[3].this_bank_we (12,37) -> (14,36)
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Info: Sink dut.GEN_BANK[3].this_bank_we_LUT4_C.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 2.22 Source dut.GEN_BANK[3].this_bank_we_LUT4_C.F
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Info: routing 0.45 2.67 Net dut.GEN_BANK[3].this_bank_we_LUT4_C_Z[3] (14,36) -> (14,36)
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Info: Sink dut.GEN_BANK[3].this_bank_we_LUT4_C_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_1.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 2.85 Source dut.GEN_BANK[3].this_bank_we_LUT4_C_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_1.F
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Info: routing 0.78 3.63 Net dut.win_tile_idx[3]_L6MUX21_Z_SD[2] (14,36) -> (13,32)
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Info: Sink dut.win_valid[3]_LUT4_Z_D_LUT4_Z_D_LUT4_Z_1.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 3.81 Source dut.win_valid[3]_LUT4_Z_D_LUT4_Z_D_LUT4_Z_1.F
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Info: routing 0.54 4.35 Net dut.win_valid[3]_LUT4_Z_D[2] (13,32) -> (13,33)
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Info: Sink dut.ack_comb_L6MUX21_Z_SD_PFUMX_Z_BLUT_LUT4_Z.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.31 4.66 Source dut.ack_comb_L6MUX21_Z_SD_PFUMX_Z_BLUT_LUT4_Z.OFX
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Info: routing 0.58 5.24 Net dut.ack_comb_L6MUX21_Z_SD[6] (13,33) -> (12,36)
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Info: Sink dut.ack_comb_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 5.43 Source dut.ack_comb_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
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Info: routing 0.26 5.70 Net dut.ack_comb[0] (12,36) -> (12,36)
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Info: Sink dut.ack_stage1_TRELLIS_FF_Q.M
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Info: Defined in:
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Info: hardware/v2/nms/rtl/nms_activation_banked.v:87.23-87.31
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Info: setup 0.00 5.70 Source dut.ack_stage1_TRELLIS_FF_Q.M
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Info: 1.61 ns logic, 4.08 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source seed[3]$tr_io.O
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Info: routing 3.88 3.88 Net seed[3]$TRELLIS_IO_IN (90,38) -> (11,37)
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Info: Sink seed_LUT4_B_Z_LUT4_Z_1.B
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:19.23-19.27
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Info: logic 0.18 4.06 Source seed_LUT4_B_Z_LUT4_Z_1.F
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Info: routing 0.12 4.18 Net seed_LUT4_B_Z[3] (11,37) -> (11,37)
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Info: Sink lfsr_TRELLIS_FF_Q_8.DI
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Info: setup 0.00 4.18 Source lfsr_TRELLIS_FF_Q_8.DI
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Info: 0.18 ns logic, 3.99 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_1.Q
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Info: routing 3.23 3.63 Net ack_LUT4_A_Z_LUT4_D_Z_LUT4_Z_D_PFUMX_Z_1_C0[0] (15,30) -> (42,0)
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Info: Sink checksum[1]$tr_io.I
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:48.15-48.18
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Info: 0.40 ns logic, 3.23 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 175.56 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.18 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.63 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 6804, 7054) |**
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Info: [ 7054, 7304) |**
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Info: [ 7304, 7554) |*****
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Info: [ 7554, 7804) |***
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Info: [ 7804, 8054) |**********
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Info: [ 8054, 8304) |****
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Info: [ 8304, 8554) |**
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Info: [ 8554, 8804) |*****
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Info: [ 8804, 9054) |*
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Info: [ 9054, 9304) |**
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Info: [ 9304, 9554) |
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Info: [ 9554, 9804) |*
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Info: [ 9804, 10054) |****
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Info: [ 10054, 10304) |********
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Info: [ 10304, 10554) |****
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Info: [ 10554, 10804) |********************************
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Info: [ 10804, 11054) |*******************************************************
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Info: [ 11054, 11304) |****************************************************
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Info: [ 11304, 11554) |***************************
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Info: [ 11554, 11804) |*******************************
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Info: Program finished normally.
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