V2.0.0 hardware freeze - single SDRAM
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
@@ -0,0 +1,195 @@
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 70/43848 0%
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Info: logic LUTs: 46/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 16/ 5481 0%
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Info: RAMW LUTs: 8/10962 0%
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Info: Total DFFs: 69/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 30 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x405aa89a
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 69/ 43848 0%
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Info: TRELLIS_COMB: 72/ 43848 0%
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Info: TRELLIS_RAMW: 4/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 74 cells, random placement wirelen = 6821.
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Info: at initial placer iter 0, wirelen = 1333
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Info: at initial placer iter 1, wirelen = 948
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Info: at initial placer iter 2, wirelen = 883
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Info: at initial placer iter 3, wirelen = 855
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Info: Running main analytical placer, max placement attempts per cell = 10000.
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Info: at iteration #1, type ALL: wirelen solved = 852, spread = 934, legal = 1006; time = 0.00s
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Info: HeAP Placer Time: 0.02s
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Info: of which solving equations: 0.00s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 15, wirelen = 1006
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Info: at iteration #5: temp = 0.000000, timing cost = 14, wirelen = 654
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Info: at iteration #10: temp = 0.000000, timing cost = 13, wirelen = 644
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Info: at iteration #14: temp = 0.000000, timing cost = 13, wirelen = 643
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Info: SA placement time 0.02s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 292.48 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.44 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.59 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 9081, 9214) |*
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Info: [ 9214, 9347) |
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Info: [ 9347, 9480) |
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Info: [ 9480, 9613) |
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Info: [ 9613, 9746) |
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Info: [ 9746, 9879) |
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Info: [ 9879, 10012) |
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Info: [ 10012, 10145) |
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Info: [ 10145, 10278) |***
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Info: [ 10278, 10411) |*****
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Info: [ 10411, 10544) |****
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Info: [ 10544, 10677) |**********
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Info: [ 10677, 10810) |****************
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Info: [ 10810, 10943) |**********************
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Info: [ 10943, 11076) |*******************************
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Info: [ 11076, 11209) |************
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Info: [ 11209, 11342) |**
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Info: [ 11342, 11475) |**************
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Info: [ 11475, 11608) |*****
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Info: [ 11608, 11741) |*********************************
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Info: Checksum: 0x784333ab
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 464 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 558 | 88 455 | 88 455 | 0| 0.04 0.04|
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Info: Routing complete.
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Info: Router1 time 0.04s
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Info: Checksum: 0x7e03b65b
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_3.Q
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Info: routing 0.76 1.15 Net fill_data[38] (2,33) -> (2,32)
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Info: Sink dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.A
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:34.28-34.45
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Info: logic 0.18 1.34 Source dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.F
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Info: routing 0.00 1.34 Net dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT (2,32) -> (2,32)
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Info: Sink dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z.F1
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
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Info: logic 0.13 1.46 Source dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
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Info: routing 0.00 1.46 Net dut.win_tile_idx[1]_L6MUX21_Z_1_D1 (2,32) -> (2,32)
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Info: Sink dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
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Info: logic 0.18 1.64 Source dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
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Info: routing 0.67 2.31 Net dut.ack_stage1_TRELLIS_FF_Q_DI_PFUMX_Z_ALUT_LUT4_Z_C[3] (2,32) -> (2,31)
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Info: Sink dut.ack_stage1_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.D
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Info: Defined in:
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Info: hardware/v2/nms/rtl/nms_activation_banked.v:85.20-85.32
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Info: logic 0.31 2.62 Source dut.ack_stage1_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.OFX
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Info: routing 0.32 2.94 Net dut.ack_stage1_TRELLIS_FF_Q_DI (2,31) -> (3,31)
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Info: Sink dut.ack_stage1_TRELLIS_FF_Q.M
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Info: setup 0.00 2.94 Source dut.ack_stage1_TRELLIS_FF_Q.M
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Info: 1.19 ns logic, 1.76 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source rst$tr_io.O
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Info: routing 4.25 4.25 Net rst$TRELLIS_IO_IN (42,0) -> (2,33)
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Info: Sink seed_LUT4_B_Z_LUT4_Z_3.C
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:18.17-18.20
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Info: logic 0.18 4.43 Source seed_LUT4_B_Z_LUT4_Z_3.F
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Info: routing 0.12 4.55 Net seed_LUT4_B_Z[5] (2,33) -> (2,33)
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Info: Sink lfsr_TRELLIS_FF_Q_2.DI
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Info: setup 0.00 4.55 Source lfsr_TRELLIS_FF_Q_2.DI
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Info: 0.18 ns logic, 4.36 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_5.Q
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Info: routing 3.81 4.21 Net checksum[4]$TRELLIS_IO_OUT (3,30) -> (90,29)
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Info: Sink checksum[4]$tr_io.I
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:48.15-48.18
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Info: 0.40 ns logic, 3.81 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 339.79 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.55 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.21 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 9557, 9669) |*
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Info: [ 9669, 9781) |
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Info: [ 9781, 9893) |
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Info: [ 9893, 10005) |
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Info: [ 10005, 10117) |
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Info: [ 10117, 10229) |
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Info: [ 10229, 10341) |**
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Info: [ 10341, 10453) |*
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Info: [ 10453, 10565) |*****
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Info: [ 10565, 10677) |*****
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Info: [ 10677, 10789) |**
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Info: [ 10789, 10901) |****************
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Info: [ 10901, 11013) |**************************
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Info: [ 11013, 11125) |***********************
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Info: [ 11125, 11237) |***************
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Info: [ 11237, 11349) |*************************
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Info: [ 11349, 11461) |*********
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Info: [ 11461, 11573) |******
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Info: [ 11573, 11685) |*********
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Info: [ 11685, 11797) |*************
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Info: Program finished normally.
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Load Diff
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Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,219 @@
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 436/43848 0%
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Info: logic LUTs: 388/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 32/ 5481 0%
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Info: RAMW LUTs: 16/10962 0%
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Info: Total DFFs: 98/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 54 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x16d4eaf3
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 98/ 43848 0%
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Info: TRELLIS_COMB: 437/ 43848 0%
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Info: TRELLIS_RAMW: 8/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 312 cells, random placement wirelen = 26489.
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Info: at initial placer iter 0, wirelen = 1407
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Info: at initial placer iter 1, wirelen = 971
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Info: at initial placer iter 2, wirelen = 890
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Info: at initial placer iter 3, wirelen = 903
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Info: Running main analytical placer, max placement attempts per cell = 39480.
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Info: at iteration #1, type ALL: wirelen solved = 883, spread = 2048, legal = 2107; time = 0.01s
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Info: at iteration #2, type ALL: wirelen solved = 1056, spread = 1913, legal = 1949; time = 0.01s
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Info: at iteration #3, type ALL: wirelen solved = 1092, spread = 1800, legal = 1830; time = 0.01s
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Info: at iteration #4, type ALL: wirelen solved = 1133, spread = 1919, legal = 1962; time = 0.01s
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Info: at iteration #5, type ALL: wirelen solved = 1216, spread = 1852, legal = 1915; time = 0.01s
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Info: at iteration #6, type ALL: wirelen solved = 1274, spread = 1780, legal = 1812; time = 0.01s
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Info: at iteration #7, type ALL: wirelen solved = 1290, spread = 1862, legal = 1892; time = 0.01s
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Info: at iteration #8, type ALL: wirelen solved = 1366, spread = 1947, legal = 1972; time = 0.01s
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Info: at iteration #9, type ALL: wirelen solved = 1412, spread = 1883, legal = 1892; time = 0.01s
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Info: at iteration #10, type ALL: wirelen solved = 1446, spread = 1968, legal = 1972; time = 0.01s
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Info: at iteration #11, type ALL: wirelen solved = 1496, spread = 1878, legal = 1913; time = 0.01s
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Info: HeAP Placer Time: 0.09s
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Info: of which solving equations: 0.06s
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Info: of which spreading cells: 0.01s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 78, wirelen = 1812
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Info: at iteration #5: temp = 0.000000, timing cost = 81, wirelen = 1563
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Info: at iteration #10: temp = 0.000000, timing cost = 77, wirelen = 1523
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Info: at iteration #11: temp = 0.000000, timing cost = 81, wirelen = 1515
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Info: SA placement time 0.08s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 142.96 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.88 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.66 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 5505, 5817) |*
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Info: [ 5817, 6129) |
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Info: [ 6129, 6441) |
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Info: [ 6441, 6753) |*
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Info: [ 6753, 7065) |*****
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Info: [ 7065, 7377) |**
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Info: [ 7377, 7689) |**********
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Info: [ 7689, 8001) |*********
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Info: [ 8001, 8313) |*****
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Info: [ 8313, 8625) |*
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Info: [ 8625, 8937) |
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Info: [ 8937, 9249) |*
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Info: [ 9249, 9561) |*
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Info: [ 9561, 9873) |********
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Info: [ 9873, 10185) |*************************
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Info: [ 10185, 10497) |*****************
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Info: [ 10497, 10809) |****************************************************
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Info: [ 10809, 11121) |**************************************************
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Info: [ 11121, 11433) |**************************
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Info: [ 11433, 11745) |************************************
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Info: Checksum: 0x99bbbc03
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 1929 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 271 728 | 271 728 | 1233| 0.06 0.06|
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Info: 2000 | 551 1361 | 280 633 | 532| 0.05 0.11|
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Info: 2579 | 599 1866 | 48 505 | 0| 0.03 0.15|
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Info: Routing complete.
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Info: Router1 time 0.15s
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||||
Info: Checksum: 0x518249c2
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_5.Q
|
||||
Info: routing 0.87 1.26 Net fill_data[1] (9,38) -> (12,37)
|
||||
Info: Sink dut.GEN_BANK[3].this_bank_we_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:33.24-33.33
|
||||
Info: logic 0.18 1.44 Source dut.GEN_BANK[3].this_bank_we_LUT4_Z.F
|
||||
Info: routing 0.59 2.04 Net dut.GEN_BANK[3].this_bank_we (12,37) -> (14,36)
|
||||
Info: Sink dut.GEN_BANK[3].this_bank_we_LUT4_C.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 2.22 Source dut.GEN_BANK[3].this_bank_we_LUT4_C.F
|
||||
Info: routing 0.45 2.67 Net dut.GEN_BANK[3].this_bank_we_LUT4_C_Z[3] (14,36) -> (14,36)
|
||||
Info: Sink dut.GEN_BANK[3].this_bank_we_LUT4_C_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 2.85 Source dut.GEN_BANK[3].this_bank_we_LUT4_C_D_LUT4_C_Z_LUT4_D_Z_LUT4_Z_1.F
|
||||
Info: routing 0.78 3.63 Net dut.win_tile_idx[3]_L6MUX21_Z_SD[2] (14,36) -> (13,32)
|
||||
Info: Sink dut.win_valid[3]_LUT4_Z_D_LUT4_Z_D_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 3.81 Source dut.win_valid[3]_LUT4_Z_D_LUT4_Z_D_LUT4_Z_1.F
|
||||
Info: routing 0.54 4.35 Net dut.win_valid[3]_LUT4_Z_D[2] (13,32) -> (13,33)
|
||||
Info: Sink dut.ack_comb_L6MUX21_Z_SD_PFUMX_Z_BLUT_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.31 4.66 Source dut.ack_comb_L6MUX21_Z_SD_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.58 5.24 Net dut.ack_comb_L6MUX21_Z_SD[6] (13,33) -> (12,36)
|
||||
Info: Sink dut.ack_comb_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 5.43 Source dut.ack_comb_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.26 5.70 Net dut.ack_comb[0] (12,36) -> (12,36)
|
||||
Info: Sink dut.ack_stage1_TRELLIS_FF_Q.M
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_banked.v:87.23-87.31
|
||||
Info: setup 0.00 5.70 Source dut.ack_stage1_TRELLIS_FF_Q.M
|
||||
Info: 1.61 ns logic, 4.08 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[3]$tr_io.O
|
||||
Info: routing 3.88 3.88 Net seed[3]$TRELLIS_IO_IN (90,38) -> (11,37)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_1.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:19.23-19.27
|
||||
Info: logic 0.18 4.06 Source seed_LUT4_B_Z_LUT4_Z_1.F
|
||||
Info: routing 0.12 4.18 Net seed_LUT4_B_Z[3] (11,37) -> (11,37)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_8.DI
|
||||
Info: setup 0.00 4.18 Source lfsr_TRELLIS_FF_Q_8.DI
|
||||
Info: 0.18 ns logic, 3.99 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_1.Q
|
||||
Info: routing 3.23 3.63 Net ack_LUT4_A_Z_LUT4_D_Z_LUT4_Z_D_PFUMX_Z_1_C0[0] (15,30) -> (42,0)
|
||||
Info: Sink checksum[1]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:48.15-48.18
|
||||
Info: 0.40 ns logic, 3.23 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 175.56 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.18 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.63 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 6804, 7054) |**
|
||||
Info: [ 7054, 7304) |**
|
||||
Info: [ 7304, 7554) |*****
|
||||
Info: [ 7554, 7804) |***
|
||||
Info: [ 7804, 8054) |**********
|
||||
Info: [ 8054, 8304) |****
|
||||
Info: [ 8304, 8554) |**
|
||||
Info: [ 8554, 8804) |*****
|
||||
Info: [ 8804, 9054) |*
|
||||
Info: [ 9054, 9304) |**
|
||||
Info: [ 9304, 9554) |
|
||||
Info: [ 9554, 9804) |*
|
||||
Info: [ 9804, 10054) |****
|
||||
Info: [ 10054, 10304) |********
|
||||
Info: [ 10304, 10554) |****
|
||||
Info: [ 10554, 10804) |********************************
|
||||
Info: [ 10804, 11054) |*******************************************************
|
||||
Info: [ 11054, 11304) |****************************************************
|
||||
Info: [ 11304, 11554) |***************************
|
||||
Info: [ 11554, 11804) |*******************************
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,271 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 1666/43848 3%
|
||||
Info: logic LUTs: 1618/43848 3%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 32/ 5481 0%
|
||||
Info: RAMW LUTs: 16/10962 0%
|
||||
|
||||
Info: Total DFFs: 102/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 59 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0xee0ee104
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 102/ 43848 0%
|
||||
Info: TRELLIS_COMB: 1667/ 43848 3%
|
||||
Info: TRELLIS_RAMW: 8/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 1097 cells, random placement wirelen = 78612.
|
||||
Info: at initial placer iter 0, wirelen = 1786
|
||||
Info: at initial placer iter 1, wirelen = 1138
|
||||
Info: at initial placer iter 2, wirelen = 1117
|
||||
Info: at initial placer iter 3, wirelen = 1091
|
||||
Info: Running main analytical placer, max placement attempts per cell = 403202.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 1023, spread = 6894, legal = 6975; time = 0.01s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 1803, spread = 5497, legal = 5610; time = 0.01s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 2036, spread = 5487, legal = 5600; time = 0.01s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 2159, spread = 5011, legal = 5100; time = 0.01s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 2451, spread = 4995, legal = 5256; time = 0.01s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 2448, spread = 4778, legal = 4923; time = 0.01s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 2634, spread = 4937, legal = 5040; time = 0.01s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 2796, spread = 4945, legal = 5024; time = 0.01s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 2886, spread = 4809, legal = 4849; time = 0.01s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 2882, spread = 5015, legal = 5171; time = 0.01s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 3179, spread = 4938, legal = 5108; time = 0.01s
|
||||
Info: at iteration #12, type ALL: wirelen solved = 3245, spread = 5203, legal = 5304; time = 0.01s
|
||||
Info: at iteration #13, type ALL: wirelen solved = 3413, spread = 5138, legal = 5319; time = 0.01s
|
||||
Info: at iteration #14, type ALL: wirelen solved = 3518, spread = 4959, legal = 5121; time = 0.01s
|
||||
Info: HeAP Placer Time: 0.24s
|
||||
Info: of which solving equations: 0.16s
|
||||
Info: of which spreading cells: 0.03s
|
||||
Info: of which strict legalisation: 0.01s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 810, wirelen = 4849
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 521, wirelen = 4141
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 596, wirelen = 4004
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 497, wirelen = 3865
|
||||
Info: at iteration #18: temp = 0.000000, timing cost = 461, wirelen = 3826
|
||||
Info: SA placement time 0.42s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 92.60 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.95 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.16 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 1701, 2197) |*+
|
||||
Info: [ 2197, 2693) |**+
|
||||
Info: [ 2693, 3189) |+
|
||||
Info: [ 3189, 3685) |**+
|
||||
Info: [ 3685, 4181) |******+
|
||||
Info: [ 4181, 4677) |***+
|
||||
Info: [ 4677, 5173) |*+
|
||||
Info: [ 5173, 5669) |*+
|
||||
Info: [ 5669, 6165) |*+
|
||||
Info: [ 6165, 6661) |*+
|
||||
Info: [ 6661, 7157) |*+
|
||||
Info: [ 7157, 7653) |*+
|
||||
Info: [ 7653, 8149) |*+
|
||||
Info: [ 8149, 8645) |
|
||||
Info: [ 8645, 9141) |
|
||||
Info: [ 9141, 9637) |
|
||||
Info: [ 9637, 10133) |******+
|
||||
Info: [ 10133, 10629) |************************************************************
|
||||
Info: [ 10629, 11125) |*******************************************************+
|
||||
Info: [ 11125, 11621) |********+
|
||||
Info: Checksum: 0x23829f4c
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 6315 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 189 810 | 189 810 | 5529| 0.08 0.08|
|
||||
Info: 2000 | 472 1527 | 283 717 | 4856| 0.08 0.15|
|
||||
Info: 3000 | 838 2161 | 366 634 | 4315| 0.08 0.24|
|
||||
Info: 4000 | 1186 2813 | 348 652 | 3831| 0.08 0.32|
|
||||
Info: 5000 | 1568 3431 | 382 618 | 3324| 0.08 0.39|
|
||||
Info: 6000 | 1956 4043 | 388 612 | 2835| 0.08 0.47|
|
||||
Info: 7000 | 2224 4661 | 268 618 | 2150| 0.05 0.52|
|
||||
Info: 8000 | 2593 5211 | 369 550 | 1542| 0.06 0.58|
|
||||
Info: 9000 | 2889 5887 | 296 676 | 866| 0.06 0.63|
|
||||
Info: 9961 | 2984 6557 | 95 670 | 0| 0.08 0.72|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.72s
|
||||
Info: Checksum: 0xf9e6caa1
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source dut.rr_ptr[1]_TRELLIS_FF_Q_2.Q
|
||||
Info: routing 0.88 1.27 Net dut.rr_ptr[1][2] (7,16) -> (5,15)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_2_C_LUT4_Z.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 1.46 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_2_C_LUT4_Z.F
|
||||
Info: routing 0.75 2.21 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_1_D_LUT4_D_Z_LUT4_D_Z_PFUMX_BLUT_Z_PFUMX_Z_C0[1] (5,15) -> (5,12)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_1_D_PFUMX_C0_Z_L6MUX21_D1_Z_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 2.39 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_1_D_PFUMX_C0_Z_L6MUX21_D1_Z_LUT4_Z.F
|
||||
Info: routing 0.47 2.86 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z_LUT4_Z_D_LUT4_Z_1_D_PFUMX_C0_Z_L6MUX21_D1_Z[3] (5,12) -> (5,12)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_ALUT_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 3.04 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_ALUT_LUT4_Z.F
|
||||
Info: routing 0.00 3.04 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_ALUT (5,12) -> (5,12)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_BLUT_LUT4_Z.F1
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
|
||||
Info: logic 0.13 3.16 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D_PFUMX_Z_2_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.82 3.99 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1_D[2] (5,12) -> (4,14)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.17 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z_LUT4_Z_1.F
|
||||
Info: routing 0.53 4.70 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_3_C_LUT4_B_Z_LUT4_D_Z[4] (4,14) -> (4,16)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 4.89 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.00 4.89 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1 (4,16) -> (4,16)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
|
||||
Info: logic 0.18 5.07 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.50 5.57 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_A_LUT4_B_Z[0] (4,16) -> (4,18)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.75 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z.F
|
||||
Info: routing 0.33 6.07 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] (4,18) -> (4,18)
|
||||
Info: Sink dut.win_valid[1]_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.25 Source dut.win_valid[1]_LUT4_Z.F
|
||||
Info: routing 0.56 6.81 Net dut.win_valid[1] (4,18) -> (3,17)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A.A
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.99 Source dut.win_valid[1]_LUT4_A.F
|
||||
Info: routing 0.00 6.99 Net dut.win_valid[1]_LUT4_A_Z (3,17) -> (3,17)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_BLUT_LUT4_Z.F1
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
|
||||
Info: logic 0.13 7.12 Source dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.00 7.12 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z (3,17) -> (3,17)
|
||||
Info: Sink dut.win_valid[1]_LUT4_A.FXB
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
|
||||
Info: logic 0.18 7.30 Source dut.win_valid[1]_LUT4_A.OFX
|
||||
Info: routing 0.53 7.83 Net dut.win_valid[1]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[5] (3,17) -> (2,18)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 8.02 Source dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.00 8.02 Net dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1 (2,18) -> (2,18)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
|
||||
Info: logic 0.18 8.20 Source dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.92 9.12 Net dut.rr_ptr[1]_TRELLIS_FF_Q_1_DI[2] (2,18) -> (7,16)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_2.M
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_banked.v:141.48-141.67
|
||||
Info: /opt/homebrew/bin/../share/yosys/techmap.v:270.26-270.27
|
||||
Info: setup 0.00 9.12 Source dut.rr_ptr[1]_TRELLIS_FF_Q_2.M
|
||||
Info: 2.83 ns logic, 6.29 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[5]$tr_io.O
|
||||
Info: routing 3.69 3.69 Net seed[5]$TRELLIS_IO_IN (90,20) -> (8,20)
|
||||
Info: Sink seed_LUT4_B.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:19.23-19.27
|
||||
Info: logic 0.18 3.87 Source seed_LUT4_B.F
|
||||
Info: routing 0.12 3.99 Net seed_LUT4_B_Z[5] (8,20) -> (8,20)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_11.DI
|
||||
Info: setup 0.00 3.99 Source lfsr_TRELLIS_FF_Q_11.DI
|
||||
Info: 0.18 ns logic, 3.81 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_1.Q
|
||||
Info: routing 3.63 4.03 Net ack_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_3_D_LUT4_Z_2_D[0] (13,16) -> (90,17)
|
||||
Info: Sink checksum[1]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:48.15-48.18
|
||||
Info: 0.40 ns logic, 3.63 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 109.61 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.99 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.03 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 3377, 3787) |*+
|
||||
Info: [ 3787, 4197) |**+
|
||||
Info: [ 4197, 4607) |****+
|
||||
Info: [ 4607, 5017) |****+
|
||||
Info: [ 5017, 5427) |*****+
|
||||
Info: [ 5427, 5837) |***+
|
||||
Info: [ 5837, 6247) |***+
|
||||
Info: [ 6247, 6657) |+
|
||||
Info: [ 6657, 7067) |
|
||||
Info: [ 7067, 7477) |+
|
||||
Info: [ 7477, 7887) |*+
|
||||
Info: [ 7887, 8297) |**+
|
||||
Info: [ 8297, 8707) |+
|
||||
Info: [ 8707, 9117) |
|
||||
Info: [ 9117, 9527) |
|
||||
Info: [ 9527, 9937) |
|
||||
Info: [ 9937, 10347) |*****+
|
||||
Info: [ 10347, 10757) |***************************************+
|
||||
Info: [ 10757, 11167) |************************************************************
|
||||
Info: [ 11167, 11577) |*******************************************+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,283 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 3347/43848 7%
|
||||
Info: logic LUTs: 3251/43848 7%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 64/ 5481 1%
|
||||
Info: RAMW LUTs: 32/10962 0%
|
||||
|
||||
Info: Total DFFs: 152/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 99 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x0b56304c
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 152/ 43848 0%
|
||||
Info: TRELLIS_COMB: 3348/ 43848 7%
|
||||
Info: TRELLIS_RAMW: 16/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 2264 cells, random placement wirelen = 158616.
|
||||
Info: at initial placer iter 0, wirelen = 1648
|
||||
Info: at initial placer iter 1, wirelen = 1027
|
||||
Info: at initial placer iter 2, wirelen = 932
|
||||
Info: at initial placer iter 3, wirelen = 919
|
||||
Info: Running main analytical placer, max placement attempts per cell = 1562028.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 933, spread = 19704, legal = 19815; time = 0.03s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 2379, spread = 11209, legal = 11486; time = 0.03s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 2956, spread = 11099, legal = 11438; time = 0.03s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 3333, spread = 11091, legal = 11234; time = 0.02s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 3919, spread = 11008, legal = 11309; time = 0.02s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 4552, spread = 10629, legal = 10922; time = 0.02s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 4646, spread = 11001, legal = 11238; time = 0.02s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 5200, spread = 10783, legal = 11062; time = 0.02s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 5585, spread = 10301, legal = 10538; time = 0.02s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 5824, spread = 9874, legal = 10052; time = 0.02s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 5874, spread = 9825, legal = 10026; time = 0.02s
|
||||
Info: at iteration #12, type ALL: wirelen solved = 6003, spread = 9579, legal = 9859; time = 0.02s
|
||||
Info: at iteration #13, type ALL: wirelen solved = 5986, spread = 9661, legal = 9851; time = 0.02s
|
||||
Info: at iteration #14, type ALL: wirelen solved = 6272, spread = 9364, legal = 9624; time = 0.02s
|
||||
Info: at iteration #15, type ALL: wirelen solved = 6239, spread = 9626, legal = 9869; time = 0.02s
|
||||
Info: at iteration #16, type ALL: wirelen solved = 6751, spread = 9439, legal = 9687; time = 0.02s
|
||||
Info: at iteration #17, type ALL: wirelen solved = 6820, spread = 9289, legal = 9533; time = 0.02s
|
||||
Info: at iteration #18, type ALL: wirelen solved = 6680, spread = 9369, legal = 9610; time = 0.02s
|
||||
Info: at iteration #19, type ALL: wirelen solved = 6767, spread = 9305, legal = 9522; time = 0.02s
|
||||
Info: at iteration #20, type ALL: wirelen solved = 6853, spread = 9392, legal = 9571; time = 0.02s
|
||||
Info: at iteration #21, type ALL: wirelen solved = 7071, spread = 9487, legal = 9759; time = 0.02s
|
||||
Info: at iteration #22, type ALL: wirelen solved = 7071, spread = 9385, legal = 9674; time = 0.02s
|
||||
Info: at iteration #23, type ALL: wirelen solved = 7131, spread = 9262, legal = 9503; time = 0.02s
|
||||
Info: at iteration #24, type ALL: wirelen solved = 7204, spread = 9047, legal = 9267; time = 0.02s
|
||||
Info: at iteration #25, type ALL: wirelen solved = 7121, spread = 9278, legal = 9505; time = 0.02s
|
||||
Info: at iteration #26, type ALL: wirelen solved = 7284, spread = 9101, legal = 9333; time = 0.02s
|
||||
Info: at iteration #27, type ALL: wirelen solved = 7183, spread = 9020, legal = 9246; time = 0.02s
|
||||
Info: at iteration #28, type ALL: wirelen solved = 7222, spread = 9071, legal = 9348; time = 0.02s
|
||||
Info: at iteration #29, type ALL: wirelen solved = 7185, spread = 9020, legal = 9330; time = 0.02s
|
||||
Info: at iteration #30, type ALL: wirelen solved = 7358, spread = 9022, legal = 9281; time = 0.02s
|
||||
Info: at iteration #31, type ALL: wirelen solved = 7405, spread = 8946, legal = 9241; time = 0.02s
|
||||
Info: HeAP Placer Time: 0.91s
|
||||
Info: of which solving equations: 0.62s
|
||||
Info: of which spreading cells: 0.12s
|
||||
Info: of which strict legalisation: 0.02s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 763, wirelen = 9241
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 1232, wirelen = 8180
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 1209, wirelen = 7859
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 1100, wirelen = 7693
|
||||
Info: at iteration #17: temp = 0.000000, timing cost = 1187, wirelen = 7667
|
||||
Info: SA placement time 0.77s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 92.87 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.05 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.84 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 1732, 2226) |*+
|
||||
Info: [ 2226, 2720) |***+
|
||||
Info: [ 2720, 3214) |******+
|
||||
Info: [ 3214, 3708) |*******+
|
||||
Info: [ 3708, 4202) |*******+
|
||||
Info: [ 4202, 4696) |**************+
|
||||
Info: [ 4696, 5190) |*+
|
||||
Info: [ 5190, 5684) |****+
|
||||
Info: [ 5684, 6178) |
|
||||
Info: [ 6178, 6672) |
|
||||
Info: [ 6672, 7166) |
|
||||
Info: [ 7166, 7660) |
|
||||
Info: [ 7660, 8154) |************+
|
||||
Info: [ 8154, 8648) |*******+
|
||||
Info: [ 8648, 9142) |***********************+
|
||||
Info: [ 9142, 9636) |************************************************************
|
||||
Info: [ 9636, 10130) |*******************************************+
|
||||
Info: [ 10130, 10624) |******************+
|
||||
Info: [ 10624, 11118) |*************************+
|
||||
Info: [ 11118, 11612) |*******************+
|
||||
Info: Checksum: 0x58e9efa5
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 12053 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 219 780 | 219 780 | 11316| 0.10 0.10|
|
||||
Info: 2000 | 448 1551 | 229 771 | 10614| 0.07 0.18|
|
||||
Info: 3000 | 805 2194 | 357 643 | 10026| 0.07 0.25|
|
||||
Info: 4000 | 1172 2827 | 367 633 | 9478| 0.08 0.33|
|
||||
Info: 5000 | 1513 3486 | 341 659 | 8877| 0.08 0.41|
|
||||
Info: 6000 | 1830 4169 | 317 683 | 8265| 0.08 0.50|
|
||||
Info: 7000 | 2205 4794 | 375 625 | 7732| 0.09 0.58|
|
||||
Info: 8000 | 2542 5457 | 337 663 | 7159| 0.08 0.67|
|
||||
Info: 9000 | 2905 6094 | 363 637 | 6635| 0.09 0.76|
|
||||
Info: 10000 | 3275 6724 | 370 630 | 6084| 0.08 0.84|
|
||||
Info: 11000 | 3664 7335 | 389 611 | 5558| 0.08 0.92|
|
||||
Info: 12000 | 4037 7962 | 373 627 | 5038| 0.08 1.00|
|
||||
Info: 13000 | 4367 8580 | 330 618 | 4443| 0.07 1.07|
|
||||
Info: 14000 | 4618 9181 | 251 601 | 3732| 0.05 1.13|
|
||||
Info: 15000 | 4993 9718 | 375 537 | 3138| 0.06 1.19|
|
||||
Info: 16000 | 5400 10260 | 407 542 | 2580| 0.06 1.25|
|
||||
Info: 17000 | 5761 10868 | 361 608 | 1965| 0.06 1.31|
|
||||
Info: 18000 | 6058 11546 | 297 678 | 1271| 0.07 1.38|
|
||||
Info: 19000 | 6181 12241 | 123 695 | 404| 0.06 1.44|
|
||||
Info: 19409 | 6184 12476 | 3 235 | 0| 0.03 1.47|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 1.47s
|
||||
Info: Checksum: 0x95778c56
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_6.Q
|
||||
Info: routing 1.28 1.67 Net fill_data[30] (7,17) -> (6,4)
|
||||
Info: Sink dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_1_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:34.28-34.45
|
||||
Info: logic 0.31 1.98 Source dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_1_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.00 1.98 Net dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_1_SD_L6MUX21_Z_D1 (6,4) -> (6,4)
|
||||
Info: Sink dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_1_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
|
||||
Info: logic 0.18 2.16 Source dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_1_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.51 2.66 Net dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_1_SD[6] (6,4) -> (6,3)
|
||||
Info: Sink dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 2.86 Source dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_C0_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.47 3.33 Net dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_C0[4] (6,3) -> (5,3)
|
||||
Info: Sink dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 3.53 Source dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.63 4.16 Net dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z_D[0] (5,3) -> (5,4)
|
||||
Info: Sink dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.34 Source dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z_LUT4_Z.F
|
||||
Info: routing 0.93 5.27 Net dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_C_LUT4_Z_1_C_L6MUX21_SD_Z_PFUMX_C0_Z[6] (5,4) -> (6,9)
|
||||
Info: Sink dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_C_LUT4_B_Z_PFUMX_BLUT_Z_PFUMX_Z_2_C0_LUT4_D_2_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 5.46 Source dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_C_LUT4_B_Z_PFUMX_BLUT_Z_PFUMX_Z_2_C0_LUT4_D_2_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.69 6.15 Net dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_C_LUT4_B_Z_PFUMX_BLUT_Z_PFUMX_Z_2_C0_LUT4_D_2_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[4] (6,9) -> (4,11)
|
||||
Info: Sink dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_C_LUT4_C.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.33 Source dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_C_LUT4_C.F
|
||||
Info: routing 0.60 6.93 Net dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_C_LUT4_C_Z[2] (4,11) -> (4,11)
|
||||
Info: Sink dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.31 7.24 Source dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.00 7.24 Net dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D0 (4,11) -> (4,11)
|
||||
Info: Sink dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.FXA
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.34-141.36
|
||||
Info: logic 0.18 7.42 Source dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.47 7.89 Net dut.win_valid[5]_LUT4_A_Z_PFUMX_ALUT_Z[4] (4,11) -> (5,11)
|
||||
Info: Sink dut.rr_ptr[5]_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 8.08 Source dut.rr_ptr[5]_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.00 8.08 Net dut.rr_ptr[5]_TRELLIS_FF_Q_DI_L6MUX21_Z_D1 (5,11) -> (5,11)
|
||||
Info: Sink dut.rr_ptr[5]_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
|
||||
Info: logic 0.18 8.26 Source dut.rr_ptr[5]_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.67 8.94 Net dut.rr_ptr[5]_TRELLIS_FF_Q_DI[2] (5,11) -> (4,6)
|
||||
Info: Sink dut.rr_ptr[5]_TRELLIS_FF_Q_1.M
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_banked.v:141.48-141.67
|
||||
Info: /opt/homebrew/bin/../share/yosys/techmap.v:270.26-270.27
|
||||
Info: setup 0.00 8.94 Source dut.rr_ptr[5]_TRELLIS_FF_Q_1.M
|
||||
Info: 2.68 ns logic, 6.26 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[5]$tr_io.O
|
||||
Info: routing 5.11 5.11 Net seed[5]$TRELLIS_IO_IN (90,47) -> (7,19)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_1.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:19.23-19.27
|
||||
Info: logic 0.18 5.29 Source seed_LUT4_B_Z_LUT4_Z_1.F
|
||||
Info: routing 0.12 5.41 Net seed_LUT4_B_Z[5] (7,19) -> (7,19)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_4.DI
|
||||
Info: setup 0.00 5.41 Source lfsr_TRELLIS_FF_Q_4.DI
|
||||
Info: 0.18 ns logic, 5.23 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
|
||||
Info: routing 4.88 5.27 Net ack_LUT4_B_D[0] (20,13) -> (90,47)
|
||||
Info: Sink checksum[0]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:48.15-48.18
|
||||
Info: 0.40 ns logic, 4.88 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 111.92 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.41 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.27 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 3565, 3973) |**+
|
||||
Info: [ 3973, 4381) |******+
|
||||
Info: [ 4381, 4789) |*****+
|
||||
Info: [ 4789, 5197) |******+
|
||||
Info: [ 5197, 5605) |********+
|
||||
Info: [ 5605, 6013) |******+
|
||||
Info: [ 6013, 6421) |*+
|
||||
Info: [ 6421, 6829) |
|
||||
Info: [ 6829, 7237) |
|
||||
Info: [ 7237, 7645) |
|
||||
Info: [ 7645, 8053) |
|
||||
Info: [ 8053, 8461) |
|
||||
Info: [ 8461, 8869) |****+
|
||||
Info: [ 8869, 9277) |****+
|
||||
Info: [ 9277, 9685) |*******+
|
||||
Info: [ 9685, 10093) |*******+
|
||||
Info: [ 10093, 10501) |************************************************************
|
||||
Info: [ 10501, 10909) |******************************************+
|
||||
Info: [ 10909, 11317) |*******************************+
|
||||
Info: [ 11317, 11725) |*************+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,251 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 1052/43848 2%
|
||||
Info: logic LUTs: 1052/43848 2%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 0/ 5481 0%
|
||||
Info: RAMW LUTs: 0/10962 0%
|
||||
|
||||
Info: Total DFFs: 54/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 18 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x0daa9abb
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 54/ 43848 0%
|
||||
Info: TRELLIS_COMB: 1053/ 43848 2%
|
||||
Info: TRELLIS_RAMW: 0/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 641 cells, random placement wirelen = 49069.
|
||||
Info: at initial placer iter 0, wirelen = 965
|
||||
Info: at initial placer iter 1, wirelen = 631
|
||||
Info: at initial placer iter 2, wirelen = 595
|
||||
Info: at initial placer iter 3, wirelen = 592
|
||||
Info: Running main analytical placer, max placement attempts per cell = 158484.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 591, spread = 5395, legal = 5487; time = 0.01s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 740, spread = 3599, legal = 3675; time = 0.01s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 896, spread = 3294, legal = 3391; time = 0.01s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 1095, spread = 3237, legal = 3345; time = 0.01s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 1261, spread = 3201, legal = 3309; time = 0.01s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 1306, spread = 3200, legal = 3261; time = 0.01s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 1347, spread = 3058, legal = 3136; time = 0.01s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 1392, spread = 2954, legal = 3052; time = 0.01s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 1471, spread = 3069, legal = 3185; time = 0.01s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 1582, spread = 2977, legal = 3087; time = 0.01s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 1666, spread = 2861, legal = 2996; time = 0.01s
|
||||
Info: at iteration #12, type ALL: wirelen solved = 1620, spread = 3062, legal = 3153; time = 0.01s
|
||||
Info: at iteration #13, type ALL: wirelen solved = 1734, spread = 3087, legal = 3136; time = 0.01s
|
||||
Info: at iteration #14, type ALL: wirelen solved = 1828, spread = 2951, legal = 3009; time = 0.01s
|
||||
Info: at iteration #15, type ALL: wirelen solved = 1832, spread = 3389, legal = 3471; time = 0.01s
|
||||
Info: at iteration #16, type ALL: wirelen solved = 2061, spread = 3114, legal = 3179; time = 0.01s
|
||||
Info: HeAP Placer Time: 0.15s
|
||||
Info: of which solving equations: 0.09s
|
||||
Info: of which spreading cells: 0.02s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 528, wirelen = 2996
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 436, wirelen = 2473
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 417, wirelen = 2399
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 435, wirelen = 2333
|
||||
Info: at iteration #20: temp = 0.000000, timing cost = 347, wirelen = 2265
|
||||
Info: at iteration #22: temp = 0.000000, timing cost = 344, wirelen = 2259
|
||||
Info: SA placement time 0.30s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 86.37 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.28 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 2.13 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 922, 1463) |*
|
||||
Info: [ 1463, 2004) |
|
||||
Info: [ 2004, 2545) |
|
||||
Info: [ 2545, 3086) |***
|
||||
Info: [ 3086, 3627) |******
|
||||
Info: [ 3627, 4168) |**
|
||||
Info: [ 4168, 4709) |***
|
||||
Info: [ 4709, 5250) |******
|
||||
Info: [ 5250, 5791) |*
|
||||
Info: [ 5791, 6332) |
|
||||
Info: [ 6332, 6873) |**
|
||||
Info: [ 6873, 7414) |*
|
||||
Info: [ 7414, 7955) |
|
||||
Info: [ 7955, 8496) |
|
||||
Info: [ 8496, 9037) |
|
||||
Info: [ 9037, 9578) |
|
||||
Info: [ 9578, 10119) |
|
||||
Info: [ 10119, 10660) |****
|
||||
Info: [ 10660, 11201) |*************
|
||||
Info: [ 11201, 11742) |************************
|
||||
Info: Checksum: 0x6d11e7b4
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 3620 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 283 716 | 283 716 | 2927| 0.07 0.07|
|
||||
Info: 2000 | 630 1369 | 347 653 | 2306| 0.07 0.14|
|
||||
Info: 3000 | 1001 1998 | 371 629 | 1749| 0.07 0.21|
|
||||
Info: 4000 | 1367 2597 | 366 599 | 1191| 0.06 0.26|
|
||||
Info: 5000 | 1715 3152 | 348 555 | 566| 0.05 0.31|
|
||||
Info: 5742 | 1888 3547 | 173 395 | 0| 0.07 0.39|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.39s
|
||||
Info: Checksum: 0xbef4cf31
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source dut.rr_ptr[1]_TRELLIS_FF_Q.Q
|
||||
Info: routing 1.10 1.50 Net dut.fill_we_LUT4_C_Z_PFUMX_ALUT_C0[1] (26,4) -> (30,3)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_C_Z_LUT4_Z_1_B_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_1_C0_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 1.68 Source dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_C_Z_LUT4_Z_1_B_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_1_C0_LUT4_Z.F
|
||||
Info: routing 0.31 1.98 Net dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_C_Z_LUT4_Z_1_B_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_1_C0[4] (30,3) -> (30,3)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_C_Z_LUT4_Z_1_B_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 2.17 Source dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_C_Z_LUT4_Z_1_B_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.51 2.69 Net dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_C_Z_LUT4_Z_1_B_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_PFUMX_Z_C0_LUT4_D_Z[3] (30,3) -> (27,3)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_D_C_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.31 2.99 Source dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_D_C_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.00 2.99 Net dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_D_C_LUT4_D_Z_L6MUX21_Z_1_D1 (27,3) -> (27,3)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_D_C_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
|
||||
Info: logic 0.18 3.17 Source dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_D_C_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.61 3.78 Net dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_D_C_LUT4_D_Z[5] (27,3) -> (29,3)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_LUT4_Z_1_D_LUT4_Z_1.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 3.96 Source dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_LUT4_Z_1_D_LUT4_Z_1.F
|
||||
Info: routing 0.50 4.46 Net dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_LUT4_Z_1_D[6] (29,3) -> (29,4)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_C_L6MUX21_SD_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 4.66 Source dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_C_L6MUX21_SD_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.82 5.47 Net dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_C_1_Z_LUT4_Z_C[2] (29,4) -> (28,6)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.66 Source dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z_LUT4_Z.F
|
||||
Info: routing 0.45 6.11 Net dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_C_LUT4_D_Z[3] (28,6) -> (28,6)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_B_PFUMX_Z_BLUT_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.31 6.41 Source dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_B_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.55 6.97 Net dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_B[4] (28,6) -> (26,5)
|
||||
Info: Sink dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_D_C_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 7.16 Source dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_D_C_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.68 7.83 Net dut.rr_ptr[1]_TRELLIS_FF_Q_DI_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_1_B_LUT4_D_C_LUT4_C_Z[6] (26,5) -> (25,7)
|
||||
Info: Sink dut.win_tile_idx[3]_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_D1_Z_L6MUX21_Z_3_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 8.03 Source dut.win_tile_idx[3]_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_D1_Z_L6MUX21_Z_3_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.68 8.70 Net dut.win_tile_idx[3]_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_D1_Z[3] (25,7) -> (21,7)
|
||||
Info: Sink dut.ack_comb_PFUMX_Z_BLUT_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.31 9.01 Source dut.ack_comb_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.35 9.36 Net dut.ack_comb[0] (21,7) -> (21,7)
|
||||
Info: Sink dut.ack_stage1_TRELLIS_FF_Q.M
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_banked.v:87.23-87.31
|
||||
Info: setup 0.00 9.36 Source dut.ack_stage1_TRELLIS_FF_Q.M
|
||||
Info: 2.81 ns logic, 6.55 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source rst$tr_io.O
|
||||
Info: routing 5.41 5.41 Net rst$TRELLIS_IO_IN (62,0) -> (2,53)
|
||||
Info: Sink chk_TRELLIS_FF_Q_5.LSR
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:18.17-18.20
|
||||
Info: setup 0.29 5.70 Source chk_TRELLIS_FF_Q_5.LSR
|
||||
Info: 0.29 ns logic, 5.41 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_1.Q
|
||||
Info: routing 1.37 1.77 Net ack_LUT4_D_Z[1] (73,32) -> (90,32)
|
||||
Info: Sink checksum[1]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_banked.v:48.15-48.18
|
||||
Info: 0.40 ns logic, 1.37 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 106.84 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.70 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 1.77 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 3140, 3573) |*
|
||||
Info: [ 3573, 4006) |
|
||||
Info: [ 4006, 4439) |**
|
||||
Info: [ 4439, 4872) |*****
|
||||
Info: [ 4872, 5305) |*
|
||||
Info: [ 5305, 5738) |******
|
||||
Info: [ 5738, 6171) |*****
|
||||
Info: [ 6171, 6604) |**
|
||||
Info: [ 6604, 7037) |***
|
||||
Info: [ 7037, 7470) |
|
||||
Info: [ 7470, 7903) |
|
||||
Info: [ 7903, 8336) |
|
||||
Info: [ 8336, 8769) |
|
||||
Info: [ 8769, 9202) |
|
||||
Info: [ 9202, 9635) |
|
||||
Info: [ 9635, 10068) |
|
||||
Info: [ 10068, 10501) |
|
||||
Info: [ 10501, 10934) |********
|
||||
Info: [ 10934, 11367) |*****************
|
||||
Info: [ 11367, 11800) |****************
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,180 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 40/43848 0%
|
||||
Info: logic LUTs: 16/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 16/ 5481 0%
|
||||
Info: RAMW LUTs: 8/10962 0%
|
||||
|
||||
Info: Total DFFs: 56/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 32 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0xd1317d1e
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 56/ 43848 0%
|
||||
Info: TRELLIS_COMB: 42/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 4/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 45 cells, random placement wirelen = 4304.
|
||||
Info: at initial placer iter 0, wirelen = 1329
|
||||
Info: at initial placer iter 1, wirelen = 1030
|
||||
Info: at initial placer iter 2, wirelen = 966
|
||||
Info: at initial placer iter 3, wirelen = 959
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 956, spread = 1017, legal = 1022; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.02s
|
||||
Info: of which solving equations: 0.00s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 19, wirelen = 1022
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 24, wirelen = 822
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 20, wirelen = 797
|
||||
Info: at iteration #12: temp = 0.000000, timing cost = 28, wirelen = 806
|
||||
Info: SA placement time 0.01s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 654.02 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.40 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.67 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10971, 11010) |*******************
|
||||
Info: [ 11010, 11049) |
|
||||
Info: [ 11049, 11088) |******
|
||||
Info: [ 11088, 11127) |*******************************
|
||||
Info: [ 11127, 11166) |
|
||||
Info: [ 11166, 11205) |******
|
||||
Info: [ 11205, 11244) |****************************
|
||||
Info: [ 11244, 11283) |
|
||||
Info: [ 11283, 11322) |**********
|
||||
Info: [ 11322, 11361) |****
|
||||
Info: [ 11361, 11400) |****
|
||||
Info: [ 11400, 11439) |********
|
||||
Info: [ 11439, 11478) |
|
||||
Info: [ 11478, 11517) |******
|
||||
Info: [ 11517, 11556) |**
|
||||
Info: [ 11556, 11595) |
|
||||
Info: [ 11595, 11634) |*************
|
||||
Info: [ 11634, 11673) |
|
||||
Info: [ 11673, 11712) |
|
||||
Info: [ 11712, 11751) |*************
|
||||
Info: Checksum: 0x5249d1ff
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 300 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 324 | 23 301 | 23 301 | 0| 0.09 0.09|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.09s
|
||||
Info: Checksum: 0xb595ea98
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_13.Q
|
||||
Info: routing 0.94 1.33 Net fill_addr[1] (34,35) -> (36,36)
|
||||
Info: Sink dut.GEN_COPY[0].mem.0.1$DPRAM_COMB1.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:37.24-37.29
|
||||
Info: logic 0.18 1.51 Source dut.GEN_COPY[0].mem.0.1$DPRAM_COMB1.F
|
||||
Info: routing 0.12 1.63 Net dut.GEN_COPY[0].mem.0.0_DO[5] (36,36) -> (36,36)
|
||||
Info: Sink dut.GEN_COPY[0].rd_data_reg_TRELLIS_FF_Q_6.DI
|
||||
Info: setup 0.00 1.63 Source dut.GEN_COPY[0].rd_data_reg_TRELLIS_FF_Q_6.DI
|
||||
Info: 0.57 ns logic, 1.05 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source rst$tr_io.O
|
||||
Info: routing 2.96 2.96 Net rst$TRELLIS_IO_IN (0,38) -> (36,37)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:22.17-22.20
|
||||
Info: logic 0.18 3.14 Source seed_LUT4_B_Z_LUT4_Z_1.F
|
||||
Info: routing 0.12 3.26 Net seed_LUT4_B_Z[7] (36,37) -> (36,37)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_24.DI
|
||||
Info: setup 0.00 3.26 Source lfsr_TRELLIS_FF_Q_24.DI
|
||||
Info: 0.18 ns logic, 3.08 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_2.Q
|
||||
Info: routing 2.77 3.16 Net checksum[2]$TRELLIS_IO_OUT (32,36) -> (42,0)
|
||||
Info: Sink checksum[2]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:50.15-50.18
|
||||
Info: 0.40 ns logic, 2.77 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 613.87 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.26 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.16 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10871, 10918) |*************
|
||||
Info: [ 10918, 10965) |***
|
||||
Info: [ 10965, 11012) |**
|
||||
Info: [ 11012, 11059) |
|
||||
Info: [ 11059, 11106) |******
|
||||
Info: [ 11106, 11153) |**************
|
||||
Info: [ 11153, 11200) |************************
|
||||
Info: [ 11200, 11247) |******
|
||||
Info: [ 11247, 11294) |**
|
||||
Info: [ 11294, 11341) |********************
|
||||
Info: [ 11341, 11388) |****************
|
||||
Info: [ 11388, 11435) |******
|
||||
Info: [ 11435, 11482) |**
|
||||
Info: [ 11482, 11529) |***
|
||||
Info: [ 11529, 11576) |***
|
||||
Info: [ 11576, 11623) |**********
|
||||
Info: [ 11623, 11670) |
|
||||
Info: [ 11670, 11717) |******
|
||||
Info: [ 11717, 11764) |***
|
||||
Info: [ 11764, 11811) |***********
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,180 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 72/43848 0%
|
||||
Info: logic LUTs: 24/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 32/ 5481 0%
|
||||
Info: RAMW LUTs: 16/10962 0%
|
||||
|
||||
Info: Total DFFs: 72/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 40 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x12571da3
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 72/ 43848 0%
|
||||
Info: TRELLIS_COMB: 74/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 8/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 57 cells, random placement wirelen = 5943.
|
||||
Info: at initial placer iter 0, wirelen = 1261
|
||||
Info: at initial placer iter 1, wirelen = 997
|
||||
Info: at initial placer iter 2, wirelen = 970
|
||||
Info: at initial placer iter 3, wirelen = 960
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 945, spread = 1040, legal = 1090; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.02s
|
||||
Info: of which solving equations: 0.00s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 24, wirelen = 1090
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 19, wirelen = 869
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 18, wirelen = 859
|
||||
Info: at iteration #12: temp = 0.000000, timing cost = 15, wirelen = 849
|
||||
Info: SA placement time 0.02s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 410.34 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.84 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.67 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10063, 10147) |*
|
||||
Info: [ 10147, 10231) |**
|
||||
Info: [ 10231, 10315) |***
|
||||
Info: [ 10315, 10399) |
|
||||
Info: [ 10399, 10483) |**
|
||||
Info: [ 10483, 10567) |
|
||||
Info: [ 10567, 10651) |*****
|
||||
Info: [ 10651, 10735) |
|
||||
Info: [ 10735, 10819) |****
|
||||
Info: [ 10819, 10903) |******************************
|
||||
Info: [ 10903, 10987) |************
|
||||
Info: [ 10987, 11071) |*************************
|
||||
Info: [ 11071, 11155) |********************************************************
|
||||
Info: [ 11155, 11239) |***************************************************
|
||||
Info: [ 11239, 11323) |*****
|
||||
Info: [ 11323, 11407) |***************
|
||||
Info: [ 11407, 11491) |*************************
|
||||
Info: [ 11491, 11575) |*
|
||||
Info: [ 11575, 11659) |************
|
||||
Info: [ 11659, 11743) |***********
|
||||
Info: Checksum: 0x1eb2f5c5
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 531 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 621 | 86 527 | 86 527 | 0| 0.06 0.06|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.06s
|
||||
Info: Checksum: 0xb377ad17
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source dut.GEN_COPY[3].rd_data_reg_TRELLIS_FF_Q_1.Q
|
||||
Info: routing 0.92 1.32 Net rd_data_flat[199] (35,36) -> (36,38)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.A
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_replicated.v:34.50-34.62
|
||||
Info: logic 0.31 1.62 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.35 1.98 Net chk_TRELLIS_FF_Q_DI[7] (36,38) -> (36,38)
|
||||
Info: Sink chk_TRELLIS_FF_Q_7.M
|
||||
Info: setup 0.00 1.98 Source chk_TRELLIS_FF_Q_7.M
|
||||
Info: 0.70 ns logic, 1.28 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[6]$tr_io.O
|
||||
Info: routing 2.78 2.78 Net seed[6]$TRELLIS_IO_IN (42,0) -> (36,37)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_3.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:23.23-23.27
|
||||
Info: logic 0.18 2.96 Source seed_LUT4_B_Z_LUT4_Z_3.F
|
||||
Info: routing 0.12 3.07 Net seed_LUT4_B_Z[6] (36,37) -> (36,37)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_1.DI
|
||||
Info: setup 0.00 3.07 Source lfsr_TRELLIS_FF_Q_1.DI
|
||||
Info: 0.18 ns logic, 2.89 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_4.Q
|
||||
Info: routing 2.83 3.22 Net checksum[4]$TRELLIS_IO_OUT (34,37) -> (90,38)
|
||||
Info: Sink checksum[4]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:50.15-50.18
|
||||
Info: 0.40 ns logic, 2.83 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 505.82 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.07 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.22 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10523, 10587) |*
|
||||
Info: [ 10587, 10651) |******
|
||||
Info: [ 10651, 10715) |***********
|
||||
Info: [ 10715, 10779) |*******
|
||||
Info: [ 10779, 10843) |*********
|
||||
Info: [ 10843, 10907) |************
|
||||
Info: [ 10907, 10971) |******
|
||||
Info: [ 10971, 11035) |*******************
|
||||
Info: [ 11035, 11099) |**
|
||||
Info: [ 11099, 11163) |**************
|
||||
Info: [ 11163, 11227) |**************************************************
|
||||
Info: [ 11227, 11291) |***********************
|
||||
Info: [ 11291, 11355) |***************************************
|
||||
Info: [ 11355, 11419) |*********
|
||||
Info: [ 11419, 11483) |***
|
||||
Info: [ 11483, 11547) |****************
|
||||
Info: [ 11547, 11611) |****************
|
||||
Info: [ 11611, 11675) |**
|
||||
Info: [ 11675, 11739) |*******
|
||||
Info: [ 11739, 11803) |********
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,197 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 136/43848 0%
|
||||
Info: logic LUTs: 40/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 64/ 5481 1%
|
||||
Info: RAMW LUTs: 32/10962 0%
|
||||
|
||||
Info: Total DFFs: 104/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 72 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x46141fa9
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 104/ 43848 0%
|
||||
Info: TRELLIS_COMB: 138/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 16/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 81 cells, random placement wirelen = 9806.
|
||||
Info: at initial placer iter 0, wirelen = 1338
|
||||
Info: at initial placer iter 1, wirelen = 1038
|
||||
Info: at initial placer iter 2, wirelen = 1036
|
||||
Info: at initial placer iter 3, wirelen = 983
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 979, spread = 1364, legal = 1395; time = 0.00s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 1007, spread = 1255, legal = 1274; time = 0.00s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 971, spread = 1233, legal = 1249; time = 0.00s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 969, spread = 1216, legal = 1250; time = 0.00s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 1003, spread = 1255, legal = 1272; time = 0.00s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 992, spread = 1194, legal = 1240; time = 0.00s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 997, spread = 1203, legal = 1245; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.04s
|
||||
Info: of which solving equations: 0.01s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 13, wirelen = 1240
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 17, wirelen = 878
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 16, wirelen = 875
|
||||
Info: at iteration #13: temp = 0.000000, timing cost = 18, wirelen = 863
|
||||
Info: SA placement time 0.03s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 334.56 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.27 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.16 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 9511, 9623) |+
|
||||
Info: [ 9623, 9735) |
|
||||
Info: [ 9735, 9847) |+
|
||||
Info: [ 9847, 9959) |
|
||||
Info: [ 9959, 10071) |**+
|
||||
Info: [ 10071, 10183) |*+
|
||||
Info: [ 10183, 10295) |+
|
||||
Info: [ 10295, 10407) |*******+
|
||||
Info: [ 10407, 10519) |**********+
|
||||
Info: [ 10519, 10631) |*************************+
|
||||
Info: [ 10631, 10743) |****************************************+
|
||||
Info: [ 10743, 10855) |****************+
|
||||
Info: [ 10855, 10967) |*************************************+
|
||||
Info: [ 10967, 11079) |************************************************************
|
||||
Info: [ 11079, 11191) |*************************************************+
|
||||
Info: [ 11191, 11303) |************************+
|
||||
Info: [ 11303, 11415) |***************************+
|
||||
Info: [ 11415, 11527) |**********+
|
||||
Info: [ 11527, 11639) |******+
|
||||
Info: [ 11639, 11751) |*****+
|
||||
Info: Checksum: 0xe86f58c8
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 932 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 84 907 | 84 907 | 45| 0.05 0.05|
|
||||
Info: 1044 | 84 952 | 0 45 | 0| 0.01 0.07|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.07s
|
||||
Info: Checksum: 0x41fe45e9
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source dut.GEN_COPY[4].rd_data_reg_TRELLIS_FF_Q.Q
|
||||
Info: routing 0.49 0.88 Net rd_data_flat[257] (12,24) -> (12,24)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_replicated.v:34.50-34.62
|
||||
Info: logic 0.18 1.06 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0_LUT4_Z_1.F
|
||||
Info: routing 0.74 1.80 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0[3] (12,24) -> (12,27)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_ALUT_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 1.98 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_ALUT_LUT4_Z.F
|
||||
Info: routing 0.00 1.98 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_ALUT (12,27) -> (12,27)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_BLUT_LUT4_Z.F1
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
|
||||
Info: logic 0.13 2.10 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.51 2.61 Net chk_TRELLIS_FF_Q_DI[1] (12,27) -> (12,26)
|
||||
Info: Sink chk_TRELLIS_FF_Q.M
|
||||
Info: setup 0.00 2.61 Source chk_TRELLIS_FF_Q.M
|
||||
Info: 0.88 ns logic, 1.73 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[7]$tr_io.O
|
||||
Info: routing 2.85 2.85 Net seed[7]$TRELLIS_IO_IN (42,0) -> (16,24)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_5.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:23.23-23.27
|
||||
Info: logic 0.18 3.03 Source seed_LUT4_B_Z_LUT4_Z_5.F
|
||||
Info: routing 0.12 3.15 Net seed_LUT4_B_Z[7] (16,24) -> (16,24)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_6.DI
|
||||
Info: setup 0.00 3.15 Source lfsr_TRELLIS_FF_Q_6.DI
|
||||
Info: 0.18 ns logic, 2.97 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_6.Q
|
||||
Info: routing 3.56 3.95 Net checksum[0]$TRELLIS_IO_OUT (10,25) -> (90,26)
|
||||
Info: Sink checksum[0]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 3.56 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 382.56 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.15 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.95 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 9886, 9982) |+
|
||||
Info: [ 9982, 10078) |**+
|
||||
Info: [ 10078, 10174) |+
|
||||
Info: [ 10174, 10270) |*+
|
||||
Info: [ 10270, 10366) |
|
||||
Info: [ 10366, 10462) |
|
||||
Info: [ 10462, 10558) |**+
|
||||
Info: [ 10558, 10654) |*****+
|
||||
Info: [ 10654, 10750) |********+
|
||||
Info: [ 10750, 10846) |*************+
|
||||
Info: [ 10846, 10942) |*************************************************+
|
||||
Info: [ 10942, 11038) |*********************************************+
|
||||
Info: [ 11038, 11134) |***********************************************+
|
||||
Info: [ 11134, 11230) |************************************************************
|
||||
Info: [ 11230, 11326) |******************************+
|
||||
Info: [ 11326, 11422) |********************************+
|
||||
Info: [ 11422, 11518) |************+
|
||||
Info: [ 11518, 11614) |******+
|
||||
Info: [ 11614, 11710) |***+
|
||||
Info: [ 11710, 11806) |****+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,203 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 135/43848 0%
|
||||
Info: logic LUTs: 135/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 0/ 5481 0%
|
||||
Info: RAMW LUTs: 0/10962 0%
|
||||
|
||||
Info: Total DFFs: 136/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 12 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x3465a66a
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 8/ 108 7%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 136/ 43848 0%
|
||||
Info: TRELLIS_COMB: 137/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 0/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 234 cells, random placement wirelen = 20216.
|
||||
Info: at initial placer iter 0, wirelen = 1287
|
||||
Info: at initial placer iter 1, wirelen = 1268
|
||||
Info: at initial placer iter 2, wirelen = 1125
|
||||
Info: at initial placer iter 3, wirelen = 1242
|
||||
Info: Running main analytical placer, max placement attempts per cell = 11250.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 1102, spread = 5281, legal = 5096; time = 0.01s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 1089, spread = 4459, legal = 4472; time = 0.00s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 1165, spread = 4233, legal = 4268; time = 0.00s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 1160, spread = 4531, legal = 4593; time = 0.00s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 1190, spread = 4586, legal = 4614; time = 0.00s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 1216, spread = 4637, legal = 4688; time = 0.00s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 1273, spread = 4686, legal = 4720; time = 0.00s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 1297, spread = 4821, legal = 4849; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.05s
|
||||
Info: of which solving equations: 0.03s
|
||||
Info: of which spreading cells: 0.01s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 75, wirelen = 4268
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 60, wirelen = 3430
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 71, wirelen = 3374
|
||||
Info: at iteration #11: temp = 0.000000, timing cost = 71, wirelen = 3365
|
||||
Info: SA placement time 0.03s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 119.60 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.57 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.97 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 2 endpoint(s)
|
||||
Info: + represents [1,2) endpoint(s)
|
||||
Info: [ 4139, 4519) |*+
|
||||
Info: [ 4519, 4899) |+
|
||||
Info: [ 4899, 5279) |+
|
||||
Info: [ 5279, 5659) |
|
||||
Info: [ 5659, 6039) |
|
||||
Info: [ 6039, 6419) |
|
||||
Info: [ 6419, 6799) |
|
||||
Info: [ 6799, 7179) |
|
||||
Info: [ 7179, 7559) |
|
||||
Info: [ 7559, 7939) |
|
||||
Info: [ 7939, 8319) |
|
||||
Info: [ 8319, 8699) |*+
|
||||
Info: [ 8699, 9079) |*+
|
||||
Info: [ 9079, 9459) |****+
|
||||
Info: [ 9459, 9839) |*********************+
|
||||
Info: [ 9839, 10219) |************************************************************
|
||||
Info: [ 10219, 10599) |**********************************************************+
|
||||
Info: [ 10599, 10979) |**********************************+
|
||||
Info: [ 10979, 11359) |**********************+
|
||||
Info: [ 11359, 11739) |************+
|
||||
Info: Checksum: 0x53011214
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 1160 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 251 733 | 251 733 | 452| 0.14 0.14|
|
||||
Info: 1521 | 317 1176 | 66 443 | 0| 0.08 0.22|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.22s
|
||||
Info: Checksum: 0x10253a26
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 4.10 4.10 Source dut.GEN_COPY[2].mem.0.0.DOA7
|
||||
Info: routing 1.55 5.65 Net dut.GEN_COPY[2].mem.0.0_DOA7[1] (15,34) -> (8,23)
|
||||
Info: Sink dut.GEN_COPY[1].mem.0.0_DOA7_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.83 Source dut.GEN_COPY[1].mem.0.0_DOA7_LUT4_Z.F
|
||||
Info: routing 0.46 6.29 Net dut.GEN_COPY[1].mem.0.0_DOA7[3] (8,23) -> (8,23)
|
||||
Info: Sink dut.GEN_COPY[0].mem.0.0_DOA7_LUT4_C_Z_LUT4_Z_2.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.47 Source dut.GEN_COPY[0].mem.0.0_DOA7_LUT4_C_Z_LUT4_Z_2.F
|
||||
Info: routing 0.60 7.07 Net dut.GEN_COPY[0].mem.0.0_DOA7_LUT4_C_Z[3] (8,23) -> (8,20)
|
||||
Info: Sink dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_ALUT_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.25 Source dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_ALUT_LUT4_Z.F
|
||||
Info: routing 0.00 7.25 Net dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_ALUT (8,20) -> (8,20)
|
||||
Info: Sink dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_BLUT_LUT4_Z.F1
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
|
||||
Info: logic 0.13 7.38 Source dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.27 7.65 Net dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z[7] (8,20) -> (8,20)
|
||||
Info: Sink chk_TRELLIS_FF_Q_7.M
|
||||
Info: setup 0.00 7.65 Source chk_TRELLIS_FF_Q_7.M
|
||||
Info: 4.76 ns logic, 2.89 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[4]$tr_io.O
|
||||
Info: routing 3.47 3.47 Net seed[4]$TRELLIS_IO_IN (90,23) -> (14,23)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_4.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:23.23-23.27
|
||||
Info: logic 0.18 3.65 Source seed_LUT4_B_Z_LUT4_Z_4.F
|
||||
Info: routing 0.12 3.77 Net seed_LUT4_B_Z[4] (14,23) -> (14,23)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_28.DI
|
||||
Info: setup 0.00 3.77 Source lfsr_TRELLIS_FF_Q_28.DI
|
||||
Info: 0.18 ns logic, 3.59 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_5.Q
|
||||
Info: routing 3.56 3.95 Net checksum[5]$TRELLIS_IO_OUT (11,20) -> (90,20)
|
||||
Info: Sink checksum[5]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 3.56 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 130.70 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.77 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.95 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 4 endpoint(s)
|
||||
Info: + represents [1,4) endpoint(s)
|
||||
Info: [ 4849, 5197) |+
|
||||
Info: [ 5197, 5545) |+
|
||||
Info: [ 5545, 5893) |+
|
||||
Info: [ 5893, 6241) |
|
||||
Info: [ 6241, 6589) |
|
||||
Info: [ 6589, 6937) |
|
||||
Info: [ 6937, 7285) |
|
||||
Info: [ 7285, 7633) |
|
||||
Info: [ 7633, 7981) |
|
||||
Info: [ 7981, 8329) |
|
||||
Info: [ 8329, 8677) |
|
||||
Info: [ 8677, 9025) |+
|
||||
Info: [ 9025, 9373) |*+
|
||||
Info: [ 9373, 9721) |+
|
||||
Info: [ 9721, 10069) |**+
|
||||
Info: [ 10069, 10417) |*************************+
|
||||
Info: [ 10417, 10765) |************************************************************
|
||||
Info: [ 10765, 11113) |****************************+
|
||||
Info: [ 11113, 11461) |******************+
|
||||
Info: [ 11461, 11809) |*****+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,62 @@
|
||||
// ================================================================
|
||||
// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
|
||||
// Same pattern as harness_nms_activation_replicated.v /
|
||||
// hardware/v2/synthesis/harness_memory_manager.v: reduces
|
||||
// nms_activation_banked's wide ports to an LFSR-driven input side and
|
||||
// an XOR-checksum output side, keeping only clk/rst/seed/checksum as
|
||||
// real pins.
|
||||
// ================================================================
|
||||
module harness_nms_activation_banked #(
|
||||
parameter DATA_WIDTH = 8,
|
||||
parameter P_IN = 8,
|
||||
parameter N_SLOTS = 4,
|
||||
parameter N_BANKS = 4,
|
||||
parameter MAX_TILES = 16,
|
||||
parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES)
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [7:0] seed,
|
||||
output wire [7:0] checksum
|
||||
);
|
||||
|
||||
reg [31:0] lfsr;
|
||||
always @(posedge clk) begin
|
||||
if (rst) lfsr <= {24'h0, seed} | 32'h1;
|
||||
else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
|
||||
end
|
||||
|
||||
wire fill_we = lfsr[0];
|
||||
wire [TIW-1:0] fill_tile_idx = lfsr[TIW-1:0];
|
||||
wire [DATA_WIDTH*P_IN-1:0] fill_data = {(DATA_WIDTH*P_IN/32+1){lfsr}};
|
||||
|
||||
wire [N_SLOTS-1:0] req_valid = lfsr[N_SLOTS-1:0];
|
||||
wire [N_SLOTS*TIW-1:0] req_tile_idx_flat = {(N_SLOTS*TIW/32+1){lfsr}};
|
||||
wire [N_SLOTS-1:0] ack;
|
||||
wire [N_SLOTS*DATA_WIDTH*P_IN-1:0] rd_data_flat;
|
||||
|
||||
nms_activation_banked #(
|
||||
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .N_SLOTS(N_SLOTS), .N_BANKS(N_BANKS), .MAX_TILES(MAX_TILES)
|
||||
) dut (
|
||||
.clk(clk), .rst(rst),
|
||||
.fill_we(fill_we), .fill_tile_idx(fill_tile_idx), .fill_data(fill_data),
|
||||
.req_valid(req_valid), .req_tile_idx_flat(req_tile_idx_flat),
|
||||
.ack(ack), .rd_data_flat(rd_data_flat)
|
||||
);
|
||||
|
||||
integer k;
|
||||
reg [7:0] chk;
|
||||
reg [7:0] chk_next;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
chk <= 8'h0;
|
||||
end else begin
|
||||
chk_next = chk ^ {7'h0, ack[0]};
|
||||
for (k = 0; k < N_SLOTS; k = k + 1)
|
||||
chk_next = chk_next ^ rd_data_flat[k*DATA_WIDTH*P_IN +: 8];
|
||||
chk <= chk_next;
|
||||
end
|
||||
end
|
||||
assign checksum = chk;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,64 @@
|
||||
// ================================================================
|
||||
// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
|
||||
// Same pattern as hardware/v2/synthesis/harness_memory_manager.v (see
|
||||
// its own header and errors.log ERR-0005): nms_activation_replicated's
|
||||
// wide ports (rd_data_flat alone is N_SLOTS*DATA_WIDTH*P_IN bits, e.g.
|
||||
// 512 bits at N_SLOTS=8) exceed the LFE5U-45F's TRELLIS_IO budget as a
|
||||
// bare top-level module (confirmed: nextpnr placement failed with
|
||||
// "no BELs remaining to implement cell type TRELLIS_IO" before this
|
||||
// harness existed). Drives every input from an internal LFSR and
|
||||
// reduces every output to a small XOR checksum, keeping only
|
||||
// clk/rst/seed/checksum as real pins, to get a representative Fmax for
|
||||
// the module's own logic/routing/BRAM.
|
||||
// ================================================================
|
||||
module harness_nms_activation_replicated #(
|
||||
parameter DATA_WIDTH = 8,
|
||||
parameter P_IN = 8,
|
||||
parameter N_SLOTS = 4,
|
||||
parameter MAX_TILES = 16,
|
||||
parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES)
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [7:0] seed,
|
||||
output wire [7:0] checksum
|
||||
);
|
||||
|
||||
reg [31:0] lfsr;
|
||||
always @(posedge clk) begin
|
||||
if (rst) lfsr <= {24'h0, seed} | 32'h1;
|
||||
else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
|
||||
end
|
||||
|
||||
wire fill_we = lfsr[0];
|
||||
wire [TIW-1:0] fill_addr = lfsr[TIW-1:0];
|
||||
wire [DATA_WIDTH*P_IN-1:0] fill_data = {(DATA_WIDTH*P_IN/32+1){lfsr}};
|
||||
|
||||
wire [N_SLOTS-1:0] rd_en = lfsr[N_SLOTS-1:0];
|
||||
wire [N_SLOTS*TIW-1:0] rd_addr_flat = {(N_SLOTS*TIW/32+1){lfsr}};
|
||||
wire [N_SLOTS*DATA_WIDTH*P_IN-1:0] rd_data_flat;
|
||||
|
||||
nms_activation_replicated #(
|
||||
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .N_SLOTS(N_SLOTS), .MAX_TILES(MAX_TILES)
|
||||
) dut (
|
||||
.clk(clk), .rst(rst),
|
||||
.fill_we(fill_we), .fill_addr(fill_addr), .fill_data(fill_data),
|
||||
.rd_en(rd_en), .rd_addr_flat(rd_addr_flat), .rd_data_flat(rd_data_flat)
|
||||
);
|
||||
|
||||
integer k;
|
||||
reg [7:0] chk;
|
||||
reg [7:0] chk_next;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
chk <= 8'h0;
|
||||
end else begin
|
||||
chk_next = chk;
|
||||
for (k = 0; k < N_SLOTS; k = k + 1)
|
||||
chk_next = chk_next ^ rd_data_flat[k*DATA_WIDTH*P_IN +: 8];
|
||||
chk <= chk_next;
|
||||
end
|
||||
end
|
||||
assign checksum = chk;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,53 @@
|
||||
// ================================================================
|
||||
// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
|
||||
// Same pattern as harness_nms_activation_replicated.v.
|
||||
// ================================================================
|
||||
module harness_nms_weight_direct #(
|
||||
parameter DATA_WIDTH = 8,
|
||||
parameter P_IN = 8,
|
||||
parameter N_SLOTS = 4,
|
||||
parameter MAX_TILES = 16,
|
||||
parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES)
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [7:0] seed,
|
||||
output wire [7:0] checksum
|
||||
);
|
||||
|
||||
reg [31:0] lfsr;
|
||||
always @(posedge clk) begin
|
||||
if (rst) lfsr <= {24'h0, seed} | 32'h1;
|
||||
else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
|
||||
end
|
||||
|
||||
wire [N_SLOTS-1:0] fill_we = lfsr[N_SLOTS-1:0];
|
||||
wire [N_SLOTS*TIW-1:0] fill_addr_flat = {(N_SLOTS*TIW/32+1){lfsr}};
|
||||
wire [N_SLOTS*DATA_WIDTH*P_IN-1:0] fill_data_flat = {(N_SLOTS*DATA_WIDTH*P_IN/32+1){lfsr}};
|
||||
wire [N_SLOTS-1:0] rd_en = lfsr[N_SLOTS-1:0];
|
||||
wire [N_SLOTS*TIW-1:0] rd_addr_flat = {(N_SLOTS*TIW/32+1){lfsr}};
|
||||
wire [N_SLOTS*DATA_WIDTH*P_IN-1:0] rd_data_flat;
|
||||
|
||||
nms_weight_direct #(
|
||||
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .N_SLOTS(N_SLOTS), .MAX_TILES(MAX_TILES)
|
||||
) dut (
|
||||
.clk(clk), .rst(rst),
|
||||
.fill_we(fill_we), .fill_addr_flat(fill_addr_flat), .fill_data_flat(fill_data_flat),
|
||||
.rd_en(rd_en), .rd_addr_flat(rd_addr_flat), .rd_data_flat(rd_data_flat)
|
||||
);
|
||||
|
||||
integer k;
|
||||
reg [7:0] chk, chk_next;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
chk <= 8'h0;
|
||||
end else begin
|
||||
chk_next = chk;
|
||||
for (k = 0; k < N_SLOTS; k = k + 1)
|
||||
chk_next = chk_next ^ rd_data_flat[k*DATA_WIDTH*P_IN +: 8];
|
||||
chk <= chk_next;
|
||||
end
|
||||
end
|
||||
assign checksum = chk;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,53 @@
|
||||
// ================================================================
|
||||
// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
|
||||
// Same pattern as harness_nms_weight_direct.v, for nms_weight_packed.v.
|
||||
// ================================================================
|
||||
module harness_nms_weight_packed #(
|
||||
parameter DATA_WIDTH = 8,
|
||||
parameter P_IN = 8,
|
||||
parameter N_SLOTS = 4,
|
||||
parameter MAX_TILES = 16,
|
||||
parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES)
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [7:0] seed,
|
||||
output wire [7:0] checksum
|
||||
);
|
||||
|
||||
reg [31:0] lfsr;
|
||||
always @(posedge clk) begin
|
||||
if (rst) lfsr <= {24'h0, seed} | 32'h1;
|
||||
else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
|
||||
end
|
||||
|
||||
wire [N_SLOTS-1:0] fill_we = lfsr[N_SLOTS-1:0];
|
||||
wire [N_SLOTS*TIW-1:0] fill_addr_flat = {(N_SLOTS*TIW/32+1){lfsr}};
|
||||
wire [N_SLOTS*DATA_WIDTH*P_IN-1:0] fill_data_flat = {(N_SLOTS*DATA_WIDTH*P_IN/32+1){lfsr}};
|
||||
wire [N_SLOTS-1:0] rd_en = lfsr[N_SLOTS-1:0];
|
||||
wire [N_SLOTS*TIW-1:0] rd_addr_flat = {(N_SLOTS*TIW/32+1){lfsr}};
|
||||
wire [N_SLOTS*DATA_WIDTH*P_IN-1:0] rd_data_flat;
|
||||
|
||||
nms_weight_packed #(
|
||||
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .N_SLOTS(N_SLOTS), .MAX_TILES(MAX_TILES)
|
||||
) dut (
|
||||
.clk(clk), .rst(rst),
|
||||
.fill_we(fill_we), .fill_addr_flat(fill_addr_flat), .fill_data_flat(fill_data_flat),
|
||||
.rd_en(rd_en), .rd_addr_flat(rd_addr_flat), .rd_data_flat(rd_data_flat)
|
||||
);
|
||||
|
||||
integer k;
|
||||
reg [7:0] chk, chk_next;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
chk <= 8'h0;
|
||||
end else begin
|
||||
chk_next = chk;
|
||||
for (k = 0; k < N_SLOTS; k = k + 1)
|
||||
chk_next = chk_next ^ rd_data_flat[k*DATA_WIDTH*P_IN +: 8];
|
||||
chk <= chk_next;
|
||||
end
|
||||
end
|
||||
assign checksum = chk;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,336 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 2173/43848 4%
|
||||
Info: logic LUTs: 1407/43848 3%
|
||||
Info: carry LUTs: 304/43848 0%
|
||||
Info: RAM LUTs: 308/ 5481 5%
|
||||
Info: RAMW LUTs: 154/10962 1%
|
||||
|
||||
Info: Total DFFs: 2281/43848 5%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
|
||||
Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
|
||||
Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
|
||||
Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
|
||||
Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
|
||||
Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
|
||||
Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
|
||||
Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
|
||||
Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
|
||||
Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
|
||||
Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
|
||||
Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
|
||||
Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
|
||||
Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
|
||||
Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
|
||||
Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 1029 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0xfe3f4fd3
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 157/ 245 64%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 8/ 72 11%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 2281/ 43848 5%
|
||||
Info: TRELLIS_COMB: 2259/ 43848 5%
|
||||
Info: TRELLIS_RAMW: 77/ 5481 1%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 2625 cells, random placement wirelen = 212068.
|
||||
Info: at initial placer iter 0, wirelen = 17253
|
||||
Info: at initial placer iter 1, wirelen = 14170
|
||||
Info: at initial placer iter 2, wirelen = 13066
|
||||
Info: at initial placer iter 3, wirelen = 12284
|
||||
Info: Running main analytical placer, max placement attempts per cell = 2859636.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 12155, spread = 25573, legal = 29844; time = 0.04s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 13175, spread = 22368, legal = 25598; time = 0.04s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 13713, spread = 21083, legal = 23850; time = 0.03s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 14347, spread = 20481, legal = 23500; time = 0.03s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 14724, spread = 19681, legal = 23507; time = 0.03s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 15018, spread = 19364, legal = 22865; time = 0.03s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 15273, spread = 19177, legal = 22269; time = 0.03s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 15478, spread = 19053, legal = 22879; time = 0.03s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 15702, spread = 18973, legal = 22684; time = 0.03s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 15829, spread = 19111, legal = 22266; time = 0.03s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 16016, spread = 19453, legal = 22186; time = 0.03s
|
||||
Info: at iteration #12, type ALL: wirelen solved = 16457, spread = 19312, legal = 22493; time = 0.03s
|
||||
Info: at iteration #13, type ALL: wirelen solved = 16396, spread = 18738, legal = 23307; time = 0.03s
|
||||
Info: at iteration #14, type ALL: wirelen solved = 16340, spread = 19469, legal = 22694; time = 0.03s
|
||||
Info: at iteration #15, type ALL: wirelen solved = 16602, spread = 19460, legal = 22544; time = 0.03s
|
||||
Info: at iteration #16, type ALL: wirelen solved = 16585, spread = 20958, legal = 23613; time = 0.03s
|
||||
Info: HeAP Placer Time: 0.71s
|
||||
Info: of which solving equations: 0.39s
|
||||
Info: of which spreading cells: 0.07s
|
||||
Info: of which strict legalisation: 0.12s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 97, wirelen = 22186
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 168, wirelen = 20275
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 339, wirelen = 19647
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 393, wirelen = 19477
|
||||
Info: at iteration #19: temp = 0.000000, timing cost = 354, wirelen = 19398
|
||||
Info: SA placement time 1.01s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 139.35 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> <async> : 14.17 ns
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.47 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.64 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 9 endpoint(s)
|
||||
Info: + represents [1,9) endpoint(s)
|
||||
Info: [ 5324, 5655) |*+
|
||||
Info: [ 5655, 5986) |*******+
|
||||
Info: [ 5986, 6317) |****+
|
||||
Info: [ 6317, 6648) |**********+
|
||||
Info: [ 6648, 6979) |**************+
|
||||
Info: [ 6979, 7310) |**********************************+
|
||||
Info: [ 7310, 7641) |*************************+
|
||||
Info: [ 7641, 7972) |*************************+
|
||||
Info: [ 7972, 8303) |**********************+
|
||||
Info: [ 8303, 8634) |*******************+
|
||||
Info: [ 8634, 8965) |******************************+
|
||||
Info: [ 8965, 9296) |***********************+
|
||||
Info: [ 9296, 9627) |******************************+
|
||||
Info: [ 9627, 9958) |***********************************************************+
|
||||
Info: [ 9958, 10289) |*****************************************************+
|
||||
Info: [ 10289, 10620) |************************************************************
|
||||
Info: [ 10620, 10951) |**************************************+
|
||||
Info: [ 10951, 11282) |*************************************************+
|
||||
Info: [ 11282, 11613) |***************************************************+
|
||||
Info: [ 11613, 11944) |*****************+
|
||||
Info: Checksum: 0x53ff0ace
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 13124 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 188 811 | 188 811 | 12395| 0.20 0.20|
|
||||
Info: 2000 | 274 1725 | 86 914 | 11535| 0.10 0.30|
|
||||
Info: 3000 | 321 2678 | 47 953 | 10631| 0.13 0.43|
|
||||
Info: 4000 | 398 3601 | 77 923 | 9726| 0.08 0.51|
|
||||
Info: 5000 | 537 4462 | 139 861 | 8882| 0.07 0.58|
|
||||
Info: 6000 | 704 5273 | 167 811 | 8057| 0.09 0.67|
|
||||
Info: 7000 | 945 5993 | 241 720 | 7309| 0.06 0.73|
|
||||
Info: 8000 | 1111 6800 | 166 807 | 6506| 0.06 0.79|
|
||||
Info: 9000 | 1280 7575 | 169 775 | 5684| 0.06 0.85|
|
||||
Info: 10000 | 1356 8454 | 76 879 | 4764| 0.06 0.91|
|
||||
Info: 11000 | 1424 9312 | 68 858 | 3847| 0.07 0.98|
|
||||
Info: 12000 | 1482 10252 | 58 940 | 2915| 0.06 1.04|
|
||||
Info: 13000 | 1633 11100 | 151 848 | 2113| 0.13 1.17|
|
||||
Info: 14000 | 1698 12005 | 65 905 | 1197| 0.23 1.40|
|
||||
Info: 15000 | 1778 12897 | 80 892 | 321| 0.24 1.64|
|
||||
Info: 15417 | 1845 13236 | 67 339 | 0| 0.16 1.81|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 1.81s
|
||||
Info: Checksum: 0x77f864cc
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_dep_mgr.node_state[15]_TRELLIS_FF_Q_1.Q
|
||||
Info: routing 0.67 1.07 Net u_dataflow_core.u_dep_mgr.node_state[15][0] (23,24) -> (22,24)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z.D
|
||||
Info: logic 0.18 1.25 Source u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z.F
|
||||
Info: routing 0.61 1.85 Net u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0_PFUMX_Z_C0[4] (22,24) -> (24,23)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 2.05 Source u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.47 2.52 Net u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[4] (24,23) -> (24,24)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 2.71 Source u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.47 3.18 Net u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_C0[4] (24,24) -> (26,24)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 3.37 Source u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.32 3.69 Net u_dataflow_core.u_dep_mgr.node_state[3]_LUT4_D_Z[5] (26,24) -> (25,24)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[0]_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 3.89 Source u_dataflow_core.u_dep_mgr.node_state[0]_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.96 4.85 Net u_dataflow_core.u_dep_mgr.node_state[0]_LUT4_D_Z[4] (25,24) -> (26,17)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.first_ready_idx_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 5.04 Source u_dataflow_core.u_dep_mgr.first_ready_idx_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.90 5.95 Net u_dataflow_core.u_dep_mgr.first_ready_idx[0] (26,17) -> (27,13)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_n_tiles.0.3$DPRAM_COMB2.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:100.24-100.39
|
||||
Info: logic 0.18 6.12 Source u_dataflow_core.u_dep_mgr.node_n_tiles.0.3$DPRAM_COMB2.F
|
||||
Info: routing 0.12 6.24 Net u_dataflow_core.u_dep_mgr.node_n_tiles.0.1_DO[14] (27,13) -> (27,13)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.ready_n_tiles_TRELLIS_FF_Q_9.DI
|
||||
Info: setup 0.00 6.24 Source u_dataflow_core.u_dep_mgr.ready_n_tiles_TRELLIS_FF_Q_9.DI
|
||||
Info: 1.72 ns logic, 4.52 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source reg_node_id[0]$tr_io.O
|
||||
Info: routing 4.18 4.18 Net reg_node_id[0]$TRELLIS_IO_IN (90,47) -> (28,24)
|
||||
Info: Sink reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_D_C_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
|
||||
Info: logic 0.18 4.36 Source reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_D_C_LUT4_Z.F
|
||||
Info: routing 1.30 5.66 Net reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_D_C[2] (28,24) -> (26,23)
|
||||
Info: Sink reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1_D_LUT4_Z_2.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.84 Source reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1_D_LUT4_Z_2.F
|
||||
Info: routing 0.60 6.44 Net reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1_D[2] (26,23) -> (26,23)
|
||||
Info: Sink reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.62 Source reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1.F
|
||||
Info: routing 0.36 6.99 Net reg_valid_LUT4_C_Z_LUT4_Z_2_D[0] (26,23) -> (26,23)
|
||||
Info: Sink reg_valid_LUT4_C_Z_LUT4_Z_2.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.17 Source reg_valid_LUT4_C_Z_LUT4_Z_2.F
|
||||
Info: routing 0.03 7.20 Net reg_valid_LUT4_C_Z[4] (26,23) -> (26,23)
|
||||
Info: Sink reg_ready_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.38 Source reg_ready_LUT4_Z.F
|
||||
Info: routing 2.92 10.30 Net reg_ready$TRELLIS_IO_OUT (26,23) -> (90,23)
|
||||
Info: Sink reg_ready$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: 0.90 ns logic, 9.40 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source reg_node_id[0]$tr_io.O
|
||||
Info: routing 4.18 4.18 Net reg_node_id[0]$TRELLIS_IO_IN (90,47) -> (28,24)
|
||||
Info: Sink reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_D_C_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
|
||||
Info: logic 0.18 4.36 Source reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_D_C_LUT4_Z.F
|
||||
Info: routing 1.30 5.66 Net reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_D_C[2] (28,24) -> (26,23)
|
||||
Info: Sink reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1_D_LUT4_Z_2.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.84 Source reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1_D_LUT4_Z_2.F
|
||||
Info: routing 0.60 6.44 Net reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1_D[2] (26,23) -> (26,23)
|
||||
Info: Sink reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.62 Source reg_valid_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z_1.F
|
||||
Info: routing 0.36 6.99 Net reg_valid_LUT4_C_Z_LUT4_Z_2_D[0] (26,23) -> (26,23)
|
||||
Info: Sink reg_valid_LUT4_C_Z_LUT4_Z_2.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.17 Source reg_valid_LUT4_C_Z_LUT4_Z_2.F
|
||||
Info: routing 0.59 7.75 Net reg_valid_LUT4_C_Z[4] (26,23) -> (24,27)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[6]_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 7.95 Source u_dataflow_core.u_dep_mgr.node_state[6]_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.78 8.73 Net u_dataflow_core.u_dep_mgr.node_resolved[10]_TRELLIS_FF_Q_CE_LUT4_Z_D[4] (24,27) -> (20,29)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[2]_TRELLIS_FF_Q_LSR_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 8.91 Source u_dataflow_core.u_dep_mgr.node_resolved[2]_TRELLIS_FF_Q_LSR_LUT4_Z.F
|
||||
Info: routing 0.71 9.62 Net u_dataflow_core.u_dep_mgr.node_resolved[2]_TRELLIS_FF_Q_LSR (20,29) -> (21,26)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[2]_TRELLIS_FF_Q_2.LSR
|
||||
Info: setup 0.29 9.90 Source u_dataflow_core.u_dep_mgr.node_resolved[2]_TRELLIS_FF_Q_2.LSR
|
||||
Info: 1.38 ns logic, 8.52 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_dep_mgr.node_state[3]_TRELLIS_FF_Q_1.Q
|
||||
Info: routing 0.46 0.85 Net u_dataflow_core.u_dep_mgr.node_state[3][1] (24,26) -> (24,26)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[2]_LUT4_C_D_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 1.03 Source u_dataflow_core.u_dep_mgr.node_state[2]_LUT4_C_D_LUT4_Z.F
|
||||
Info: routing 0.45 1.49 Net u_dataflow_core.u_dep_mgr.node_state[2]_LUT4_C_D[3] (24,26) -> (24,26)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[2]_LUT4_C.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 1.67 Source u_dataflow_core.u_dep_mgr.node_state[2]_LUT4_C.F
|
||||
Info: routing 0.38 2.05 Net u_dataflow_core.u_dep_mgr.node_state[2]_LUT4_C_Z[3] (24,26) -> (24,25)
|
||||
Info: Sink reg_valid_LUT4_C_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 2.23 Source reg_valid_LUT4_C_Z_LUT4_Z.F
|
||||
Info: routing 0.76 2.99 Net reg_valid_LUT4_C_Z[2] (24,25) -> (26,23)
|
||||
Info: Sink reg_ready_LUT4_Z.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 3.17 Source reg_ready_LUT4_Z.F
|
||||
Info: routing 2.92 6.09 Net reg_ready$TRELLIS_IO_OUT (26,23) -> (90,23)
|
||||
Info: Sink reg_ready$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: 1.12 ns logic, 4.98 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 160.18 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> <async> : 10.30 ns
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.90 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.09 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 9 endpoint(s)
|
||||
Info: + represents [1,9) endpoint(s)
|
||||
Info: [ 6257, 6534) |******+
|
||||
Info: [ 6534, 6811) |**************+
|
||||
Info: [ 6811, 7088) |****************+
|
||||
Info: [ 7088, 7365) |**************+
|
||||
Info: [ 7365, 7642) |*******************+
|
||||
Info: [ 7642, 7919) |*****************+
|
||||
Info: [ 7919, 8196) |****************+
|
||||
Info: [ 8196, 8473) |************+
|
||||
Info: [ 8473, 8750) |******************+
|
||||
Info: [ 8750, 9027) |***********************+
|
||||
Info: [ 9027, 9304) |*******************+
|
||||
Info: [ 9304, 9581) |********************+
|
||||
Info: [ 9581, 9858) |***************************+
|
||||
Info: [ 9858, 10135) |***************************************+
|
||||
Info: [ 10135, 10412) |*****************************+
|
||||
Info: [ 10412, 10689) |**********************************************+
|
||||
Info: [ 10689, 10966) |************************************************************
|
||||
Info: [ 10966, 11243) |********************************************************+
|
||||
Info: [ 11243, 11520) |****************************************************+
|
||||
Info: [ 11520, 11797) |************************************+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,431 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 3134/43848 7%
|
||||
Info: logic LUTs: 1948/43848 4%
|
||||
Info: carry LUTs: 532/43848 1%
|
||||
Info: RAM LUTs: 436/ 5481 7%
|
||||
Info: RAMW LUTs: 218/10962 1%
|
||||
|
||||
Info: Total DFFs: 3522/43848 8%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
|
||||
Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
|
||||
Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
|
||||
Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
|
||||
Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
|
||||
Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
|
||||
Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
|
||||
Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
|
||||
Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
|
||||
Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
|
||||
Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
|
||||
Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
|
||||
Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
|
||||
Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
|
||||
Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
|
||||
Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 1574 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x402d222a
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 157/ 245 64%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 16/ 72 22%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 3522/ 43848 8%
|
||||
Info: TRELLIS_COMB: 3268/ 43848 7%
|
||||
Info: TRELLIS_RAMW: 109/ 5481 1%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 3884 cells, random placement wirelen = 321215.
|
||||
Info: at initial placer iter 0, wirelen = 17565
|
||||
Info: at initial placer iter 1, wirelen = 14264
|
||||
Info: at initial placer iter 2, wirelen = 13173
|
||||
Info: at initial placer iter 3, wirelen = 12611
|
||||
Info: Running main analytical placer, max placement attempts per cell = 6253416.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 12338, spread = 45332, legal = 50715; time = 0.07s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 15231, spread = 37486, legal = 42468; time = 0.06s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 16968, spread = 32224, legal = 37720; time = 0.05s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 17739, spread = 30435, legal = 35388; time = 0.05s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 18593, spread = 29680, legal = 35283; time = 0.05s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 19532, spread = 28805, legal = 34860; time = 0.05s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 20152, spread = 28933, legal = 33241; time = 0.04s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 20744, spread = 28754, legal = 34006; time = 0.05s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 20768, spread = 28888, legal = 34571; time = 0.05s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 20842, spread = 29598, legal = 34991; time = 0.05s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 21269, spread = 32317, legal = 35678; time = 0.04s
|
||||
Info: at iteration #12, type ALL: wirelen solved = 21827, spread = 32505, legal = 36242; time = 0.04s
|
||||
Info: HeAP Placer Time: 0.90s
|
||||
Info: of which solving equations: 0.51s
|
||||
Info: of which spreading cells: 0.08s
|
||||
Info: of which strict legalisation: 0.15s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 194, wirelen = 33241
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 238, wirelen = 30937
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 253, wirelen = 30039
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 264, wirelen = 29759
|
||||
Info: at iteration #20: temp = 0.000000, timing cost = 235, wirelen = 29657
|
||||
Info: at iteration #21: temp = 0.000000, timing cost = 251, wirelen = 29652
|
||||
Info: SA placement time 1.76s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 89.09 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> <async> : 16.31 ns
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 16.90 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.63 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 23 endpoint(s)
|
||||
Info: + represents [1,23) endpoint(s)
|
||||
Info: [ 1276, 1809) |*+
|
||||
Info: [ 1809, 2342) |**+
|
||||
Info: [ 2342, 2875) |****+
|
||||
Info: [ 2875, 3408) |***********+
|
||||
Info: [ 3408, 3941) |**+
|
||||
Info: [ 3941, 4474) |**+
|
||||
Info: [ 4474, 5007) |**+
|
||||
Info: [ 5007, 5540) |*****+
|
||||
Info: [ 5540, 6073) |*****+
|
||||
Info: [ 6073, 6606) |****+
|
||||
Info: [ 6606, 7139) |*****+
|
||||
Info: [ 7139, 7672) |************+
|
||||
Info: [ 7672, 8205) |****************+
|
||||
Info: [ 8205, 8738) |***************************+
|
||||
Info: [ 8738, 9271) |***********************************+
|
||||
Info: [ 9271, 9804) |***************************************+
|
||||
Info: [ 9804, 10337) |************************************************************
|
||||
Info: [ 10337, 10870) |***************************************+
|
||||
Info: [ 10870, 11403) |***************************************+
|
||||
Info: [ 11403, 11936) |******************************+
|
||||
Info: Checksum: 0x7631c1a6
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 18985 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 88 911 | 88 911 | 18087| 0.24 0.24|
|
||||
Info: 2000 | 148 1851 | 60 940 | 17194| 0.13 0.38|
|
||||
Info: 3000 | 201 2798 | 53 947 | 16254| 0.10 0.47|
|
||||
Info: 4000 | 268 3731 | 67 933 | 15338| 0.08 0.55|
|
||||
Info: 5000 | 393 4606 | 125 875 | 14481| 0.09 0.64|
|
||||
Info: 6000 | 469 5513 | 76 907 | 13559| 0.08 0.72|
|
||||
Info: 7000 | 607 6368 | 138 855 | 12713| 0.09 0.81|
|
||||
Info: 8000 | 696 7260 | 89 892 | 11813| 0.08 0.89|
|
||||
Info: 9000 | 858 8083 | 162 823 | 10987| 0.10 1.00|
|
||||
Info: 10000 | 973 8955 | 115 872 | 10113| 0.06 1.06|
|
||||
Info: 11000 | 1062 9840 | 89 885 | 9204| 0.07 1.13|
|
||||
Info: 12000 | 1119 10737 | 57 897 | 8261| 0.07 1.21|
|
||||
Info: 13000 | 1169 11607 | 50 870 | 7312| 0.06 1.27|
|
||||
Info: 14000 | 1215 12483 | 46 876 | 6366| 0.08 1.35|
|
||||
Info: 15000 | 1259 13384 | 44 901 | 5417| 0.07 1.42|
|
||||
Info: 16000 | 1318 14284 | 59 900 | 4487| 0.07 1.49|
|
||||
Info: 17000 | 1386 15213 | 68 929 | 3645| 0.08 1.57|
|
||||
Info: 18000 | 1499 16100 | 113 887 | 2793| 0.10 1.67|
|
||||
Info: 19000 | 1578 16990 | 79 890 | 1876| 0.20 1.87|
|
||||
Info: 20000 | 1645 17891 | 67 901 | 959| 0.20 2.07|
|
||||
Info: 21000 | 1773 18730 | 128 839 | 136| 0.36 2.42|
|
||||
Info: 21172 | 1806 18861 | 33 131 | 0| 0.08 2.50|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 2.50s
|
||||
Info: Checksum: 0x82e9e49c
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_act_fill.resident_tag_TRELLIS_FF_Q_15.Q
|
||||
Info: routing 0.67 1.06 Net u_dataflow_core.act_resident_tag[15] (26,37) -> (26,36)
|
||||
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 1.24 Source u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z.F
|
||||
Info: routing 0.54 1.78 Net u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_SD[6] (26,36) -> (26,35)
|
||||
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 1.98 Source u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.62 2.59 Net u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D[2] (26,35) -> (26,37)
|
||||
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 2.77 Source u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D_LUT4_Z.F
|
||||
Info: routing 0.55 3.32 Net u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z_D[3] (26,37) -> (22,37)
|
||||
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 3.50 Source u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z_LUT4_Z.F
|
||||
Info: routing 0.80 4.30 Net u_dataflow_core.GEN_SLOT[0].u_mm.operand_valid_LUT4_A_Z[4] (22,37) -> (24,40)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.48 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
|
||||
Info: routing 0.31 4.79 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_D[1] (24,40) -> (24,40)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.97 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z.F
|
||||
Info: routing 0.84 5.82 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C[1] (24,40) -> (24,38)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 6.17 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 6.17 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (24,38) -> (24,38)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 6.17 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 6.17 Net $nextpnr_CCU2C_43$CIN (24,38) -> (24,38)
|
||||
Info: Sink $nextpnr_CCU2C_43$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 6.50 Source $nextpnr_CCU2C_43$CCU2_COMB0.F
|
||||
Info: routing 0.73 7.22 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B0[4] (24,38) -> (23,40)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 7.42 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.81 8.23 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (23,40) -> (23,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
|
||||
Info: logic 0.35 8.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 8.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (23,39) -> (23,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 8.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 8.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (23,39) -> (24,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 8.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 8.64 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (24,39) -> (24,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 8.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 8.64 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (24,39) -> (24,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 8.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 8.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (24,39) -> (24,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 8.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 8.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (24,39) -> (24,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 8.75 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 8.75 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (24,39) -> (24,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 8.75 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 8.75 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (24,39) -> (24,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 8.81 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 8.81 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (24,39) -> (24,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 8.81 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 8.81 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN (24,39) -> (25,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 8.86 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 8.86 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (25,39) -> (25,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 8.86 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 8.86 Net $nextpnr_CCU2C_37$CIN (25,39) -> (25,39)
|
||||
Info: Sink $nextpnr_CCU2C_37$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 9.19 Source $nextpnr_CCU2C_37$CCU2_COMB0.F
|
||||
Info: routing 0.78 9.97 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR[2] (25,39) -> (24,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 10.15 Source u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.F
|
||||
Info: routing 0.59 10.74 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B_Z (24,35) -> (25,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_21.CE
|
||||
Info: setup 0.00 10.74 Source u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_21.CE
|
||||
Info: 3.51 ns logic, 7.23 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source reg_node_id[0]$tr_io.O
|
||||
Info: routing 4.57 4.57 Net reg_node_id[0]$TRELLIS_IO_IN (90,50) -> (5,37)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
|
||||
Info: logic 0.18 4.75 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_LUT4_Z_1.F
|
||||
Info: routing 1.17 5.92 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C[2] (5,37) -> (5,38)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.10 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
|
||||
Info: routing 0.75 6.86 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[2] (5,38) -> (7,37)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.04 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
|
||||
Info: routing 0.38 7.42 Net reg_ready_PFUMX_Z_C0[2] (7,37) -> (7,37)
|
||||
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.31 7.72 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 3.95 11.67 Net reg_ready$TRELLIS_IO_OUT (7,37) -> (90,35)
|
||||
Info: Sink reg_ready$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: 0.85 ns logic, 10.83 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source reg_node_id[0]$tr_io.O
|
||||
Info: routing 4.57 4.57 Net reg_node_id[0]$TRELLIS_IO_IN (90,50) -> (5,37)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
|
||||
Info: logic 0.18 4.75 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_LUT4_Z_1.F
|
||||
Info: routing 1.17 5.92 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C[2] (5,37) -> (5,38)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.10 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
|
||||
Info: routing 0.75 6.86 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[2] (5,38) -> (7,37)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.04 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
|
||||
Info: routing 0.38 7.42 Net reg_ready_PFUMX_Z_C0[2] (7,37) -> (7,37)
|
||||
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.31 7.72 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.79 8.52 Net reg_ready$TRELLIS_IO_OUT (7,37) -> (15,35)
|
||||
Info: Sink reg_valid_LUT4_B.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: logic 0.18 8.69 Source reg_valid_LUT4_B.F
|
||||
Info: routing 1.02 9.72 Net reg_valid_LUT4_B_Z[2] (15,35) -> (5,33)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 9.90 Source u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.F
|
||||
Info: routing 0.58 10.48 Net u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D[2] (5,33) -> (5,31)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_D_2.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 10.66 Source u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_D_2.F
|
||||
Info: routing 0.20 10.86 Net u_dataflow_core.u_dep_mgr.node_resolved[7]_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_D_2_Z[1] (5,31) -> (5,31)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[47]_LUT4_A_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 11.04 Source u_dataflow_core.u_dep_mgr.node_producer_ids[47]_LUT4_A_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z.F
|
||||
Info: routing 0.71 11.75 Net u_dataflow_core.u_dep_mgr.node_producer_ids[47]_LUT4_A_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] (5,31) -> (6,33)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q_CE_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 11.94 Source u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q_CE_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.54 12.48 Net u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q_CE (6,33) -> (5,35)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q.CE
|
||||
Info: setup 0.00 12.48 Source u_dataflow_core.u_dep_mgr.node_state[11]_TRELLIS_FF_Q.CE
|
||||
Info: 1.76 ns logic, 10.72 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_dep_mgr.node_state[7]_TRELLIS_FF_Q.Q
|
||||
Info: routing 0.50 0.89 Net u_dataflow_core.u_dep_mgr.first_ready_idx_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_C0_PFUMX_Z_C0_PFUMX_Z_C0[3] (4,39) -> (4,39)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_C0_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 1.07 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_C0_LUT4_Z.F
|
||||
Info: routing 0.61 1.68 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_C0[4] (4,39) -> (8,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 1.87 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.48 2.35 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_C[4] (8,40) -> (6,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 2.55 Source reg_ready_PFUMX_Z_C0_LUT4_Z_2_D_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.55 3.10 Net reg_ready_PFUMX_Z_C0_LUT4_Z_2_D[2] (6,40) -> (6,37)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_2.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 3.28 Source reg_ready_PFUMX_Z_C0_LUT4_Z_2.F
|
||||
Info: routing 0.34 3.62 Net reg_ready_PFUMX_Z_C0[4] (6,37) -> (7,37)
|
||||
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 3.82 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 3.95 7.76 Net reg_ready$TRELLIS_IO_OUT (7,37) -> (90,35)
|
||||
Info: Sink reg_ready$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: 1.33 ns logic, 6.43 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 93.10 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> <async> : 11.67 ns
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.48 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.76 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 25 endpoint(s)
|
||||
Info: + represents [1,25) endpoint(s)
|
||||
Info: [ 1759, 2261) |+
|
||||
Info: [ 2261, 2763) |+
|
||||
Info: [ 2763, 3265) |
|
||||
Info: [ 3265, 3767) |
|
||||
Info: [ 3767, 4269) |*+
|
||||
Info: [ 4269, 4771) |*****+
|
||||
Info: [ 4771, 5273) |*******+
|
||||
Info: [ 5273, 5775) |******+
|
||||
Info: [ 5775, 6277) |*******+
|
||||
Info: [ 6277, 6779) |*********+
|
||||
Info: [ 6779, 7281) |*****+
|
||||
Info: [ 7281, 7783) |***+
|
||||
Info: [ 7783, 8285) |*******+
|
||||
Info: [ 8285, 8787) |********************+
|
||||
Info: [ 8787, 9289) |**************************+
|
||||
Info: [ 9289, 9791) |*******************************+
|
||||
Info: [ 9791, 10293) |************************************+
|
||||
Info: [ 10293, 10795) |****************************************************+
|
||||
Info: [ 10795, 11297) |************************************************************
|
||||
Info: [ 11297, 11799) |*******************************************+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,552 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 4846/43848 11%
|
||||
Info: logic LUTs: 2812/43848 6%
|
||||
Info: carry LUTs: 996/43848 2%
|
||||
Info: RAM LUTs: 692/ 5481 12%
|
||||
Info: RAMW LUTs: 346/10962 3%
|
||||
|
||||
Info: Total DFFs: 6004/43848 13%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
|
||||
Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
|
||||
Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
|
||||
Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
|
||||
Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
|
||||
Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
|
||||
Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
|
||||
Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
|
||||
Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
|
||||
Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
|
||||
Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
|
||||
Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
|
||||
Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
|
||||
Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
|
||||
Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
|
||||
Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 2736 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x649504e0
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 157/ 245 64%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 32/ 72 44%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 6004/ 43848 13%
|
||||
Info: TRELLIS_COMB: 5080/ 43848 11%
|
||||
Info: TRELLIS_RAMW: 173/ 5481 3%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 6193 cells, random placement wirelen = 501683.
|
||||
Info: at initial placer iter 0, wirelen = 18522
|
||||
Info: at initial placer iter 1, wirelen = 15366
|
||||
Info: at initial placer iter 2, wirelen = 14364
|
||||
Info: at initial placer iter 3, wirelen = 13481
|
||||
Info: Running main analytical placer, max placement attempts per cell = 16379226.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 13356, spread = 91775, legal = 102139; time = 0.14s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 20348, spread = 65450, legal = 76519; time = 0.10s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 24614, spread = 57698, legal = 66114; time = 0.09s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 28073, spread = 53999, legal = 65606; time = 0.10s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 28434, spread = 52381, legal = 65600; time = 0.10s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 29167, spread = 50620, legal = 63488; time = 0.11s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 29950, spread = 51283, legal = 63584; time = 0.10s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 30855, spread = 50533, legal = 61410; time = 0.10s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 31395, spread = 50508, legal = 60313; time = 0.09s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 32403, spread = 50131, legal = 61572; time = 0.11s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 32885, spread = 50204, legal = 61427; time = 0.10s
|
||||
Info: at iteration #12, type ALL: wirelen solved = 33025, spread = 51042, legal = 62928; time = 0.10s
|
||||
Info: at iteration #13, type ALL: wirelen solved = 33453, spread = 51250, legal = 60701; time = 0.08s
|
||||
Info: at iteration #14, type ALL: wirelen solved = 33853, spread = 52032, legal = 64518; time = 0.09s
|
||||
Info: HeAP Placer Time: 1.99s
|
||||
Info: of which solving equations: 1.01s
|
||||
Info: of which spreading cells: 0.18s
|
||||
Info: of which strict legalisation: 0.46s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 204, wirelen = 60313
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 150, wirelen = 54376
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 136, wirelen = 52588
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 133, wirelen = 51968
|
||||
Info: at iteration #20: temp = 0.000000, timing cost = 133, wirelen = 51723
|
||||
Info: at iteration #25: temp = 0.000000, timing cost = 133, wirelen = 51589
|
||||
Info: at iteration #25: temp = 0.000000, timing cost = 133, wirelen = 51590
|
||||
Info: SA placement time 4.18s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 48.70 MHz (FAIL at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> <async> : 12.27 ns
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 18.50 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.64 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 51 endpoint(s)
|
||||
Info: + represents [1,51) endpoint(s)
|
||||
Info: [ -8033, -7035) |+
|
||||
Info: [ -7035, -6037) |+
|
||||
Info: [ -6037, -5039) |
|
||||
Info: [ -5039, -4041) |
|
||||
Info: [ -4041, -3043) |
|
||||
Info: [ -3043, -2045) |
|
||||
Info: [ -2045, -1047) |
|
||||
Info: [ -1047, -49) |
|
||||
Info: [ -49, 949) |+
|
||||
Info: [ 949, 1947) |*+
|
||||
Info: [ 1947, 2945) |*******+
|
||||
Info: [ 2945, 3943) |***+
|
||||
Info: [ 3943, 4941) |*****+
|
||||
Info: [ 4941, 5939) |***********+
|
||||
Info: [ 5939, 6937) |***************+
|
||||
Info: [ 6937, 7935) |*********************+
|
||||
Info: [ 7935, 8933) |*************************************+
|
||||
Info: [ 8933, 9931) |************************************************************
|
||||
Info: [ 9931, 10929) |***********************************************************+
|
||||
Info: [ 10929, 11927) |****************************************************+
|
||||
Info: Checksum: 0x7342e501
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 30507 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 31 968 | 31 968 | 29549| 0.24 0.24|
|
||||
Info: 2000 | 131 1868 | 100 900 | 28655| 0.14 0.38|
|
||||
Info: 3000 | 212 2787 | 81 919 | 27753| 0.13 0.51|
|
||||
Info: 4000 | 270 3729 | 58 942 | 26815| 0.13 0.64|
|
||||
Info: 5000 | 447 4552 | 177 823 | 26025| 0.11 0.75|
|
||||
Info: 6000 | 500 5499 | 53 947 | 25084| 0.09 0.84|
|
||||
Info: 7000 | 597 6368 | 97 869 | 24211| 0.12 0.96|
|
||||
Info: 8000 | 696 7255 | 99 887 | 23327| 0.11 1.08|
|
||||
Info: 9000 | 776 8174 | 80 919 | 22413| 0.10 1.18|
|
||||
Info: 10000 | 825 9125 | 49 951 | 21464| 0.10 1.28|
|
||||
Info: 11000 | 865 10085 | 40 960 | 20513| 0.10 1.38|
|
||||
Info: 12000 | 917 11026 | 52 941 | 19566| 0.13 1.51|
|
||||
Info: 13000 | 972 11968 | 55 942 | 18633| 0.08 1.59|
|
||||
Info: 14000 | 1037 12887 | 65 919 | 17735| 0.11 1.70|
|
||||
Info: 15000 | 1085 13823 | 48 936 | 16788| 0.08 1.78|
|
||||
Info: 16000 | 1126 14775 | 41 952 | 15844| 0.09 1.87|
|
||||
Info: 17000 | 1169 15711 | 43 936 | 14899| 0.08 1.96|
|
||||
Info: 18000 | 1200 16627 | 31 916 | 13934| 0.09 2.05|
|
||||
Info: 19000 | 1243 17551 | 43 924 | 12980| 0.08 2.12|
|
||||
Info: 20000 | 1276 18433 | 33 882 | 12015| 0.08 2.20|
|
||||
Info: 21000 | 1314 19344 | 38 911 | 11057| 0.06 2.26|
|
||||
Info: 22000 | 1349 20244 | 35 900 | 10101| 0.08 2.35|
|
||||
Info: 23000 | 1404 21102 | 55 858 | 9173| 0.06 2.41|
|
||||
Info: 24000 | 1449 21998 | 45 896 | 8226| 0.11 2.52|
|
||||
Info: 25000 | 1496 22909 | 47 911 | 7276| 0.06 2.59|
|
||||
Info: 26000 | 1587 23817 | 91 908 | 6402| 0.15 2.74|
|
||||
Info: 27000 | 1672 24732 | 85 915 | 5516| 0.08 2.81|
|
||||
Info: 28000 | 1825 25579 | 153 847 | 4756| 0.18 2.99|
|
||||
Info: 29000 | 1958 26446 | 133 867 | 3926| 0.10 3.09|
|
||||
Info: 30000 | 2056 27326 | 98 880 | 3049| 0.15 3.24|
|
||||
Info: 31000 | 2142 28190 | 86 864 | 2149| 0.25 3.49|
|
||||
Info: 32000 | 2264 29037 | 122 847 | 1336| 0.37 3.86|
|
||||
Info: 33000 | 2437 29828 | 173 791 | 612| 0.57 4.44|
|
||||
Info: 33917 | 2655 30496 | 218 668 | 0| 1.12 5.56|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 5.56s
|
||||
Info: Checksum: 0x198c1857
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.GEN_SLOT[0].u_mm.x_base_reg_TRELLIS_FF_Q_19.Q
|
||||
Info: routing 0.89 1.29 Net u_dataflow_core.job_x_base_flat[19] (46,30) -> (46,33)
|
||||
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:38.44-38.55
|
||||
Info: logic 0.18 1.47 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
|
||||
Info: routing 0.00 1.47 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT (46,33) -> (46,33)
|
||||
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
|
||||
Info: logic 0.13 1.59 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.00 1.59 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1 (46,33) -> (46,33)
|
||||
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
|
||||
Info: logic 0.18 1.77 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.88 2.65 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D[3] (46,33) -> (47,36)
|
||||
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 2.84 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1.F
|
||||
Info: routing 1.01 3.84 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D[2] (47,36) -> (37,37)
|
||||
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.02 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.F
|
||||
Info: routing 0.52 4.54 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C[1] (37,37) -> (38,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.72 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
|
||||
Info: routing 0.33 5.05 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D[1] (38,37) -> (38,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.23 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D.F
|
||||
Info: routing 0.86 6.08 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z[1] (38,37) -> (36,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 6.44 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 6.44 Net $nextpnr_CCU2C_35$CIN (36,36) -> (36,36)
|
||||
Info: Sink $nextpnr_CCU2C_35$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 6.77 Source $nextpnr_CCU2C_35$CCU2_COMB0.F
|
||||
Info: routing 0.37 7.14 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0[4] (36,36) -> (38,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.32 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z_LUT4_Z.F
|
||||
Info: routing 0.47 7.79 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[2] (38,36) -> (38,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D_1_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.97 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D_1_Z_LUT4_Z.F
|
||||
Info: routing 0.90 8.87 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D_1_Z[1] (38,36) -> (34,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB0.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 9.23 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 9.23 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_FCI_INT (34,35) -> (34,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 9.23 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 9.23 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN (34,35) -> (35,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 9.28 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 9.28 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_FCI_INT (35,35) -> (35,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 9.28 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 9.28 Net $nextpnr_CCU2C_31$CIN (35,35) -> (35,35)
|
||||
Info: Sink $nextpnr_CCU2C_31$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 9.61 Source $nextpnr_CCU2C_31$CCU2_COMB0.F
|
||||
Info: routing 0.40 10.01 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT (35,35) -> (36,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.18 10.19 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D.F
|
||||
Info: routing 0.78 10.96 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D_Z_LUT4_Z_C[2] (36,33) -> (35,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 11.14 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z.F
|
||||
Info: routing 1.01 12.15 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_C[1] (35,35) -> (33,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 12.50 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.50 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (33,33) -> (34,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.56 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.56 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,33) -> (34,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.56 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.56 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (34,33) -> (34,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.62 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.62 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,33) -> (34,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.62 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.62 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (34,33) -> (34,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.67 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.67 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,33) -> (34,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.67 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.67 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN (34,33) -> (34,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.73 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.73 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_FCI_INT (34,33) -> (34,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.73 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.73 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN (34,33) -> (35,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_FCI_INT (35,33) -> (35,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.78 Net $nextpnr_CCU2C_33$CIN (35,33) -> (35,33)
|
||||
Info: Sink $nextpnr_CCU2C_33$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 13.11 Source $nextpnr_CCU2C_33$CCU2_COMB0.F
|
||||
Info: routing 0.34 13.46 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_COUT (35,33) -> (37,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.18 13.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D.F
|
||||
Info: routing 0.22 13.85 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C[2] (37,33) -> (37,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 14.03 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F
|
||||
Info: routing 1.01 15.05 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1 (37,33) -> (35,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
|
||||
Info: logic 0.35 15.40 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 15.40 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,32) -> (35,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 15.46 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 15.46 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,32) -> (35,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 15.46 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 15.46 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,32) -> (36,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 15.51 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 15.51 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,32) -> (36,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 15.51 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 15.51 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,32) -> (36,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 15.57 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 15.57 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,32) -> (36,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 15.57 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 15.57 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,32) -> (36,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 15.63 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 15.63 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,32) -> (36,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 15.63 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 15.63 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,32) -> (36,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 15.68 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 15.68 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,32) -> (36,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 15.68 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 15.68 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN (36,32) -> (37,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 15.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 15.74 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (37,32) -> (37,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 15.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 15.74 Net $nextpnr_CCU2C_25$CIN (37,32) -> (37,32)
|
||||
Info: Sink $nextpnr_CCU2C_25$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 16.07 Source $nextpnr_CCU2C_25$CCU2_COMB0.F
|
||||
Info: routing 0.82 16.89 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR[2] (37,32) -> (46,31)
|
||||
Info: Sink u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 17.07 Source u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.F
|
||||
Info: routing 0.59 17.66 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B_Z (46,31) -> (41,29)
|
||||
Info: Sink u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_21.CE
|
||||
Info: setup 0.00 17.66 Source u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_21.CE
|
||||
Info: 6.26 ns logic, 11.40 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source reg_node_id[1]$tr_io.O
|
||||
Info: routing 4.96 4.96 Net reg_node_id[1]$TRELLIS_IO_IN (90,44) -> (17,15)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_C_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
|
||||
Info: logic 0.18 5.14 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_C_LUT4_Z_1.F
|
||||
Info: routing 0.88 6.02 Net reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0[2] (17,15) -> (18,14)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C_LUT4_Z_2.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.20 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C_LUT4_Z_2.F
|
||||
Info: routing 0.58 6.77 Net reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C[4] (18,14) -> (16,15)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 6.97 Source reg_ready_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.29 7.26 Net reg_ready_PFUMX_Z_C0_LUT4_Z_D[3] (16,15) -> (16,15)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.43 Source reg_ready_PFUMX_Z_C0_LUT4_Z.F
|
||||
Info: routing 0.51 7.94 Net reg_ready_PFUMX_Z_C0[4] (16,15) -> (16,16)
|
||||
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 8.13 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 1.25 9.38 Net reg_ready$TRELLIS_IO_OUT (16,16) -> (0,17)
|
||||
Info: Sink reg_ready$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: 0.93 ns logic, 8.45 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source reg_node_id[1]$tr_io.O
|
||||
Info: routing 4.96 4.96 Net reg_node_id[1]$TRELLIS_IO_IN (90,44) -> (17,15)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_C_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
|
||||
Info: logic 0.18 5.14 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_C_LUT4_Z_1.F
|
||||
Info: routing 0.88 6.02 Net reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0[2] (17,15) -> (18,14)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C_LUT4_Z_2.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.20 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C_LUT4_Z_2.F
|
||||
Info: routing 0.58 6.77 Net reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C[4] (18,14) -> (16,15)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 6.97 Source reg_ready_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.29 7.26 Net reg_ready_PFUMX_Z_C0_LUT4_Z_D[3] (16,15) -> (16,15)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.43 Source reg_ready_PFUMX_Z_C0_LUT4_Z.F
|
||||
Info: routing 0.51 7.94 Net reg_ready_PFUMX_Z_C0[4] (16,15) -> (16,16)
|
||||
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 8.13 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 1.31 9.44 Net reg_ready$TRELLIS_IO_OUT (16,16) -> (26,25)
|
||||
Info: Sink reg_valid_LUT4_B.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: logic 0.18 9.62 Source reg_valid_LUT4_B.F
|
||||
Info: routing 1.47 11.09 Net reg_valid_LUT4_B_Z[2] (26,25) -> (16,17)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 11.27 Source u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.F
|
||||
Info: routing 0.86 12.13 Net u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z_D[2] (16,17) -> (13,12)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 12.31 Source u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z.F
|
||||
Info: routing 0.39 12.70 Net u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR[1] (13,12) -> (13,12)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[50]_LUT4_B_Z_PFUMX_ALUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 12.88 Source u_dataflow_core.u_dep_mgr.node_producer_ids[50]_LUT4_B_Z_PFUMX_ALUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
|
||||
Info: routing 0.72 13.60 Net u_dataflow_core.u_dep_mgr.node_producer_ids[50]_LUT4_B_Z_PFUMX_ALUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (13,12) -> (15,13)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_CE_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 13.78 Source u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_CE_LUT4_Z.F
|
||||
Info: routing 0.58 14.36 Net u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_CE (15,13) -> (17,14)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_1.CE
|
||||
Info: setup 0.00 14.36 Source u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_1.CE
|
||||
Info: 1.83 ns logic, 12.53 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source u_psram_ctrl.dq_oe_TRELLIS_FF_Q.Q
|
||||
Info: routing 4.60 4.99 Net u_psram_ctrl.dq_oe (51,8) -> (11,64)
|
||||
Info: Sink psram_dq[6]$tr_io$invert_T.A
|
||||
Info: Defined in:
|
||||
Info: hardware/v1/rtl/psram_controller.v:188.27-188.32
|
||||
Info: logic 0.18 5.17 Source psram_dq[6]$tr_io$invert_T.F
|
||||
Info: routing 0.86 6.03 Net psram_dq[6]$tr_io$invert_T$conn$Z (11,64) -> (11,71)
|
||||
Info: Sink psram_dq[6]$tr_io.T
|
||||
Info: 0.57 ns logic, 5.46 ns routing
|
||||
|
||||
ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 56.62 MHz (FAIL at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> <async> : 9.38 ns
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 14.36 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.03 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 59 endpoint(s)
|
||||
Info: + represents [1,59) endpoint(s)
|
||||
Info: [ -5161, -4313) |+
|
||||
Info: [ -4313, -3465) |+
|
||||
Info: [ -3465, -2617) |
|
||||
Info: [ -2617, -1769) |
|
||||
Info: [ -1769, -921) |
|
||||
Info: [ -921, -73) |
|
||||
Info: [ -73, 775) |
|
||||
Info: [ 775, 1623) |
|
||||
Info: [ 1623, 2471) |+
|
||||
Info: [ 2471, 3319) |*+
|
||||
Info: [ 3319, 4167) |******+
|
||||
Info: [ 4167, 5015) |*+
|
||||
Info: [ 5015, 5863) |****+
|
||||
Info: [ 5863, 6711) |*********+
|
||||
Info: [ 6711, 7559) |**********+
|
||||
Info: [ 7559, 8407) |*****************+
|
||||
Info: [ 8407, 9255) |************************+
|
||||
Info: [ 9255, 10103) |************************************************+
|
||||
Info: [ 10103, 10951) |************************************************************
|
||||
Info: [ 10951, 11799) |*******************************************************+
|
||||
0 warnings, 1 error
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,894 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 8523/43848 19%
|
||||
Info: logic LUTs: 4805/43848 10%
|
||||
Info: carry LUTs: 1912/43848 4%
|
||||
Info: RAM LUTs: 1204/ 5481 21%
|
||||
Info: RAMW LUTs: 602/10962 5%
|
||||
|
||||
Info: Total DFFs: 10966/43848 25%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
|
||||
Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
|
||||
Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
|
||||
Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
|
||||
Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
|
||||
Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
|
||||
Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
|
||||
Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
|
||||
Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
|
||||
Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
|
||||
Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
|
||||
Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
|
||||
Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
|
||||
Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
|
||||
Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
|
||||
Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 4999 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0xcd88748e
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 157/ 245 64%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 64/ 72 88%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 10966/ 43848 25%
|
||||
Info: TRELLIS_COMB: 8953/ 43848 20%
|
||||
Info: TRELLIS_RAMW: 301/ 5481 5%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 10928 cells, random placement wirelen = 888368.
|
||||
Info: at initial placer iter 0, wirelen = 17970
|
||||
Info: at initial placer iter 1, wirelen = 15622
|
||||
Info: at initial placer iter 2, wirelen = 15109
|
||||
Info: at initial placer iter 3, wirelen = 14883
|
||||
Info: Running main analytical placer, max placement attempts per cell = 52234420.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 13670, spread = 212169, legal = 250678; time = 0.82s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 31315, spread = 142620, legal = 180431; time = 0.78s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 39835, spread = 128648, legal = 158988; time = 0.72s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 44200, spread = 120379, legal = 150878; time = 0.71s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 46996, spread = 121353, legal = 151998; time = 0.73s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 50066, spread = 121356, legal = 149815; time = 0.70s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 52166, spread = 122431, legal = 152767; time = 0.69s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 52945, spread = 125389, legal = 151575; time = 0.71s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 54575, spread = 126100, legal = 157631; time = 0.69s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 55469, spread = 126053, legal = 162107; time = 0.70s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 55395, spread = 129268, legal = 159748; time = 0.70s
|
||||
Info: HeAP Placer Time: 8.99s
|
||||
Info: of which solving equations: 1.79s
|
||||
Info: of which spreading cells: 0.28s
|
||||
Info: of which strict legalisation: 6.38s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 432, wirelen = 149815
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 343, wirelen = 136392
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 326, wirelen = 133037
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 319, wirelen = 131916
|
||||
Info: at iteration #20: temp = 0.000000, timing cost = 315, wirelen = 131398
|
||||
Info: at iteration #25: temp = 0.000000, timing cost = 315, wirelen = 131063
|
||||
Info: at iteration #30: temp = 0.000000, timing cost = 314, wirelen = 130888
|
||||
Info: at iteration #35: temp = 0.000000, timing cost = 317, wirelen = 130821
|
||||
Info: at iteration #36: temp = 0.000000, timing cost = 316, wirelen = 130811
|
||||
Info: SA placement time 13.51s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 29.59 MHz (FAIL at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> <async> : 12.76 ns
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 14.75 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.88 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 147 endpoint(s)
|
||||
Info: + represents [1,147) endpoint(s)
|
||||
Info: [-21293, -19632) |+
|
||||
Info: [-19632, -17971) |
|
||||
Info: [-17971, -16310) |
|
||||
Info: [-16310, -14649) |
|
||||
Info: [-14649, -12988) |
|
||||
Info: [-12988, -11327) |
|
||||
Info: [-11327, -9666) |
|
||||
Info: [ -9666, -8005) |
|
||||
Info: [ -8005, -6344) |
|
||||
Info: [ -6344, -4683) |
|
||||
Info: [ -4683, -3022) |+
|
||||
Info: [ -3022, -1361) |+
|
||||
Info: [ -1361, 300) |+
|
||||
Info: [ 300, 1961) |*+
|
||||
Info: [ 1961, 3622) |***+
|
||||
Info: [ 3622, 5283) |*********+
|
||||
Info: [ 5283, 6944) |****************+
|
||||
Info: [ 6944, 8605) |********************************+
|
||||
Info: [ 8605, 10266) |************************************************************
|
||||
Info: [ 10266, 11927) |*****************************************************+
|
||||
Info: Checksum: 0x929bb535
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 53981 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 202 797 | 202 797 | 53224| 0.60 0.60|
|
||||
Info: 2000 | 338 1661 | 136 864 | 52429| 0.27 0.87|
|
||||
Info: 3000 | 513 2486 | 175 825 | 51709| 0.33 1.20|
|
||||
Info: 4000 | 677 3322 | 164 836 | 50934| 0.15 1.35|
|
||||
Info: 5000 | 931 4068 | 254 746 | 50228| 0.13 1.48|
|
||||
Info: 6000 | 1114 4885 | 183 817 | 49438| 0.14 1.62|
|
||||
Info: 7000 | 1306 5693 | 192 808 | 48684| 0.18 1.79|
|
||||
Info: 8000 | 1542 6457 | 236 764 | 47987| 0.17 1.97|
|
||||
Info: 9000 | 1745 7254 | 203 797 | 47265| 0.14 2.11|
|
||||
Info: 10000 | 1825 8174 | 80 920 | 46478| 0.13 2.23|
|
||||
Info: 11000 | 1938 8990 | 113 816 | 45622| 0.13 2.37|
|
||||
Info: 12000 | 2210 9704 | 272 714 | 44953| 0.11 2.47|
|
||||
Info: 13000 | 2391 10501 | 181 797 | 44157| 0.10 2.58|
|
||||
Info: 14000 | 2431 11461 | 40 960 | 43213| 0.13 2.71|
|
||||
Info: 15000 | 2518 12373 | 87 912 | 42322| 0.12 2.83|
|
||||
Info: 16000 | 2597 13292 | 79 919 | 41521| 0.13 2.96|
|
||||
Info: 17000 | 2677 14212 | 80 920 | 40712| 0.13 3.08|
|
||||
Info: 18000 | 2742 15146 | 65 934 | 39910| 0.13 3.22|
|
||||
Info: 19000 | 2799 16089 | 57 943 | 39085| 0.17 3.39|
|
||||
Info: 20000 | 2833 17055 | 34 966 | 38166| 0.13 3.52|
|
||||
Info: 21000 | 2900 17987 | 67 932 | 37307| 0.11 3.63|
|
||||
Info: 22000 | 2961 18926 | 61 939 | 36469| 0.14 3.77|
|
||||
Info: 23000 | 3006 19881 | 45 955 | 35534| 0.11 3.88|
|
||||
Info: 24000 | 3057 20829 | 51 948 | 34692| 0.12 4.00|
|
||||
Info: 25000 | 3113 21770 | 56 941 | 33777| 0.10 4.11|
|
||||
Info: 26000 | 3198 22677 | 85 907 | 32952| 0.13 4.24|
|
||||
Info: 27000 | 3248 23622 | 50 945 | 32023| 0.12 4.36|
|
||||
Info: 28000 | 3308 24554 | 60 932 | 31196| 0.11 4.46|
|
||||
Info: 29000 | 3369 25466 | 61 912 | 30279| 0.12 4.58|
|
||||
Info: 30000 | 3419 26397 | 50 931 | 29350| 0.10 4.68|
|
||||
Info: 31000 | 3487 27314 | 68 917 | 28492| 0.11 4.79|
|
||||
Info: 32000 | 3523 28264 | 36 950 | 27538| 0.11 4.89|
|
||||
Info: 33000 | 3560 29207 | 37 943 | 26588| 0.13 5.02|
|
||||
Info: 34000 | 3632 30093 | 72 886 | 25697| 0.13 5.15|
|
||||
Info: 35000 | 3725 30970 | 93 877 | 24940| 0.16 5.30|
|
||||
Info: 36000 | 3799 31827 | 74 857 | 24092| 0.12 5.43|
|
||||
Info: 37000 | 3951 32641 | 152 814 | 23320| 0.19 5.62|
|
||||
Info: 38000 | 4008 33541 | 57 900 | 22411| 0.11 5.73|
|
||||
Info: 39000 | 4073 34418 | 65 877 | 21504| 0.12 5.85|
|
||||
Info: 40000 | 4157 35313 | 84 895 | 20622| 0.17 6.02|
|
||||
Info: 41000 | 4224 36173 | 67 860 | 19827| 0.13 6.16|
|
||||
Info: 42000 | 4262 37061 | 38 888 | 18875| 0.09 6.25|
|
||||
Info: 43000 | 4343 37914 | 81 853 | 17986| 0.14 6.39|
|
||||
Info: 44000 | 4518 38715 | 175 801 | 17276| 0.26 6.64|
|
||||
Info: 45000 | 4550 39596 | 32 881 | 16316| 0.07 6.71|
|
||||
Info: 46000 | 4632 40443 | 82 847 | 15503| 0.12 6.83|
|
||||
Info: 47000 | 4687 41294 | 55 851 | 14568| 0.09 6.93|
|
||||
Info: 48000 | 4894 42085 | 207 791 | 13913| 0.28 7.20|
|
||||
Info: 49000 | 5067 42851 | 173 766 | 13288| 0.20 7.41|
|
||||
Info: 50000 | 5132 43738 | 65 887 | 12378| 0.09 7.50|
|
||||
Info: 51000 | 5243 44614 | 111 876 | 11588| 0.11 7.61|
|
||||
Info: 52000 | 5455 45402 | 212 788 | 10951| 0.28 7.89|
|
||||
Info: 53000 | 5595 46262 | 140 860 | 10252| 0.19 8.08|
|
||||
Info: 54000 | 5658 47199 | 63 937 | 9334| 0.08 8.16|
|
||||
Info: 55000 | 5860 47997 | 202 798 | 8870| 0.29 8.45|
|
||||
Info: 56000 | 6121 48736 | 261 739 | 8240| 0.36 8.81|
|
||||
Info: 57000 | 6210 49647 | 89 911 | 7407| 0.13 8.93|
|
||||
Info: 58000 | 6376 50481 | 166 834 | 6673| 0.17 9.10|
|
||||
Info: 59000 | 6521 51336 | 145 855 | 5822| 0.10 9.20|
|
||||
Info: 60000 | 6664 52183 | 143 847 | 5269| 0.23 9.43|
|
||||
Info: 61000 | 6903 52920 | 239 737 | 4885| 0.30 9.73|
|
||||
Info: 62000 | 7054 53744 | 151 824 | 4324| 0.29 10.02|
|
||||
Info: 63000 | 7209 54544 | 155 800 | 3747| 0.26 10.29|
|
||||
Info: 64000 | 7412 55314 | 203 770 | 3236| 0.35 10.64|
|
||||
Info: 65000 | 7574 56105 | 162 791 | 2585| 0.30 10.95|
|
||||
Info: 66000 | 7732 56912 | 158 807 | 1972| 0.37 11.32|
|
||||
Info: 67000 | 7922 57684 | 190 772 | 1420| 0.50 11.82|
|
||||
Info: 68000 | 8106 58470 | 184 786 | 848| 0.36 12.18|
|
||||
Info: 69000 | 8265 59285 | 159 815 | 339| 0.36 12.53|
|
||||
Info: 69653 | 8375 59807 | 110 522 | 0| 0.28 12.81|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 12.81s
|
||||
Info: Checksum: 0xbb354049
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_act_fill.resident_tag_TRELLIS_FF_Q_7.Q
|
||||
Info: routing 0.89 1.28 Net u_dataflow_core.act_resident_tag[8] (40,40) -> (37,40)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 1.46 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_Z.F
|
||||
Info: routing 0.89 2.35 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C[0] (37,40) -> (37,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_A_Z_PFUMX_ALUT_BLUT_LUT4_Z.A
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.31 2.66 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_A_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.81 3.47 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_A_Z_PFUMX_ALUT_Z[2] (37,37) -> (35,38)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_A_Z_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 3.65 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_A_Z_LUT4_Z_1.F
|
||||
Info: routing 0.72 4.37 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_A_Z[5] (35,38) -> (34,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D_Z_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 4.56 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D_Z_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
|
||||
Info: routing 0.86 5.43 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D_Z_LUT4_Z_C[1] (34,39) -> (35,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 5.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 5.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,35) -> (35,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 5.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 5.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,35) -> (35,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 5.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 5.84 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,35) -> (35,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 5.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 5.84 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,35) -> (35,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 5.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 5.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,35) -> (35,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 5.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 5.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,35) -> (36,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 5.95 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 5.95 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,35) -> (36,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 5.95 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 5.95 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,35) -> (36,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 6.01 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 6.01 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,35) -> (36,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 6.01 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 6.01 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,35) -> (36,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 6.06 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 6.06 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,35) -> (36,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 6.06 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 6.06 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (36,35) -> (36,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 6.12 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 6.12 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (36,35) -> (36,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 6.12 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 6.12 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (36,35) -> (37,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 6.17 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 6.17 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (37,35) -> (37,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 6.17 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 6.17 Net $nextpnr_CCU2C_171$CIN (37,35) -> (37,35)
|
||||
Info: Sink $nextpnr_CCU2C_171$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 6.50 Source $nextpnr_CCU2C_171$CCU2_COMB0.F
|
||||
Info: routing 0.55 7.05 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (37,35) -> (36,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 7.23 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
|
||||
Info: routing 0.84 8.07 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[2] (36,36) -> (38,40)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 8.26 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z.F
|
||||
Info: routing 0.84 9.09 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[1] (38,40) -> (38,38)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 9.45 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 9.45 Net $nextpnr_CCU2C_183$CIN (38,38) -> (38,38)
|
||||
Info: Sink $nextpnr_CCU2C_183$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 9.77 Source $nextpnr_CCU2C_183$CCU2_COMB0.F
|
||||
Info: routing 0.52 10.30 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (38,38) -> (38,39)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 10.48 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
|
||||
Info: routing 0.80 11.28 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[2] (38,39) -> (37,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 11.46 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F
|
||||
Info: routing 0.85 12.31 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1[1] (37,36) -> (38,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 12.67 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.67 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,37) -> (38,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.72 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.72 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (38,37) -> (38,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.72 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.72 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,37) -> (39,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,37) -> (39,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,37) -> (39,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.84 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,37) -> (39,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.84 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,37) -> (39,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,37) -> (39,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (39,37) -> (39,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 12.95 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 12.95 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (39,37) -> (39,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 12.95 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 12.95 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (39,37) -> (40,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 13.00 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 13.00 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (40,37) -> (40,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 13.00 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 13.00 Net $nextpnr_CCU2C_195$CIN (40,37) -> (40,37)
|
||||
Info: Sink $nextpnr_CCU2C_195$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 13.33 Source $nextpnr_CCU2C_195$CCU2_COMB0.F
|
||||
Info: routing 0.56 13.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (40,37) -> (42,38)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 14.07 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
|
||||
Info: routing 1.00 15.08 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[2] (42,38) -> (37,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 15.26 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_Z_1.F
|
||||
Info: routing 0.80 16.06 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT[3] (37,36) -> (38,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 16.41 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 16.41 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,36) -> (39,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 16.47 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 16.47 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,36) -> (39,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 16.47 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 16.47 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,36) -> (39,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 16.52 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 16.52 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,36) -> (39,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 16.52 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 16.52 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,36) -> (39,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 16.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 16.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,36) -> (39,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 16.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 16.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (39,36) -> (39,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 16.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 16.64 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (39,36) -> (39,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 16.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 16.64 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (39,36) -> (40,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 16.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 16.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (40,36) -> (40,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 16.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 16.69 Net $nextpnr_CCU2C_199$CIN (40,36) -> (40,36)
|
||||
Info: Sink $nextpnr_CCU2C_199$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 17.02 Source $nextpnr_CCU2C_199$CCU2_COMB0.F
|
||||
Info: routing 0.79 17.81 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z_D[4] (40,36) -> (43,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_C_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 17.99 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_C_Z_LUT4_Z.F
|
||||
Info: routing 0.35 18.34 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C[2] (43,37) -> (43,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 18.52 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z.F
|
||||
Info: routing 1.01 19.53 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B1_LUT4_Z_C[1] (43,35) -> (42,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 19.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 19.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (42,37) -> (43,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 19.94 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 19.94 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (43,37) -> (43,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 19.94 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 19.94 Net $nextpnr_CCU2C_201$CIN (43,37) -> (43,37)
|
||||
Info: Sink $nextpnr_CCU2C_201$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 20.27 Source $nextpnr_CCU2C_201$CCU2_COMB0.F
|
||||
Info: routing 0.39 20.66 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (43,37) -> (44,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 20.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
|
||||
Info: routing 0.62 21.46 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C[2] (44,36) -> (37,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 21.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F
|
||||
Info: routing 0.74 22.38 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1[1] (37,35) -> (41,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 22.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 22.74 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (41,36) -> (41,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 22.79 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 22.79 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (41,36) -> (41,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 22.79 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 22.79 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (41,36) -> (41,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 22.85 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 22.85 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (41,36) -> (41,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 22.85 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 22.85 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (41,36) -> (42,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 22.91 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 22.91 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (42,36) -> (42,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 22.91 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 22.91 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (42,36) -> (42,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 22.96 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 22.96 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (42,36) -> (42,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 22.96 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 22.96 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (42,36) -> (42,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 23.02 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 23.02 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (42,36) -> (42,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 23.02 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 23.02 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (42,36) -> (42,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 23.07 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 23.07 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (42,36) -> (42,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 23.07 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 23.07 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (42,36) -> (43,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 23.13 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 23.13 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (43,36) -> (43,36)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 23.13 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 23.13 Net $nextpnr_CCU2C_17$CIN (43,36) -> (43,36)
|
||||
Info: Sink $nextpnr_CCU2C_17$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 23.46 Source $nextpnr_CCU2C_17$CCU2_COMB0.F
|
||||
Info: routing 0.56 24.02 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (43,36) -> (42,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 24.20 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
|
||||
Info: routing 0.94 25.13 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C[2] (42,35) -> (40,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_C.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 25.31 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_C.F
|
||||
Info: routing 1.04 26.35 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_C_Z[3] (40,32) -> (39,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.35 26.71 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 26.71 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,35) -> (39,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 26.77 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 26.77 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,35) -> (39,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 26.77 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 26.77 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,35) -> (40,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 26.82 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 26.82 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (40,35) -> (40,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 26.82 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 26.82 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (40,35) -> (40,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 26.88 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 26.88 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (40,35) -> (40,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 26.88 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 26.88 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (40,35) -> (40,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 26.93 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 26.93 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (40,35) -> (40,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 26.93 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 26.93 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (40,35) -> (40,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 26.99 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 26.99 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (40,35) -> (40,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 26.99 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 26.99 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN (40,35) -> (41,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 27.05 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 27.05 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (41,35) -> (41,35)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 27.05 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 27.05 Net $nextpnr_CCU2C_1$CIN (41,35) -> (41,35)
|
||||
Info: Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 27.37 Source $nextpnr_CCU2C_1$CCU2_COMB0.F
|
||||
Info: routing 0.84 28.21 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_COUT[4] (41,35) -> (40,32)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 28.41 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.81 29.22 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1 (40,32) -> (38,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
|
||||
Info: logic 0.35 29.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 29.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,33) -> (38,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 29.63 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 29.63 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (38,33) -> (38,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 29.63 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 29.63 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,33) -> (39,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 29.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 29.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,33) -> (39,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 29.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 29.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,33) -> (39,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 29.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 29.74 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,33) -> (39,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 29.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 29.74 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,33) -> (39,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 29.80 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 29.80 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,33) -> (39,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 29.80 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 29.80 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,33) -> (39,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 29.86 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 29.86 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,33) -> (39,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 29.86 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 29.86 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN (39,33) -> (40,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
|
||||
Info: logic 0.06 29.91 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
|
||||
Info: routing 0.00 29.91 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (40,33) -> (40,33)
|
||||
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
|
||||
Info: logic 0.00 29.91 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
|
||||
Info: routing 0.00 29.91 Net $nextpnr_CCU2C_3$CIN (40,33) -> (40,33)
|
||||
Info: Sink $nextpnr_CCU2C_3$CCU2_COMB0.FCI
|
||||
Info: logic 0.33 30.24 Source $nextpnr_CCU2C_3$CCU2_COMB0.F
|
||||
Info: routing 0.80 31.04 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR[2] (40,33) -> (40,37)
|
||||
Info: Sink u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 31.22 Source u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.F
|
||||
Info: routing 0.59 31.82 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B_Z (40,37) -> (41,38)
|
||||
Info: Sink u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_20.CE
|
||||
Info: setup 0.00 31.82 Source u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_20.CE
|
||||
Info: 11.38 ns logic, 20.44 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source reg_node_id[1]$tr_io.O
|
||||
Info: routing 3.02 3.02 Net reg_node_id[1]$TRELLIS_IO_IN (60,0) -> (48,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
|
||||
Info: logic 0.18 3.20 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_1.F
|
||||
Info: routing 0.99 4.19 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2_D[2] (48,40) -> (52,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.37 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2.F
|
||||
Info: routing 0.32 4.69 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D[2] (52,40) -> (52,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.87 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
|
||||
Info: routing 0.64 5.51 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[3] (52,40) -> (50,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.69 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
|
||||
Info: routing 0.56 6.26 Net reg_ready_PFUMX_Z_C0[4] (50,40) -> (49,41)
|
||||
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 6.45 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 3.80 10.24 Net reg_ready$TRELLIS_IO_OUT (49,41) -> (0,59)
|
||||
Info: Sink reg_ready$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: 0.91 ns logic, 9.33 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source reg_node_id[1]$tr_io.O
|
||||
Info: routing 3.02 3.02 Net reg_node_id[1]$TRELLIS_IO_IN (60,0) -> (48,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
|
||||
Info: logic 0.18 3.20 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_1.F
|
||||
Info: routing 0.99 4.19 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2_D[2] (48,40) -> (52,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.37 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2.F
|
||||
Info: routing 0.32 4.69 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D[2] (52,40) -> (52,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 4.87 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
|
||||
Info: routing 0.64 5.51 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[3] (52,40) -> (50,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.69 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
|
||||
Info: routing 0.56 6.26 Net reg_ready_PFUMX_Z_C0[4] (50,40) -> (49,41)
|
||||
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 6.45 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.73 7.18 Net reg_ready$TRELLIS_IO_OUT (49,41) -> (54,41)
|
||||
Info: Sink reg_valid_LUT4_B.D
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: logic 0.18 7.36 Source reg_valid_LUT4_B.F
|
||||
Info: routing 4.27 11.63 Net reg_valid_LUT4_B_Z[2] (54,41) -> (11,8)
|
||||
Info: Sink u_dataflow_core.u_dep_mgr.node_x_base.0.5$DPRAM_COMB3.WRE
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: setup 0.27 11.90 Source u_dataflow_core.u_dep_mgr.node_x_base.0.5$DPRAM_COMB3.WRE
|
||||
Info: 1.36 ns logic, 10.54 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_dep_mgr.node_state[6]_TRELLIS_FF_Q_1.Q
|
||||
Info: routing 0.99 1.38 Net u_dataflow_core.u_dep_mgr.first_ready_idx_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_C0_PFUMX_Z_C0[0] (54,37) -> (53,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 1.56 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z.F
|
||||
Info: routing 0.64 2.20 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D[1] (53,40) -> (52,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 2.38 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
|
||||
Info: routing 0.64 3.02 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[3] (52,40) -> (50,40)
|
||||
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 3.20 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
|
||||
Info: routing 0.56 3.77 Net reg_ready_PFUMX_Z_C0[4] (50,40) -> (49,41)
|
||||
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 3.96 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 3.80 7.76 Net reg_ready$TRELLIS_IO_OUT (49,41) -> (0,59)
|
||||
Info: Sink reg_ready$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
|
||||
Info: 1.13 ns logic, 6.63 ns routing
|
||||
|
||||
ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 31.43 MHz (FAIL at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> <async> : 10.24 ns
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.90 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.76 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 176 endpoint(s)
|
||||
Info: + represents [1,176) endpoint(s)
|
||||
Info: [-19315, -17759) |+
|
||||
Info: [-17759, -16203) |
|
||||
Info: [-16203, -14647) |
|
||||
Info: [-14647, -13091) |
|
||||
Info: [-13091, -11535) |
|
||||
Info: [-11535, -9979) |
|
||||
Info: [ -9979, -8423) |
|
||||
Info: [ -8423, -6867) |
|
||||
Info: [ -6867, -5311) |
|
||||
Info: [ -5311, -3755) |
|
||||
Info: [ -3755, -2199) |
|
||||
Info: [ -2199, -643) |
|
||||
Info: [ -643, 913) |+
|
||||
Info: [ 913, 2469) |+
|
||||
Info: [ 2469, 4025) |**+
|
||||
Info: [ 4025, 5581) |*******+
|
||||
Info: [ 5581, 7137) |********+
|
||||
Info: [ 7137, 8693) |*********************+
|
||||
Info: [ 8693, 10249) |***********************************************+
|
||||
Info: [ 10249, 11805) |************************************************************
|
||||
0 warnings, 1 error
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,180 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 40/43848 0%
|
||||
Info: logic LUTs: 16/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 16/ 5481 0%
|
||||
Info: RAMW LUTs: 8/10962 0%
|
||||
|
||||
Info: Total DFFs: 56/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 32 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x0abbe4f5
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 56/ 43848 0%
|
||||
Info: TRELLIS_COMB: 42/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 4/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 45 cells, random placement wirelen = 4323.
|
||||
Info: at initial placer iter 0, wirelen = 1337
|
||||
Info: at initial placer iter 1, wirelen = 1031
|
||||
Info: at initial placer iter 2, wirelen = 967
|
||||
Info: at initial placer iter 3, wirelen = 962
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 959, spread = 1017, legal = 1022; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.02s
|
||||
Info: of which solving equations: 0.00s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 33, wirelen = 1022
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 10, wirelen = 813
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 23, wirelen = 796
|
||||
Info: at iteration #11: temp = 0.000000, timing cost = 14, wirelen = 810
|
||||
Info: SA placement time 0.01s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 654.02 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.33 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.80 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10971, 11010) |*********+
|
||||
Info: [ 11010, 11049) |
|
||||
Info: [ 11049, 11088) |+
|
||||
Info: [ 11088, 11127) |************+
|
||||
Info: [ 11127, 11166) |
|
||||
Info: [ 11166, 11205) |*************+
|
||||
Info: [ 11205, 11244) |************************************************************
|
||||
Info: [ 11244, 11283) |
|
||||
Info: [ 11283, 11322) |******+
|
||||
Info: [ 11322, 11361) |***+
|
||||
Info: [ 11361, 11400) |***+
|
||||
Info: [ 11400, 11439) |******+
|
||||
Info: [ 11439, 11478) |
|
||||
Info: [ 11478, 11517) |******+
|
||||
Info: [ 11517, 11556) |**+
|
||||
Info: [ 11556, 11595) |
|
||||
Info: [ 11595, 11634) |*************+
|
||||
Info: [ 11634, 11673) |
|
||||
Info: [ 11673, 11712) |
|
||||
Info: [ 11712, 11751) |**********+
|
||||
Info: Checksum: 0x67991a37
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 300 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 334 | 32 302 | 32 302 | 0| 0.10 0.10|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.10s
|
||||
Info: Checksum: 0xcdac7e72
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_16.Q
|
||||
Info: routing 0.95 1.35 Net fill_addr_flat[1] (36,36) -> (35,37)
|
||||
Info: Sink dut.GEN_SLOT[0].mem.0.0$DPRAM_COMB0.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:27.24-27.29
|
||||
Info: logic 0.18 1.53 Source dut.GEN_SLOT[0].mem.0.0$DPRAM_COMB0.F
|
||||
Info: routing 0.12 1.65 Net dut.GEN_SLOT[0].mem.0.0_DO[0] (35,37) -> (35,37)
|
||||
Info: Sink dut.GEN_SLOT[0].rd_data_reg_TRELLIS_FF_Q_7.DI
|
||||
Info: setup 0.00 1.65 Source dut.GEN_SLOT[0].rd_data_reg_TRELLIS_FF_Q_7.DI
|
||||
Info: 0.57 ns logic, 1.07 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[5]$tr_io.O
|
||||
Info: routing 2.80 2.80 Net seed[5]$TRELLIS_IO_IN (90,35) -> (34,35)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_4.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
|
||||
Info: logic 0.18 2.98 Source seed_LUT4_B_Z_LUT4_Z_4.F
|
||||
Info: routing 0.12 3.10 Net seed_LUT4_B_Z[5] (34,35) -> (34,35)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_22.DI
|
||||
Info: setup 0.00 3.10 Source lfsr_TRELLIS_FF_Q_22.DI
|
||||
Info: 0.18 ns logic, 2.92 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_4.Q
|
||||
Info: routing 2.73 3.13 Net checksum[4]$TRELLIS_IO_OUT (33,36) -> (90,35)
|
||||
Info: Sink checksum[4]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:40.15-40.18
|
||||
Info: 0.40 ns logic, 2.73 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 607.16 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.10 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.13 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10853, 10901) |************
|
||||
Info: [ 10901, 10949) |*****
|
||||
Info: [ 10949, 10997) |*
|
||||
Info: [ 10997, 11045) |
|
||||
Info: [ 11045, 11093) |****
|
||||
Info: [ 11093, 11141) |****
|
||||
Info: [ 11141, 11189) |***************************
|
||||
Info: [ 11189, 11237) |************
|
||||
Info: [ 11237, 11285) |*
|
||||
Info: [ 11285, 11333) |************
|
||||
Info: [ 11333, 11381) |***************
|
||||
Info: [ 11381, 11429) |**********
|
||||
Info: [ 11429, 11477) |*****
|
||||
Info: [ 11477, 11525) |***************
|
||||
Info: [ 11525, 11573) |***
|
||||
Info: [ 11573, 11621) |*************
|
||||
Info: [ 11621, 11669) |
|
||||
Info: [ 11669, 11717) |********
|
||||
Info: [ 11717, 11765) |****
|
||||
Info: [ 11765, 11813) |*******
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,195 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 48/43848 0%
|
||||
Info: logic LUTs: 48/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 0/ 5481 0%
|
||||
Info: RAMW LUTs: 0/10962 0%
|
||||
|
||||
Info: Total DFFs: 88/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 18 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x4479dccd
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 2/ 108 1%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 88/ 43848 0%
|
||||
Info: TRELLIS_COMB: 50/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 0/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 111 cells, random placement wirelen = 9653.
|
||||
Info: at initial placer iter 0, wirelen = 1028
|
||||
Info: at initial placer iter 1, wirelen = 933
|
||||
Info: at initial placer iter 2, wirelen = 921
|
||||
Info: at initial placer iter 3, wirelen = 914
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 912, spread = 1513, legal = 1843; time = 0.00s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 903, spread = 1527, legal = 1842; time = 0.00s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 902, spread = 1526, legal = 2621; time = 0.00s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 914, spread = 1607, legal = 1804; time = 0.00s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 965, spread = 1424, legal = 1831; time = 0.00s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 987, spread = 1423, legal = 2161; time = 0.00s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 974, spread = 1416, legal = 1926; time = 0.00s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 971, spread = 1411, legal = 1682; time = 0.00s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 1000, spread = 1419, legal = 2354; time = 0.00s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 977, spread = 1417, legal = 2409; time = 0.00s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 999, spread = 1402, legal = 2040; time = 0.00s
|
||||
Info: at iteration #12, type ALL: wirelen solved = 981, spread = 1590, legal = 2117; time = 0.00s
|
||||
Info: at iteration #13, type ALL: wirelen solved = 997, spread = 1430, legal = 1902; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.04s
|
||||
Info: of which solving equations: 0.01s
|
||||
Info: of which spreading cells: 0.01s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 14, wirelen = 1682
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 17, wirelen = 1327
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 12, wirelen = 1268
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 16, wirelen = 1200
|
||||
Info: at iteration #17: temp = 0.000000, timing cost = 15, wirelen = 1194
|
||||
Info: SA placement time 0.02s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 166.42 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.05 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.84 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 6491, 6754) |******+
|
||||
Info: [ 6754, 7017) |
|
||||
Info: [ 7017, 7280) |+
|
||||
Info: [ 7280, 7543) |
|
||||
Info: [ 7543, 7806) |
|
||||
Info: [ 7806, 8069) |
|
||||
Info: [ 8069, 8332) |
|
||||
Info: [ 8332, 8595) |
|
||||
Info: [ 8595, 8858) |
|
||||
Info: [ 8858, 9121) |+
|
||||
Info: [ 9121, 9384) |
|
||||
Info: [ 9384, 9647) |
|
||||
Info: [ 9647, 9910) |
|
||||
Info: [ 9910, 10173) |
|
||||
Info: [ 10173, 10436) |*+
|
||||
Info: [ 10436, 10699) |**********************+
|
||||
Info: [ 10699, 10962) |**************************+
|
||||
Info: [ 10962, 11225) |************************************+
|
||||
Info: [ 11225, 11488) |************************************************************
|
||||
Info: [ 11488, 11751) |********************************+
|
||||
Info: Checksum: 0x924ae2d1
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 403 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 448 | 45 397 | 45 397 | 0| 0.07 0.07|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.07s
|
||||
Info: Checksum: 0x27362745
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 4.10 4.10 Source dut.GEN_SLOT[0].mem.0.0.DOA7
|
||||
Info: routing 0.81 4.91 Net dut.GEN_SLOT[0].mem.0.0_DOA7[2] (4,34) -> (4,25)
|
||||
Info: Sink dut.GEN_SLOT[1].mem.0.0_DOA7_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.09 Source dut.GEN_SLOT[1].mem.0.0_DOA7_LUT4_Z.F
|
||||
Info: routing 0.32 5.41 Net dut.GEN_SLOT[1].mem.0.0_DOA7[3] (4,25) -> (4,25)
|
||||
Info: Sink dut.GEN_SLOT[1].mem.0.0_DOA1_LUT4_D_Z_LUT4_Z_1.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.59 Source dut.GEN_SLOT[1].mem.0.0_DOA1_LUT4_D_Z_LUT4_Z_1.F
|
||||
Info: routing 0.12 5.71 Net dut.GEN_SLOT[1].mem.0.0_DOA1_LUT4_D_Z[7] (4,25) -> (4,25)
|
||||
Info: Sink chk_TRELLIS_FF_Q_7.DI
|
||||
Info: setup 0.00 5.71 Source chk_TRELLIS_FF_Q_7.DI
|
||||
Info: 4.46 ns logic, 1.25 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source rst$tr_io.O
|
||||
Info: routing 4.67 4.67 Net rst$TRELLIS_IO_IN (90,32) -> (5,26)
|
||||
Info: Sink chk_TRELLIS_FF_Q_3.LSR
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:13.17-13.20
|
||||
Info: setup 0.29 4.96 Source chk_TRELLIS_FF_Q_3.LSR
|
||||
Info: 0.29 ns logic, 4.67 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
|
||||
Info: routing 3.87 4.26 Net checksum[0]$TRELLIS_IO_OUT (3,26) -> (90,23)
|
||||
Info: Sink checksum[0]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 3.87 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 175.10 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.96 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.26 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 6789, 7040) |*******
|
||||
Info: [ 7040, 7291) |*
|
||||
Info: [ 7291, 7542) |
|
||||
Info: [ 7542, 7793) |
|
||||
Info: [ 7793, 8044) |
|
||||
Info: [ 8044, 8295) |
|
||||
Info: [ 8295, 8546) |
|
||||
Info: [ 8546, 8797) |
|
||||
Info: [ 8797, 9048) |*
|
||||
Info: [ 9048, 9299) |
|
||||
Info: [ 9299, 9550) |
|
||||
Info: [ 9550, 9801) |*
|
||||
Info: [ 9801, 10052) |
|
||||
Info: [ 10052, 10303) |
|
||||
Info: [ 10303, 10554) |*
|
||||
Info: [ 10554, 10805) |************************
|
||||
Info: [ 10805, 11056) |*******************************************
|
||||
Info: [ 11056, 11307) |******************************************************
|
||||
Info: [ 11307, 11558) |***********************************************
|
||||
Info: [ 11558, 11809) |**********************************
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,185 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 72/43848 0%
|
||||
Info: logic LUTs: 24/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 32/ 5481 0%
|
||||
Info: RAMW LUTs: 16/10962 0%
|
||||
|
||||
Info: Total DFFs: 72/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 40 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x16931407
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 72/ 43848 0%
|
||||
Info: TRELLIS_COMB: 74/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 8/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 57 cells, random placement wirelen = 5935.
|
||||
Info: at initial placer iter 0, wirelen = 1543
|
||||
Info: at initial placer iter 1, wirelen = 1188
|
||||
Info: at initial placer iter 2, wirelen = 1004
|
||||
Info: at initial placer iter 3, wirelen = 976
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 974, spread = 1053, legal = 1110; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.02s
|
||||
Info: of which solving equations: 0.00s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 14, wirelen = 1110
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 33, wirelen = 896
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 28, wirelen = 896
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 26, wirelen = 885
|
||||
Info: SA placement time 0.01s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 456.83 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.94 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.36 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10311, 10383) |**+
|
||||
Info: [ 10383, 10455) |****+
|
||||
Info: [ 10455, 10527) |
|
||||
Info: [ 10527, 10599) |
|
||||
Info: [ 10599, 10671) |****+
|
||||
Info: [ 10671, 10743) |**+
|
||||
Info: [ 10743, 10815) |****+
|
||||
Info: [ 10815, 10887) |*****************************+
|
||||
Info: [ 10887, 10959) |**+
|
||||
Info: [ 10959, 11031) |**********************+
|
||||
Info: [ 11031, 11103) |*****************************+
|
||||
Info: [ 11103, 11175) |***********************+
|
||||
Info: [ 11175, 11247) |************************************************************
|
||||
Info: [ 11247, 11319) |
|
||||
Info: [ 11319, 11391) |****************+
|
||||
Info: [ 11391, 11463) |****+
|
||||
Info: [ 11463, 11535) |**************+
|
||||
Info: [ 11535, 11607) |+
|
||||
Info: [ 11607, 11679) |****+
|
||||
Info: [ 11679, 11751) |*******+
|
||||
Info: Checksum: 0x1b42f28c
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 531 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 667 | 126 533 | 126 533 | 0| 0.05 0.05|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.05s
|
||||
Info: Checksum: 0x96dc7282
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source dut.GEN_SLOT[1].rd_data_reg_TRELLIS_FF_Q_3.Q
|
||||
Info: routing 0.85 1.25 Net rd_data_flat[65] (37,42) -> (36,41)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_ALUT_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_weight_direct.v:28.50-28.62
|
||||
Info: logic 0.18 1.43 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_ALUT_LUT4_Z.F
|
||||
Info: routing 0.00 1.43 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_ALUT (36,41) -> (36,41)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_BLUT_LUT4_Z.F1
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
|
||||
Info: logic 0.13 1.55 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.46 2.02 Net chk_TRELLIS_FF_Q_DI[1] (36,41) -> (37,41)
|
||||
Info: Sink chk_TRELLIS_FF_Q_1.M
|
||||
Info: setup 0.00 2.02 Source chk_TRELLIS_FF_Q_1.M
|
||||
Info: 0.70 ns logic, 1.32 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[6]$tr_io.O
|
||||
Info: routing 2.93 2.93 Net seed[6]$TRELLIS_IO_IN (42,0) -> (38,41)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_3.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
|
||||
Info: logic 0.18 3.11 Source seed_LUT4_B_Z_LUT4_Z_3.F
|
||||
Info: routing 0.12 3.23 Net seed_LUT4_B_Z[6] (38,41) -> (38,41)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_1.DI
|
||||
Info: setup 0.00 3.23 Source lfsr_TRELLIS_FF_Q_1.DI
|
||||
Info: 0.18 ns logic, 3.05 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_5.Q
|
||||
Info: routing 2.87 3.26 Net checksum[5]$TRELLIS_IO_OUT (38,44) -> (42,0)
|
||||
Info: Sink checksum[5]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:40.15-40.18
|
||||
Info: 0.40 ns logic, 2.87 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 496.03 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.23 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.26 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10484, 10550) |*
|
||||
Info: [ 10550, 10616) |**
|
||||
Info: [ 10616, 10682) |***********
|
||||
Info: [ 10682, 10748) |**********
|
||||
Info: [ 10748, 10814) |********
|
||||
Info: [ 10814, 10880) |*********
|
||||
Info: [ 10880, 10946) |***
|
||||
Info: [ 10946, 11012) |************
|
||||
Info: [ 11012, 11078) |******
|
||||
Info: [ 11078, 11144) |**************************************
|
||||
Info: [ 11144, 11210) |*********************
|
||||
Info: [ 11210, 11276) |********************
|
||||
Info: [ 11276, 11342) |*******************************
|
||||
Info: [ 11342, 11408) |***********************************************
|
||||
Info: [ 11408, 11474) |************
|
||||
Info: [ 11474, 11540) |***************************
|
||||
Info: [ 11540, 11606) |*********
|
||||
Info: [ 11606, 11672) |*
|
||||
Info: [ 11672, 11738) |************
|
||||
Info: [ 11738, 11804) |****
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,208 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 93/43848 0%
|
||||
Info: logic LUTs: 93/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 0/ 5481 0%
|
||||
Info: RAMW LUTs: 0/10962 0%
|
||||
|
||||
Info: Total DFFs: 104/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 10 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x267d8a3c
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 4/ 108 3%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 104/ 43848 0%
|
||||
Info: TRELLIS_COMB: 95/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 0/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 172 cells, random placement wirelen = 15989.
|
||||
Info: at initial placer iter 0, wirelen = 1106
|
||||
Info: at initial placer iter 1, wirelen = 1095
|
||||
Info: at initial placer iter 2, wirelen = 994
|
||||
Info: at initial placer iter 3, wirelen = 971
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 962, spread = 2116, legal = 3978; time = 0.00s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 991, spread = 1988, legal = 3748; time = 0.00s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 1030, spread = 1908, legal = 2805; time = 0.00s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 1033, spread = 1975, legal = 3224; time = 0.00s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 1098, spread = 1987, legal = 3050; time = 0.00s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 1095, spread = 1975, legal = 3154; time = 0.00s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 1104, spread = 1985, legal = 2658; time = 0.00s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 1126, spread = 2006, legal = 2807; time = 0.00s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 1118, spread = 2008, legal = 3116; time = 0.00s
|
||||
Info: at iteration #10, type ALL: wirelen solved = 1157, spread = 2009, legal = 2744; time = 0.00s
|
||||
Info: at iteration #11, type ALL: wirelen solved = 1172, spread = 1942, legal = 2283; time = 0.00s
|
||||
Info: at iteration #12, type ALL: wirelen solved = 1143, spread = 2031, legal = 2137; time = 0.00s
|
||||
Info: at iteration #13, type ALL: wirelen solved = 1184, spread = 1943, legal = 2479; time = 0.00s
|
||||
Info: at iteration #14, type ALL: wirelen solved = 1172, spread = 1941, legal = 2420; time = 0.00s
|
||||
Info: at iteration #15, type ALL: wirelen solved = 1170, spread = 1948, legal = 2178; time = 0.00s
|
||||
Info: at iteration #16, type ALL: wirelen solved = 1172, spread = 2083, legal = 2122; time = 0.00s
|
||||
Info: at iteration #17, type ALL: wirelen solved = 1263, spread = 2044, legal = 2189; time = 0.00s
|
||||
Info: at iteration #18, type ALL: wirelen solved = 1280, spread = 2077, legal = 2101; time = 0.00s
|
||||
Info: at iteration #19, type ALL: wirelen solved = 1302, spread = 2059, legal = 2168; time = 0.00s
|
||||
Info: at iteration #20, type ALL: wirelen solved = 1287, spread = 2124, legal = 2319; time = 0.00s
|
||||
Info: at iteration #21, type ALL: wirelen solved = 1317, spread = 2071, legal = 2202; time = 0.00s
|
||||
Info: at iteration #22, type ALL: wirelen solved = 1294, spread = 2096, legal = 2419; time = 0.00s
|
||||
Info: at iteration #23, type ALL: wirelen solved = 1304, spread = 2205, legal = 2564; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.08s
|
||||
Info: of which solving equations: 0.04s
|
||||
Info: of which spreading cells: 0.01s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 31, wirelen = 2101
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 24, wirelen = 1430
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 22, wirelen = 1391
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 18, wirelen = 1354
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 16, wirelen = 1371
|
||||
Info: SA placement time 0.03s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 145.26 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.95 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.09 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 2 endpoint(s)
|
||||
Info: + represents [1,2) endpoint(s)
|
||||
Info: [ 5616, 5922) |**
|
||||
Info: [ 5922, 6228) |*+
|
||||
Info: [ 6228, 6534) |+
|
||||
Info: [ 6534, 6840) |
|
||||
Info: [ 6840, 7146) |
|
||||
Info: [ 7146, 7452) |
|
||||
Info: [ 7452, 7758) |
|
||||
Info: [ 7758, 8064) |
|
||||
Info: [ 8064, 8370) |
|
||||
Info: [ 8370, 8676) |
|
||||
Info: [ 8676, 8982) |+
|
||||
Info: [ 8982, 9288) |*
|
||||
Info: [ 9288, 9594) |+
|
||||
Info: [ 9594, 9900) |
|
||||
Info: [ 9900, 10206) |
|
||||
Info: [ 10206, 10512) |****+
|
||||
Info: [ 10512, 10818) |************************************
|
||||
Info: [ 10818, 11124) |************************************************************
|
||||
Info: [ 11124, 11430) |*************************************
|
||||
Info: [ 11430, 11736) |**********************************
|
||||
Info: Checksum: 0xc75c98af
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 716 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 853 | 128 708 | 128 708 | 0| 0.16 0.16|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.16s
|
||||
Info: Checksum: 0x81680254
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 4.10 4.10 Source dut.GEN_SLOT[2].mem.0.0.DOA4
|
||||
Info: routing 1.03 5.13 Net dut.GEN_SLOT[2].mem.0.0_DOA4[0] (10,10) -> (3,9)
|
||||
Info: Sink dut.GEN_SLOT[3].mem.0.0_DOA4_LUT4_Z_1.A
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.31 Source dut.GEN_SLOT[3].mem.0.0_DOA4_LUT4_Z_1.F
|
||||
Info: routing 0.55 5.86 Net dut.GEN_SLOT[3].mem.0.0_DOA4[4] (3,9) -> (4,8)
|
||||
Info: Sink dut.GEN_SLOT[3].mem.0.0_DOA5_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 6.05 Source dut.GEN_SLOT[3].mem.0.0_DOA5_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.47 6.52 Net dut.GEN_SLOT[3].mem.0.0_DOA5_LUT4_D_Z_LUT4_D_Z[4] (4,8) -> (3,8)
|
||||
Info: Sink chk_TRELLIS_FF_Q_1.M
|
||||
Info: setup 0.00 6.52 Source chk_TRELLIS_FF_Q_1.M
|
||||
Info: 4.47 ns logic, 2.04 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[5]$tr_io.O
|
||||
Info: routing 3.65 3.65 Net seed[5]$TRELLIS_IO_IN (90,11) -> (8,11)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_5.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
|
||||
Info: logic 0.18 3.83 Source seed_LUT4_B_Z_LUT4_Z_5.F
|
||||
Info: routing 0.12 3.95 Net seed_LUT4_B_Z[5] (8,11) -> (8,11)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_9.DI
|
||||
Info: setup 0.00 3.95 Source lfsr_TRELLIS_FF_Q_9.DI
|
||||
Info: 0.18 ns logic, 3.77 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_4.Q
|
||||
Info: routing 4.04 4.44 Net checksum[6]$TRELLIS_IO_OUT (3,9) -> (90,14)
|
||||
Info: Sink checksum[6]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 4.04 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 153.47 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.95 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.44 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 2 endpoint(s)
|
||||
Info: + represents [1,2) endpoint(s)
|
||||
Info: [ 5984, 6275) |**+
|
||||
Info: [ 6275, 6566) |+
|
||||
Info: [ 6566, 6857) |
|
||||
Info: [ 6857, 7148) |
|
||||
Info: [ 7148, 7439) |
|
||||
Info: [ 7439, 7730) |
|
||||
Info: [ 7730, 8021) |
|
||||
Info: [ 8021, 8312) |
|
||||
Info: [ 8312, 8603) |
|
||||
Info: [ 8603, 8894) |
|
||||
Info: [ 8894, 9185) |
|
||||
Info: [ 9185, 9476) |+
|
||||
Info: [ 9476, 9767) |*+
|
||||
Info: [ 9767, 10058) |
|
||||
Info: [ 10058, 10349) |*+
|
||||
Info: [ 10349, 10640) |******+
|
||||
Info: [ 10640, 10931) |*****************************************+
|
||||
Info: [ 10931, 11222) |************************************************************
|
||||
Info: [ 11222, 11513) |*******************************+
|
||||
Info: [ 11513, 11804) |******************+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,187 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 136/43848 0%
|
||||
Info: logic LUTs: 40/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 64/ 5481 1%
|
||||
Info: RAMW LUTs: 32/10962 0%
|
||||
|
||||
Info: Total DFFs: 104/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 72 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0xe3dbdc7e
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 104/ 43848 0%
|
||||
Info: TRELLIS_COMB: 138/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 16/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 81 cells, random placement wirelen = 9539.
|
||||
Info: at initial placer iter 0, wirelen = 1594
|
||||
Info: at initial placer iter 1, wirelen = 1147
|
||||
Info: at initial placer iter 2, wirelen = 1015
|
||||
Info: at initial placer iter 3, wirelen = 993
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 978, spread = 1266, legal = 1299; time = 0.00s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 1063, spread = 1290, legal = 1324; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.02s
|
||||
Info: of which solving equations: 0.01s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 19, wirelen = 1299
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 23, wirelen = 1077
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 23, wirelen = 1040
|
||||
Info: at iteration #11: temp = 0.000000, timing cost = 21, wirelen = 1044
|
||||
Info: SA placement time 0.03s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 349.04 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.02 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.17 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 9635, 9740) |+
|
||||
Info: [ 9740, 9845) |
|
||||
Info: [ 9845, 9950) |*+
|
||||
Info: [ 9950, 10055) |*+
|
||||
Info: [ 10055, 10160) |+
|
||||
Info: [ 10160, 10265) |+
|
||||
Info: [ 10265, 10370) |**+
|
||||
Info: [ 10370, 10475) |
|
||||
Info: [ 10475, 10580) |********+
|
||||
Info: [ 10580, 10685) |**********+
|
||||
Info: [ 10685, 10790) |*********************+
|
||||
Info: [ 10790, 10895) |*******************************+
|
||||
Info: [ 10895, 11000) |*************************************************+
|
||||
Info: [ 11000, 11105) |***************+
|
||||
Info: [ 11105, 11210) |************************************************************
|
||||
Info: [ 11210, 11315) |**********************************************+
|
||||
Info: [ 11315, 11420) |******************+
|
||||
Info: [ 11420, 11525) |*****+
|
||||
Info: [ 11525, 11630) |***************+
|
||||
Info: [ 11630, 11735) |**+
|
||||
Info: Checksum: 0xfca4c844
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 931 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 97 894 | 97 894 | 35| 0.05 0.05|
|
||||
Info: 1034 | 97 929 | 0 35 | 0| 0.03 0.07|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.07s
|
||||
Info: Checksum: 0x2aed6580
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source dut.GEN_SLOT[5].rd_data_reg_TRELLIS_FF_Q_4.Q
|
||||
Info: routing 0.86 1.25 Net rd_data_flat[324] (24,43) -> (23,42)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_C0_LUT4_Z_1.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_weight_direct.v:28.50-28.62
|
||||
Info: logic 0.18 1.43 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_C0_LUT4_Z_1.F
|
||||
Info: routing 0.71 2.15 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_C0[4] (23,42) -> (23,45)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 2.34 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_6_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.35 2.69 Net chk_TRELLIS_FF_Q_DI[4] (23,45) -> (23,45)
|
||||
Info: Sink chk_TRELLIS_FF_Q_3.M
|
||||
Info: setup 0.00 2.69 Source chk_TRELLIS_FF_Q_3.M
|
||||
Info: 0.77 ns logic, 1.92 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[2]$tr_io.O
|
||||
Info: routing 3.08 3.08 Net seed[2]$TRELLIS_IO_IN (42,0) -> (28,41)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
|
||||
Info: logic 0.18 3.26 Source seed_LUT4_B_Z_LUT4_Z.F
|
||||
Info: routing 0.12 3.37 Net seed_LUT4_B_Z[2] (28,41) -> (28,41)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_14.DI
|
||||
Info: setup 0.00 3.37 Source lfsr_TRELLIS_FF_Q_14.DI
|
||||
Info: 0.18 ns logic, 3.19 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
|
||||
Info: routing 3.29 3.68 Net checksum[1]$TRELLIS_IO_OUT (26,42) -> (42,0)
|
||||
Info: Sink checksum[1]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 3.29 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 371.47 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.37 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.68 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 9808, 9908) |*+
|
||||
Info: [ 9908, 10008) |+
|
||||
Info: [ 10008, 10108) |**+
|
||||
Info: [ 10108, 10208) |
|
||||
Info: [ 10208, 10308) |
|
||||
Info: [ 10308, 10408) |+
|
||||
Info: [ 10408, 10508) |**+
|
||||
Info: [ 10508, 10608) |****+
|
||||
Info: [ 10608, 10708) |*+
|
||||
Info: [ 10708, 10808) |***************+
|
||||
Info: [ 10808, 10908) |****************+
|
||||
Info: [ 10908, 11008) |***************************+
|
||||
Info: [ 11008, 11108) |****************************************+
|
||||
Info: [ 11108, 11208) |************************************************************
|
||||
Info: [ 11208, 11308) |*********************************+
|
||||
Info: [ 11308, 11408) |*******************************************************+
|
||||
Info: [ 11408, 11508) |*******************+
|
||||
Info: [ 11508, 11608) |***********************+
|
||||
Info: [ 11608, 11708) |*****+
|
||||
Info: [ 11708, 11808) |*+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,199 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 124/43848 0%
|
||||
Info: logic LUTs: 124/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 0/ 5481 0%
|
||||
Info: RAMW LUTs: 0/10962 0%
|
||||
|
||||
Info: Total DFFs: 136/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 18 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x1670f00e
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 8/ 108 7%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 136/ 43848 0%
|
||||
Info: TRELLIS_COMB: 126/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 0/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 239 cells, random placement wirelen = 22024.
|
||||
Info: at initial placer iter 0, wirelen = 1121
|
||||
Info: at initial placer iter 1, wirelen = 1054
|
||||
Info: at initial placer iter 2, wirelen = 1018
|
||||
Info: at initial placer iter 3, wirelen = 1001
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10440.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 990, spread = 4556, legal = 4538; time = 0.01s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 1000, spread = 4277, legal = 4337; time = 0.00s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 1000, spread = 4304, legal = 4342; time = 0.00s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 1134, spread = 4250, legal = 4315; time = 0.00s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 1164, spread = 4520, legal = 4547; time = 0.00s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 1153, spread = 4554, legal = 4606; time = 0.00s
|
||||
Info: at iteration #7, type ALL: wirelen solved = 1216, spread = 4502, legal = 4552; time = 0.00s
|
||||
Info: at iteration #8, type ALL: wirelen solved = 1240, spread = 4698, legal = 4704; time = 0.00s
|
||||
Info: at iteration #9, type ALL: wirelen solved = 1227, spread = 4951, legal = 4986; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.06s
|
||||
Info: of which solving equations: 0.03s
|
||||
Info: of which spreading cells: 0.01s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 41, wirelen = 4315
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 46, wirelen = 3439
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 42, wirelen = 3372
|
||||
Info: at iteration #11: temp = 0.000000, timing cost = 36, wirelen = 3375
|
||||
Info: SA placement time 0.03s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 118.54 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.07 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.53 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 3 endpoint(s)
|
||||
Info: + represents [1,3) endpoint(s)
|
||||
Info: [ 4064, 4448) |+
|
||||
Info: [ 4448, 4832) |+
|
||||
Info: [ 4832, 5216) |+
|
||||
Info: [ 5216, 5600) |+
|
||||
Info: [ 5600, 5984) |
|
||||
Info: [ 5984, 6368) |
|
||||
Info: [ 6368, 6752) |
|
||||
Info: [ 6752, 7136) |
|
||||
Info: [ 7136, 7520) |
|
||||
Info: [ 7520, 7904) |
|
||||
Info: [ 7904, 8288) |
|
||||
Info: [ 8288, 8672) |
|
||||
Info: [ 8672, 9056) |
|
||||
Info: [ 9056, 9440) |**+
|
||||
Info: [ 9440, 9824) |***************+
|
||||
Info: [ 9824, 10208) |******************************************+
|
||||
Info: [ 10208, 10592) |************************************************************
|
||||
Info: [ 10592, 10976) |*******************************************+
|
||||
Info: [ 10976, 11360) |*********************+
|
||||
Info: [ 11360, 11744) |***********+
|
||||
Info: Checksum: 0x9978c53f
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 1105 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 157 836 | 157 836 | 275| 0.17 0.17|
|
||||
Info: 1316 | 194 1111 | 37 275 | 0| 0.04 0.21|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.21s
|
||||
Info: Checksum: 0xf5d95f64
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 4.10 4.10 Source dut.GEN_SLOT[0].mem.0.0.DOA4
|
||||
Info: routing 1.34 5.43 Net dut.GEN_SLOT[0].mem.0.0_DOA4[1] (10,10) -> (5,20)
|
||||
Info: Sink dut.GEN_SLOT[6].mem.0.0_DOA4_LUT4_Z.C
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 5.61 Source dut.GEN_SLOT[6].mem.0.0_DOA4_LUT4_Z.F
|
||||
Info: routing 0.31 5.93 Net dut.GEN_SLOT[6].mem.0.0_DOA4[3] (5,20) -> (5,20)
|
||||
Info: Sink dut.GEN_SLOT[2].mem.0.0_DOA4_LUT4_C_Z_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.11 Source dut.GEN_SLOT[2].mem.0.0_DOA4_LUT4_C_Z_LUT4_Z.F
|
||||
Info: routing 0.51 6.61 Net dut.GEN_SLOT[2].mem.0.0_DOA4_LUT4_C_Z[4] (5,20) -> (5,21)
|
||||
Info: Sink dut.GEN_SLOT[2].mem.0.0_DOA0_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 6.81 Source dut.GEN_SLOT[2].mem.0.0_DOA0_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.51 7.31 Net dut.GEN_SLOT[2].mem.0.0_DOA0_LUT4_D_Z_LUT4_D_Z[4] (5,21) -> (5,20)
|
||||
Info: Sink chk_TRELLIS_FF_Q_1.M
|
||||
Info: setup 0.00 7.31 Source chk_TRELLIS_FF_Q_1.M
|
||||
Info: 4.65 ns logic, 2.66 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[4]$tr_io.O
|
||||
Info: routing 3.89 3.89 Net seed[4]$TRELLIS_IO_IN (90,26) -> (6,26)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
|
||||
Info: logic 0.18 4.07 Source seed_LUT4_B_Z_LUT4_Z.F
|
||||
Info: routing 0.12 4.18 Net seed_LUT4_B_Z[4] (6,26) -> (6,26)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_18.DI
|
||||
Info: setup 0.00 4.18 Source lfsr_TRELLIS_FF_Q_18.DI
|
||||
Info: 0.18 ns logic, 4.01 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
|
||||
Info: routing 3.83 4.22 Net checksum[3]$TRELLIS_IO_OUT (4,18) -> (90,17)
|
||||
Info: Sink checksum[3]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 3.83 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 136.72 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.18 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.22 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 4 endpoint(s)
|
||||
Info: + represents [1,4) endpoint(s)
|
||||
Info: [ 5186, 5517) |*+
|
||||
Info: [ 5517, 5848) |+
|
||||
Info: [ 5848, 6179) |
|
||||
Info: [ 6179, 6510) |
|
||||
Info: [ 6510, 6841) |
|
||||
Info: [ 6841, 7172) |
|
||||
Info: [ 7172, 7503) |
|
||||
Info: [ 7503, 7834) |
|
||||
Info: [ 7834, 8165) |
|
||||
Info: [ 8165, 8496) |
|
||||
Info: [ 8496, 8827) |
|
||||
Info: [ 8827, 9158) |+
|
||||
Info: [ 9158, 9489) |+
|
||||
Info: [ 9489, 9820) |+
|
||||
Info: [ 9820, 10151) |***+
|
||||
Info: [ 10151, 10482) |***************************************+
|
||||
Info: [ 10482, 10813) |************************************************************
|
||||
Info: [ 10813, 11144) |***************************+
|
||||
Info: [ 11144, 11475) |*********************+
|
||||
Info: [ 11475, 11806) |****+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,180 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 40/43848 0%
|
||||
Info: logic LUTs: 16/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 16/ 5481 0%
|
||||
Info: RAMW LUTs: 8/10962 0%
|
||||
|
||||
Info: Total DFFs: 56/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 32 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x66fb0815
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 56/ 43848 0%
|
||||
Info: TRELLIS_COMB: 42/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 4/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 45 cells, random placement wirelen = 4472.
|
||||
Info: at initial placer iter 0, wirelen = 1154
|
||||
Info: at initial placer iter 1, wirelen = 977
|
||||
Info: at initial placer iter 2, wirelen = 954
|
||||
Info: at initial placer iter 3, wirelen = 946
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 940, spread = 976, legal = 985; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.02s
|
||||
Info: of which solving equations: 0.00s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 31, wirelen = 985
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 27, wirelen = 677
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 17, wirelen = 683
|
||||
Info: at iteration #13: temp = 0.000000, timing cost = 15, wirelen = 686
|
||||
Info: SA placement time 0.01s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 611.62 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.67 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.28 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10865, 10909) |*****
|
||||
Info: [ 10909, 10953) |
|
||||
Info: [ 10953, 10997) |************
|
||||
Info: [ 10997, 11041) |
|
||||
Info: [ 11041, 11085) |*****
|
||||
Info: [ 11085, 11129) |****
|
||||
Info: [ 11129, 11173) |
|
||||
Info: [ 11173, 11217) |********
|
||||
Info: [ 11217, 11261) |*********************************************************
|
||||
Info: [ 11261, 11305) |
|
||||
Info: [ 11305, 11349) |**************
|
||||
Info: [ 11349, 11393) |
|
||||
Info: [ 11393, 11437) |*********
|
||||
Info: [ 11437, 11481) |
|
||||
Info: [ 11481, 11525) |***********
|
||||
Info: [ 11525, 11569) |****
|
||||
Info: [ 11569, 11613) |********************
|
||||
Info: [ 11613, 11657) |
|
||||
Info: [ 11657, 11701) |
|
||||
Info: [ 11701, 11745) |*********
|
||||
Info: Checksum: 0x0346d215
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 301 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 322 | 18 304 | 18 304 | 0| 0.04 0.04|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.04s
|
||||
Info: Checksum: 0xd78872d0
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_3.Q
|
||||
Info: routing 1.09 1.48 Net fill_addr_flat[1] (8,28) -> (6,30)
|
||||
Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0$DPRAM_COMB2.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:27.24-27.29
|
||||
Info: logic 0.18 1.66 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0$DPRAM_COMB2.F
|
||||
Info: routing 0.12 1.78 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.1_DO[2] (6,30) -> (6,30)
|
||||
Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].rd_data_reg_TRELLIS_FF_Q_7.DI
|
||||
Info: setup 0.00 1.78 Source dut.GEN_SLOT[0].GEN_LANE[0].rd_data_reg_TRELLIS_FF_Q_7.DI
|
||||
Info: 0.57 ns logic, 1.20 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source rst$tr_io.O
|
||||
Info: routing 4.21 4.21 Net rst$TRELLIS_IO_IN (90,29) -> (8,28)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_5.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:13.17-13.20
|
||||
Info: logic 0.18 4.39 Source seed_LUT4_B_Z_LUT4_Z_5.F
|
||||
Info: routing 0.12 4.51 Net seed_LUT4_B_Z[1] (8,28) -> (8,28)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_3.DI
|
||||
Info: setup 0.00 4.51 Source lfsr_TRELLIS_FF_Q_3.DI
|
||||
Info: 0.18 ns logic, 4.33 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
|
||||
Info: routing 3.76 4.16 Net checksum[1]$TRELLIS_IO_OUT (8,31) -> (90,32)
|
||||
Info: Sink checksum[1]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:40.15-40.18
|
||||
Info: 0.40 ns logic, 3.76 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 562.11 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.51 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.16 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10721, 10775) |****
|
||||
Info: [ 10775, 10829) |
|
||||
Info: [ 10829, 10883) |****
|
||||
Info: [ 10883, 10937) |****
|
||||
Info: [ 10937, 10991) |**********
|
||||
Info: [ 10991, 11045) |
|
||||
Info: [ 11045, 11099) |******
|
||||
Info: [ 11099, 11153) |*
|
||||
Info: [ 11153, 11207) |*******************
|
||||
Info: [ 11207, 11261) |***********
|
||||
Info: [ 11261, 11315) |*****************
|
||||
Info: [ 11315, 11369) |*****************
|
||||
Info: [ 11369, 11423) |**********
|
||||
Info: [ 11423, 11477) |*********
|
||||
Info: [ 11477, 11531) |****
|
||||
Info: [ 11531, 11585) |**************
|
||||
Info: [ 11585, 11639) |******
|
||||
Info: [ 11639, 11693) |**********
|
||||
Info: [ 11693, 11747) |******
|
||||
Info: [ 11747, 11801) |******
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,186 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 39/43848 0%
|
||||
Info: logic LUTs: 39/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 0/ 5481 0%
|
||||
Info: RAMW LUTs: 0/10962 0%
|
||||
|
||||
Info: Total DFFs: 56/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 10 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0xeb969a4d
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 2/ 108 1%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 56/ 43848 0%
|
||||
Info: TRELLIS_COMB: 41/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 0/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 70 cells, random placement wirelen = 6062.
|
||||
Info: at initial placer iter 0, wirelen = 1086
|
||||
Info: at initial placer iter 1, wirelen = 997
|
||||
Info: at initial placer iter 2, wirelen = 981
|
||||
Info: at initial placer iter 3, wirelen = 973
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 971, spread = 1237, legal = 1557; time = 0.00s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 960, spread = 1285, legal = 1710; time = 0.00s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 971, spread = 1270, legal = 1845; time = 0.00s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 968, spread = 1264, legal = 1744; time = 0.00s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 969, spread = 1317, legal = 1636; time = 0.00s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 970, spread = 1246, legal = 1595; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.03s
|
||||
Info: of which solving equations: 0.00s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 34, wirelen = 1557
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 14, wirelen = 947
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 11, wirelen = 880
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 13, wirelen = 842
|
||||
Info: at iteration #19: temp = 0.000000, timing cost = 12, wirelen = 831
|
||||
Info: SA placement time 0.02s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 169.69 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.95 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.35 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 6607, 6864) |*******
|
||||
Info: [ 6864, 7121) |
|
||||
Info: [ 7121, 7378) |
|
||||
Info: [ 7378, 7635) |*
|
||||
Info: [ 7635, 7892) |
|
||||
Info: [ 7892, 8149) |
|
||||
Info: [ 8149, 8406) |
|
||||
Info: [ 8406, 8663) |
|
||||
Info: [ 8663, 8920) |
|
||||
Info: [ 8920, 9177) |*
|
||||
Info: [ 9177, 9434) |
|
||||
Info: [ 9434, 9691) |
|
||||
Info: [ 9691, 9948) |
|
||||
Info: [ 9948, 10205) |
|
||||
Info: [ 10205, 10462) |**
|
||||
Info: [ 10462, 10719) |********
|
||||
Info: [ 10719, 10976) |**********************
|
||||
Info: [ 10976, 11233) |******************
|
||||
Info: [ 11233, 11490) |**************************
|
||||
Info: [ 11490, 11747) |********************
|
||||
Info: Checksum: 0xda48d919
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 278 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 321 | 40 268 | 40 268 | 0| 0.05 0.05|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.05s
|
||||
Info: Checksum: 0x69cb9087
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 4.26 4.26 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0.DOB1
|
||||
Info: routing 0.62 4.88 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB1[2] (8,34) -> (6,33)
|
||||
Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_D_Z_PFUMX_Z_2_BLUT_LUT4_Z.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16
|
||||
Info: logic 0.31 5.19 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_D_Z_PFUMX_Z_2_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.47 5.66 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_D_Z[1] (6,33) -> (7,33)
|
||||
Info: Sink chk_TRELLIS_FF_Q_1.M
|
||||
Info: setup 0.00 5.66 Source chk_TRELLIS_FF_Q_1.M
|
||||
Info: 4.57 ns logic, 1.09 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[7]$tr_io.O
|
||||
Info: routing 3.69 3.69 Net seed[7]$TRELLIS_IO_IN (90,29) -> (8,29)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_5.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:14.23-14.27
|
||||
Info: logic 0.18 3.87 Source seed_LUT4_B_Z_LUT4_Z_5.F
|
||||
Info: routing 0.12 3.98 Net seed_LUT4_B_Z[7] (8,29) -> (8,29)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_9.DI
|
||||
Info: setup 0.00 3.98 Source lfsr_TRELLIS_FF_Q_9.DI
|
||||
Info: 0.18 ns logic, 3.81 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_1.Q
|
||||
Info: routing 3.80 4.19 Net checksum[1]$TRELLIS_IO_OUT (7,33) -> (90,32)
|
||||
Info: Sink checksum[1]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 3.80 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 176.77 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.98 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.19 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 6843, 7091) |******
|
||||
Info: [ 7091, 7339) |*
|
||||
Info: [ 7339, 7587) |*
|
||||
Info: [ 7587, 7835) |
|
||||
Info: [ 7835, 8083) |
|
||||
Info: [ 8083, 8331) |
|
||||
Info: [ 8331, 8579) |
|
||||
Info: [ 8579, 8827) |
|
||||
Info: [ 8827, 9075) |
|
||||
Info: [ 9075, 9323) |
|
||||
Info: [ 9323, 9571) |*
|
||||
Info: [ 9571, 9819) |
|
||||
Info: [ 9819, 10067) |
|
||||
Info: [ 10067, 10315) |
|
||||
Info: [ 10315, 10563) |*
|
||||
Info: [ 10563, 10811) |***********
|
||||
Info: [ 10811, 11059) |**********************
|
||||
Info: [ 11059, 11307) |*****************************
|
||||
Info: [ 11307, 11555) |*************
|
||||
Info: [ 11555, 11803) |********************
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,185 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 72/43848 0%
|
||||
Info: logic LUTs: 24/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 32/ 5481 0%
|
||||
Info: RAMW LUTs: 16/10962 0%
|
||||
|
||||
Info: Total DFFs: 72/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 40 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x08e681ff
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 72/ 43848 0%
|
||||
Info: TRELLIS_COMB: 74/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 8/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 57 cells, random placement wirelen = 5888.
|
||||
Info: at initial placer iter 0, wirelen = 1162
|
||||
Info: at initial placer iter 1, wirelen = 1051
|
||||
Info: at initial placer iter 2, wirelen = 1014
|
||||
Info: at initial placer iter 3, wirelen = 984
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 983, spread = 1123, legal = 1130; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.02s
|
||||
Info: of which solving equations: 0.00s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 15, wirelen = 1130
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 22, wirelen = 763
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 30, wirelen = 741
|
||||
Info: at iteration #14: temp = 0.000000, timing cost = 18, wirelen = 742
|
||||
Info: SA placement time 0.02s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 432.34 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.71 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.61 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10187, 10265) |*
|
||||
Info: [ 10265, 10343) |***
|
||||
Info: [ 10343, 10421) |
|
||||
Info: [ 10421, 10499) |****
|
||||
Info: [ 10499, 10577) |
|
||||
Info: [ 10577, 10655) |******
|
||||
Info: [ 10655, 10733) |****
|
||||
Info: [ 10733, 10811) |**********************************
|
||||
Info: [ 10811, 10889) |***************
|
||||
Info: [ 10889, 10967) |*************
|
||||
Info: [ 10967, 11045) |*******************************
|
||||
Info: [ 11045, 11123) |******************************************************
|
||||
Info: [ 11123, 11201) |*****
|
||||
Info: [ 11201, 11279) |************************************************
|
||||
Info: [ 11279, 11357) |****************
|
||||
Info: [ 11357, 11435) |*********
|
||||
Info: [ 11435, 11513) |**************
|
||||
Info: [ 11513, 11591) |*
|
||||
Info: [ 11591, 11669) |***************
|
||||
Info: [ 11669, 11747) |***********
|
||||
Info: Checksum: 0x3a3fcdd5
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 532 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 687 | 134 545 | 134 545 | 0| 0.05 0.05|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.05s
|
||||
Info: Checksum: 0x452b9643
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source dut.GEN_SLOT[2].GEN_LANE[0].rd_data_reg_TRELLIS_FF_Q_7.Q
|
||||
Info: routing 0.75 1.14 Net rd_data_flat[135] (36,12) -> (35,11)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_ALUT_LUT4_Z.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_weight_packed.v:30.50-30.62
|
||||
Info: logic 0.18 1.32 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_ALUT_LUT4_Z.F
|
||||
Info: routing 0.00 1.32 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_ALUT (35,11) -> (35,11)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.F1
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
|
||||
Info: logic 0.13 1.45 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.46 1.91 Net chk_TRELLIS_FF_Q_DI[7] (35,11) -> (36,11)
|
||||
Info: Sink chk_TRELLIS_FF_Q_7.M
|
||||
Info: setup 0.00 1.91 Source chk_TRELLIS_FF_Q_7.M
|
||||
Info: 0.70 ns logic, 1.21 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source rst$tr_io.O
|
||||
Info: routing 3.14 3.14 Net rst$TRELLIS_IO_IN (90,11) -> (34,14)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_2.C
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:13.17-13.20
|
||||
Info: logic 0.18 3.32 Source seed_LUT4_B_Z_LUT4_Z_2.F
|
||||
Info: routing 0.12 3.44 Net seed_LUT4_B_Z[6] (34,14) -> (34,14)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_7.DI
|
||||
Info: setup 0.00 3.44 Source lfsr_TRELLIS_FF_Q_7.DI
|
||||
Info: 0.18 ns logic, 3.26 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_6.Q
|
||||
Info: routing 2.79 3.18 Net checksum[6]$TRELLIS_IO_OUT (35,13) -> (90,14)
|
||||
Info: Sink checksum[6]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:40.15-40.18
|
||||
Info: 0.40 ns logic, 2.79 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 523.29 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.44 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.18 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 10589, 10650) |***
|
||||
Info: [ 10650, 10711) |***************
|
||||
Info: [ 10711, 10772) |****
|
||||
Info: [ 10772, 10833) |**
|
||||
Info: [ 10833, 10894) |******************
|
||||
Info: [ 10894, 10955) |*******************
|
||||
Info: [ 10955, 11016) |*****
|
||||
Info: [ 11016, 11077) |************
|
||||
Info: [ 11077, 11138) |************************
|
||||
Info: [ 11138, 11199) |***********************
|
||||
Info: [ 11199, 11260) |******************
|
||||
Info: [ 11260, 11321) |*******************
|
||||
Info: [ 11321, 11382) |******************************
|
||||
Info: [ 11382, 11443) |*******************************
|
||||
Info: [ 11443, 11504) |**
|
||||
Info: [ 11504, 11565) |****************
|
||||
Info: [ 11565, 11626) |******************
|
||||
Info: [ 11626, 11687) |*********
|
||||
Info: [ 11687, 11748) |**********
|
||||
Info: [ 11748, 11809) |******
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,192 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 42/43848 0%
|
||||
Info: logic LUTs: 42/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 0/ 5481 0%
|
||||
Info: RAMW LUTs: 0/10962 0%
|
||||
|
||||
Info: Total DFFs: 56/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 16 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0xb4abc577
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 4/ 108 3%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 56/ 43848 0%
|
||||
Info: TRELLIS_COMB: 44/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 0/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 75 cells, random placement wirelen = 7922.
|
||||
Info: at initial placer iter 0, wirelen = 1177
|
||||
Info: at initial placer iter 1, wirelen = 1085
|
||||
Info: at initial placer iter 2, wirelen = 1038
|
||||
Info: at initial placer iter 3, wirelen = 1014
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 1012, spread = 1503, legal = 2089; time = 0.00s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 1002, spread = 1408, legal = 2121; time = 0.00s
|
||||
Info: at iteration #3, type ALL: wirelen solved = 1045, spread = 1417, legal = 2123; time = 0.00s
|
||||
Info: at iteration #4, type ALL: wirelen solved = 998, spread = 1452, legal = 2320; time = 0.00s
|
||||
Info: at iteration #5, type ALL: wirelen solved = 1010, spread = 1419, legal = 2320; time = 0.00s
|
||||
Info: at iteration #6, type ALL: wirelen solved = 1012, spread = 1464, legal = 2353; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.03s
|
||||
Info: of which solving equations: 0.00s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 31, wirelen = 2089
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 31, wirelen = 1310
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 31, wirelen = 1292
|
||||
Info: at iteration #15: temp = 0.000000, timing cost = 28, wirelen = 1285
|
||||
Info: at iteration #20: temp = 0.000000, timing cost = 27, wirelen = 1236
|
||||
Info: at iteration #20: temp = 0.000000, timing cost = 27, wirelen = 1236
|
||||
Info: SA placement time 0.02s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 159.67 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.95 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.35 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 6237, 6512) |******
|
||||
Info: [ 6512, 6787) |
|
||||
Info: [ 6787, 7062) |*
|
||||
Info: [ 7062, 7337) |*
|
||||
Info: [ 7337, 7612) |
|
||||
Info: [ 7612, 7887) |
|
||||
Info: [ 7887, 8162) |*
|
||||
Info: [ 8162, 8437) |
|
||||
Info: [ 8437, 8712) |
|
||||
Info: [ 8712, 8987) |
|
||||
Info: [ 8987, 9262) |
|
||||
Info: [ 9262, 9537) |
|
||||
Info: [ 9537, 9812) |
|
||||
Info: [ 9812, 10087) |**
|
||||
Info: [ 10087, 10362) |****
|
||||
Info: [ 10362, 10637) |*************
|
||||
Info: [ 10637, 10912) |**************************
|
||||
Info: [ 10912, 11187) |**********************
|
||||
Info: [ 11187, 11462) |********************************
|
||||
Info: [ 11462, 11737) |*******************************
|
||||
Info: Checksum: 0x22f96075
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 317 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 440 | 117 316 | 117 316 | 0| 0.07 0.07|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.07s
|
||||
Info: Checksum: 0xcc51a16f
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 4.10 4.10 Source dut.GEN_SLOT[1].GEN_LANE[0].mem.0.0.DOA0
|
||||
Info: routing 1.43 5.53 Net rd_data_flat[64] (13,34) -> (9,25)
|
||||
Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C.A
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_weight_packed.v:30.50-30.62
|
||||
Info: logic 0.18 5.71 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C.F
|
||||
Info: routing 0.32 6.03 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z[2] (9,25) -> (9,25)
|
||||
Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z_LUT4_D.D
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.18 6.21 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z_LUT4_D.F
|
||||
Info: routing 0.12 6.33 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z_LUT4_D_Z[0] (9,25) -> (9,25)
|
||||
Info: Sink chk_TRELLIS_FF_Q_2.DI
|
||||
Info: setup 0.00 6.33 Source chk_TRELLIS_FF_Q_2.DI
|
||||
Info: 4.46 ns logic, 1.87 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[7]$tr_io.O
|
||||
Info: routing 3.88 3.88 Net seed[7]$TRELLIS_IO_IN (90,35) -> (12,33)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:14.23-14.27
|
||||
Info: logic 0.18 4.06 Source seed_LUT4_B_Z_LUT4_Z.F
|
||||
Info: routing 0.12 4.18 Net seed_LUT4_B_Z[7] (12,33) -> (12,33)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_8.DI
|
||||
Info: setup 0.00 4.18 Source lfsr_TRELLIS_FF_Q_8.DI
|
||||
Info: 0.18 ns logic, 4.00 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_7.Q
|
||||
Info: routing 3.72 4.11 Net checksum[5]$TRELLIS_IO_OUT (8,33) -> (90,32)
|
||||
Info: Sink checksum[5]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 3.72 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 157.98 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.18 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.11 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 6170, 6455) |***
|
||||
Info: [ 6455, 6740) |*****
|
||||
Info: [ 6740, 7025) |
|
||||
Info: [ 7025, 7310) |
|
||||
Info: [ 7310, 7595) |
|
||||
Info: [ 7595, 7880) |
|
||||
Info: [ 7880, 8165) |
|
||||
Info: [ 8165, 8450) |
|
||||
Info: [ 8450, 8735) |
|
||||
Info: [ 8735, 9020) |
|
||||
Info: [ 9020, 9305) |*
|
||||
Info: [ 9305, 9590) |
|
||||
Info: [ 9590, 9875) |
|
||||
Info: [ 9875, 10160) |
|
||||
Info: [ 10160, 10445) |*
|
||||
Info: [ 10445, 10730) |********
|
||||
Info: [ 10730, 11015) |********************************
|
||||
Info: [ 11015, 11300) |**********************************************
|
||||
Info: [ 11300, 11585) |**********************
|
||||
Info: [ 11585, 11870) |*********************
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,187 @@
|
||||
|
||||
|
||||
Info: Logic utilisation before packing:
|
||||
Info: Total LUT4s: 136/43848 0%
|
||||
Info: logic LUTs: 40/43848 0%
|
||||
Info: carry LUTs: 0/43848 0%
|
||||
Info: RAM LUTs: 64/ 5481 1%
|
||||
Info: RAMW LUTs: 32/10962 0%
|
||||
|
||||
Info: Total DFFs: 104/43848 0%
|
||||
|
||||
Info: Packing IOs..
|
||||
Info: Packing constants..
|
||||
Info: Packing carries...
|
||||
Info: Packing LUTs...
|
||||
Info: Packing LUT5-7s...
|
||||
Info: Packing FFs...
|
||||
Info: 72 FFs paired with LUTs.
|
||||
Info: Generating derived timing constraints...
|
||||
Info: Promoting globals...
|
||||
Info: promoting clock net clk$TRELLIS_IO_IN to global network
|
||||
Info: Checksum: 0x9978010a
|
||||
|
||||
Info: Device utilisation:
|
||||
Info: TRELLIS_IO: 18/ 245 7%
|
||||
Info: DCCA: 1/ 56 1%
|
||||
Info: DP16KD: 0/ 108 0%
|
||||
Info: MULT18X18D: 0/ 72 0%
|
||||
Info: ALU54B: 0/ 36 0%
|
||||
Info: EHXPLLL: 0/ 4 0%
|
||||
Info: EXTREFB: 0/ 2 0%
|
||||
Info: DCUA: 0/ 2 0%
|
||||
Info: PCSCLKDIV: 0/ 2 0%
|
||||
Info: IOLOGIC: 0/ 160 0%
|
||||
Info: SIOLOGIC: 0/ 85 0%
|
||||
Info: GSR: 0/ 1 0%
|
||||
Info: JTAGG: 0/ 1 0%
|
||||
Info: OSCG: 0/ 1 0%
|
||||
Info: SEDGA: 0/ 1 0%
|
||||
Info: DTR: 0/ 1 0%
|
||||
Info: USRMCLK: 0/ 1 0%
|
||||
Info: CLKDIVF: 0/ 4 0%
|
||||
Info: ECLKSYNCB: 0/ 10 0%
|
||||
Info: DLLDELD: 0/ 8 0%
|
||||
Info: DDRDLL: 0/ 4 0%
|
||||
Info: DQSBUFM: 0/ 10 0%
|
||||
Info: TRELLIS_ECLKBUF: 0/ 8 0%
|
||||
Info: ECLKBRIDGECS: 0/ 2 0%
|
||||
Info: DCSC: 0/ 2 0%
|
||||
Info: TRELLIS_FF: 104/ 43848 0%
|
||||
Info: TRELLIS_COMB: 138/ 43848 0%
|
||||
Info: TRELLIS_RAMW: 16/ 5481 0%
|
||||
|
||||
Info: Placed 0 cells based on constraints.
|
||||
Info: Creating initial analytic placement for 81 cells, random placement wirelen = 10077.
|
||||
Info: at initial placer iter 0, wirelen = 1550
|
||||
Info: at initial placer iter 1, wirelen = 1160
|
||||
Info: at initial placer iter 2, wirelen = 1079
|
||||
Info: at initial placer iter 3, wirelen = 1019
|
||||
Info: Running main analytical placer, max placement attempts per cell = 10000.
|
||||
Info: at iteration #1, type ALL: wirelen solved = 1028, spread = 1264, legal = 1320; time = 0.00s
|
||||
Info: at iteration #2, type ALL: wirelen solved = 1039, spread = 1256, legal = 1297; time = 0.00s
|
||||
Info: HeAP Placer Time: 0.02s
|
||||
Info: of which solving equations: 0.01s
|
||||
Info: of which spreading cells: 0.00s
|
||||
Info: of which strict legalisation: 0.00s
|
||||
|
||||
Info: Running simulated annealing placer for refinement.
|
||||
Info: at iteration #1: temp = 0.000000, timing cost = 27, wirelen = 1297
|
||||
Info: at iteration #5: temp = 0.000000, timing cost = 22, wirelen = 982
|
||||
Info: at iteration #10: temp = 0.000000, timing cost = 20, wirelen = 982
|
||||
Info: at iteration #12: temp = 0.000000, timing cost = 13, wirelen = 993
|
||||
Info: SA placement time 0.03s
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 363.37 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.33 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.05 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 9748, 9848) |*+
|
||||
Info: [ 9848, 9948) |*+
|
||||
Info: [ 9948, 10048) |*+
|
||||
Info: [ 10048, 10148) |+
|
||||
Info: [ 10148, 10248) |+
|
||||
Info: [ 10248, 10348) |
|
||||
Info: [ 10348, 10448) |+
|
||||
Info: [ 10448, 10548) |******+
|
||||
Info: [ 10548, 10648) |************+
|
||||
Info: [ 10648, 10748) |***************************+
|
||||
Info: [ 10748, 10848) |********+
|
||||
Info: [ 10848, 10948) |********************************+
|
||||
Info: [ 10948, 11048) |***********************************************+
|
||||
Info: [ 11048, 11148) |************************************************************
|
||||
Info: [ 11148, 11248) |***********************************+
|
||||
Info: [ 11248, 11348) |****+
|
||||
Info: [ 11348, 11448) |******************+
|
||||
Info: [ 11448, 11548) |***+
|
||||
Info: [ 11548, 11648) |******+
|
||||
Info: [ 11648, 11748) |**+
|
||||
Info: Checksum: 0x74c6e3b4
|
||||
Info: Routing globals...
|
||||
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
|
||||
|
||||
Info: Routing..
|
||||
Info: Setting up routing queue.
|
||||
Info: Routing 932 arcs.
|
||||
Info: | (re-)routed arcs | delta | remaining| time spent |
|
||||
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
|
||||
Info: 1000 | 116 875 | 116 875 | 73| 0.04 0.04|
|
||||
Info: 1074 | 118 948 | 2 73 | 0| 0.02 0.06|
|
||||
Info: Routing complete.
|
||||
Info: Router1 time 0.06s
|
||||
Info: Checksum: 0xc1b54c25
|
||||
|
||||
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source dut.GEN_SLOT[6].GEN_LANE[0].rd_data_reg_TRELLIS_FF_Q_6.Q
|
||||
Info: routing 0.80 1.19 Net rd_data_flat[390] (24,31) -> (25,30)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0_LUT4_Z_1.A
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/rtl/nms_weight_packed.v:30.50-30.62
|
||||
Info: logic 0.18 1.37 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0_LUT4_Z_1.F
|
||||
Info: routing 0.77 2.14 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0[4] (25,30) -> (22,32)
|
||||
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_BLUT_LUT4_Z.M
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: logic 0.19 2.34 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_BLUT_LUT4_Z.OFX
|
||||
Info: routing 0.27 2.61 Net chk_TRELLIS_FF_Q_DI[6] (22,32) -> (22,32)
|
||||
Info: Sink chk_TRELLIS_FF_Q_6.M
|
||||
Info: setup 0.00 2.61 Source chk_TRELLIS_FF_Q_6.M
|
||||
Info: 0.77 ns logic, 1.84 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
|
||||
Info: type curr total name
|
||||
Info: source 0.00 0.00 Source seed[4]$tr_io.O
|
||||
Info: routing 3.23 3.23 Net seed[4]$TRELLIS_IO_IN (90,32) -> (24,29)
|
||||
Info: Sink seed_LUT4_B_Z_LUT4_Z_2.B
|
||||
Info: Defined in:
|
||||
Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:14.23-14.27
|
||||
Info: logic 0.18 3.41 Source seed_LUT4_B_Z_LUT4_Z_2.F
|
||||
Info: routing 0.12 3.53 Net seed_LUT4_B_Z[4] (24,29) -> (24,29)
|
||||
Info: Sink lfsr_TRELLIS_FF_Q_5.DI
|
||||
Info: setup 0.00 3.53 Source lfsr_TRELLIS_FF_Q_5.DI
|
||||
Info: 0.18 ns logic, 3.35 ns routing
|
||||
|
||||
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
|
||||
Info: type curr total name
|
||||
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_2.Q
|
||||
Info: routing 2.92 3.31 Net checksum[2]$TRELLIS_IO_OUT (27,32) -> (90,32)
|
||||
Info: Sink checksum[2]$tr_io.I
|
||||
Info: Defined in:
|
||||
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
|
||||
Info: 0.40 ns logic, 2.92 ns routing
|
||||
|
||||
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 383.73 MHz (PASS at 80.00 MHz)
|
||||
|
||||
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.53 ns
|
||||
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.31 ns
|
||||
|
||||
Info: Slack histogram:
|
||||
Info: legend: * represents 1 endpoint(s)
|
||||
Info: + represents [1,1) endpoint(s)
|
||||
Info: [ 9894, 9989) |+
|
||||
Info: [ 9989, 10084) |*+
|
||||
Info: [ 10084, 10179) |+
|
||||
Info: [ 10179, 10274) |**+
|
||||
Info: [ 10274, 10369) |
|
||||
Info: [ 10369, 10464) |
|
||||
Info: [ 10464, 10559) |
|
||||
Info: [ 10559, 10654) |***********+
|
||||
Info: [ 10654, 10749) |*****************+
|
||||
Info: [ 10749, 10844) |************+
|
||||
Info: [ 10844, 10939) |***************+
|
||||
Info: [ 10939, 11034) |*******************************+
|
||||
Info: [ 11034, 11129) |***********************************+
|
||||
Info: [ 11129, 11224) |****************************************************+
|
||||
Info: [ 11224, 11319) |************************************+
|
||||
Info: [ 11319, 11414) |************************************************************
|
||||
Info: [ 11414, 11509) |******************+
|
||||
Info: [ 11509, 11604) |**************+
|
||||
Info: [ 11604, 11699) |****+
|
||||
Info: [ 11699, 11794) |***+
|
||||
|
||||
Info: Program finished normally.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user