V2.0.0 hardware freeze - single SDRAM

FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/OPEN_ITEMS.md

@@ -0,0 +1,88 @@
+# FPGA-Neural V2 — OPEN ITEMS
+
+Consolidated from HARDWARE_FREEZE.md, PINOUT.md, CLOCK_ARCHITECTURE.md,
+POWER_ARCHITECTURE.md, SCHEMATIC_READINESS.md. Classified per the
+governing spec's own rule: BLOCKER / CRITICAL / WARNING / OPEN /
+FUTURE.
+
+## BLOCKER (impede la realizzazione o il funzionamento del chip)
+
+1. **No physical host interface exists.** The RTL's own "host" ports
+   are a 110-pin raw parallel job-registration bus
+   (`reg_valid`/`reg_node_id`/`reg_required`/`reg_producer_ids`/
+   `reg_x_base`/`reg_w_base`/`reg_n_tiles`/`reg_result_addr`) — a
+   simulation/testbench convenience, not a real board protocol. No
+   RTL exists to serialize it (e.g. SPI, matching V1's own
+   `spi_neuron_top.v` precedent).
+2. **The 110-pin host/registration bus has no real ball assignment**
+   (deliberately — it is not yet a real physical protocol, see item 1).
+   The SDRAM bus (37 signals) and clk/rst (2 signals) now DO have a
+   real, sourced, P&R-verified assignment (`hardware/v2/constraints/
+   v2_unified.lpf`, from the real Lattice pinout CSV found at
+   `~/Downloads/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv` during this
+   step's own pre-commit review) — this item is narrower than
+   originally scoped.
+3. **No schematic exists; no PCB has been started.**
+
+## CRITICAL (rischio elevato, deve essere risolto prima del freeze)
+
+1. **Timing closure is MARGINAL, with an unfavorable pass rate.** 8
+   real P&R seeds for the frozen N=4 single-SDRAM design: only 1/8
+   reach ≥80MHz (66.97–81.84MHz range). This is WORSE than STEP18's
+   own dual-memory design (5/8 pass). The critical path itself is
+   unchanged (still `dependency_manager.v`'s own pre-existing
+   `first_ready_idx`/`reg_ready` chain) — the regression is attributed
+   to added overall die/routing pressure from consolidation, not a new
+   RTL defect, but it is real and unresolved.
+2. **Clock source/oscillator gap.** The RTL requires a direct ≥80MHz
+   clock (no PLL exists anywhere in the hierarchy — confirmed via
+   `EHXPLLL: 0/4` in every real synthesis run). Prior project memory
+   records a 16MHz board oscillator. Neither "source an 80MHz+
+   oscillator" nor "add a real PLL to the RTL" has been decided.
+3. **Two physical memories were required through STEP18** — RESOLVED
+   this round (DEC-0034): the V2 physical path no longer instantiates
+   `hardware/v1/rtl/psram_controller.v` at all. Kept here only as a
+   closed CRITICAL item for the historical record.
+
+## WARNING (non blocca il prototipo ma deve essere documentato)
+
+1. N=2's real Fmax (86.04MHz in STEP18's own dual-memory design) and
+   the STEP19 single-SDRAM N=2 config were not both measured with the
+   same best-of-N-seed rigor as N=4 — a real, disclosed gap in
+   measurement thoroughness, not a functional issue.
+2. `W_ENTRIES`/cache sizing in the weight-fetch path was set to match
+   `N_SLOTS` (4) by construction reasoning, not swept for optimality.
+3. I/O standard (LVCMOS33 assumed for all 149 signals) has not been
+   verified per real VCCIO bank once ball assignment becomes possible.
+
+## OPEN (decisione ancora da prendere)
+
+1. Configuration-flash part number / SPI-flash-boot vs JTAG-only
+   bring-up.
+2. Power regulator topology and part numbers (the previously-recorded
+   `../basic-ecp5-pcb` reference design is not accessible this
+   session to confirm as a concrete plan).
+3. Real current budget (requires running a real power-estimation tool
+   against the actual synthesized netlist — not done this round).
+4. Decoupling/bulk capacitance values (depend on regulator selection).
+5. Reset synchronization to a real external POR/supervisor source.
+6. Real per-bank VCCIO/I-O-standard verification once ball data is
+   available.
+
+## FUTURE EVOLUTION (miglioramento post-freeze — explicitly deferred)
+
+1. N=8 evaluation.
+2. A smarter W/AR priority scheme in `sdram_unified_backend.v` to
+   recover some of the +10.8% (N=4) / +5.1% (N=2) cycle-count cost of
+   single-SDRAM unification (STEP18 EXP-0046's own packing win is
+   still present — this is about the NEW W-vs-AR contention specifically).
+   generic
+3. Page-mode / keep-row-open SDRAM controller redesign (STEP18's own
+   identified next bottleneck for raw memory bandwidth, independent of
+   the single-vs-dual-memory question).
+4. True multi-outstanding SDRAM request pipelining (STEP18 Part E's
+   own documented, deliberately out-of-scope boundary).
+5. A real physical host-interface RTL bridge (SPI or similar),
+   resolving BLOCKER #1 above.
+6. Floorplanning / seed-pinning work to convert the current MARGINAL
+   timing result into a reliable PASS.