V2.0.0 hardware freeze - single SDRAM

FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/CHIP_READINESS.md

@@ -0,0 +1,72 @@
+# FPGA-Neural V2 — CHIP READINESS
+
+Precise, non-vague criteria per the governing spec's own definition:
+V2 hardware is READY only when EVERY box below is checked. If even one
+fundamental item is missing, **HARDWARE READY = NO** — no OPEN ITEM is
+masked.
+
+```
+[x] RTL frozen                       -- nms_neural_multiprocessor_sdram_unified.v,
+                                         zero V1 dependency, strict lint clean
+[x] regression PASS                  -- 461/461 (isolated controller, 9 configs),
+                                         40/40 (isolated unified backend)
+[x] bit-exact PASS                   -- 256/256 neurons, N=2 AND N=4, single SDRAM
+[x] SDRAM validation PASS            -- init/refresh/read/write/burst/masked-write,
+                                         40 real refresh events, zero corruption
+[x] N4 synthesis PASS                -- real Yosys 0.68+post, zero errors
+[ ] N4 timing >= 80 MHz              -- MARGINAL: only 1/8 real P&R seeds pass
+[ ] constraints complete             -- v2_unified.lpf exists, REAL and P&R-verified
+                                         for 39/149 signals (clk/rst + full SDRAM bus);
+                                         110-signal host bus still unassigned
+[ ] pinout complete                  -- 149-signal inventory complete; SDRAM+clk/rst
+                                         (39 signals) REALLY assigned from the official
+                                         Lattice CSV and P&R-confirmed; host bus (110
+                                         signals) deliberately unassigned (see below)
+[ ] clock defined                    -- oscillator-vs-PLL decision NOT made
+[ ] power defined                    -- rail voltages known; regulators NOT selected
+[ ] FPGA configuration defined       -- standard pins identified; flash NOT chosen
+[ ] host interface defined           -- BLOCKER: 110-pin raw bus, no real protocol
+[x] schematic requirements complete  -- SCHEMATIC_READINESS.md's own block diagram
+                                         and interconnection list are complete
+[x] first-power-on test defined      -- FIRST_POWER_ON.md's own 12-step procedure
+[ ] bitstream reproducible           -- NOT verified: no ball-assigned LPF exists to
+                                         produce a REAL, board-usable bitstream from;
+                                         the free-placement bitstreams used for
+                                         verification this round are reproducible
+                                         AS SIMULATION/FIT PROOFS ONLY, not as a
+                                         real board-programmable artifact
+```
+
+**7 of 14 items checked. HARDWARE READY = NO.**
+
+## Why each unchecked item is unchecked (no vague language)
+
+| Item | Why NOT checked |
+|---|---|
+| N4 timing ≥80MHz | 8 real P&R seeds measured; only 1 (81.84MHz) clears 80MHz. This is a real MARGINAL result, not a PASS, per the governing spec's own explicit classification rule (some seeds pass, most do not). |
+| Constraints complete | `v2_unified.lpf` real and P&R-verified for 39/149 signals (clock frequency + clk/rst + the full 37-signal SDRAM bus, sourced from the real Lattice pinout CSV found at `~/Downloads/` during this step's own pre-commit review). The 110-signal host bus is deliberately left unassigned. |
+| Pinout complete | Signal inventory is complete (149, exactly matching real P&R); SDRAM+clk/rst (39 signals, 26%) are now really assigned and P&R-confirmed; the 110-signal host bus is unassigned, not because pin data is missing, but because that bus is not yet a real physical protocol (see below) — assigning it balls now would be premature. |
+| Clock defined | No PLL exists in the RTL (confirmed: 0/4 EHXPLLL in every synthesis run); the board's real oscillator frequency (16MHz per prior project memory) does not match the RTL's own 80MHz requirement, and neither "new oscillator" nor "add a PLL" has been decided. |
+| Power defined | Rail VOLTAGES are known from real datasheets; regulator SELECTION, CURRENT budget, and decoupling are not — no real power-estimation tool was run, and the previously-referenced board power-tree design is not accessible this session to confirm as a concrete plan. |
+| FPGA configuration defined | Standard ECP5 config pins (TDI/TDO/TCK/TMS/PROGRAMN/INITN/DONE/CCLK) are correctly identified as existing and standard, but no configuration-flash part number or SPI-vs-JTAG-only bring-up approach has been chosen for V2 specifically. |
+| Host interface defined | The RTL's own "host" ports are a 110-pin raw parallel test-harness bus (`reg_valid`/`reg_node_id`/etc.), not a real board protocol. No serializing bridge RTL exists. This is the single largest real gap between "simulated/synthesized" and "physically buildable." |
+| Bitstream reproducible | Every P&R run this project has performed used free (unconstrained) I/O placement — a real, valid way to prove the design FITS the package, but not a way to produce a bitstream a real board's own fixed wiring could actually use. |
+
+## What this means, precisely
+
+The V2 hardware architecture itself — SDRAM device, controller,
+memory subsystem, compute datapath, N4/P8 configuration — is **real,
+validated, and correct**: bit-exact simulation, real synthesis, real
+place-and-route all confirm this. What remains is **entirely physical-
+integration work**: a real host interface, a real ball-level pinout, a
+real clock source decision, and real power/configuration component
+selection. None of these are memory-architecture, datapath, or
+correctness questions anymore — they are the next, concrete, well-
+defined engineering tasks, precisely enumerated in OPEN_ITEMS.md.
+
+## Final answer
+
+```
+HARDWARE FREEZE: PASS (architectural decision + RTL correctness)
+CHIP READY:      NO
+```