feat: SDRAM 8MB->64MB upgrade (AS4C32M16SB-7BIN) + N_SLOTS=8 support
Memory upgrade, at the user's own explicit request: Alliance Memory AS4C4M16SA-6TIN (64Mbit/8MB) -> AS4C32M16SB-7BIN (512Mbit/64MB, 54-ball TFBGA), the largest same-family SDR SDRAM Alliance Memory offers. Real-datasheet-driven (whole AS4C4M16SA/AS4C8M16SA/AS4C16M16SA/ AS4C32M16SA family investigated): 13 row bits (was 12, one new FPGA pin sdram_a[12]/ball F1), 10 column bits (was 8), real -7-grade AC timing (tRCD/tRP improved to 15ns, tREFI halved to 7.8us for the doubled row count). sdram_controller.v and sdram_model.v gained real ROW_BITS/COL_BITS/BANK_BITS parameters (was hardcoded 12/8/2). ADDR_WIDTH widened 23->26 bits across the live instantiation tree. This required a real SPI protocol change (spi_host_bridge.v): a 26-bit byte address no longer fits in 3 bytes -- every address field widened 3->4 bytes (WRITE_JOB 15->18 payload bytes, WRITE_MEM/READ_MEM header 5->6 bytes). Found and fixed two real timing regressions via nextpnr-ecp5 P&R (not assumed): neural_director.v's own runtime-indexed demux write (ERR-0027, was silently synthesizing an extra MULT18X18D) and nms_activation_fill_ctrl_v3.v's own linear N_SLOTS-wide max-scan (ERR-0028, became dominant at N_SLOTS=8) -- both replaced with constant-indexed/tree-based equivalents, bit-exact same behavior, confirmed via full D-Stress N=2/4/8 regression (identical cycle counts). N_SLOTS=4 now fully closes timing at 64MHz (8/8 seeds); N_SLOTS=8 significantly improved but not yet fully reliable (5/8 seeds) -- honestly disclosed, not claimed complete. Full regression re-verified: sdram_controller (461/461, 18 configs), tb_sdram_boundary (21/21), D-Stress N=2/4/8 (bit-exact), spi_host_bridge (18/18), board-level SPI smoke test (11/11), unified backend (40/40). See hardware/v2/docs/MEMORY_UPGRADE_64MB_N8.md for the full investigation, and errors.log/decisions.log (ERR-0027, ERR-0028, DEC-0039) for the complete root-cause writeups. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
@@ -43,7 +43,7 @@
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module dependency_manager #(
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parameter N_NODES = 16,
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parameter MAX_DEPS = 4,
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parameter ADDR_WIDTH = 23
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parameter ADDR_WIDTH = 26
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)(
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input wire clk,
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input wire rst,
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@@ -30,7 +30,7 @@
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// ================================================================
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module neural_director #(
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parameter ADDR_WIDTH = 23,
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parameter ADDR_WIDTH = 26,
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parameter N_SLOTS = 4,
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parameter QUEUE_DEPTH = 8
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)(
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@@ -48,11 +48,16 @@ module neural_director #(
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input wire [15:0] job_in_node_id,
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// ---- per-slot memory_manager job control (arrayed, §9) ----
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output reg [N_SLOTS-1:0] slot_job_start,
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output reg [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base,
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output reg [ADDR_WIDTH*N_SLOTS-1:0] slot_w_base,
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output reg [16*N_SLOTS-1:0] slot_n_tiles,
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output reg [ADDR_WIDTH*N_SLOTS-1:0] slot_result_addr,
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// Ports are `wire`, driven by the GEN_SLOT_OUT generate block below
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// from internal unpacked-array registers (see that block's own
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// comment for why -- a real, measured timing regression found this
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// session when ADDR_WIDTH grew from 23 to 26 bits, section
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// "post-PRE-PCB-FREEZE memory upgrade").
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output wire [N_SLOTS-1:0] slot_job_start,
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output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base,
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output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_w_base,
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output wire [16*N_SLOTS-1:0] slot_n_tiles,
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output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_result_addr,
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// slot_node_id: which node_id is currently occupying each slot --
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// not needed by memory_manager itself (it has no notion of node
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// ids), but needed by a caller (dataflow_core.v, M7) that must
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@@ -60,7 +65,7 @@ module neural_director #(
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// to notify the Dependency Manager (M6). Purely additive: existing
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// callers (hardware/v2/sim/tb_neural_director.v, M5) that don't
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// connect it are unaffected.
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output reg [16*N_SLOTS-1:0] slot_node_id,
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output wire [16*N_SLOTS-1:0] slot_node_id,
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input wire [N_SLOTS-1:0] slot_job_done,
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// ---- completion notification (§9 "rilevamento dei completamenti") ----
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@@ -121,6 +126,45 @@ module neural_director #(
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end
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end
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// ---- per-slot output storage (unpacked arrays, one real register
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// set per slot) + constant-indexed generate wiring out to the
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// packed ports above. Found and fixed this session (post-PRE-PCB-
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// FREEZE memory upgrade, ADDR_WIDTH 23->26): the PREVIOUS design
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// used one wide packed `output reg` per field and wrote it with a
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// RUNTIME-computed part-select (`slot_x_base[free_slot_idx*
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// ADDR_WIDTH +: ADDR_WIDTH] <= ...`). A variable-indexed write into
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// a wide packed register is not free logic -- Yosys/synth_ecp5
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// synthesized the index computation (`free_slot_idx*ADDR_WIDTH`)
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// as an actual MULT18X18D hard multiplier feeding a wide demux/
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// crossbar into the destination slot, and this got measurably
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// worse as ADDR_WIDTH grew (real nextpnr-ecp5 P&R: worst-seed Fmax
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// collapsed from 68.51MHz at ADDR_WIDTH=23 to ~40-47MHz at
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// ADDR_WIDTH=26, confirmed across 8 seeds, all failing the 64MHz
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// target). The fix below replaces the runtime-indexed demux write
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// with N_SLOTS parallel CONSTANT-indexed comparisons (`fi ==
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// free_slot_idx`, each a cheap few-bit compare, no multiply) each
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// gating its own slot's own narrow register -- functionally
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// IDENTICAL behavior, bit-exact same external port semantics, only
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// the internal implementation changed.
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reg slot_job_start_r [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] slot_x_base_r [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] slot_w_base_r [0:N_SLOTS-1];
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reg [15:0] slot_n_tiles_r [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] slot_result_addr_r [0:N_SLOTS-1];
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reg [15:0] slot_node_id_r [0:N_SLOTS-1];
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genvar gs;
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generate
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for (gs = 0; gs < N_SLOTS; gs = gs + 1) begin : GEN_SLOT_OUT
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assign slot_job_start[gs] = slot_job_start_r[gs];
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assign slot_x_base[gs*ADDR_WIDTH +: ADDR_WIDTH] = slot_x_base_r[gs];
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assign slot_w_base[gs*ADDR_WIDTH +: ADDR_WIDTH] = slot_w_base_r[gs];
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assign slot_n_tiles[gs*16 +: 16] = slot_n_tiles_r[gs];
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assign slot_result_addr[gs*ADDR_WIDTH +: ADDR_WIDTH] = slot_result_addr_r[gs];
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assign slot_node_id[gs*16 +: 16] = slot_node_id_r[gs];
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end
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endgenerate
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// Priority-encoded lowest-indexed slot reporting job_done this
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// cycle (combinational, so it reflects THIS cycle's slot_job_done
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// bus directly -- a register-based "already reported one" flag
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@@ -143,16 +187,18 @@ module neural_director #(
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q_tail <= {Q_ADDR_WIDTH{1'b0}};
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q_count <= {(Q_ADDR_WIDTH+1){1'b0}};
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slot_busy <= {N_SLOTS{1'b0}};
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slot_job_start <= {N_SLOTS{1'b0}};
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slot_x_base <= {(ADDR_WIDTH*N_SLOTS){1'b0}};
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slot_w_base <= {(ADDR_WIDTH*N_SLOTS){1'b0}};
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slot_n_tiles <= {(16*N_SLOTS){1'b0}};
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slot_result_addr <= {(ADDR_WIDTH*N_SLOTS){1'b0}};
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slot_node_id <= {(16*N_SLOTS){1'b0}};
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for (fi = 0; fi < N_SLOTS; fi = fi + 1) begin
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slot_job_start_r[fi] <= 1'b0;
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slot_x_base_r[fi] <= {ADDR_WIDTH{1'b0}};
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slot_w_base_r[fi] <= {ADDR_WIDTH{1'b0}};
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slot_n_tiles_r[fi] <= 16'b0;
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slot_result_addr_r[fi] <= {ADDR_WIDTH{1'b0}};
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slot_node_id_r[fi] <= 16'b0;
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end
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job_out_done <= 1'b0;
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job_out_slot <= '0;
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end else begin
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slot_job_start <= {N_SLOTS{1'b0}};
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for (fi = 0; fi < N_SLOTS; fi = fi + 1) slot_job_start_r[fi] <= 1'b0;
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job_out_done <= 1'b0;
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// ---- Accept a new job into the ready queue (independent
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@@ -201,14 +247,21 @@ module neural_director #(
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end
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DIR_ALLOCATE: begin
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// Dispatch the head of the queue to the first
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// free slot found this cycle.
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slot_job_start[free_slot_idx] <= 1'b1;
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slot_x_base[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= q_x_base[q_head];
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slot_w_base[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= q_w_base[q_head];
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slot_n_tiles[free_slot_idx*16 +: 16] <= q_n_tiles[q_head];
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slot_result_addr[free_slot_idx*ADDR_WIDTH +: ADDR_WIDTH] <= q_result_addr[q_head];
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slot_node_id[free_slot_idx*16 +: 16] <= q_node_id[q_head];
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// Dispatch the head of the queue to the first free
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// slot found this cycle -- N_SLOTS parallel
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// constant-indexed compares (cheap) instead of one
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// runtime-indexed wide demux write (see
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// slot_x_base_r's own declaration comment for why).
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for (fi = 0; fi < N_SLOTS; fi = fi + 1) begin
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if (fi[$clog2(N_SLOTS)-1:0] == free_slot_idx) begin
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slot_job_start_r[fi] <= 1'b1;
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slot_x_base_r[fi] <= q_x_base[q_head];
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slot_w_base_r[fi] <= q_w_base[q_head];
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slot_n_tiles_r[fi] <= q_n_tiles[q_head];
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slot_result_addr_r[fi] <= q_result_addr[q_head];
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slot_node_id_r[fi] <= q_node_id[q_head];
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end
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end
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slot_busy[free_slot_idx] <= 1'b1;
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q_head <= (q_head == QUEUE_DEPTH[Q_ADDR_WIDTH-1:0]-1'b1) ? {Q_ADDR_WIDTH{1'b0}} : q_head + 1'b1;
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dir_state <= DIR_SCAN_READY;
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@@ -52,7 +52,7 @@
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// ================================================================
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module slot_mem_arbiter #(
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parameter ADDR_WIDTH = 23,
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parameter ADDR_WIDTH = 26,
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parameter N_PORTS = 4
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)(
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input wire clk,
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@@ -53,7 +53,7 @@
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module slot_mem_arbiter_wide #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 23,
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parameter ADDR_WIDTH = 26,
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parameter N_PORTS = 4
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)(
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input wire clk,
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@@ -26,15 +26,17 @@
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// 0x00 NOP -- 0 payload bytes.
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// 0x0F RESET -- 0 payload bytes. Pulses soft_rst_pulse for
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// one clk cycle after CS rises.
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// 0x10 WRITE_JOB -- 15 payload bytes, registers one dependency-
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// manager job (== one reg_valid/reg_* handshake):
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// 0x10 WRITE_JOB -- 18 payload bytes (widened from 15 -- see
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// "ADDRESS WIDTH" note below), registers one
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// dependency-manager job (== one reg_valid/
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// reg_* handshake):
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// byte0 = {4'b0,node_id[3:0]}
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// byte1 = {5'b0,required[2:0]}
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// byte2:3 = producer_ids[15:0]
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// byte4:6 = x_base[22:0] (byte4 msb={1'b0,x_base[22:16]})
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// byte7:9 = w_base[22:0]
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// byte10:11= n_tiles[15:0]
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// byte12:14= result_addr[22:0]
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// byte4:7 = x_base[25:0] (byte4 msb={6'b0,x_base[25:24]})
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// byte8:11 = w_base[25:0]
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// byte12:13= n_tiles[15:0]
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// byte14:17= result_addr[25:0]
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// reg_valid is asserted and HELD until the
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// cycle reg_ready also reads 1 (same-cycle
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// valid&&ready acceptance, matching
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@@ -46,31 +48,42 @@
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// bit1 = mem_busy (WRITE_MEM/READ_MEM waiting on mem_ready)
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// bit2 = last_job_accepted (sticky, cleared by next WRITE_JOB)
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// bits[7:3] = 0 (reserved)
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// 0x01 WRITE_MEM -- 5 header bytes + 2*len_words payload bytes:
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// byte0:2 = addr[22:0] (WORD address, matches
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// 0x01 WRITE_MEM -- 6 header bytes (widened from 5) + 2*len_words
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// payload bytes:
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// byte0:3 = addr[25:0] (WORD address, matches
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// sdram_unified_backend's AR port
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// convention -- NOT a byte address)
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// byte3:4 = len_words[15:0] (number of 16-bit
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// convention -- NOT a byte address;
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// byte0 msb={6'b0,addr[25:24]})
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// byte4:5 = len_words[15:0] (number of 16-bit
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// words to write, len_words>=1)
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// then len_words * 2 bytes of data, MSB-first
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// per word; each word is written via one
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// mem_req/mem_ready handshake (lb_n=ub_n=0,
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// full 16-bit write) before the next word's
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// bytes are accepted.
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// 0x02 READ_MEM -- 5 header bytes (addr + len_words, same shape
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// 0x02 READ_MEM -- 6 header bytes (addr + len_words, same shape
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// as WRITE_MEM), 0 further MOSI payload; the
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// 2*len_words response bytes are clocked out
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// on MISO starting at payload byte 6, MSB-
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// on MISO starting at payload byte 7, MSB-
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// first per word, one mem_req/mem_ready
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// read per word.
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//
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// ADDRESS WIDTH (post-PRE-PCB-FREEZE memory upgrade): ADDR_WIDTH grew
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// from 23 to 26 bits (SDRAM capacity upgrade, AS4C4M16SA-6TIN 8MB ->
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// AS4C32M16SA-7TIN 64MB -- see sdram_controller.v's own header). A
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// 26-bit address no longer fits in 3 bytes (24 bits) with a spare
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// reserved bit the way the old 23-bit address did -- every address
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// field below therefore widened from 3 to 4 bytes (6 reserved bits in
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// the new top byte instead of 1), growing WRITE_JOB from 15 to 18
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// payload bytes and the WRITE_MEM/READ_MEM header from 5 to 6 bytes.
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//
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// Any opcode byte not listed above is treated as NOP (0 payload,
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// MISO drives 0x00) -- matches spi_engine.v's own "unknown opcode is
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// inert, never wedges the bus" precedent.
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// ================================================================
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module spi_host_bridge #(
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parameter ADDR_WIDTH = 23,
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parameter ADDR_WIDTH = 26,
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parameter N_NODES = 16,
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parameter MAX_DEPS = 4
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)(
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@@ -226,9 +239,9 @@ module spi_host_bridge #(
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localparam OP_STATUS = 8'h20;
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localparam ST_OPCODE = 4'd0;
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localparam ST_JOB = 4'd1; // collecting 15 WRITE_JOB payload bytes
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localparam ST_JOB = 4'd1; // collecting 18 WRITE_JOB payload bytes
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localparam ST_JOB_WAIT= 4'd2; // reg_valid held, waiting reg_ready
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localparam ST_MEM_ADDR= 4'd3; // collecting 3 addr bytes
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localparam ST_MEM_ADDR= 4'd3; // collecting 4 addr bytes
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localparam ST_MEM_LEN = 4'd4; // collecting 2 length bytes
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localparam ST_MEM_WD = 4'd5; // WRITE_MEM: collecting 2 data bytes/word
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localparam ST_MEM_WISS= 4'd6; // WRITE_MEM: issue+wait mem_req
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@@ -238,7 +251,7 @@ module spi_host_bridge #(
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reg [3:0] state;
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reg [7:0] opcode;
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reg [3:0] byte_idx; // generic byte counter within a field
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reg [4:0] byte_idx; // generic byte counter within a field (up to 17, WRITE_JOB)
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reg [15:0] len_words;
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reg [15:0] word_cnt;
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reg [15:0] cur_word; // WRITE_MEM: assembling MSB,LSB; READ_MEM: holding readback
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@@ -252,13 +265,13 @@ module spi_host_bridge #(
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if (opcode == OP_STATUS)
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tx_mux = {5'b0, last_job_accepted_r, mem_busy_r, job_busy_r};
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else if (opcode == OP_READ_MEM && state == ST_MEM_ROUT)
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tx_mux = (byte_idx == 4'd0) ? cur_word[15:8] : cur_word[7:0];
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tx_mux = (byte_idx == 5'd0) ? cur_word[15:8] : cur_word[7:0];
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end
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assign tx_byte = tx_mux;
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_OPCODE; opcode <= 8'h00; byte_idx <= 4'd0;
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state <= ST_OPCODE; opcode <= 8'h00; byte_idx <= 5'd0;
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len_words <= 16'd0; word_cnt <= 16'd0; cur_word <= 16'd0;
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reg_valid <= 1'b0; reg_node_id <= {NODEW{1'b0}}; reg_required <= {REQW{1'b0}};
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reg_producer_ids <= {(MAX_DEPS*NODEW){1'b0}};
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@@ -292,12 +305,12 @@ module spi_host_bridge #(
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// to cs_rose below.
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if (cs_fell && state != ST_JOB_WAIT && state != ST_MEM_WISS && state != ST_MEM_RISS) begin
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state <= ST_OPCODE;
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byte_idx <= 4'd0;
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byte_idx <= 5'd0;
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end else if (!cs_fell && rx_valid) begin
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case (state)
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ST_OPCODE: begin
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opcode <= rx_byte;
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byte_idx <= 4'd0;
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byte_idx <= 5'd0;
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case (rx_byte)
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OP_WRITE_JOB: state <= ST_JOB;
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OP_WRITE_MEM: state <= ST_MEM_ADDR;
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@@ -309,59 +322,63 @@ module spi_host_bridge #(
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ST_JOB: begin
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case (byte_idx)
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4'd0: reg_node_id <= rx_byte[NODEW-1:0];
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4'd1: reg_required <= rx_byte[REQW-1:0];
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4'd2: reg_producer_ids[15:8] <= rx_byte;
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4'd3: reg_producer_ids[7:0] <= rx_byte;
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4'd4: reg_x_base[22:16] <= rx_byte[6:0];
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4'd5: reg_x_base[15:8] <= rx_byte;
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4'd6: reg_x_base[7:0] <= rx_byte;
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4'd7: reg_w_base[22:16] <= rx_byte[6:0];
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4'd8: reg_w_base[15:8] <= rx_byte;
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4'd9: reg_w_base[7:0] <= rx_byte;
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4'd10: reg_n_tiles[15:8] <= rx_byte;
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4'd11: reg_n_tiles[7:0] <= rx_byte;
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4'd12: reg_result_addr[22:16] <= rx_byte[6:0];
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4'd13: reg_result_addr[15:8] <= rx_byte;
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||||
4'd14: begin
|
||||
5'd0: reg_node_id <= rx_byte[NODEW-1:0];
|
||||
5'd1: reg_required <= rx_byte[REQW-1:0];
|
||||
5'd2: reg_producer_ids[15:8] <= rx_byte;
|
||||
5'd3: reg_producer_ids[7:0] <= rx_byte;
|
||||
5'd4: reg_x_base[25:24] <= rx_byte[1:0];
|
||||
5'd5: reg_x_base[23:16] <= rx_byte;
|
||||
5'd6: reg_x_base[15:8] <= rx_byte;
|
||||
5'd7: reg_x_base[7:0] <= rx_byte;
|
||||
5'd8: reg_w_base[25:24] <= rx_byte[1:0];
|
||||
5'd9: reg_w_base[23:16] <= rx_byte;
|
||||
5'd10: reg_w_base[15:8] <= rx_byte;
|
||||
5'd11: reg_w_base[7:0] <= rx_byte;
|
||||
5'd12: reg_n_tiles[15:8] <= rx_byte;
|
||||
5'd13: reg_n_tiles[7:0] <= rx_byte;
|
||||
5'd14: reg_result_addr[25:24] <= rx_byte[1:0];
|
||||
5'd15: reg_result_addr[23:16] <= rx_byte;
|
||||
5'd16: reg_result_addr[15:8] <= rx_byte;
|
||||
5'd17: begin
|
||||
reg_result_addr[7:0] <= rx_byte;
|
||||
reg_valid <= 1'b1;
|
||||
last_job_accepted_r <= 1'b0;
|
||||
state <= ST_JOB_WAIT;
|
||||
end
|
||||
endcase
|
||||
if (byte_idx != 4'd14) byte_idx <= byte_idx + 4'd1;
|
||||
if (byte_idx != 5'd17) byte_idx <= byte_idx + 5'd1;
|
||||
end
|
||||
|
||||
ST_MEM_ADDR: begin
|
||||
case (byte_idx)
|
||||
4'd0: mem_addr[22:16] <= rx_byte[6:0];
|
||||
4'd1: mem_addr[15:8] <= rx_byte;
|
||||
4'd2: begin
|
||||
5'd0: mem_addr[25:24] <= rx_byte[1:0];
|
||||
5'd1: mem_addr[23:16] <= rx_byte;
|
||||
5'd2: mem_addr[15:8] <= rx_byte;
|
||||
5'd3: begin
|
||||
mem_addr[7:0] <= rx_byte;
|
||||
state <= ST_MEM_LEN;
|
||||
end
|
||||
endcase
|
||||
if (byte_idx != 4'd2) byte_idx <= byte_idx + 4'd1;
|
||||
else byte_idx <= 4'd0;
|
||||
if (byte_idx != 5'd3) byte_idx <= byte_idx + 5'd1;
|
||||
else byte_idx <= 5'd0;
|
||||
end
|
||||
|
||||
ST_MEM_LEN: begin
|
||||
if (byte_idx == 4'd0) begin
|
||||
if (byte_idx == 5'd0) begin
|
||||
len_words[15:8] <= rx_byte;
|
||||
byte_idx <= 4'd1;
|
||||
byte_idx <= 5'd1;
|
||||
end else begin
|
||||
len_words[7:0] <= rx_byte;
|
||||
word_cnt <= {len_words[15:8], rx_byte};
|
||||
byte_idx <= 4'd0;
|
||||
byte_idx <= 5'd0;
|
||||
state <= (opcode == OP_WRITE_MEM) ? ST_MEM_WD : ST_MEM_RISS;
|
||||
end
|
||||
end
|
||||
|
||||
ST_MEM_WD: begin
|
||||
if (byte_idx == 4'd0) begin
|
||||
if (byte_idx == 5'd0) begin
|
||||
cur_word[15:8] <= rx_byte;
|
||||
byte_idx <= 4'd1;
|
||||
byte_idx <= 5'd1;
|
||||
end else begin
|
||||
cur_word[7:0] <= rx_byte;
|
||||
state <= ST_MEM_WISS;
|
||||
@@ -390,7 +407,7 @@ module spi_host_bridge #(
|
||||
mem_busy_r <= 1'b0;
|
||||
mem_addr <= mem_addr + 1'b1;
|
||||
word_cnt <= word_cnt - 1'b1;
|
||||
byte_idx <= 4'd0;
|
||||
byte_idx <= 5'd0;
|
||||
state <= (word_cnt == 16'd1) ? ST_IGNORE : ST_MEM_WD;
|
||||
end
|
||||
|
||||
@@ -403,7 +420,7 @@ module spi_host_bridge #(
|
||||
end else if (state == ST_MEM_RISS && mem_busy_r && mem_ready) begin
|
||||
mem_busy_r <= 1'b0;
|
||||
cur_word <= mem_rdata;
|
||||
byte_idx <= 4'd0;
|
||||
byte_idx <= 5'd0;
|
||||
state <= ST_MEM_ROUT;
|
||||
end
|
||||
if (state == ST_MEM_ROUT && rx_valid) begin
|
||||
@@ -412,12 +429,12 @@ module spi_host_bridge #(
|
||||
// it is also the correct "advance" event for MISO-side
|
||||
// bookkeeping (mirrors spi_slave's own documented
|
||||
// rx_valid-drives-advancement convention).
|
||||
if (byte_idx == 4'd0) begin
|
||||
byte_idx <= 4'd1;
|
||||
if (byte_idx == 5'd0) begin
|
||||
byte_idx <= 5'd1;
|
||||
end else begin
|
||||
mem_addr <= mem_addr + 1'b1;
|
||||
word_cnt <= word_cnt - 1'b1;
|
||||
byte_idx <= 4'd0;
|
||||
byte_idx <= 5'd0;
|
||||
state <= (word_cnt == 16'd1) ? ST_IGNORE : ST_MEM_RISS;
|
||||
end
|
||||
end
|
||||
|
||||
Reference in New Issue
Block a user