docs: consolidate all V2 datasheets into one current, complete document
The repository had accumulated multiple, contradictory "current state" documents for V2 hardware: an old V1 IT/EN datasheet copy nested inside hardware/v2/docs/datasheet/, a stray untracked duplicate at repo root (docs/DatasheetLatex/), and a second, much older documentation track (hardware/v2/docs/*.md: PRE_PCB_VERIFICATION.md, PRE_PCB_CLOSURE_4POINT.md, MEMORY_UPGRADE_64MB_N8.md, and 10 more) describing an earlier PSRAM/ N_SLOTS<=2 milestone alongside the real, current SDRAM/N_SLOTS=4 board. The LaTeX datasheet's own front matter (features/pinout cover pages) and chapter 9 (benchmarks) were themselves still describing that obsolete architecture, contradicting the real, current chapters 5/7/10 elsewhere in the same document. This commit: - Flattens hardware/v2/docs/datasheet/files/docs/datasheet/v2-en/* up to hardware/v2/docs/datasheet/ (was 4 levels of redundant nesting). - Removes the old V1 IT/EN LaTeX copies and the stray root-level duplicate entirely (recoverable from git history, not from disk). - Preserves the real component reference PDFs (ECP5 eval board, ISSI PSRAM, programming cables) under datasheet/references/. - Removes 13 superseded hardware/v2/docs/*.md status documents after folding every real, unique fact they contained into the datasheet: SPI max verified clock (12MHz, exact 12.8MHz CDC edge), SDRAM directed boundary test (21/21 PASS), 16MHz oscillator MPN (ECS-3225MV-160-BN-TR), and the real FPGA<->SDRAM ball mapping cross-check. - Rewrites the datasheet's own front matter, ch.4 (parameters), ch.8 (top-level module -- was documenting the wrong, non-physical top entirely), and ch.9 (benchmarks) to describe the current, real SDRAM/ N_SLOTS=4 production board, while keeping the real PSRAM-era chapters as clearly-labeled history rather than deleting correctly-measured work. - Fixes a title-page tikzpicture that was clipped off the page edge (pre-existing, unrelated to this change) by scaling it to fit. Net: 85 files changed, -8814/+498 lines. hardware/v2/docs/ now contains exactly one current datasheet plus FIRST_POWER_ON.md (a bring-up runbook, not a duplicate spec). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
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\chapter{Architecture}
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\label{ch:arch}
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\begin{fnnote}[Scheduling core unchanged; memory backend and slot count
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have]
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\code{dependency\_manager.v} and \code{neural\_director.v} (this
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chapter's own subject) are identical between the PSRAM-era milestone
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described below and the current, real SDRAM board --- the scheduling
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logic itself did not change. What changed since is the memory backend
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(single SDR SDRAM, not PSRAM, \S\ref{sec:sdram-mem-addendum}), the
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absence of the shared \textbf{Activation Cache} module from the current
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physical top (ch.~\ref{ch:toplevel}), and the production slot count
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(\code{N\_SLOTS}=4, not 2).
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\end{fnnote}
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\section{Module map}
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\begin{center}
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\begin{tikzpicture}[node distance=7mm and 11mm,font=\footnotesize]
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\node[fnblockD,minimum width=34mm,minimum height=13mm] (dm){\textbf{Dependency Manager}\\{\scriptsize node table, wake-up}};
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\node[fnblockT,right=13mm of dm,minimum width=32mm,minimum height=13mm] (dir){\textbf{Neural Director}\\{\scriptsize first-free dispatch}};
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\node[fnreg,fill=white,right=13mm of dir,minimum width=34mm,minimum height=20mm] (mm0){
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\begin{tabular}{c}\textbf{Memory Manager} 0\\ $+$ \textbf{Neural Processor} 0\end{tabular}};
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\node[fnreg,fill=white,below=3mm of mm0,minimum width=34mm,minimum height=20mm] (mm1){
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\begin{tabular}{c}\textbf{Memory Manager} 1\\ $+$ \textbf{Neural Processor} 1\end{tabular}};
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\node[fnblockA,below=9mm of dir,minimum width=32mm,minimum height=13mm] (cache){\textbf{Activation Cache}\\{\scriptsize shared, single-tag}};
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\node[fnblock,right=13mm of mm0,minimum width=26mm,minimum height=13mm] (arb){\textbf{Slot Memory}\\\textbf{Arbiter}};
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\node[fnblockD,below right=9mm and 13mm of arb,minimum width=30mm,minimum height=13mm] (psram){\textbf{Real V1 PSRAM chain}\\{\scriptsize memory\_interface $\to$ psram\_controller}};
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\draw[fnbus] (dm) -- node[fnlbl,above]{ready\_valid/ready} (dir);
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\draw[fnbus] (dir) -- (mm0);
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\draw[fnbus] (dir) -- (mm1);
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\draw[fnarrowT] (mm0.south) |- (cache.east);
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\draw[fnarrowT] (mm1.west) -- (cache.east);
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\draw[fnarrowT] (cache.north) |- node[fnlbl,above,pos=0.3]{producer\_done} (dm.south);
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\draw[fnbus] (mm0) -- (arb);
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\draw[fnbus] (mm1) -- (arb);
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\draw[fnbus] (cache.south) |- (arb.west);
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\draw[fnbus] (arb) -- (psram);
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\end{tikzpicture}
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\end{center}
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\begin{center}\footnotesize\itshape\color{fnGrey}
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PSRAM-era diagram, N\_SLOTS=2 shown; the architecture is parametric in
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N\_SLOTS. Every arrow is a real signal path verified in Verilator
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simulation and real Yosys/nextpnr-ecp5 synthesis. The current, real
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board (N\_SLOTS=4, single SDRAM, no Activation Cache module) is shown
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in ch.~\ref{ch:toplevel}'s own hierarchy listing.\end{center}
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\section{Dependency Manager}
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Holds a table of \code{N\_NODES} job descriptors, each tracking: node
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id, state (\code{EMPTY}/\code{WAITING}/\code{READY}/\code{DISPATCHED}),
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required-dependency count, resolved-dependency count, up to
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\code{MAX\_DEPS} producer node ids, and the job descriptor fields
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(\code{x\_base}, \code{w\_base}, \code{n\_tiles}, \code{result\_addr}). A
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node with zero required dependencies is immediately \code{READY} on
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registration. When a producer completes, \emph{every} \code{WAITING}
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node listing it among its own producers gets its resolved-dependency
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count incremented --- a single producer can satisfy several waiting
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consumers (shared-producer/multi-consumer), and a node depending on
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several producers accumulates resolution across separate events
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(multiple dependencies). Verified for both 1-hop and 2-hop transitive
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(diamond) graphs. Ready nodes are handed to the Neural Director one at a
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time over a backpressure-safe valid/ready interface.
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\begin{fnwarn}[No slot reclamation]
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\code{ST\_DISPATCHED} is terminal: node table slots are never reused
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once dispatched. A long-running system that keeps registering new
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nodes without limit will eventually exhaust \code{N\_NODES} --- this is
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a real, measured consequence (a benchmark testbench hit exactly this
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deadlock via node-id wraparound before \code{N\_NODES} was sized
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generously enough). Slot reclamation is explicitly deferred, not
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forgotten.
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\end{fnwarn}
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\section{Neural Director}
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Dispatches ready job descriptors to whichever of \code{N\_SLOTS} Memory
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Manager instances is currently free --- \textbf{first-free} scheduling: a
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fixed, lowest-index-wins priority scan, not load-balanced. Slot-busy
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tracking and completion detection are always-active, independent of
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whatever the allocate/scan control state happens to be that cycle (the
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same ``don't gate a per-unit event behind one shared FSM state''
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principle applied throughout this design). A completed slot's node id
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is tracked (\code{slot\_node\_id}) so its completion can be resolved back
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to a \code{producer\_done} event for the Dependency Manager, closing the
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wake-up loop without any external glue logic.
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\begin{fnnote}[Measured scheduling imbalance]
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Real per-slot data (\code{N\_SLOTS}=4, a 128-neuron workload) shows
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slots 0/1 delivering 1008 real tiles each while slots 2/3 deliver only
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16 each, despite all four slots reporting near-100\% ``busy''
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utilization --- direct, measured evidence that fixed lowest-index
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priority does not distribute load evenly once the shared PSRAM port is
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the real constraint. See ch.~\ref{ch:impl2}.
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\end{fnnote}
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\section{Memory Manager + Neural Processor (per slot)}
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Each slot pairs one \code{memory\_manager.v} instance with one
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\code{neural\_processor.v} instance. The Memory Manager double-buffers
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tile fetches (compute tile $N$ while prefetching tile $N{+}1$) and
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presents the Neural Processor with a simple ``data available''
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interface (\code{operand\_valid/ready}, \code{tile\_last}) --- the
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processor never sees PSRAM request/wait cycles directly. A tile's
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activation half is requested from the shared Activation Cache; its
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weight half is fetched directly (weights are per-neuron, never shared,
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so caching them would not help). A bank is presentable to the processor
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only once \emph{both} halves have arrived
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(\code{bank\_ready = bank\_x\_ready \& bank\_w\_ready}).
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\section{Activation Cache}
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\label{sec:archcache}
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A single shared instance (not one per slot) serving every Memory
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Manager's activation-fetch requests. Single-tag design: one cached
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\code{x\_base} at a time, filled tile-by-tile on first use, served
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directly from an on-chip buffer on every subsequent request for the same
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vector --- no PSRAM access on a hit. A request for a different
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\code{x\_base} invalidates the cache and restarts filling from tile~0;
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this is always \emph{correct} (never serves stale data) but can thrash
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under interleaved, genuinely-different-\code{x\_base} concurrent
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traffic --- an honestly documented limitation, not exercised by this
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project's own realistic dense-layer workloads (where many neurons of one
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layer share one input vector, dispatched together). Full detail,
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including the real Fmax cost this module introduces, in
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ch.~\ref{ch:mem}.
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\section{Slot Memory Arbiter}
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Funnels \code{N\_SLOTS}$+$1 independent backend ports (one per Memory
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Manager's weight/write-back traffic, plus one for the Activation
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Cache's own traffic) down to the one real physical PSRAM port. Fixed
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lowest-index priority, same convention as the Director. Every incoming
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request is latched into a per-port pending register regardless of
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arbiter state --- a byte-level backend protocol quirk discovered by real
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simulation (a fire-and-forget single-cycle request pulse can arrive
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while the shared bus is owned by another port; a naive ``grant only
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while live'' arbiter would silently drop it) made this latch a
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correctness requirement, not an optimization.
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\section{Real, unmodified V1 PSRAM backend}
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\code{memory\_interface.v} and \code{psram\_controller.v} are reused
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byte-for-byte from the frozen \code{hardware/v1/} tree. The controller's
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own real page-mode support (fast same-page continuation vs.\ a slower
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cold access) was already implemented in V1 and is exploited more
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effectively by V2's word-level burst rewrite (ch.~\ref{ch:mem}) --- no
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change to the controller itself was needed or made.
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