docs: consolidate all V2 datasheets into one current, complete document

The repository had accumulated multiple, contradictory "current state"
documents for V2 hardware: an old V1 IT/EN datasheet copy nested inside
hardware/v2/docs/datasheet/, a stray untracked duplicate at repo root
(docs/DatasheetLatex/), and a second, much older documentation track
(hardware/v2/docs/*.md: PRE_PCB_VERIFICATION.md, PRE_PCB_CLOSURE_4POINT.md,
MEMORY_UPGRADE_64MB_N8.md, and 10 more) describing an earlier PSRAM/
N_SLOTS<=2 milestone alongside the real, current SDRAM/N_SLOTS=4 board.
The LaTeX datasheet's own front matter (features/pinout cover pages) and
chapter 9 (benchmarks) were themselves still describing that obsolete
architecture, contradicting the real, current chapters 5/7/10 elsewhere
in the same document.

This commit:
- Flattens hardware/v2/docs/datasheet/files/docs/datasheet/v2-en/* up to
  hardware/v2/docs/datasheet/ (was 4 levels of redundant nesting).
- Removes the old V1 IT/EN LaTeX copies and the stray root-level
  duplicate entirely (recoverable from git history, not from disk).
- Preserves the real component reference PDFs (ECP5 eval board, ISSI
  PSRAM, programming cables) under datasheet/references/.
- Removes 13 superseded hardware/v2/docs/*.md status documents after
  folding every real, unique fact they contained into the datasheet:
  SPI max verified clock (12MHz, exact 12.8MHz CDC edge), SDRAM directed
  boundary test (21/21 PASS), 16MHz oscillator MPN (ECS-3225MV-160-BN-TR),
  and the real FPGA<->SDRAM ball mapping cross-check.
- Rewrites the datasheet's own front matter, ch.4 (parameters), ch.8
  (top-level module -- was documenting the wrong, non-physical top
  entirely), and ch.9 (benchmarks) to describe the current, real SDRAM/
  N_SLOTS=4 production board, while keeping the real PSRAM-era chapters
  as clearly-labeled history rather than deleting correctly-measured
  work.
- Fixes a title-page tikzpicture that was clipped off the page edge
  (pre-existing, unrelated to this change) by scaling it to fit.

Net: 85 files changed, -8814/+498 lines. hardware/v2/docs/ now contains
exactly one current datasheet plus FIRST_POWER_ON.md (a bring-up
runbook, not a duplicate spec).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/datasheet/chapters/01-overview.tex

@@ -0,0 +1,99 @@
+\chapter{Overview and design philosophy}
+\label{ch:overview}
+
+\section{From sequential accelerator to dataflow machine}
+V1 is, structurally, a single pipeline: one neuron computes at a time,
+driven by the host over SPI, one MAC group at a time, one layer at a
+time. It is fast for what it is (the V1 datasheet's own ``ECP5
+implementation'' chapter documents its real Fmax/timing-closure history),
+but it cannot keep
+more than one computational unit genuinely busy at once, and it has no
+notion of a dependency graph --- the host sequences everything.
+
+V2 keeps V1's own proven INT8 datapath (bit-exact, byte-for-byte reused
+math) but wraps it in a fundamentally different control architecture:
+a \textbf{Dependency Manager} tracks a graph of neuron ``jobs'', each
+with an explicit list of producer nodes it depends on; a \textbf{Neural
+Director} dispatches every node whose dependencies have resolved to
+whichever of \code{N\_SLOTS} concurrent (Memory Manager $+$ Neural
+Processor) pairs is free; a slot's completion feeds back to wake up any
+node that was waiting on it. Once a graph is loaded, the whole system
+runs autonomously --- no per-neuron host intervention.
+
+\section{What did NOT change}
+\begin{itemize}
+\item The INT8$\times$INT8$\to$INT32 MAC math, the balanced adder tree,
+      ReLU/linear activation with saturation --- \code{neural\_processor.v}
+      is a direct, bit-exact-verified port of V1's own
+      \code{neuron\_parallel.v}/\code{mac8.v}/\code{mac\_unit.v}.
+\item V1's own PSRAM backend files (\code{memory\_interface.v},
+      \code{psram\_controller.v}) remain byte-for-byte, unmodified
+      copies throughout the repository --- V1 itself, as a tree
+      (\code{hardware/v1/}), is frozen and was never touched.
+      \textbf{Not currently part of V2's physical board}, however: the
+      project has since replaced external memory with a single SDR
+      SDRAM device (\S\ref{sec:sdram-mem-addendum}); the PSRAM-era
+      chapters that follow document real, correctly-measured work for
+      the architecture it was measured on, not the current board.
+\item The target device (Lattice ECP5 \code{LFE5U-45F-8BG381C}) and the
+      real-toolchain-only measurement discipline: every number in this
+      datasheet is labelled \textsc{Theoretical}, \textsc{Simulated},
+      \textsc{Post-P\&R measured}, or \textsc{Derived}, and no result was
+      invented to make V2 look better than it measured (§\ref{ch:impl2}).
+\end{itemize}
+
+\section{What DID change}
+\begin{itemize}
+\item \textbf{Concurrency}: from one active neuron to \code{N\_SLOTS}
+      independent Neural Processor instances, each fed by its own Memory
+      Manager.
+\item \textbf{Scheduling}: from host-sequenced SPI opcodes to an on-chip
+      dependency graph, resolved autonomously.
+\item \textbf{Memory backend granularity}: from byte-at-a-time fetches
+      (through \code{int8\_memory\_access.v}, still frozen V1 but no
+      longer instantiated in V2's own datapath) to word-level bursts
+      talking to \code{memory\_interface.v} directly --- a real, measured
+      2.24--2.37$\times$ speedup (ch.~\ref{ch:mem}).
+\item \textbf{Memory traffic pattern}: a new shared on-chip
+      \textbf{activation cache} eliminates redundant re-fetching of an
+      input vector shared by many neurons of the same layer --- a
+      further real 1.66--2.00$\times$ cycle reduction, at a real, honestly
+      reported Fmax cost (ch.~\ref{ch:mem}).
+\end{itemize}
+
+\section{The central, measured finding}
+The single most important result of this project's own benchmark
+campaign is that \textbf{V2 is memory-bound, not compute-bound}: the
+real compute-to-memory-wait ratio is on the order of 1:170--1:220, and
+the one physical PSRAM port saturates at $\approx$90\% utilization
+regardless of \code{N\_SLOTS}$\ge$2. Real parallel scaling from
+\code{N\_SLOTS}=1 to \code{N\_SLOTS}=8 is essentially flat for
+large/sustained workloads (1.05--1.06$\times$), and once real,
+place\&route-measured Fmax degradation from added routing congestion is
+also accounted for, \code{N\_SLOTS}=4 measures as \emph{slower} in real
+wall-clock time than \code{N\_SLOTS}=1 for the largest workload tested
+--- more hardware parallelism made that specific configuration worse,
+not better, because the bottleneck was never compute. This finding
+directly shaped both post-campaign optimizations in ch.~\ref{ch:mem}.
+
+\begin{fnwarn}[Architecture changed since this finding: SDRAM, not PSRAM]
+This memory-bound finding was measured on the PSRAM-era architecture
+described above. The project has since replaced PSRAM with a single
+SDR SDRAM device (\S\ref{sec:sdram-mem-addendum}) and closed on
+\textbf{\code{N\_SLOTS}=4 as the production configuration} --- chosen
+primarily because it is the largest slot count that reliably closes
+real timing (8/8 seeds @ 64\,MHz, ch.~\ref{ch:hw}
+\S\ref{sec:clock-closure-current}), not from a re-run of this specific
+utilization/scaling study. Whether the SDRAM backend's own
+utilization/saturation ratio matches the PSRAM-era $\approx$90\% figure
+above has \textbf{not been independently re-measured} --- disclosed as
+an open item, not assumed to carry over.
+\end{fnwarn}
+
+\begin{fnnote}[Reproducibility]
+Every real number in this datasheet traces to a specific, append-only
+log entry (\code{EXP-\textit{NNNN}}, \code{DEC-\textit{NNNN}},
+\code{ERR-\textit{NNNN}}) in \code{hardware/v2/logs/}, a specific git
+commit, and an exact toolchain command --- the same discipline applied
+throughout V1's own development.
+\end{fnnote}