feat(v2): M6 Dependency Manager, multi-dependency wake-up

Implements M6: dependency_manager.v tracks a table of node
descriptors (node_id/state/required_dependencies/resolved_
dependencies/producer_ids -- §10's exact field list), incrementing a
waiting node's resolved count whenever one of its listed producers
completes, transitioning it to READY once resolved==required, and
dispatching ready nodes to the Neural Director (M5) one at a time via
a backpressure-safe valid/ready interface.

Verified with Verilator on a small hand-built DAG: node0/node1 have no
dependencies (dispatch immediately); node2 depends on BOTH node0 AND
node1 ("dipendenze multiple") and stays WAITING until both complete,
confirmed via an explicit negative check after only one resolves;
node3 depends on node0 ALONE, demonstrating a single producer
("node0") satisfying two different consumers' dependencies
("risultati condivisi... piu' consumer") -- node3 fully, node2
partially. 4/4 tests pass.

Scope for this milestone (decisions.log DEC-0008): dependency
COUNTING/readiness only, no direct producer-to-consumer value
forwarding (§11 frames that as a "quando possibile" optimization, not
a correctness requirement -- deferred until real bandwidth
measurements justify it) and no node-slot reclamation after dispatch
(not exercised by any scenario built so far).

Real synthesis: 0 CHECK problems, 763 LUT4/474 FF/0 DSP/0 CCU2C. Real
place&route (module fits the TRELLIS_IO budget as a bare top-level
this time, no harness needed): Fmax 155.30 MHz, PASS at 80MHz.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/logs/experiments.log

@@ -322,3 +322,46 @@ next_action: M6 -- dependency_manager.v (ready/waiting queue,
   dependency counters, wake-up, producer tracking) -- the first
   milestone where job READINESS itself, not just free-slot dispatch,
   becomes the Director's actual gating condition.
+
+EXP-0007
+timestamp: 2026-09-05T18:00:00Z
+git_commit: 2e4cedc (+ uncommitted M6 work)
+session: v2-M6-dependency-manager
+module: hardware/v2/rtl/dependency_manager.v
+configuration: N_NODES=8 (sim), N_NODES=16 (synth default),
+  MAX_DEPS=4, ADDR_WIDTH=23
+action: M6 -- dependency-count tracking table (node_id/state/
+  required_dependencies/resolved_dependencies/producer_ids, §10
+  exact field list), first-found-ready dispatch to the Director.
+command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal
+  --top-module tb -o /tmp/vtb_dep hardware/v2/rtl/dependency_manager.v
+  hardware/v2/sim/tb_dependency_manager.v && /tmp/vtb_dep
+command (synth/timing): yosys -p "synth_ecp5 -json .../top.json -top
+  dependency_manager" hardware/v2/rtl/dependency_manager.v;
+  nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80
+  --lpf-allow-unconstrained (no timing harness needed this time --
+  module's ports fit within the TRELLIS_IO budget as a bare top-level).
+result:
+  SIMULATED: 4/4 tests PASS on a small hand-built DAG (node0, node1:
+    no dependencies; node2: depends on BOTH node0 and node1 --
+    "dipendenze multiple"; node3: depends on node0 ALONE -- "risultati
+    condivisi... piu' consumer"): node0/node1 dispatch immediately;
+    node3 becomes READY the cycle node0's producer_done arrives (before
+    node1 completes); node2 stays WAITING until BOTH node0 AND node1
+    have completed, confirmed by an explicit negative check (still
+    WAITING after only one of its two dependencies resolved).
+  SYNTHESIZED: 0 CHECK problems, 763 LUT4, 474 TRELLIS_FF, 0 DSP,
+    0 CCU2C.
+  POST-P&R (real, no harness needed): Fmax = 155.30 MHz, PASS at
+    80MHz.
+errors: one testbench syntax error (nested nonblocking nested-
+  replication `{(N){M{1'b0}}}` needs an extra brace level, Verilator
+  correctly rejected it) -- fixed by building reg_producer_ids via
+  explicit bit-slice assignment instead of one big concatenation
+  expression. Not an RTL bug.
+decision: see decisions.log DEC-0008 (no value forwarding yet, no
+  slot reclamation yet -- both explicitly deferred, not missing by
+  oversight).
+next_action: M7 -- dataflow_core.v, integrating Director + Dependency
+  Manager + Memory Manager + Processor Array + Buffers into one top-
+  level module for the first time.