chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze
hardware/v1/ was created (dc0b331) as a frozen snapshot of the V1
project that then lived at the repo root (rtl/, sim/, synth/, tools/,
docs/). Root received zero further commits to those files after the
freeze -- confirmed byte-identical to the hardware/v1/ copy for every
file removed here. Root was the "before", hardware/v1/ is the
curated, canonical "after".
Removed (all verified exact-hash duplicates of hardware/v1/ content):
- rtl/ (20 files, 100% covered by hardware/v1/rtl/)
- tools/{netasm,pinout,run_regression.py,flash_catalog,validation,
fpga_benchmark.py} (19 files, 100% covered by hardware/v1/tools/;
tools/neural_sim/ kept -- unique, post-freeze, no counterpart)
- sim/*.v (47 testbenches, 100% covered by hardware/v1/sim/; the
~38 remaining sim/ entries are compiled binaries and .vcd
waveform dumps, left as a separate cleanup decision)
- synth/ecp5/{p2,p4,p8,post_fix_verify} (25 files, exact duplicates
of hardware/v1/synthesis/; the other ~84 synth/ecp5/* experiment
build directories are historical artifacts never carried into the
freeze, left as a separate decision)
- WORKLOG.md (duplicate of hardware/v1/docs/WORKLOG.md)
- docs/{FPGA-Neural-Datapatch-Benchmark,FPGA-Neural-Hardware-Design,
FPGA-NeuralNetwork-Engine}.md, docs/validation/*.md (18 files),
docs/FPGA-Neural-Datasheet-{EN,IT}.pdf -- all exact duplicates of
hardware/v1/docs/ content
- hardware/v1/docs/DatasheetLatex/ (24 files) -- exact duplicate of
hardware/v2/docs/datasheet/files/docs/datasheet/en/ (discovered
during this audit; not the same DatasheetLatex already removed
from hardware/v2/docs/ in an earlier commit)
Moved (genuine, unique, post-freeze V2 content -- not duplicated
anywhere, just living in the wrong/legacy root docs/ location):
- docs/architecture/*.md -> hardware/v2/docs/architecture/
- docs/pinouts.md, docs/FPGA_NEURAL_V2_DATASHEET.md,
docs/FPGA_NEURAL_V2_SCHEMATIC.md,
docs/FPGA-Neural-V2-Datasheet-EN.pdf -> hardware/v2/docs/
Left untouched (separate decisions, not part of this cleanup):
- docs/FPGA-Neural-Flash-Subsystem-Verification.md, docs/
v2-description.md -- orphaned root-only content, no duplicate
found anywhere, but also not part of the reviewed plan
- synth/ecp5/* experiment dirs and sim/*_sim + sim/*.vcd build
artifacts -- not literal duplicates, flagged as candidates for a
future, separate cleanup pass
Verified no functional breakage: grepped all remaining scripts/docs
for references to every removed path -- only prose/comment mentions
found, no executable imports or build-script paths broken.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
@@ -1,114 +0,0 @@
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#!/usr/bin/env python3
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"""
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Independent host-side oracle for the flash-subsystem catalog (Phase F4).
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Per WORKLOG.md's verification standard (§A.1, "regola d'oro"): CRC and
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catalog-layout expected values used by the RTL testbenches must come from
|
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a source INDEPENDENT of the RTL/testbench author's own understanding, not
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be re-derived from the same design intent that produced the hardware. This
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script is that source -- it uses Python's stdlib `zlib.crc32` (a
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widely-used, pre-existing, independently-implemented CRC32 -- not
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hand-derived here to match the RTL) and a from-scratch description of the
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catalog byte layout, written by reading the byte offsets directly rather
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than importing anything from rtl/flash_slot_manager.v.
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Catalog entry layout (16 bytes, matches rtl/flash_slot_manager.v's own
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header comment -- kept in sync by hand, cross-checked by the testbenches
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comparing actual hardware output against THIS script's output byte-for-
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byte, not by either side trusting the other's prose description):
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offset[0:3) -- 24-bit flash byte offset of the slot's data, MSB first
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offset[3:6) -- 24-bit slot length in bytes, MSB first
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offset[6] -- 8-bit slot type (opaque, host-defined)
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offset[7] -- valid flag: 0x01 = valid, anything else = invalid
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(a freshly-erased catalog sector is all-0xFF, so an
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unwritten slot is invalid by construction, no format
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step needed)
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offset[8:12) -- CRC32 (IEEE 802.3 / zlib) of the slot's data payload,
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MSB first
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offset[12:16) -- reserved, always 0x00000000
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16 slots x 16 bytes = 256 bytes = one flash page, comfortably inside the
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4KB catalog sector (sector 0, address 0x000000 -- reserved, never used for
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slot data, per rtl/flash_slot_manager.v's CATALOG_SECTOR_ADDR).
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"""
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import zlib
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import struct
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ENTRY_SIZE = 16
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N_SLOTS = 16
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CATALOG_BYTES = ENTRY_SIZE * N_SLOTS # 256
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VALID_MARK = 0x01
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def crc32(data: bytes) -> int:
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"""IEEE 802.3 CRC32 (same polynomial/reflection/init as zlib.crc32),
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the independent oracle value the RTL's crc32 module (rtl/crc32.v)
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must match bit-for-bit."""
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return zlib.crc32(data) & 0xFFFFFFFF
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def pack_entry(offset: int, length: int, slot_type: int, valid: bool, data: bytes) -> bytes:
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"""Build one 16-byte catalog entry exactly as rtl/flash_slot_manager.v
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is expected to persist it. `data` is the slot's actual payload bytes
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(used only to compute the CRC field here -- the RTL computes the same
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CRC by streaming the payload through rtl/crc32.v as it moves the
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bytes, not by re-reading this function's output)."""
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if not (0 <= offset < (1 << 24)):
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raise ValueError("offset out of 24-bit range")
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if not (0 <= length < (1 << 24)):
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raise ValueError("length out of 24-bit range")
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if not (0 <= slot_type < 256):
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raise ValueError("type out of 8-bit range")
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crc = crc32(data)
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valid_byte = VALID_MARK if valid else 0x00
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return (
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offset.to_bytes(3, "big")
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+ length.to_bytes(3, "big")
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+ bytes([slot_type])
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+ bytes([valid_byte])
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+ crc.to_bytes(4, "big")
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+ b"\x00\x00\x00\x00"
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)
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def unpack_entry(entry: bytes):
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"""Inverse of pack_entry -- parses a raw 16-byte catalog entry (e.g.
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read back from the RTL's own catalog register file / persisted flash
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sector) into its fields, for testbench comparison."""
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if len(entry) != ENTRY_SIZE:
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raise ValueError(f"entry must be exactly {ENTRY_SIZE} bytes, got {len(entry)}")
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offset = int.from_bytes(entry[0:3], "big")
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length = int.from_bytes(entry[3:6], "big")
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slot_type = entry[6]
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valid = entry[7] == VALID_MARK
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crc = int.from_bytes(entry[8:12], "big")
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reserved = entry[12:16]
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return dict(offset=offset, length=length, type=slot_type, valid=valid, crc=crc, reserved=reserved)
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def build_catalog(entries: dict) -> bytes:
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"""entries: {slot_id: (offset, length, type, valid, data)} -> full
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256-byte catalog table (unwritten slots left as 0xFF, matching a
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freshly-erased sector -- see module docstring)."""
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table = bytearray(b"\xff" * CATALOG_BYTES)
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for slot_id, (offset, length, slot_type, valid, data) in entries.items():
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if not (0 <= slot_id < N_SLOTS):
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raise ValueError("slot_id out of range")
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entry = pack_entry(offset, length, slot_type, valid, data)
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table[slot_id * ENTRY_SIZE:(slot_id + 1) * ENTRY_SIZE] = entry
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return bytes(table)
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if __name__ == "__main__":
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# Self-check / example: printed so a Verilog testbench's $display
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# output can be diffed against this by eye during bring-up.
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payload = bytes([0x10 + i for i in range(32)])
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entry = pack_entry(offset=0x001000, length=len(payload), slot_type=0x01, valid=True, data=payload)
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print("payload CRC32 =", hex(crc32(payload)))
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print("packed entry (hex) =", entry.hex())
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print("unpacked =", unpack_entry(entry))
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File diff suppressed because it is too large
Load Diff
@@ -1,105 +0,0 @@
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# netasm
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Host-side assembler for the FPGA-Neural network engine. Compiles a
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small pseudo-assembly description of a network (dense Type #1 or
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sparse-graph Type #2, see the project spec §9) into:
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- the exact on-disk byte layout (descriptor table + edge blocks,
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spec §4), and
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- the SPI command sequence (`SET_NET_TYPE` / `SET_BASE` / `WRITE_RAM`
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/ `RUN_NETWORK`) needed to load and start it.
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This is **host tooling only**. Nothing here runs on the FPGA — see
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`rtl/graph_engine.v` and `rtl/spi_engine.v` for the hardware side of
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this protocol.
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## Grammar
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```
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; Tipo #1 (dense)
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NET dense
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INPUTS 256
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LAYER 64 relu
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LAYER 16 relu
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LAYER 4 none
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END
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```
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```
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; Tipo #2 (graph)
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NET graph
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INPUTS 4 ; id 0..3
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NEURON n4 relu bias=2
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CONN 0 w=5
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CONN 1 w=-3
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NEURON n5 none bias=0
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CONN n4 w=2 ; symbolic reference to n4's output
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CONN 2 w=7
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OUTPUT n5
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END
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```
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`;` starts a comment that runs to end of line. A `CONN <src> w=<int>`
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source is either a bare decimal id (typically one of the network's
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inputs) or the name of a previously declared `NEURON`.
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For `NET dense`, only layer **sizes** and activations are declared —
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weight/bias **values** come from a trained model and are loaded by
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the host separately (unchanged `WRITE_RAM` flow); netasm's job there
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is layout (address allocation, PARALLEL-alignment validation,
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descriptor table, load/run commands).
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For `NET graph`, netasm assigns every neuron's signal id (inputs get
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0..N_in-1; every `OUTPUT` neuron is guaranteed the highest ids, as
|
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required by spec §4.4 — reordering non-output neurons is never
|
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needed for correctness since the grammar already forces
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before-you-use declaration order), resolves symbolic `CONN`
|
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references, pads each neuron's edge list to a `PARALLEL` multiple
|
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with zero-weight edges (spec §2.6 — this is a full, physical
|
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edge block, not a hint: hardware just streams `n_conn_padded` real
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||||
bytes from PSRAM), and emits the descriptor table + edge blocks +
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load/run command sequence.
|
||||
|
||||
## Compile-time validation
|
||||
|
||||
Catches these before the runtime load-time guard in
|
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`rtl/graph_engine.v` ever would (spec §9's whole point):
|
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|
||||
- `src_id < out_id` (no cycles / forward references)
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- `src_id`, `out_id` < `N_TOTAL`
|
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- an `OUTPUT` neuron is never used as another neuron's source
|
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- every `CONN` reference (symbolic or literal) resolves to a real id
|
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- a neuron's *padded* connection count fits the hardware's
|
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build-time `MAX_CONN`
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- (dense) every layer's real input count is a `PARALLEL` multiple
|
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## Usage
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```
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python3 tools/netasm/cli.py <input.netasm> -o <out_prefix> \
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[--parallel 8] [--max-conn 32] [--n-total 4096] \
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[--table-base 0x...] [--edges-base 0x...] [--x-base 0x...] \
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[--out-base 0x...] [--buf-b-base 0x...] [--weights-base 0x...]
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```
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Produces:
|
||||
|
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- `<out_prefix>.frames.bin` — length-prefixed SPI transaction bytes
|
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(2-byte big-endian length + that many payload bytes, repeated); a
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host driver replays each record by asserting CS, shifting the
|
||||
bytes out, then deasserting CS.
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- `<out_prefix>.debug.txt` — human-readable id/address/byte dump for
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review before flashing real hardware.
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See `examples/graph_example.netasm` and `examples/dense_example.netasm`.
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## Tests
|
||||
|
||||
```
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python3 tools/netasm/tests/test_netasm.py -v
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```
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Includes a byte-exact test against the same worked graph example
|
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used throughout the RTL testbenches (`sim/graph_format_tb.v`,
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`sim/graph_engine_tb.v`, `sim/spi_neuron_top_graph_tb.v`), plus one
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test per compile-time guard above.
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@@ -1,20 +0,0 @@
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from .parser import parse, DenseNet, GraphNet, NetasmSyntaxError
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from .assembler import (
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assemble_dense,
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assemble_graph,
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dump_dense_debug,
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dump_graph_debug,
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NetasmError,
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)
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__all__ = [
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"parse",
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"DenseNet",
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"GraphNet",
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"NetasmSyntaxError",
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"assemble_dense",
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"assemble_graph",
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"dump_dense_debug",
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"dump_graph_debug",
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"NetasmError",
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]
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@@ -1,405 +0,0 @@
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"""
|
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netasm assembler -- turns a parsed DenseNet/GraphNet (see parser.py)
|
||||
into exact byte layouts (descriptor tables, edge blocks) and the SPI
|
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command sequence to load them, per the data formats in the project
|
||||
spec (§4). Runs entirely on the host; nothing here executes on the
|
||||
FPGA (§10).
|
||||
|
||||
Compile-time validation performed here (spec §9's whole point: catch
|
||||
these BEFORE the runtime load-time guard in rtl/graph_engine.v ever
|
||||
sees them):
|
||||
- graph: src_id < out_id, src_id/out_id < N_TOTAL, an OUTPUT neuron
|
||||
is never used as another neuron's source, every symbolic/literal
|
||||
CONN reference resolves to a real signal id.
|
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- graph: a neuron's padded connection count (see PARALLEL padding
|
||||
below) must fit the hardware's build-time MAX_CONN.
|
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- dense: every layer's real input count must be a PARALLEL
|
||||
multiple (the same runtime convention neuron_parallel.v/
|
||||
neuron_memory.v already require of n_inputs_real).
|
||||
"""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import math
|
||||
from dataclasses import dataclass, field
|
||||
from typing import Dict, List, Optional
|
||||
|
||||
try:
|
||||
from . import frames as F
|
||||
from .parser import Conn, DenseNet, GraphNet, Neuron
|
||||
except ImportError:
|
||||
# See cli.py's matching fallback: allows this module to load when
|
||||
# imported as a bare top-level module too, not only as part of
|
||||
# the `tools.netasm` package.
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||||
import frames as F
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||||
from parser import Conn, DenseNet, GraphNet, Neuron
|
||||
|
||||
|
||||
class NetasmError(Exception):
|
||||
pass
|
||||
|
||||
|
||||
def _act_code(name: str) -> int:
|
||||
return F.ACT_RELU if name.lower() == "relu" else F.ACT_NONE
|
||||
|
||||
|
||||
def _pad_to_parallel(n_conn: int, parallel: int) -> int:
|
||||
# At least one full PARALLEL group even for n_conn == 0 -- a
|
||||
# zero-group neuron would forward n_inputs_real=0 into
|
||||
# neuron_parallel, which hangs (see rtl/neuron_parallel.v's
|
||||
# GROUPS==0 failure mode, and rtl/graph_engine.v's matching
|
||||
# load-time guard). Padding edges are (src_id=0, weight=0);
|
||||
# src_id=0 is always a valid, already-computed signal for any
|
||||
# neuron with id > 0 (every real network has n_in >= 1 inputs at
|
||||
# id 0), so this never trips the src_id < out_id guard.
|
||||
return max(parallel, math.ceil(max(n_conn, 1) / parallel) * parallel)
|
||||
|
||||
|
||||
# ================================================================
|
||||
# GRAPH (Type #2)
|
||||
# ================================================================
|
||||
|
||||
|
||||
@dataclass
|
||||
class GraphLayout:
|
||||
n_in: int
|
||||
num_neurons: int
|
||||
n_out: int
|
||||
n_total: int
|
||||
id_of: Dict[str, int]
|
||||
order: List[str] # neuron names in ascending-id order
|
||||
table_base: int
|
||||
x_base: int
|
||||
out_base: int
|
||||
edges_base: Dict[str, int]
|
||||
descriptor_bytes: bytes
|
||||
edge_bytes: Dict[str, bytes]
|
||||
n_conn_real: Dict[str, int]
|
||||
n_conn_padded: Dict[str, int]
|
||||
out_ids: List[str] # neuron names, in out_base byte order
|
||||
frames: List[F.Frame] = field(default_factory=list)
|
||||
|
||||
|
||||
def _resolve_src(
|
||||
src_token: str, id_of: Dict[str, int], n_in: int, line: int
|
||||
) -> int:
|
||||
if src_token in id_of:
|
||||
return id_of[src_token]
|
||||
try:
|
||||
v = int(src_token, 0)
|
||||
except ValueError:
|
||||
raise NetasmError(f"line {line}: unknown source '{src_token}'")
|
||||
return v
|
||||
|
||||
|
||||
def assemble_graph(
|
||||
net: GraphNet,
|
||||
parallel: int,
|
||||
max_conn: int = 32,
|
||||
n_total: int = 4096,
|
||||
table_base: int = 0x000000,
|
||||
edges_base: int = 0x010000,
|
||||
x_base: int = 0x000000,
|
||||
out_base: int = 0x020000,
|
||||
) -> GraphLayout:
|
||||
|
||||
if parallel <= 0 or (parallel & (parallel - 1)) != 0:
|
||||
raise NetasmError(f"PARALLEL must be a positive power of two, got {parallel}")
|
||||
|
||||
n_in = net.n_inputs
|
||||
declared_names = [n.name for n in net.neurons]
|
||||
neuron_by_name = {n.name: n for n in net.neurons}
|
||||
|
||||
for out_name in net.outputs:
|
||||
if out_name not in neuron_by_name:
|
||||
raise NetasmError(f"OUTPUT '{out_name}' refers to an undeclared neuron")
|
||||
if len(set(net.outputs)) != len(net.outputs):
|
||||
raise NetasmError("duplicate name in OUTPUT list")
|
||||
|
||||
# A neuron used as ANY other neuron's source can never be an
|
||||
# output sink (spec §4.4's invariant, enforced here at compile
|
||||
# time rather than left to the runtime guard).
|
||||
referenced_as_source = set()
|
||||
for n in net.neurons:
|
||||
for c in n.conns:
|
||||
if c.src in neuron_by_name:
|
||||
referenced_as_source.add(c.src)
|
||||
for out_name in net.outputs:
|
||||
if out_name in referenced_as_source:
|
||||
raise NetasmError(
|
||||
f"OUTPUT '{out_name}' is used as a source by another neuron -- "
|
||||
"output ids must be pure sinks (spec §4.4)"
|
||||
)
|
||||
|
||||
output_set = set(net.outputs)
|
||||
non_output_order = [n for n in declared_names if n not in output_set]
|
||||
order = non_output_order + list(net.outputs)
|
||||
|
||||
id_of: Dict[str, int] = {}
|
||||
for i, name in enumerate(order):
|
||||
id_of[name] = n_in + i
|
||||
|
||||
num_neurons = len(order)
|
||||
n_total_used = n_in + num_neurons
|
||||
if n_total_used > n_total:
|
||||
raise NetasmError(
|
||||
f"network needs {n_total_used} signal ids (N_in={n_in} + "
|
||||
f"{num_neurons} neurons), exceeds N_TOTAL={n_total}"
|
||||
)
|
||||
|
||||
edges_base_of: Dict[str, int] = {}
|
||||
edge_bytes: Dict[str, bytes] = {}
|
||||
n_conn_real: Dict[str, int] = {}
|
||||
n_conn_padded: Dict[str, int] = {}
|
||||
cursor = edges_base
|
||||
|
||||
for name in order:
|
||||
neuron = neuron_by_name[name]
|
||||
out_id = id_of[name]
|
||||
n_conn = len(neuron.conns)
|
||||
padded = _pad_to_parallel(n_conn, parallel)
|
||||
if padded > max_conn:
|
||||
raise NetasmError(
|
||||
f"neuron '{name}' (line {neuron.line}): {n_conn} connection(s) pad "
|
||||
f"to {padded} at PARALLEL={parallel}, exceeds MAX_CONN={max_conn}"
|
||||
)
|
||||
|
||||
edges_base_of[name] = cursor
|
||||
buf = bytearray()
|
||||
|
||||
for c in neuron.conns:
|
||||
src_id = _resolve_src(c.src, id_of, n_in, c.line)
|
||||
if src_id >= n_total:
|
||||
raise NetasmError(
|
||||
f"line {c.line}: src id {src_id} >= N_TOTAL={n_total}"
|
||||
)
|
||||
if src_id >= out_id:
|
||||
raise NetasmError(
|
||||
f"line {c.line}: neuron '{name}' (id {out_id}) connects from "
|
||||
f"src id {src_id}, which is not a strictly earlier signal "
|
||||
"(src_id must be < out_id, §7)"
|
||||
)
|
||||
buf += src_id.to_bytes(2, "big")
|
||||
buf.append(c.weight & 0xFF)
|
||||
buf.append(0x00) # reserved
|
||||
|
||||
for _ in range(padded - n_conn):
|
||||
buf += (0).to_bytes(2, "big") # src_id = 0 (always valid, weight 0)
|
||||
buf.append(0x00) # weight = 0
|
||||
buf.append(0x00) # reserved
|
||||
|
||||
edge_bytes[name] = bytes(buf)
|
||||
n_conn_real[name] = n_conn
|
||||
n_conn_padded[name] = padded
|
||||
cursor += len(buf)
|
||||
|
||||
descriptor = bytearray()
|
||||
for name in order:
|
||||
neuron = neuron_by_name[name]
|
||||
out_id = id_of[name]
|
||||
n_conn = n_conn_real[name]
|
||||
descriptor += edges_base_of[name].to_bytes(3, "big")
|
||||
descriptor += n_conn.to_bytes(2, "big")
|
||||
descriptor += out_id.to_bytes(2, "big")
|
||||
descriptor.append(_act_code(neuron.activation))
|
||||
descriptor.append(neuron.bias & 0xFF)
|
||||
descriptor += b"\x00\x00" # reserved
|
||||
|
||||
n_out = len(net.outputs)
|
||||
|
||||
layout = GraphLayout(
|
||||
n_in=n_in,
|
||||
num_neurons=num_neurons,
|
||||
n_out=n_out,
|
||||
n_total=n_total_used,
|
||||
id_of=id_of,
|
||||
order=order,
|
||||
table_base=table_base,
|
||||
x_base=x_base,
|
||||
out_base=out_base,
|
||||
edges_base=edges_base_of,
|
||||
descriptor_bytes=bytes(descriptor),
|
||||
edge_bytes=edge_bytes,
|
||||
n_conn_real=n_conn_real,
|
||||
n_conn_padded=n_conn_padded,
|
||||
out_ids=list(net.outputs),
|
||||
)
|
||||
|
||||
fr: List[F.Frame] = []
|
||||
fr.append(F.write_ram(table_base, layout.descriptor_bytes))
|
||||
for name in order:
|
||||
fr.append(F.write_ram(edges_base_of[name], edge_bytes[name]))
|
||||
fr.append(F.set_net_type(F.NET_TYPE_GRAPH))
|
||||
fr.append(F.set_base(F.SEL_X_BASE, x_base))
|
||||
fr.append(F.set_base(F.SEL_TABLE_BASE, table_base))
|
||||
fr.append(F.set_base(F.SEL_BUF_A_BASE, out_base))
|
||||
fr.append(F.set_base(F.SEL_N_INPUTS, n_in))
|
||||
fr.append(F.set_base(F.SEL_NUM_NEURONS_GRAPH, num_neurons))
|
||||
fr.append(F.set_base(F.SEL_N_OUT, n_out))
|
||||
fr.append(F.run_network(0))
|
||||
layout.frames = fr
|
||||
|
||||
return layout
|
||||
|
||||
|
||||
def dump_graph_debug(layout: GraphLayout) -> str:
|
||||
lines = []
|
||||
lines.append("=== netasm graph debug dump ===")
|
||||
lines.append(f"N_in={layout.n_in} num_neurons={layout.num_neurons} "
|
||||
f"n_out={layout.n_out} N_TOTAL_used={layout.n_total}")
|
||||
lines.append(f"table_base=0x{layout.table_base:06x} x_base=0x{layout.x_base:06x} "
|
||||
f"out_base=0x{layout.out_base:06x}")
|
||||
lines.append("")
|
||||
lines.append("id assignment (ascending):")
|
||||
for name in layout.order:
|
||||
marker = " <- OUTPUT" if name in layout.out_ids else ""
|
||||
lines.append(
|
||||
f" id={layout.id_of[name]:4d} {name:16s} n_conn={layout.n_conn_real[name]} "
|
||||
f"padded={layout.n_conn_padded[name]} edges@0x{layout.edges_base[name]:06x}{marker}"
|
||||
)
|
||||
lines.append("")
|
||||
lines.append(f"descriptor table ({len(layout.descriptor_bytes)} bytes):")
|
||||
lines.append(" " + layout.descriptor_bytes.hex(" "))
|
||||
lines.append("")
|
||||
for name in layout.order:
|
||||
lines.append(f"edges for {name} ({len(layout.edge_bytes[name])} bytes):")
|
||||
lines.append(" " + layout.edge_bytes[name].hex(" "))
|
||||
lines.append("")
|
||||
lines.append("SPI load sequence:")
|
||||
lines.append(F.frames_as_hex(layout.frames))
|
||||
return "\n".join(lines)
|
||||
|
||||
|
||||
# ================================================================
|
||||
# DENSE (Type #1)
|
||||
#
|
||||
# The grammar (spec §9) only declares layer SIZES/activations, not
|
||||
# weight VALUES -- those come from a trained model and are loaded by
|
||||
# the host separately (existing WRITE_RAM flow, unchanged from
|
||||
# before this tool existed). netasm's job for dense is therefore
|
||||
# layout + descriptor table + load/run command generation: it
|
||||
# allocates address ranges for each layer's weight matrix and bias
|
||||
# vector, validates PARALLEL alignment, and reports exactly where
|
||||
# the host must WRITE_RAM the real weight/bias content before
|
||||
# RUN_NETWORK.
|
||||
# ================================================================
|
||||
|
||||
|
||||
@dataclass
|
||||
class DenseLayerLayout:
|
||||
n_inputs_real: int
|
||||
n_neurons_real: int
|
||||
activation: str
|
||||
w_base: int
|
||||
bias_addr: int
|
||||
|
||||
|
||||
@dataclass
|
||||
class DenseLayout:
|
||||
n_inputs: int
|
||||
layers: List[DenseLayerLayout]
|
||||
table_base: int
|
||||
x_base: int
|
||||
buf_a_base: int
|
||||
buf_b_base: int
|
||||
descriptor_bytes: bytes
|
||||
frames: List[F.Frame] = field(default_factory=list)
|
||||
|
||||
|
||||
def assemble_dense(
|
||||
net: DenseNet,
|
||||
parallel: int,
|
||||
table_base: int = 0x000000,
|
||||
weights_base: int = 0x010000,
|
||||
x_base: int = 0x000000,
|
||||
buf_a_base: int = 0x020000,
|
||||
buf_b_base: int = 0x021000,
|
||||
) -> DenseLayout:
|
||||
|
||||
if parallel <= 0 or (parallel & (parallel - 1)) != 0:
|
||||
raise NetasmError(f"PARALLEL must be a positive power of two, got {parallel}")
|
||||
|
||||
layers: List[DenseLayerLayout] = []
|
||||
cursor = weights_base
|
||||
prev_n = net.n_inputs
|
||||
|
||||
for layer in net.layers:
|
||||
if prev_n % parallel != 0:
|
||||
raise NetasmError(
|
||||
f"line {layer.line}: layer's real input count {prev_n} is not a "
|
||||
f"multiple of PARALLEL={parallel} (neuron_parallel.v/"
|
||||
"neuron_memory.v both require this at runtime)"
|
||||
)
|
||||
w_base = cursor
|
||||
cursor += prev_n * layer.n_neurons
|
||||
bias_addr = cursor
|
||||
cursor += layer.n_neurons
|
||||
layers.append(
|
||||
DenseLayerLayout(
|
||||
n_inputs_real=prev_n,
|
||||
n_neurons_real=layer.n_neurons,
|
||||
activation=layer.activation,
|
||||
w_base=w_base,
|
||||
bias_addr=bias_addr,
|
||||
)
|
||||
)
|
||||
prev_n = layer.n_neurons
|
||||
|
||||
descriptor = bytearray()
|
||||
for l in layers:
|
||||
descriptor += l.w_base.to_bytes(3, "big")
|
||||
descriptor += l.bias_addr.to_bytes(3, "big")
|
||||
descriptor.append(_act_code(l.activation))
|
||||
descriptor += l.n_inputs_real.to_bytes(2, "big")
|
||||
descriptor += l.n_neurons_real.to_bytes(2, "big")
|
||||
|
||||
layout = DenseLayout(
|
||||
n_inputs=net.n_inputs,
|
||||
layers=layers,
|
||||
table_base=table_base,
|
||||
x_base=x_base,
|
||||
buf_a_base=buf_a_base,
|
||||
buf_b_base=buf_b_base,
|
||||
descriptor_bytes=bytes(descriptor),
|
||||
)
|
||||
|
||||
fr: List[F.Frame] = []
|
||||
fr.append(F.write_ram(table_base, layout.descriptor_bytes))
|
||||
fr.append(F.set_net_type(F.NET_TYPE_DENSE))
|
||||
fr.append(F.set_base(F.SEL_X_BASE, x_base))
|
||||
fr.append(F.set_base(F.SEL_TABLE_BASE, table_base))
|
||||
fr.append(F.set_base(F.SEL_BUF_A_BASE, buf_a_base))
|
||||
fr.append(F.set_base(F.SEL_BUF_B_BASE, buf_b_base))
|
||||
fr.append(F.run_network(len(net.layers)))
|
||||
layout.frames = fr
|
||||
|
||||
return layout
|
||||
|
||||
|
||||
def dump_dense_debug(layout: DenseLayout) -> str:
|
||||
lines = []
|
||||
lines.append("=== netasm dense debug dump ===")
|
||||
lines.append(f"N_inputs={layout.n_inputs} layers={len(layout.layers)}")
|
||||
lines.append(f"table_base=0x{layout.table_base:06x} x_base=0x{layout.x_base:06x} "
|
||||
f"buf_a_base=0x{layout.buf_a_base:06x} buf_b_base=0x{layout.buf_b_base:06x}")
|
||||
lines.append("")
|
||||
lines.append("NOTE: weight/bias VALUES are not part of this program -- the")
|
||||
lines.append("host must WRITE_RAM the real trained weights/bias at the")
|
||||
lines.append("addresses below before RUN_NETWORK.")
|
||||
lines.append("")
|
||||
for i, l in enumerate(layout.layers):
|
||||
lines.append(
|
||||
f" layer {i}: n_inputs_real={l.n_inputs_real} n_neurons_real={l.n_neurons_real} "
|
||||
f"activation={l.activation}"
|
||||
)
|
||||
lines.append(
|
||||
f" w_base=0x{l.w_base:06x} ({l.n_inputs_real * l.n_neurons_real} bytes) "
|
||||
f"bias_addr=0x{l.bias_addr:06x} ({l.n_neurons_real} bytes)"
|
||||
)
|
||||
lines.append("")
|
||||
lines.append(f"descriptor table ({len(layout.descriptor_bytes)} bytes):")
|
||||
lines.append(" " + layout.descriptor_bytes.hex(" "))
|
||||
lines.append("")
|
||||
lines.append("SPI load sequence:")
|
||||
lines.append(F.frames_as_hex(layout.frames))
|
||||
return "\n".join(lines)
|
||||
@@ -1,120 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
"""
|
||||
netasm CLI: compiles a .netasm source file (see parser.py's docstring
|
||||
for the grammar) into an SPI load sequence + human-readable debug
|
||||
dump. Host-side tool only -- see rtl/graph_engine.v / spi_engine.v
|
||||
for the hardware side of this protocol.
|
||||
|
||||
Usage:
|
||||
python3 -m tools.netasm.cli input.netasm -o out_prefix \\
|
||||
[--parallel 8] [--max-conn 32] [--n-total 4096]
|
||||
|
||||
Produces:
|
||||
out_prefix.frames.bin -- length-prefixed SPI transaction bytes
|
||||
out_prefix.debug.txt -- human-readable id/address/byte dump
|
||||
"""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import argparse
|
||||
import sys
|
||||
|
||||
try:
|
||||
from . import frames as F
|
||||
from .assembler import (
|
||||
NetasmError,
|
||||
assemble_dense,
|
||||
assemble_graph,
|
||||
dump_dense_debug,
|
||||
dump_graph_debug,
|
||||
)
|
||||
from .parser import DenseNet, GraphNet, NetasmSyntaxError, parse
|
||||
except ImportError:
|
||||
# Allow running this file directly (`python3 tools/netasm/cli.py`)
|
||||
# without the package being importable as `tools.netasm` -- e.g.
|
||||
# an unrelated `tools` namespace package earlier on PYTHONPATH
|
||||
# shadowing this repo's tools/ directory.
|
||||
import os
|
||||
import sys
|
||||
sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
|
||||
import frames as F
|
||||
from assembler import (
|
||||
NetasmError,
|
||||
assemble_dense,
|
||||
assemble_graph,
|
||||
dump_dense_debug,
|
||||
dump_graph_debug,
|
||||
)
|
||||
from parser import DenseNet, GraphNet, NetasmSyntaxError, parse
|
||||
|
||||
|
||||
def main(argv=None) -> int:
|
||||
ap = argparse.ArgumentParser(description=__doc__)
|
||||
ap.add_argument("source", help="path to a .netasm source file")
|
||||
ap.add_argument("-o", "--output", required=True, help="output file prefix")
|
||||
ap.add_argument("--parallel", type=int, default=8, help="hardware PARALLEL (default 8)")
|
||||
ap.add_argument("--max-conn", type=int, default=32, help="graph_engine's MAX_CONN (default 32)")
|
||||
ap.add_argument("--n-total", type=int, default=4096, help="graph_engine's N_TOTAL (default 4096)")
|
||||
ap.add_argument("--table-base", type=lambda s: int(s, 0), default=0x000000)
|
||||
ap.add_argument("--edges-base", type=lambda s: int(s, 0), default=0x010000)
|
||||
ap.add_argument("--x-base", type=lambda s: int(s, 0), default=0x000000)
|
||||
ap.add_argument("--out-base", type=lambda s: int(s, 0), default=0x020000,
|
||||
help="graph out_base / dense buf_a_base")
|
||||
ap.add_argument("--buf-b-base", type=lambda s: int(s, 0), default=0x021000,
|
||||
help="dense buf_b_base only")
|
||||
ap.add_argument("--weights-base", type=lambda s: int(s, 0), default=0x010000,
|
||||
help="dense weight/bias region base")
|
||||
args = ap.parse_args(argv)
|
||||
|
||||
with open(args.source, "r") as f:
|
||||
text = f.read()
|
||||
|
||||
try:
|
||||
net = parse(text)
|
||||
except NetasmSyntaxError as e:
|
||||
print(f"{args.source}: syntax error: {e}", file=sys.stderr)
|
||||
return 1
|
||||
|
||||
try:
|
||||
if isinstance(net, GraphNet):
|
||||
layout = assemble_graph(
|
||||
net,
|
||||
parallel=args.parallel,
|
||||
max_conn=args.max_conn,
|
||||
n_total=args.n_total,
|
||||
table_base=args.table_base,
|
||||
edges_base=args.edges_base,
|
||||
x_base=args.x_base,
|
||||
out_base=args.out_base,
|
||||
)
|
||||
debug = dump_graph_debug(layout)
|
||||
frames = layout.frames
|
||||
else:
|
||||
assert isinstance(net, DenseNet)
|
||||
layout = assemble_dense(
|
||||
net,
|
||||
parallel=args.parallel,
|
||||
table_base=args.table_base,
|
||||
weights_base=args.weights_base,
|
||||
x_base=args.x_base,
|
||||
buf_a_base=args.out_base,
|
||||
buf_b_base=args.buf_b_base,
|
||||
)
|
||||
debug = dump_dense_debug(layout)
|
||||
frames = layout.frames
|
||||
except NetasmError as e:
|
||||
print(f"{args.source}: assembly error: {e}", file=sys.stderr)
|
||||
return 1
|
||||
|
||||
F.dump_frames(frames, args.output + ".frames.bin")
|
||||
with open(args.output + ".debug.txt", "w") as f:
|
||||
f.write(debug + "\n")
|
||||
|
||||
print(f"wrote {args.output}.frames.bin ({sum(len(fr.data) for fr in frames)} payload bytes, "
|
||||
f"{len(frames)} SPI transactions)")
|
||||
print(f"wrote {args.output}.debug.txt")
|
||||
return 0
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
sys.exit(main())
|
||||
@@ -1,7 +0,0 @@
|
||||
; Simple 3-layer dense classifier.
|
||||
NET dense
|
||||
INPUTS 256
|
||||
LAYER 64 relu
|
||||
LAYER 16 relu
|
||||
LAYER 4 none
|
||||
END
|
||||
@@ -1,13 +0,0 @@
|
||||
; Worked example from the project spec (§3): 4 inputs, two neurons,
|
||||
; n5 is the sole output. See docs for the hand-computed expected
|
||||
; result with x = [10, 1, 4, 0]: n4=49, n5=126.
|
||||
NET graph
|
||||
INPUTS 4 ; id 0..3
|
||||
NEURON n4 relu bias=2
|
||||
CONN 0 w=5
|
||||
CONN 1 w=-3
|
||||
NEURON n5 none bias=0
|
||||
CONN n4 w=2 ; symbolic reference to n4's output
|
||||
CONN 2 w=7
|
||||
OUTPUT n5
|
||||
END
|
||||
@@ -1,131 +0,0 @@
|
||||
"""
|
||||
SPI frame encoding matching rtl/spi_engine.v's opcode set (§5 of the
|
||||
spec). A "frame" is the exact sequence of bytes shifted over MOSI
|
||||
during one CS-low transaction -- opcode byte first, then whatever
|
||||
fixed-size payload that opcode expects. This module only builds
|
||||
byte sequences; it does not talk to real hardware.
|
||||
"""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
from dataclasses import dataclass
|
||||
from typing import List
|
||||
|
||||
OP_NOP = 0x00
|
||||
OP_WRITE_RAM = 0x01
|
||||
OP_READ_RAM = 0x02
|
||||
OP_RESET = 0x0F
|
||||
OP_SET_BASE = 0x10
|
||||
OP_SET_NET_TYPE = 0x11
|
||||
OP_START = 0x20
|
||||
OP_STATUS = 0x21
|
||||
OP_READ_OUTPUT = 0x22
|
||||
OP_RUN_NETWORK = 0x23
|
||||
OP_READ_CONFIG = 0x30
|
||||
|
||||
SEL_X_BASE = 0x00
|
||||
SEL_W_BASE = 0x01
|
||||
SEL_BIAS_ADDR = 0x02
|
||||
SEL_TABLE_BASE = 0x03
|
||||
SEL_BUF_A_BASE = 0x04
|
||||
SEL_BUF_B_BASE = 0x05
|
||||
SEL_ACTIVATION = 0x06
|
||||
SEL_N_INPUTS = 0x07
|
||||
SEL_N_NEURONS = 0x08
|
||||
SEL_NUM_NEURONS_GRAPH = 0x09
|
||||
SEL_N_OUT = 0x0A
|
||||
|
||||
NET_TYPE_DENSE = 0x01
|
||||
NET_TYPE_GRAPH = 0x02
|
||||
|
||||
ACT_NONE = 0
|
||||
ACT_RELU = 1
|
||||
|
||||
|
||||
def _u24(v: int) -> bytes:
|
||||
if not (0 <= v < (1 << 24)):
|
||||
raise ValueError(f"address 0x{v:x} does not fit in 24 bits")
|
||||
return bytes([(v >> 16) & 0xFF, (v >> 8) & 0xFF, v & 0xFF])
|
||||
|
||||
|
||||
def _u16(v: int) -> bytes:
|
||||
if not (0 <= v < (1 << 16)):
|
||||
raise ValueError(f"value 0x{v:x} does not fit in 16 bits")
|
||||
return bytes([(v >> 8) & 0xFF, v & 0xFF])
|
||||
|
||||
|
||||
def _i8(v: int) -> int:
|
||||
if not (-128 <= v <= 127):
|
||||
raise ValueError(f"value {v} does not fit in a signed byte")
|
||||
return v & 0xFF
|
||||
|
||||
|
||||
@dataclass
|
||||
class Frame:
|
||||
label: str
|
||||
data: bytes
|
||||
|
||||
|
||||
def reset() -> Frame:
|
||||
return Frame("RESET", bytes([OP_RESET]))
|
||||
|
||||
|
||||
def set_net_type(net_type: int) -> Frame:
|
||||
return Frame(f"SET_NET_TYPE({net_type:#04x})", bytes([OP_SET_NET_TYPE, net_type & 0xFF]))
|
||||
|
||||
|
||||
def set_base(sel: int, addr: int) -> Frame:
|
||||
return Frame(
|
||||
f"SET_BASE(sel={sel:#04x}, addr={addr:#08x})",
|
||||
bytes([OP_SET_BASE, sel & 0xFF]) + _u24(addr),
|
||||
)
|
||||
|
||||
|
||||
def write_ram(addr: int, data: bytes) -> Frame:
|
||||
return Frame(
|
||||
f"WRITE_RAM(addr={addr:#08x}, len={len(data)})",
|
||||
bytes([OP_WRITE_RAM]) + _u24(addr) + _u16(len(data)) + bytes(data),
|
||||
)
|
||||
|
||||
|
||||
def read_ram(addr: int, length: int) -> Frame:
|
||||
return Frame(
|
||||
f"READ_RAM(addr={addr:#08x}, len={length})",
|
||||
bytes([OP_READ_RAM]) + _u24(addr) + _u16(length),
|
||||
)
|
||||
|
||||
|
||||
def run_network(payload_byte: int = 0) -> Frame:
|
||||
return Frame(f"RUN_NETWORK(payload={payload_byte:#04x})", bytes([OP_RUN_NETWORK, payload_byte & 0xFF]))
|
||||
|
||||
|
||||
def start() -> Frame:
|
||||
return Frame("START", bytes([OP_START]))
|
||||
|
||||
|
||||
def status() -> Frame:
|
||||
return Frame("STATUS", bytes([OP_STATUS, 0x00]))
|
||||
|
||||
|
||||
def read_config() -> Frame:
|
||||
return Frame("READ_CONFIG", bytes([OP_READ_CONFIG] + [0x00] * 10))
|
||||
|
||||
|
||||
def dump_frames(frames: List[Frame], path: str) -> None:
|
||||
"""Length-prefixed binary dump: for each frame, a 2-byte
|
||||
big-endian length followed by that many payload bytes. A simple
|
||||
host driver replays this by, for each record, asserting CS,
|
||||
shifting out the bytes, then deasserting CS."""
|
||||
with open(path, "wb") as f:
|
||||
for fr in frames:
|
||||
n = len(fr.data)
|
||||
f.write(bytes([(n >> 8) & 0xFF, n & 0xFF]))
|
||||
f.write(fr.data)
|
||||
|
||||
|
||||
def frames_as_hex(frames: List[Frame]) -> str:
|
||||
lines = []
|
||||
for fr in frames:
|
||||
hexbytes = " ".join(f"{b:02x}" for b in fr.data)
|
||||
lines.append(f"{fr.label:40s} : {hexbytes}")
|
||||
return "\n".join(lines)
|
||||
@@ -1,229 +0,0 @@
|
||||
"""
|
||||
netasm parser -- turns the pseudo-assembly text described in the
|
||||
project spec (§9) into a small AST (DenseNet / GraphNet).
|
||||
|
||||
This is host-side tooling only, has nothing to do with synthesizable
|
||||
RTL, and does not run on the FPGA (see spec §10: "Non mettere un
|
||||
interprete di istruzioni nell'FPGA").
|
||||
|
||||
Grammar (line-oriented, `;` starts a comment that runs to end of line,
|
||||
blank lines ignored):
|
||||
|
||||
NET dense
|
||||
INPUTS <n>
|
||||
LAYER <n_neurons> <relu|none>
|
||||
...
|
||||
END
|
||||
|
||||
NET graph
|
||||
INPUTS <n>
|
||||
NEURON <name> <relu|none> bias=<int>
|
||||
CONN <src> w=<int>
|
||||
...
|
||||
OUTPUT <name>
|
||||
...
|
||||
END
|
||||
|
||||
`<src>` in a CONN line is either a bare decimal integer (a literal
|
||||
signal id -- typically one of the network's inputs, 0..INPUTS-1) or
|
||||
the symbolic name of a previously declared NEURON.
|
||||
"""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
from dataclasses import dataclass, field
|
||||
from typing import List, Optional
|
||||
|
||||
|
||||
class NetasmSyntaxError(Exception):
|
||||
def __init__(self, message: str, line_no: int):
|
||||
super().__init__(f"line {line_no}: {message}")
|
||||
self.message = message
|
||||
self.line_no = line_no
|
||||
|
||||
|
||||
@dataclass
|
||||
class DenseLayer:
|
||||
n_neurons: int
|
||||
activation: str
|
||||
line: int
|
||||
|
||||
|
||||
@dataclass
|
||||
class DenseNet:
|
||||
n_inputs: int
|
||||
layers: List[DenseLayer] = field(default_factory=list)
|
||||
kind: str = "dense"
|
||||
|
||||
|
||||
@dataclass
|
||||
class Conn:
|
||||
src: str # literal id (decimal string) or symbolic neuron name
|
||||
weight: int
|
||||
line: int
|
||||
|
||||
|
||||
@dataclass
|
||||
class Neuron:
|
||||
name: str
|
||||
activation: str
|
||||
bias: int
|
||||
conns: List[Conn] = field(default_factory=list)
|
||||
line: int = 0
|
||||
|
||||
|
||||
@dataclass
|
||||
class GraphNet:
|
||||
n_inputs: int
|
||||
neurons: List[Neuron] = field(default_factory=list)
|
||||
outputs: List[str] = field(default_factory=list)
|
||||
kind: str = "graph"
|
||||
|
||||
|
||||
def _strip_comment(line: str) -> str:
|
||||
idx = line.find(";")
|
||||
return line if idx < 0 else line[:idx]
|
||||
|
||||
|
||||
def _parse_kv(token: str, key: str, line_no: int) -> int:
|
||||
prefix = key + "="
|
||||
if not token.startswith(prefix):
|
||||
raise NetasmSyntaxError(f"expected '{key}=<int>', got '{token}'", line_no)
|
||||
try:
|
||||
return int(token[len(prefix):], 0)
|
||||
except ValueError:
|
||||
raise NetasmSyntaxError(f"invalid integer in '{token}'", line_no)
|
||||
|
||||
|
||||
def _check_activation(tok: str, line_no: int) -> str:
|
||||
t = tok.lower()
|
||||
if t not in ("relu", "none"):
|
||||
raise NetasmSyntaxError(f"unknown activation '{tok}' (expected relu|none)", line_no)
|
||||
return t
|
||||
|
||||
|
||||
def parse(text: str) -> "DenseNet | GraphNet":
|
||||
lines = text.splitlines()
|
||||
|
||||
net_kind: Optional[str] = None
|
||||
n_inputs: Optional[int] = None
|
||||
dense_layers: List[DenseLayer] = []
|
||||
graph_neurons: List[Neuron] = []
|
||||
graph_outputs: List[str] = []
|
||||
seen_names = set()
|
||||
cur_neuron: Optional[Neuron] = None
|
||||
ended = False
|
||||
|
||||
for i, raw in enumerate(lines, start=1):
|
||||
line = _strip_comment(raw).strip()
|
||||
if not line:
|
||||
continue
|
||||
|
||||
tokens = line.split()
|
||||
kw = tokens[0].upper()
|
||||
|
||||
if kw == "NET":
|
||||
if net_kind is not None:
|
||||
raise NetasmSyntaxError("duplicate NET directive", i)
|
||||
if len(tokens) != 2 or tokens[1].lower() not in ("dense", "graph"):
|
||||
raise NetasmSyntaxError("expected 'NET dense' or 'NET graph'", i)
|
||||
net_kind = tokens[1].lower()
|
||||
continue
|
||||
|
||||
if net_kind is None:
|
||||
raise NetasmSyntaxError("expected 'NET dense|graph' as the first directive", i)
|
||||
|
||||
if kw == "INPUTS":
|
||||
if n_inputs is not None:
|
||||
raise NetasmSyntaxError("duplicate INPUTS directive", i)
|
||||
if len(tokens) != 2:
|
||||
raise NetasmSyntaxError("expected 'INPUTS <n>'", i)
|
||||
try:
|
||||
n_inputs = int(tokens[1], 0)
|
||||
except ValueError:
|
||||
raise NetasmSyntaxError(f"invalid input count '{tokens[1]}'", i)
|
||||
if n_inputs <= 0:
|
||||
raise NetasmSyntaxError("INPUTS must be positive", i)
|
||||
continue
|
||||
|
||||
if n_inputs is None:
|
||||
raise NetasmSyntaxError("expected 'INPUTS <n>' before any layer/neuron", i)
|
||||
|
||||
if kw == "END":
|
||||
ended = True
|
||||
continue
|
||||
|
||||
if ended:
|
||||
raise NetasmSyntaxError("no directives allowed after END", i)
|
||||
|
||||
if net_kind == "dense":
|
||||
if kw != "LAYER":
|
||||
raise NetasmSyntaxError(f"unexpected directive '{tokens[0]}' in NET dense", i)
|
||||
if len(tokens) != 3:
|
||||
raise NetasmSyntaxError("expected 'LAYER <n_neurons> <relu|none>'", i)
|
||||
try:
|
||||
n_neurons = int(tokens[1], 0)
|
||||
except ValueError:
|
||||
raise NetasmSyntaxError(f"invalid neuron count '{tokens[1]}'", i)
|
||||
if n_neurons <= 0:
|
||||
raise NetasmSyntaxError("LAYER neuron count must be positive", i)
|
||||
activation = _check_activation(tokens[2], i)
|
||||
dense_layers.append(DenseLayer(n_neurons=n_neurons, activation=activation, line=i))
|
||||
continue
|
||||
|
||||
# net_kind == "graph"
|
||||
if kw == "NEURON":
|
||||
if len(tokens) != 4:
|
||||
raise NetasmSyntaxError(
|
||||
"expected 'NEURON <name> <relu|none> bias=<int>'", i
|
||||
)
|
||||
name = tokens[1]
|
||||
if name in seen_names or name.lstrip("-").isdigit():
|
||||
raise NetasmSyntaxError(f"duplicate or reserved neuron name '{name}'", i)
|
||||
seen_names.add(name)
|
||||
activation = _check_activation(tokens[2], i)
|
||||
bias = _parse_kv(tokens[3], "bias", i)
|
||||
if not (-128 <= bias <= 127):
|
||||
raise NetasmSyntaxError(f"bias {bias} out of INT8 range", i)
|
||||
cur_neuron = Neuron(name=name, activation=activation, bias=bias, line=i)
|
||||
graph_neurons.append(cur_neuron)
|
||||
continue
|
||||
|
||||
if kw == "CONN":
|
||||
if cur_neuron is None:
|
||||
raise NetasmSyntaxError("CONN outside of a NEURON block", i)
|
||||
if len(tokens) != 3:
|
||||
raise NetasmSyntaxError("expected 'CONN <src> w=<int>'", i)
|
||||
src = tokens[1]
|
||||
weight = _parse_kv(tokens[2], "w", i)
|
||||
if not (-128 <= weight <= 127):
|
||||
raise NetasmSyntaxError(f"weight {weight} out of INT8 range", i)
|
||||
cur_neuron.conns.append(Conn(src=src, weight=weight, line=i))
|
||||
continue
|
||||
|
||||
if kw == "OUTPUT":
|
||||
if len(tokens) != 2:
|
||||
raise NetasmSyntaxError("expected 'OUTPUT <name>'", i)
|
||||
graph_outputs.append(tokens[1])
|
||||
cur_neuron = None
|
||||
continue
|
||||
|
||||
raise NetasmSyntaxError(f"unexpected directive '{tokens[0]}' in NET graph", i)
|
||||
|
||||
if net_kind is None:
|
||||
raise NetasmSyntaxError("empty program: missing NET directive", len(lines) + 1)
|
||||
if not ended:
|
||||
raise NetasmSyntaxError("missing END directive", len(lines) + 1)
|
||||
if n_inputs is None:
|
||||
raise NetasmSyntaxError("missing INPUTS directive", len(lines) + 1)
|
||||
|
||||
if net_kind == "dense":
|
||||
if not dense_layers:
|
||||
raise NetasmSyntaxError("NET dense with no LAYER directives", len(lines) + 1)
|
||||
return DenseNet(n_inputs=n_inputs, layers=dense_layers)
|
||||
|
||||
if not graph_neurons:
|
||||
raise NetasmSyntaxError("NET graph with no NEURON directives", len(lines) + 1)
|
||||
if not graph_outputs:
|
||||
raise NetasmSyntaxError("NET graph with no OUTPUT directive", len(lines) + 1)
|
||||
return GraphNet(n_inputs=n_inputs, neurons=graph_neurons, outputs=graph_outputs)
|
||||
@@ -1,285 +0,0 @@
|
||||
import importlib.util
|
||||
import os
|
||||
import sys
|
||||
import unittest
|
||||
|
||||
# Load this repo's tools/netasm package by explicit file path rather
|
||||
# than via `import tools.netasm`: some environments put an unrelated
|
||||
# `tools` namespace package earlier on PYTHONPATH (e.g. Project
|
||||
# Trellis's own tools/ directory), which would otherwise shadow this
|
||||
# repo's tools/ and break the dotted import regardless of sys.path
|
||||
# ordering tricks.
|
||||
_PKG_DIR = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
|
||||
_spec = importlib.util.spec_from_file_location(
|
||||
"netasm_under_test", os.path.join(_PKG_DIR, "__init__.py"),
|
||||
submodule_search_locations=[_PKG_DIR],
|
||||
)
|
||||
_netasm = importlib.util.module_from_spec(_spec)
|
||||
sys.modules["netasm_under_test"] = _netasm
|
||||
_spec.loader.exec_module(_netasm)
|
||||
|
||||
parse = _netasm.parse
|
||||
NetasmSyntaxError = _netasm.NetasmSyntaxError
|
||||
GraphNet = _netasm.GraphNet
|
||||
DenseNet = _netasm.DenseNet
|
||||
assemble_graph = _netasm.assemble_graph
|
||||
assemble_dense = _netasm.assemble_dense
|
||||
NetasmError = _netasm.NetasmError
|
||||
F = importlib.import_module("netasm_under_test.frames")
|
||||
|
||||
# The worked example from spec §3 / already validated byte-exact in
|
||||
# sim/graph_format_tb.v and end-to-end in sim/graph_engine_tb.v and
|
||||
# sim/spi_neuron_top_graph_tb.v: 4 inputs, n4 = relu(x0*5+x1*(-3)+2),
|
||||
# n5 = x2*7 + act[n4]*2, output = n5.
|
||||
GRAPH_SRC = """
|
||||
; worked example, spec §3
|
||||
NET graph
|
||||
INPUTS 4
|
||||
NEURON n4 relu bias=2
|
||||
CONN 0 w=5
|
||||
CONN 1 w=-3
|
||||
NEURON n5 none bias=0
|
||||
CONN n4 w=2
|
||||
CONN 2 w=7
|
||||
OUTPUT n5
|
||||
END
|
||||
"""
|
||||
|
||||
|
||||
class TestParser(unittest.TestCase):
|
||||
def test_parses_graph(self):
|
||||
net = parse(GRAPH_SRC)
|
||||
self.assertIsInstance(net, GraphNet)
|
||||
self.assertEqual(net.n_inputs, 4)
|
||||
self.assertEqual([n.name for n in net.neurons], ["n4", "n5"])
|
||||
self.assertEqual(net.outputs, ["n5"])
|
||||
|
||||
def test_parses_dense(self):
|
||||
src = """
|
||||
NET dense
|
||||
INPUTS 256
|
||||
LAYER 64 relu
|
||||
LAYER 16 relu
|
||||
LAYER 4 none
|
||||
END
|
||||
"""
|
||||
net = parse(src)
|
||||
self.assertIsInstance(net, DenseNet)
|
||||
self.assertEqual(net.n_inputs, 256)
|
||||
self.assertEqual([l.n_neurons for l in net.layers], [64, 16, 4])
|
||||
self.assertEqual([l.activation for l in net.layers], ["relu", "relu", "none"])
|
||||
|
||||
def test_missing_net_directive(self):
|
||||
with self.assertRaises(NetasmSyntaxError):
|
||||
parse("INPUTS 4\nEND\n")
|
||||
|
||||
def test_missing_end(self):
|
||||
with self.assertRaises(NetasmSyntaxError):
|
||||
parse("NET graph\nINPUTS 4\nNEURON n0 relu bias=0\n CONN 0 w=1\nOUTPUT n0\n")
|
||||
|
||||
def test_conn_outside_neuron(self):
|
||||
with self.assertRaises(NetasmSyntaxError):
|
||||
parse("NET graph\nINPUTS 4\nCONN 0 w=1\nEND\n")
|
||||
|
||||
def test_bad_weight_range(self):
|
||||
with self.assertRaises(NetasmSyntaxError):
|
||||
parse(
|
||||
"NET graph\nINPUTS 4\nNEURON n0 relu bias=0\n CONN 0 w=200\n"
|
||||
"OUTPUT n0\nEND\n"
|
||||
)
|
||||
|
||||
def test_comments_and_blank_lines_ignored(self):
|
||||
src = "; comment\nNET graph\n\nINPUTS 4 ; trailing comment\n" \
|
||||
"NEURON n0 relu bias=0\n CONN 0 w=1\nOUTPUT n0\nEND\n"
|
||||
net = parse(src)
|
||||
self.assertEqual(net.n_inputs, 4)
|
||||
|
||||
|
||||
class TestGraphAssembler(unittest.TestCase):
|
||||
def setUp(self):
|
||||
self.net = parse(GRAPH_SRC)
|
||||
|
||||
def test_id_assignment(self):
|
||||
layout = assemble_graph(self.net, parallel=2)
|
||||
self.assertEqual(layout.id_of["n4"], 4)
|
||||
self.assertEqual(layout.id_of["n5"], 5)
|
||||
self.assertEqual(layout.num_neurons, 2)
|
||||
self.assertEqual(layout.n_out, 1)
|
||||
self.assertEqual(layout.n_total, 6) # 4 inputs + 2 neurons
|
||||
|
||||
def test_byte_exact_descriptor_and_edges_no_padding(self):
|
||||
# PARALLEL=2, n_conn=2 for both neurons -> n_conn_padded=2,
|
||||
# i.e. no padding edges at all: exactly matches the byte
|
||||
# layout hand-verified in sim/graph_format_tb.v.
|
||||
layout = assemble_graph(
|
||||
self.net, parallel=2, table_base=0x000000, edges_base=0x000100
|
||||
)
|
||||
|
||||
n4_edges_addr = 0x000100
|
||||
n5_edges_addr = 0x000100 + 8 # n4 has exactly 2 edges, 4 bytes each, no padding
|
||||
|
||||
expected_desc = bytes([
|
||||
# n4: conn_ptr, n_conn=2, out_id=4, act=RELU(1), bias=2, reserved
|
||||
(n4_edges_addr >> 16) & 0xFF, (n4_edges_addr >> 8) & 0xFF, n4_edges_addr & 0xFF,
|
||||
0x00, 0x02,
|
||||
0x00, 0x04,
|
||||
0x01,
|
||||
0x02,
|
||||
0x00, 0x00,
|
||||
# n5: conn_ptr, n_conn=2, out_id=5, act=NONE(0), bias=0, reserved
|
||||
(n5_edges_addr >> 16) & 0xFF, (n5_edges_addr >> 8) & 0xFF, n5_edges_addr & 0xFF,
|
||||
0x00, 0x02,
|
||||
0x00, 0x05,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, 0x00,
|
||||
])
|
||||
self.assertEqual(layout.descriptor_bytes, expected_desc)
|
||||
|
||||
expected_n4_edges = bytes([
|
||||
0x00, 0x00, 0x05, 0x00, # src=0, w=5
|
||||
0x00, 0x01, (-3) & 0xFF, 0x00, # src=1, w=-3
|
||||
])
|
||||
expected_n5_edges = bytes([
|
||||
0x00, 0x04, 0x02, 0x00, # src=4 (n4), w=2
|
||||
0x00, 0x02, 0x07, 0x00, # src=2, w=7
|
||||
])
|
||||
self.assertEqual(layout.edge_bytes["n4"], expected_n4_edges)
|
||||
self.assertEqual(layout.edge_bytes["n5"], expected_n5_edges)
|
||||
|
||||
def test_parallel_padding(self):
|
||||
# Same graph, PARALLEL=4 -> n_conn=2 pads to 4 (2 extra
|
||||
# zero-weight, src=0 edges per neuron), as exercised end to
|
||||
# end in sim/graph_engine_tb.v.
|
||||
layout = assemble_graph(self.net, parallel=4, max_conn=8)
|
||||
self.assertEqual(layout.n_conn_padded["n4"], 4)
|
||||
self.assertEqual(layout.n_conn_padded["n5"], 4)
|
||||
self.assertEqual(len(layout.edge_bytes["n4"]), 16)
|
||||
# padding tail is (src=0, w=0, reserved=0)
|
||||
self.assertEqual(layout.edge_bytes["n4"][8:], bytes(8))
|
||||
self.assertEqual(layout.edge_bytes["n5"][8:], bytes(8))
|
||||
# descriptor's n_conn is the REAL count, not padded (§4.2)
|
||||
self.assertEqual(layout.descriptor_bytes[3:5], bytes([0x00, 0x02]))
|
||||
|
||||
def test_zero_conn_neuron_still_pads_to_one_group(self):
|
||||
src = (
|
||||
"NET graph\nINPUTS 2\n"
|
||||
"NEURON n2 none bias=5\nOUTPUT n2\nEND\n"
|
||||
)
|
||||
net = parse(src)
|
||||
layout = assemble_graph(net, parallel=4, max_conn=8)
|
||||
self.assertEqual(layout.n_conn_padded["n2"], 4)
|
||||
|
||||
def test_frames_sequence(self):
|
||||
layout = assemble_graph(self.net, parallel=2)
|
||||
labels = [fr.label.split("(")[0] for fr in layout.frames]
|
||||
self.assertEqual(
|
||||
labels,
|
||||
[
|
||||
"WRITE_RAM", # table
|
||||
"WRITE_RAM", # n4 edges
|
||||
"WRITE_RAM", # n5 edges
|
||||
"SET_NET_TYPE",
|
||||
"SET_BASE", # x_base
|
||||
"SET_BASE", # table_base
|
||||
"SET_BASE", # out_base (buf_a_base)
|
||||
"SET_BASE", # n_inputs_real (N_in)
|
||||
"SET_BASE", # num_neurons_graph
|
||||
"SET_BASE", # n_out
|
||||
"RUN_NETWORK",
|
||||
],
|
||||
)
|
||||
run_frame = layout.frames[-1]
|
||||
self.assertEqual(run_frame.data[0], F.OP_RUN_NETWORK)
|
||||
|
||||
# ---- compile-time guard tests (mirrors sim/graph_engine_guard_tb.v) ----
|
||||
|
||||
def test_self_reference_rejected(self):
|
||||
# n1 references itself; n2 (not n1) is the actual OUTPUT, so
|
||||
# this isolates the src_id < out_id check from the separate
|
||||
# "output used as source" check below.
|
||||
src = (
|
||||
"NET graph\nINPUTS 1\n"
|
||||
"NEURON n1 relu bias=0\n CONN n1 w=1\n"
|
||||
"NEURON n2 relu bias=0\n CONN 0 w=1\n"
|
||||
"OUTPUT n2\nEND\n"
|
||||
)
|
||||
net = parse(src)
|
||||
with self.assertRaisesRegex(NetasmError, "not a strictly earlier signal"):
|
||||
assemble_graph(net, parallel=2)
|
||||
|
||||
def test_forward_reference_rejected(self):
|
||||
# n1 references n2, declared AFTER it; n3 (not n2) is the
|
||||
# actual OUTPUT, so n2 is an ordinary (non-output) neuron and
|
||||
# this isolates the src_id < out_id check from "output used
|
||||
# as source" below.
|
||||
src = (
|
||||
"NET graph\nINPUTS 1\n"
|
||||
"NEURON n1 relu bias=0\n CONN n2 w=1\n"
|
||||
"NEURON n2 relu bias=0\n CONN 0 w=1\n"
|
||||
"NEURON n3 relu bias=0\n CONN n1 w=1\n"
|
||||
"OUTPUT n3\nEND\n"
|
||||
)
|
||||
net = parse(src)
|
||||
with self.assertRaisesRegex(NetasmError, "not a strictly earlier signal"):
|
||||
assemble_graph(net, parallel=2)
|
||||
|
||||
def test_output_used_as_source_rejected(self):
|
||||
src = (
|
||||
"NET graph\nINPUTS 2\n"
|
||||
"NEURON n2 relu bias=0\n CONN 0 w=1\n"
|
||||
"NEURON n3 relu bias=0\n CONN n2 w=1\n"
|
||||
"OUTPUT n2\nOUTPUT n3\nEND\n"
|
||||
)
|
||||
net = parse(src)
|
||||
with self.assertRaisesRegex(NetasmError, "used as a source"):
|
||||
assemble_graph(net, parallel=2)
|
||||
|
||||
def test_max_conn_overflow_rejected(self):
|
||||
conns = "\n".join(f" CONN 0 w=1" for _ in range(10))
|
||||
src = f"NET graph\nINPUTS 1\nNEURON n1 relu bias=0\n{conns}\nOUTPUT n1\nEND\n"
|
||||
net = parse(src)
|
||||
with self.assertRaisesRegex(NetasmError, "MAX_CONN"):
|
||||
assemble_graph(net, parallel=4, max_conn=8) # 10 conns pad to 12 > 8
|
||||
|
||||
def test_n_total_overflow_rejected(self):
|
||||
layout_ok = assemble_graph(self.net, parallel=2, n_total=6) # exactly fits
|
||||
self.assertEqual(layout_ok.n_total, 6)
|
||||
with self.assertRaisesRegex(NetasmError, "N_TOTAL"):
|
||||
assemble_graph(self.net, parallel=2, n_total=5)
|
||||
|
||||
def test_undeclared_output_rejected(self):
|
||||
src = "NET graph\nINPUTS 1\nNEURON n1 relu bias=0\n CONN 0 w=1\nOUTPUT ghost\nEND\n"
|
||||
net = parse(src)
|
||||
with self.assertRaisesRegex(NetasmError, "undeclared"):
|
||||
assemble_graph(net, parallel=2)
|
||||
|
||||
|
||||
class TestDenseAssembler(unittest.TestCase):
|
||||
def test_layout_and_descriptor(self):
|
||||
src = "NET dense\nINPUTS 8\nLAYER 4 relu\nLAYER 2 none\nEND\n"
|
||||
net = parse(src)
|
||||
layout = assemble_dense(net, parallel=4, table_base=0, weights_base=0x1000)
|
||||
|
||||
self.assertEqual(layout.layers[0].n_inputs_real, 8)
|
||||
self.assertEqual(layout.layers[0].n_neurons_real, 4)
|
||||
self.assertEqual(layout.layers[1].n_inputs_real, 4)
|
||||
self.assertEqual(layout.layers[1].n_neurons_real, 2)
|
||||
|
||||
# layer0: w_base at weights_base, 8*4=32 bytes, then bias 4 bytes
|
||||
self.assertEqual(layout.layers[0].w_base, 0x1000)
|
||||
self.assertEqual(layout.layers[0].bias_addr, 0x1000 + 32)
|
||||
# layer1 follows immediately after layer0's bias region
|
||||
self.assertEqual(layout.layers[1].w_base, 0x1000 + 32 + 4)
|
||||
|
||||
self.assertEqual(len(layout.descriptor_bytes), 11 * 2)
|
||||
|
||||
def test_non_multiple_of_parallel_rejected(self):
|
||||
src = "NET dense\nINPUTS 6\nLAYER 4 relu\nEND\n" # 6 not a multiple of 4
|
||||
net = parse(src)
|
||||
with self.assertRaisesRegex(NetasmError, "PARALLEL"):
|
||||
assemble_dense(net, parallel=4)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
unittest.main()
|
||||
@@ -1,116 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
"""
|
||||
Generates synth/ecp5/spi_neuron_top.lpf (LOCATE/IOBUF constraints) for
|
||||
spi_neuron_top's SPI + PSRAM ports on the real LFE5U-45F-8BG381C part,
|
||||
using Project Trellis's own device database as the source of ball/bank/
|
||||
dual-function data (the same data nextpnr-ecp5 itself uses) -- not
|
||||
invented numbers.
|
||||
|
||||
Requires prjtrellis installed (Homebrew: `brew install prjtrellis`) and
|
||||
its iodb.json for LFE5U-45F. See docs/FPGA-Neural-Hardware-Design.md §7
|
||||
for the full placement rationale (bank/die-edge geometry, why banks 2+3
|
||||
hold the PSRAM bus and bank 7 holds SPI/clock/reset).
|
||||
|
||||
Re-run this whenever the port list of rtl/spi_neuron_top.v's top-level
|
||||
SPI/PSRAM interface changes (ADDR_WIDTH, MEM_DATA_WIDTH, etc.) -- it does
|
||||
NOT try to read the RTL; the port list/widths are hardcoded below and
|
||||
must be kept in sync by hand.
|
||||
"""
|
||||
|
||||
import json
|
||||
import re
|
||||
import glob
|
||||
import sys
|
||||
|
||||
CLK_BALL = "H5" # GR_PCLK7_0, bank 7 -- dedicated global clock pad
|
||||
ADDR_BITS = 23 # ADDR_WIDTH (byte address); only [21:0] carry real address, see §3
|
||||
DATA_BITS = 16 # MEM_DATA_WIDTH
|
||||
|
||||
def find_iodb():
|
||||
candidates = glob.glob(
|
||||
"/opt/homebrew/Cellar/prjtrellis/*/share/trellis/database/ECP5/LFE5U-45F/iodb.json"
|
||||
) + glob.glob(
|
||||
"/usr/share/trellis/database/ECP5/LFE5U-45F/iodb.json"
|
||||
)
|
||||
if not candidates:
|
||||
sys.exit("prjtrellis iodb.json not found -- install prjtrellis (brew install prjtrellis)")
|
||||
return candidates[0]
|
||||
|
||||
|
||||
def load_balls(iodb_path, package="CABGA381"):
|
||||
d = json.load(open(iodb_path))
|
||||
pkg = d["packages"][package]
|
||||
meta_idx = {}
|
||||
for m in d["pio_metadata"]:
|
||||
meta_idx.setdefault((m["col"], m["row"], m["pio"]), []).append(m)
|
||||
out = {}
|
||||
for ball, info in pkg.items():
|
||||
key = (info["col"], info["row"], info["pio"])
|
||||
metas = meta_idx.get(key, [])
|
||||
bank = metas[0]["bank"] if metas else None
|
||||
funcs = sorted(set(m.get("function", "") for m in metas if m.get("function")))
|
||||
out[ball] = dict(col=info["col"], row=info["row"], bank=bank, funcs=funcs)
|
||||
return out
|
||||
|
||||
|
||||
def bank_balls(rows, bank, exclude=()):
|
||||
items = [(b, v) for b, v in rows.items() if v["bank"] == bank and b not in exclude]
|
||||
plain = sorted((x for x in items if not x[1]["funcs"]), key=lambda x: (x[1]["row"], x[1]["col"], x[0]))
|
||||
special = sorted((x for x in items if x[1]["funcs"]), key=lambda x: (x[1]["row"], x[1]["col"], x[0]))
|
||||
return plain + special
|
||||
|
||||
|
||||
def assign(rows):
|
||||
psram_pool = bank_balls(rows, 2) + bank_balls(rows, 3)
|
||||
ctrl_pool = bank_balls(rows, 7, exclude={CLK_BALL})
|
||||
|
||||
a = {}
|
||||
for i, (ball, _) in enumerate(psram_pool[0:ADDR_BITS - 1]):
|
||||
a[f"psram_a[{i}]"] = ball
|
||||
for i, (ball, _) in enumerate(psram_pool[ADDR_BITS - 1:ADDR_BITS - 1 + DATA_BITS]):
|
||||
a[f"psram_dq[{i}]"] = ball
|
||||
ctrl_names = ["psram_ce_n", "psram_oe_n", "psram_we_n", "psram_lb_n", "psram_ub_n", "psram_zz_n"]
|
||||
for name, (ball, _) in zip(ctrl_names, psram_pool[ADDR_BITS - 1 + DATA_BITS:ADDR_BITS - 1 + DATA_BITS + 6]):
|
||||
a[name] = ball
|
||||
a[f"psram_a[{ADDR_BITS - 1}]"] = psram_pool[ADDR_BITS - 1 + DATA_BITS + 6][0] # always-0 spare bit
|
||||
|
||||
# Application SPI + reset + host attention pins (irq_n/data_ready_n,
|
||||
# added 2026-09-03), all in bank 7 alongside clk -- kept away from
|
||||
# the PSRAM bus (banks 2+3) per the same "opposite edges" rationale
|
||||
# as the SPI signals. flash_sclk/flash_mosi/flash_miso/flash_cs_n
|
||||
# (added 2026-09-04, revised same day to drop the USRMCLK/CCLK
|
||||
# coupling -- see rtl/spi_flash_master.v's header) join the same
|
||||
# pool for the same reason -- this is a fully independent,
|
||||
# ordinary-GPIO SPI bus toward the boot/persistence flash
|
||||
# (rtl/spi_flash_master.v), physically distinct from both the host
|
||||
# SPI above and the dedicated config-SPI pins (never touched by
|
||||
# user logic, see docs/FPGA-Neural-Hardware-Design.md §6). No pin
|
||||
# is shared with any ECP5 config primitive.
|
||||
# flash_sclk appended LAST (not inserted among the other flash
|
||||
# signals) so this regeneration stays additive: flash_mosi/
|
||||
# flash_miso/flash_cs_n keep the exact balls already committed to
|
||||
# the datasheet/schematic notes, only one genuinely new ball is
|
||||
# allocated for flash_sclk.
|
||||
spi_names = ["sclk", "mosi", "miso", "cs_n", "rst", "irq_n", "data_ready_n",
|
||||
"flash_mosi", "flash_miso", "flash_cs_n", "flash_sclk"]
|
||||
for name, (ball, _) in zip(spi_names, ctrl_pool[0:11]):
|
||||
a[name] = ball
|
||||
a["clk"] = CLK_BALL
|
||||
return a
|
||||
|
||||
|
||||
def write_lpf(assignment, path):
|
||||
lines = ["BLOCK ASYNCPATHS;", "BLOCK RESETPATHS;", ""]
|
||||
for sig, ball in sorted(assignment.items()):
|
||||
lines.append(f'LOCATE COMP "{sig}" SITE "{ball}";')
|
||||
lines.append(f'IOBUF PORT "{sig}" IO_TYPE=LVCMOS33;')
|
||||
lines.append("")
|
||||
open(path, "w").write("\n".join(lines))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
out_path = sys.argv[1] if len(sys.argv) > 1 else "synth/ecp5/spi_neuron_top.lpf"
|
||||
rows = load_balls(find_iodb())
|
||||
assignment = assign(rows)
|
||||
write_lpf(assignment, out_path)
|
||||
print(f"wrote {len(assignment)} signal constraints to {out_path}")
|
||||
@@ -1,175 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
"""
|
||||
Fase 0 (docs/validation/00-inventario.md) regression runner.
|
||||
|
||||
No such script existed in the repo before this -- every prior "N testbenches,
|
||||
all pass" claim in WORKLOG.md was produced by manually assembling per-test
|
||||
iverilog command lines, never re-run from a single reproducible harness. This
|
||||
script builds the module dependency graph directly from the source (regex
|
||||
over instantiation sites), not from memory/WORKLOG claims, then compiles and
|
||||
runs every sim/*_tb.v fresh with `iverilog -g2012` + `vvp`.
|
||||
|
||||
Usage: python3 tools/run_regression.py [--keep] [pattern]
|
||||
--keep keep the compiled .out files in /tmp/regression (default: cleaned)
|
||||
pattern only run testbenches whose filename contains this substring
|
||||
"""
|
||||
import glob
|
||||
import os
|
||||
import re
|
||||
import subprocess
|
||||
import sys
|
||||
import tempfile
|
||||
|
||||
REPO = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
|
||||
|
||||
# Testbenches that are DELIBERATELY meant to fail elaboration (they verify a
|
||||
# compile-time guard by trying to violate it -- see each file's own header
|
||||
# comment for the citation). A naive PASS/FAIL-marker scan misclassifies
|
||||
# these as broken; confirmed by reading the source, not assumed.
|
||||
EXPECTED_COMPILE_FAIL = {
|
||||
"neuron_parallel_guard_negative_degenerate",
|
||||
"neuron_parallel_guard_negative_nonmultiple",
|
||||
"neuron_parallel_bug002_n_inputs_zero",
|
||||
}
|
||||
# Benchmarks: print measured numbers, no PASS/FAIL verdict by design (see
|
||||
# each file's own header -- same category as sim/flash_latency_bench.v,
|
||||
# which isn't even named *_tb.v and so isn't picked up by this glob at all,
|
||||
# an inconsistent naming convention worth flagging in the inventory).
|
||||
BENCHMARK_NO_VERDICT = {
|
||||
"graph_engine_bandwidth",
|
||||
}
|
||||
|
||||
# Every module-defining file under rtl/ and the sim/ behavioral models used
|
||||
# as test doubles (flash_model.v, psram_model.v) -- sim/top.v is EXCLUDED
|
||||
# deliberately: it's dead code (references a FRAC_BITS parameter that no
|
||||
# longer exists on neuron_parallel.v, confirmed failing to elaborate on its
|
||||
# own, see docs/validation/00-inventario.md).
|
||||
SOURCE_FILES = sorted(
|
||||
glob.glob(os.path.join(REPO, "rtl", "*.v"))
|
||||
+ [os.path.join(REPO, "sim", "flash_model.v"), os.path.join(REPO, "sim", "psram_model.v")]
|
||||
)
|
||||
|
||||
MODULE_RE = re.compile(r"^\s*module\s+([A-Za-z_][A-Za-z0-9_]*)", re.MULTILINE)
|
||||
# Matches "modname instname (" or "modname #(" instantiation sites, not
|
||||
# "module modname" definitions and not plain calls/keywords.
|
||||
INST_RE = re.compile(
|
||||
r"^\s*([A-Za-z_][A-Za-z0-9_]*)\s+(?:#\s*\(|[A-Za-z_][A-Za-z0-9_]*\s*\()",
|
||||
re.MULTILINE,
|
||||
)
|
||||
KEYWORDS = {
|
||||
"if", "else", "for", "while", "case", "begin", "end", "assign", "wire",
|
||||
"reg", "input", "output", "inout", "parameter", "localparam", "function",
|
||||
"task", "always", "initial", "module", "endmodule", "generate",
|
||||
"endgenerate", "genvar", "integer", "real", "signed", "unsigned",
|
||||
}
|
||||
|
||||
def module_defined_in(path):
|
||||
txt = open(path, encoding="utf-8", errors="replace").read()
|
||||
return MODULE_RE.findall(txt)
|
||||
|
||||
def instantiated_modules(path):
|
||||
txt = open(path, encoding="utf-8", errors="replace").read()
|
||||
found = set(INST_RE.findall(txt)) - KEYWORDS
|
||||
return found
|
||||
|
||||
def build_module_map():
|
||||
m = {}
|
||||
for f in SOURCE_FILES:
|
||||
for name in module_defined_in(f):
|
||||
m.setdefault(name, f)
|
||||
return m
|
||||
|
||||
def resolve_deps(tb_path, module_map):
|
||||
needed_files = {tb_path}
|
||||
frontier = instantiated_modules(tb_path)
|
||||
seen_files = set()
|
||||
while frontier:
|
||||
mod = frontier.pop()
|
||||
if mod not in module_map:
|
||||
continue
|
||||
f = module_map[mod]
|
||||
if f in needed_files:
|
||||
continue
|
||||
needed_files.add(f)
|
||||
if f in seen_files:
|
||||
continue
|
||||
seen_files.add(f)
|
||||
frontier |= instantiated_modules(f)
|
||||
return sorted(needed_files)
|
||||
|
||||
def main():
|
||||
keep = "--keep" in sys.argv
|
||||
args = [a for a in sys.argv[1:] if a != "--keep"]
|
||||
pattern = args[0] if args else ""
|
||||
|
||||
module_map = build_module_map()
|
||||
tbs = sorted(glob.glob(os.path.join(REPO, "sim", "*_tb.v")))
|
||||
tbs = [t for t in tbs if pattern in os.path.basename(t)]
|
||||
|
||||
results = []
|
||||
workdir = tempfile.mkdtemp(prefix="regression_")
|
||||
for tb in tbs:
|
||||
name = os.path.basename(tb)[:-len("_tb.v")]
|
||||
files = resolve_deps(tb, module_map)
|
||||
out = os.path.join(workdir, name + ".out")
|
||||
cc = subprocess.run(
|
||||
["iverilog", "-g2012", "-o", out] + files,
|
||||
cwd=REPO, capture_output=True, text=True,
|
||||
)
|
||||
if cc.returncode != 0:
|
||||
if name in EXPECTED_COMPILE_FAIL:
|
||||
results.append((name, "PASS (compile-time guard fired as designed)", cc.stderr.strip().splitlines()[-2:], files))
|
||||
else:
|
||||
results.append((name, "COMPILE_FAIL", cc.stderr.strip(), files))
|
||||
continue
|
||||
elif name in EXPECTED_COMPILE_FAIL:
|
||||
results.append((name, "FAIL (was expected to NOT compile, but it compiled)", [], files))
|
||||
continue
|
||||
run = subprocess.run(["vvp", out], cwd=REPO, capture_output=True, text=True, timeout=120)
|
||||
combined = run.stdout + run.stderr
|
||||
low = combined.lower()
|
||||
if name in BENCHMARK_NO_VERDICT:
|
||||
status = "BENCHMARK (no pass/fail verdict by design)" if run.returncode == 0 else f"RUNTIME_ERROR(rc={run.returncode})"
|
||||
elif "fail" in low and "PASSED" not in combined and "PASS" not in combined:
|
||||
status = "FAIL"
|
||||
elif run.returncode != 0:
|
||||
status = f"RUNTIME_ERROR(rc={run.returncode})"
|
||||
elif "PASSED" in combined or "PASS" in combined or "ALL TESTS" in combined:
|
||||
status = "PASS"
|
||||
else:
|
||||
status = "UNKNOWN (no PASS/FAIL marker found)"
|
||||
results.append((name, status, combined.strip().splitlines()[-3:], files))
|
||||
|
||||
print(f"{'TESTBENCH':45s} {'RESULT'}")
|
||||
print("-" * 70)
|
||||
n_pass = n_fail = n_other = 0
|
||||
for name, status, tail, files in results:
|
||||
print(f"{name:45s} {status}")
|
||||
if status.startswith("PASS"):
|
||||
n_pass += 1
|
||||
elif status.startswith("BENCHMARK"):
|
||||
n_other += 1
|
||||
for line in (tail if isinstance(tail, list) else [tail]):
|
||||
print(f" | {line}")
|
||||
elif status.startswith("FAIL") or status.startswith("COMPILE_FAIL") or status.startswith("RUNTIME_ERROR"):
|
||||
n_fail += 1
|
||||
for line in (tail if isinstance(tail, list) else [tail]):
|
||||
print(f" | {line}")
|
||||
else:
|
||||
n_other += 1
|
||||
for line in (tail if isinstance(tail, list) else [tail]):
|
||||
print(f" | {line}")
|
||||
|
||||
print("-" * 70)
|
||||
print(f"TOTAL: {len(results)} PASS: {n_pass} FAIL/ERROR: {n_fail} OTHER/UNKNOWN: {n_other}")
|
||||
|
||||
if not keep:
|
||||
import shutil
|
||||
shutil.rmtree(workdir, ignore_errors=True)
|
||||
else:
|
||||
print(f"Compiled binaries kept in {workdir}")
|
||||
|
||||
sys.exit(1 if (n_fail or n_other) else 0)
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@@ -1,313 +0,0 @@
|
||||
010102010000000000000003
|
||||
01010201000003e8000003eb
|
||||
02010101000003e8000003eb
|
||||
bd4be50f0018cd950018b85f
|
||||
ff7afec3ffe201f6ffe201f6
|
||||
0a733a08ffefd14affefd798
|
||||
0cc49dadfff87fccfff89d15
|
||||
1d9b7be4000dc1da000da8f5
|
||||
518e08db0006102e0005eaf4
|
||||
020873adffe94b82ffe92649
|
||||
4586613effe49f1fffe495bb
|
||||
5dc3db5efffb7993fffb55d4
|
||||
000d8ec2ffe7b08bffe7cc27
|
||||
6a2d0d24ffff2aeeffff3f64
|
||||
9fdb2eeefffd2e32fffd38fb
|
||||
60e536130005083e00050220
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
98d4b1300000c8ee0000cbfe
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
667a3b760000eb8f0001375d
|
||||
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|
||||
60be22ba0005dc600005ba54
|
||||
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|
||||
2e56624300007ae20000a3fc
|
||||
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|
||||
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|
||||
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|
||||
a8e6ebadfff8c48ffff8d44e
|
||||
5fa08676fffc382cfffbdc50
|
||||
53e41748000a084b000a05af
|
||||
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|
||||
71eb5c63001072fa00108d49
|
||||
6fabe1a0ffea6066ffea472b
|
||||
a71a8387000f27ef000f59fa
|
||||
4e1173f2001a5d5f001a5c43
|
||||
29b8b1470004b00300048e92
|
||||
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|
||||
3b77d220fffbe3dbfffbf988
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
7279f2e600177a630017b1b1
|
||||
8fb5eb02000a150b000a35fc
|
||||
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|
||||
e018796700012509000152b8
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
a470fb25ffe95c3dffe93344
|
||||
7ac9d65e0008739a000849f8
|
||||
3e9b54bb000e8812000e58f8
|
||||
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|
||||
53718c9d00072b4f00077cce
|
||||
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|
||||
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|
||||
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|
||||
541bdc500014c30a0014c0a6
|
||||
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|
||||
7f70d3bb000c6d70000cb121
|
||||
d8a0830ffff605ebfff60d98
|
||||
e8f75f56ffeb152affeb35ec
|
||||
b2116cd8ffe82a97ffe81489
|
||||
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|
||||
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|
||||
05eefe06fffd2a9efffd2a38
|
||||
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|
||||
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|
||||
c839475afffaeea7fffafb25
|
||||
1eb92900ffebe60cffebddba
|
||||
3387b1eaffffbcbeffffab6d
|
||||
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|
||||
37c0abaefff16e10fff17b8a
|
||||
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|
||||
0608f0a9001aa3bc001aa95c
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
cb59e67c0010e45f0010c55a
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
807f807f400000003fff8100
|
||||
80808080c0000000c0008000
|
||||
807f807fc0000000bfff8100
|
||||
@@ -1,313 +0,0 @@
|
||||
0101020103010401050106010701080109010a010b010c010d010e010f0110011101120113011401150116011701180119011a011b011c011d011e011f0120010000000000000210
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||||
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||||
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|
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|
||||
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|
||||
@@ -1,81 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
"""
|
||||
Independent Python oracle for rtl/mac_unit.v and rtl/mac8.v (aspect C.1 of
|
||||
the re-certification campaign, docs/validation/01-datapath.md).
|
||||
|
||||
Deliberately reimplements the arithmetic from first principles (two's
|
||||
complement wraparound, sign extension) -- NOT by reading the Verilog and
|
||||
transcribing it. Every function below is checked against Python's own
|
||||
built-in arbitrary-precision integers, which have no width and cannot
|
||||
share a truncation/sign-extension bug with the RTL.
|
||||
|
||||
Run standalone to regenerate the golden vectors used by
|
||||
sim/mac_unit_tb.v / sim/mac8_tree_tb.v:
|
||||
python3 tools/validation/mac_oracle.py
|
||||
"""
|
||||
|
||||
def to_signed(val: int, width: int) -> int:
|
||||
"""Interpret the low `width` bits of `val` as two's complement."""
|
||||
val &= (1 << width) - 1
|
||||
if val >= (1 << (width - 1)):
|
||||
val -= (1 << width)
|
||||
return val
|
||||
|
||||
def to_unsigned(val: int, width: int) -> int:
|
||||
return val & ((1 << width) - 1)
|
||||
|
||||
def mac_unit(x: int, w: int, acc_in: int, data_width: int = 8, acc_width: int = 32) -> int:
|
||||
"""Bit-exact model of rtl/mac_unit.v: acc_out = acc_in + sign_extend(x*w)."""
|
||||
assert -(1 << (data_width - 1)) <= x < (1 << (data_width - 1))
|
||||
assert -(1 << (data_width - 1)) <= w < (1 << (data_width - 1))
|
||||
product = x * w # Python int, exact, no width -- the whole point of an independent oracle
|
||||
prod_width = 2 * data_width
|
||||
assert -(1 << (prod_width - 1)) <= product < (1 << (prod_width - 1)), \
|
||||
"product overflowed PROD_WIDTH -- data_width assumption violated"
|
||||
raw = to_unsigned(acc_in, acc_width) + to_unsigned(product, prod_width if product >= 0 else prod_width)
|
||||
# acc_in + sign_extend(product) computed directly in signed arithmetic,
|
||||
# then wrapped to acc_width bits (matches Verilog's silent wraparound
|
||||
# on a fixed-width signed reg/wire -- confirmed intentional, not a
|
||||
# bug, because callers rely on it: see docs/validation/01-datapath.md).
|
||||
return to_signed(acc_in + product, acc_width)
|
||||
|
||||
def mac8_tree(products: list[int], acc_in: int, acc_width: int = 32) -> int:
|
||||
"""
|
||||
Bit-exact model of rtl/mac8.v's balanced binary adder tree +
|
||||
final accumulator add. `products` must have length PARALLEL (a power
|
||||
of two, matching the RTL's $clog2-based tree construction).
|
||||
"""
|
||||
n = len(products)
|
||||
assert n > 0 and (n & (n - 1)) == 0, "PARALLEL must be a power of two"
|
||||
level = list(products)
|
||||
while len(level) > 1:
|
||||
level = [to_signed(level[i] + level[i + 1], acc_width) for i in range(0, len(level), 2)]
|
||||
return to_signed(acc_in + level[0], acc_width)
|
||||
|
||||
def mac8_full(x_vals: list[int], w_vals: list[int], acc_in: int,
|
||||
data_width: int = 8, acc_width: int = 32) -> int:
|
||||
"""End-to-end oracle: PARALLEL independent products -> balanced tree -> + acc_in."""
|
||||
assert len(x_vals) == len(w_vals)
|
||||
products = [mac_unit(x, w, 0, data_width, acc_width) for x, w in zip(x_vals, w_vals)]
|
||||
return mac8_tree(products, acc_in, acc_width)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
# Self-check: a handful of hand-verifiable cases, printed for a human
|
||||
# to eyeball before trusting this file as an oracle for anything else.
|
||||
cases = [
|
||||
(5, 7, 0, 35),
|
||||
(-128, -128, 0, 16384), # the one INT8 x INT8 case that does NOT fit in INT16 magnitude terms symmetrically
|
||||
(127, 127, 0, 16129),
|
||||
(-128, 127, 0, -16256),
|
||||
(0, 0, 0, 0),
|
||||
(-1, -1, 0, 1),
|
||||
]
|
||||
ok = True
|
||||
for x, w, acc_in, expected in cases:
|
||||
got = mac_unit(x, w, acc_in)
|
||||
status = "OK" if got == expected else "MISMATCH"
|
||||
if got != expected:
|
||||
ok = False
|
||||
print(f"mac_unit(x={x}, w={w}, acc_in={acc_in}) = {got} (expected {expected}) {status}")
|
||||
print("ALL SELF-CHECKS PASSED" if ok else "SELF-CHECK FAILURE -- oracle itself is wrong, fix before using it")
|
||||
@@ -1,486 +0,0 @@
|
||||
bde50000000000000711
|
||||
4b0f0000000000000465
|
||||
fffe0000000000000002
|
||||
7ac300000000ffffe2ee
|
||||
840a00000000fffffb28
|
||||
3a730000000000001a0e
|
||||
08f200000000ffffff90
|
||||
0c9d00000000fffffb5c
|
||||
c4ad0000000000001374
|
||||
381d0000000000000658
|
||||
7b9b00000000ffffcf79
|
||||
e45100000000fffff724
|
||||
088e00000000fffffc70
|
||||
db0200000000ffffffb6
|
||||
73080000000000000398
|
||||
adbe0000000000001566
|
||||
45610000000000001a25
|
||||
863e00000000ffffe274
|
||||
995d00000000ffffda95
|
||||
dbc300000000000008d1
|
||||
5e4f0000000000001d02
|
||||
008e0000000000000000
|
||||
0dc200000000fffffcda
|
||||
b16a00000000ffffdf4a
|
||||
0d2d0000000000000249
|
||||
246d0000000000000f54
|
||||
9f2e00000000ffffee92
|
||||
dbee000000000000029a
|
||||
5d6000000000000022e0
|
||||
36e500000000fffffa4e
|
||||
13fc00000000ffffffb4
|
||||
4fbe00000000ffffeba2
|
||||
a5c300000000000015af
|
||||
14460000000000000578
|
||||
688e00000000ffffd1b0
|
||||
ecc60000000000000488
|
||||
c7d800000000000008e8
|
||||
c47200000000ffffe548
|
||||
629000000000ffffd520
|
||||
197d0000000000000c35
|
||||
36df00000000fffff90a
|
||||
25600000000000000de0
|
||||
aa6c00000000ffffdbb8
|
||||
d4a90000000000000ef4
|
||||
9a5600000000ffffddbc
|
||||
df890000000000000f57
|
||||
f5f80000000000000058
|
||||
ba4a00000000ffffebc4
|
||||
398400000000ffffe464
|
||||
c11600000000fffffa96
|
||||
f8cd0000000100000199
|
||||
38d700000001fffff709
|
||||
bf7c00000001ffffe085
|
||||
801100000001fffff781
|
||||
7dec00000001fffff63d
|
||||
923d00000001ffffe5cb
|
||||
32e700000001fffffb1f
|
||||
239600000001fffff183
|
||||
3d750000000100001be2
|
||||
86d80000000100001311
|
||||
374b000000010000101e
|
||||
2a540000000100000dc9
|
||||
43c600000001fffff0d3
|
||||
8eff0000000100000073
|
||||
bc0100000001ffffffbd
|
||||
479100000001ffffe138
|
||||
5a8900000001ffffd62b
|
||||
bea800000001000016b1
|
||||
32c400000001fffff449
|
||||
55b700000001ffffe7c4
|
||||
5f7b0000000100002da6
|
||||
d06800000001ffffec81
|
||||
764e00000001000023f5
|
||||
dd5600000001fffff43f
|
||||
42400000000100001081
|
||||
9f5000000001ffffe1b1
|
||||
41ca00000001fffff24b
|
||||
178800000001fffff539
|
||||
c9a800000001000012e9
|
||||
57c800000001ffffecf9
|
||||
6f3d0000000100001a74
|
||||
36aa00000001ffffeddd
|
||||
99e00000000100000ce1
|
||||
59220000000100000bd3
|
||||
50a600000001ffffe3e1
|
||||
990100000001ffffff9a
|
||||
d7ae0000000100000d23
|
||||
a84500000001ffffe849
|
||||
8fa7000000010000274a
|
||||
850a00000001fffffb33
|
||||
21750000000100000f16
|
||||
51b400000001ffffe7f5
|
||||
bd1800000001fffff9b9
|
||||
e8fc0000000100000061
|
||||
0726000000010000010b
|
||||
8d0e00000001fffff9b7
|
||||
ce6f00000001ffffea53
|
||||
f2f300000001000000b7
|
||||
123c0000000100000439
|
||||
244700000001000009fd
|
||||
49e8fffffffffffff927
|
||||
3e1affffffff0000064b
|
||||
90baffffffff00001e9f
|
||||
a68effffffff00002813
|
||||
0673ffffffff000002b1
|
||||
4607ffffffff000001e9
|
||||
cfdfffffffff00000650
|
||||
ea01ffffffffffffffe9
|
||||
675effffffff000025d1
|
||||
57effffffffffffffa38
|
||||
db48fffffffffffff597
|
||||
4dd0fffffffffffff18f
|
||||
a1e0ffffffff00000bdf
|
||||
9018fffffffffffff57f
|
||||
4ebfffffffffffffec31
|
||||
1a74ffffffff00000bc7
|
||||
4d90ffffffffffffde4f
|
||||
0cc5fffffffffffffd3b
|
||||
43bdffffffffffffee76
|
||||
c45affffffffffffeae7
|
||||
fa82ffffffff000002f3
|
||||
d323fffffffffffff9d8
|
||||
518affffffffffffdaa9
|
||||
cc02ffffffffffffff97
|
||||
a9e5ffffffff0000092c
|
||||
9c2affffffffffffef97
|
||||
00eeffffffffffffffff
|
||||
f9f2ffffffff00000061
|
||||
2665ffffffff00000efd
|
||||
2de2fffffffffffffab9
|
||||
e877fffffffffffff4d7
|
||||
3c86ffffffffffffe367
|
||||
96c0ffffffff00001a7f
|
||||
b7d3ffffffff00000cd4
|
||||
1a34ffffffff00000547
|
||||
1551ffffffff000006a4
|
||||
86e4ffffffff00000d57
|
||||
25edfffffffffffffd40
|
||||
286dffffffff00001107
|
||||
8172ffffffffffffc771
|
||||
8dc3ffffffff00001b66
|
||||
5614ffffffff000006b7
|
||||
9ac1ffffffff00001919
|
||||
8fc6ffffffff00001999
|
||||
6656ffffffff00002243
|
||||
fdd8ffffffff00000077
|
||||
8b8cffffffff00003503
|
||||
2b89ffffffffffffec02
|
||||
da53fffffffffffff3ad
|
||||
0761ffffffff000002a6
|
||||
bdd17fffffff80000c4c
|
||||
23b37fffffff7ffff578
|
||||
be087fffffff7ffffdef
|
||||
226a7fffffff80000e13
|
||||
a34e7fffffff7fffe3a9
|
||||
16a27fffffff7ffff7eb
|
||||
e8e57fffffff80000287
|
||||
a5187fffffff7ffff777
|
||||
dd067fffffff7fffff2d
|
||||
b6cc7fffffff80000f07
|
||||
010f7fffffff8000000e
|
||||
f0da7fffffff8000025f
|
||||
e18b7fffffff80000e2a
|
||||
f8067fffffff7fffffcf
|
||||
f9747fffffff7ffffcd3
|
||||
a02c7fffffff7fffef7f
|
||||
d1dd7fffffff8000066c
|
||||
1d707fffffff80000caf
|
||||
67e67fffffff7ffff589
|
||||
6e9c7fffffff7fffd507
|
||||
e8be7fffffff8000062f
|
||||
22f77fffffff7ffffecd
|
||||
24647fffffff80000e0f
|
||||
6d747fffffff80003163
|
||||
d9ec7fffffff8000030b
|
||||
e7757fffffff7ffff492
|
||||
a4107fffffff7ffffa3f
|
||||
d4877fffffff800014cb
|
||||
68fb7fffffff7ffffdf7
|
||||
454c7fffffff8000147b
|
||||
42ad7fffffff7fffea99
|
||||
13857fffffff7ffff6de
|
||||
ddd47fffffff80000603
|
||||
c8dd7fffffff800007a7
|
||||
572c7fffffff80000ef3
|
||||
e4f57fffffff80000133
|
||||
10867fffffff7ffff85f
|
||||
e07b7fffffff7ffff09f
|
||||
e0877fffffff80000f1f
|
||||
8d3e7fffffff7fffe425
|
||||
5a057fffffff800001c1
|
||||
58be7fffffff7fffe94f
|
||||
1b287fffffff80000437
|
||||
8bbe7fffffff80001e29
|
||||
00c67fffffff7fffffff
|
||||
95b07fffffff8000216f
|
||||
280e7fffffff8000022f
|
||||
51857fffffff7fffd914
|
||||
047c7fffffff800001ef
|
||||
0d3a7fffffff800002f1
|
||||
cf68800000007fffec18
|
||||
9e008000000080000000
|
||||
9850800000007fffdf80
|
||||
cd0f800000007ffffd03
|
||||
27e2800000007ffffb6e
|
||||
a5e28000000080000aaa
|
||||
022e800000008000005c
|
||||
24b2800000007ffff508
|
||||
1cdc800000007ffffc10
|
||||
0fcc800000007ffffcf4
|
||||
fb7b800000007ffffd99
|
||||
ad4d800000007fffe709
|
||||
ed9780000000800007cb
|
||||
f78b800000008000041d
|
||||
be908000000080001ce0
|
||||
12d9800000007ffffd42
|
||||
5fde800000007ffff362
|
||||
8274800000007fffc6e8
|
||||
3f368000000080000d4a
|
||||
d7d4800000008000070c
|
||||
211580000000800002b5
|
||||
b88c80000000800020a0
|
||||
06cb800000007ffffec2
|
||||
f99380000000800002fb
|
||||
1092800000007ffff920
|
||||
08248000000080000120
|
||||
bcd98000000080000a5c
|
||||
defe8000000080000044
|
||||
ce7a800000007fffe82c
|
||||
98fe80000000800000d0
|
||||
e65b800000007ffff6c2
|
||||
38d5800000007ffff698
|
||||
e8e280000000800002d0
|
||||
db958000000080000f77
|
||||
ab988000000080002288
|
||||
b1d48000000080000d94
|
||||
307a80000000800016e0
|
||||
d23e800000007ffff4dc
|
||||
0d3c800000008000030c
|
||||
17bb800000007ffff9cd
|
||||
8cb9800000008000202c
|
||||
486d8000000080001ea8
|
||||
0d7d8000000080000659
|
||||
28e4800000007ffffba0
|
||||
376e80000000800017a2
|
||||
6695800000007fffd55e
|
||||
165f800000008000082a
|
||||
e4d08000000080000540
|
||||
e9ca80000000800004da
|
||||
c9818000000080001b49
|
||||
ac04400000003ffffeb0
|
||||
fbc94000000040000113
|
||||
f262400000003ffffaa4
|
||||
fc14400000003fffffb0
|
||||
7bc7400000003fffe49d
|
||||
7281400000003fffc772
|
||||
3a4b40000000400010fe
|
||||
93964000000040002d22
|
||||
1e9a400000003ffff40c
|
||||
80984000000040003400
|
||||
704f4000000040002290
|
||||
146640000000400007f8
|
||||
3b7a4000000040001c1e
|
||||
767b40000000400038b2
|
||||
f564400000003ffffbb4
|
||||
8251400000003fffd822
|
||||
2a604000000040000fc0
|
||||
22be400000003ffff73c
|
||||
bae740000000400006d6
|
||||
3ae3400000003ffff96e
|
||||
562e4000000040000f74
|
||||
625640000000400020ec
|
||||
43774000000040001f25
|
||||
7e3040000000400017a0
|
||||
8c39400000003fffe62c
|
||||
7a414000000040001efa
|
||||
e4ad4000000040000914
|
||||
5285400000003fffd89a
|
||||
ed8b40000000400008af
|
||||
67a8400000003fffdc98
|
||||
ebe64000000040000222
|
||||
ad3a400000003fffed32
|
||||
5f86400000003fffd2ba
|
||||
a076400000003fffd3c0
|
||||
55534000000040001b8f
|
||||
17e4400000003ffffd7c
|
||||
4895400000003fffe1e8
|
||||
b6cb4000000040000f52
|
||||
ac71400000003fffdaec
|
||||
5ceb400000003ffff874
|
||||
636f4000000040002aed
|
||||
e1ab4000000040000a4b
|
||||
a0c74000000040001560
|
||||
a7834000000040002b75
|
||||
1a87400000003ffff3b6
|
||||
4e73400000004000230a
|
||||
11f2400000003fffff12
|
||||
29b1400000003ffff359
|
||||
b847400000003fffec08
|
||||
dbd740000000400005ed
|
||||
1ce5c0000000bffffd0c
|
||||
343bc0000000c0000bfc
|
||||
d277c0000000bfffea9e
|
||||
2053c0000000c0000a60
|
||||
ff8ac0000000c0000076
|
||||
2be7c0000000bffffbcd
|
||||
b614c0000000bffffa38
|
||||
ad1cc0000000bffff6ec
|
||||
b8cbc0000000c0000ee8
|
||||
c1e9c0000000c00005a9
|
||||
f820c0000000bfffff00
|
||||
5f77c0000000c0002c29
|
||||
ca0ec0000000bffffd0c
|
||||
7291c0000000bfffce92
|
||||
f52cc0000000bffffe1c
|
||||
ea27c0000000bffffca6
|
||||
ecc9c0000000c000044c
|
||||
6b41c0000000c0001b2b
|
||||
0372c0000000c0000156
|
||||
f279c0000000bffff962
|
||||
e68fc0000000c0000b7a
|
||||
ebb5c0000000c0000627
|
||||
02d0c0000000bfffffa0
|
||||
af61c0000000bfffe14f
|
||||
2576c0000000c000110e
|
||||
e079c0000000bffff0e0
|
||||
1867c0000000c00009a8
|
||||
7dcfc0000000bfffe813
|
||||
ff68c0000000bfffff98
|
||||
b8bfc0000000c0001248
|
||||
da6ac0000000bffff044
|
||||
3958c0000000c0001398
|
||||
f1d1c0000000c00002c1
|
||||
44c5c0000000bffff054
|
||||
7d9ac0000000bfffce32
|
||||
5abcc0000000bfffe818
|
||||
a1efc0000000c000064f
|
||||
53e2c0000000bffff646
|
||||
85c1c0000000c0001e45
|
||||
15a4c0000000bffff874
|
||||
fb70c0000000bffffdd0
|
||||
25bfc0000000bffff69b
|
||||
7ad6c0000000bfffebfc
|
||||
c95ec0000000bfffebce
|
||||
3e54c0000000c0001458
|
||||
9bbbc0000000c0001b39
|
||||
535ac0000000c0001d2e
|
||||
adedc0000000c0000629
|
||||
bd53c0000000bfffea47
|
||||
8c71c0000000bfffcccc
|
||||
9d5a00bc614e00bc3e80
|
||||
4ea800bc614e00bc467e
|
||||
258a00bc614e00bc5040
|
||||
146f00bc614e00bc69fa
|
||||
d3a300bc614e00bc71a7
|
||||
e80c00bc614e00bc602e
|
||||
ee5400bc614e00bc5b66
|
||||
dc1b00bc614e00bc5d82
|
||||
50dd00bc614e00bc565e
|
||||
2e7e00bc614e00bc77f2
|
||||
2f7f00bc614e00bc789f
|
||||
d37000bc614e00bc4d9e
|
||||
bbd800bc614e00bc6c16
|
||||
83a000bc614e00bc902e
|
||||
0f2400bc614e00bc636a
|
||||
e85f00bc614e00bc5866
|
||||
f75600bc614e00bc5e48
|
||||
ccb200bc614e00bc7126
|
||||
6c1100bc614e00bc687a
|
||||
d8b500bc614e00bc6d06
|
||||
e8f300bc614e00bc6286
|
||||
c8f400bc614e00bc63ee
|
||||
c9c100bc614e00bc6ed7
|
||||
ddcc00bc614e00bc686a
|
||||
05fe00bc614e00bc6144
|
||||
ee0600bc614e00bc60e2
|
||||
5dc700bc614e00bc4c99
|
||||
f40200bc614e00bc6136
|
||||
ddfe00bc614e00bc6194
|
||||
5f9000bc614e00bc37be
|
||||
e5ab00bc614e00bc6a45
|
||||
c84700bc614e00bc51c6
|
||||
395a00bc614e00bc7558
|
||||
4b1e00bc614e00bc6a18
|
||||
29b900bc614e00bc55ef
|
||||
00d300bc614e00bc614e
|
||||
33b100bc614e00bc5191
|
||||
87ea00bc614e00bc6bb4
|
||||
723700bc614e00bc79cc
|
||||
195300bc614e00bc6969
|
||||
a63600bc614e00bc4e52
|
||||
37ab00bc614e00bc4f0b
|
||||
c0ae00bc614e00bc75ce
|
||||
ff5800bc614e00bc60f6
|
||||
5de100bc614e00bc560b
|
||||
9dbe00bc614e00bc7ad4
|
||||
06f000bc614e00bc60ee
|
||||
08a900bc614e00bc5e96
|
||||
577a00bc614e00bc8ac4
|
||||
38e800bc614e00bc5c0e
|
||||
1bd5ff439eb2ff439a29
|
||||
7b0cff439eb2ff43a476
|
||||
f05bff439eb2ff439902
|
||||
766fff439eb2ff43d1dc
|
||||
5f0aff439eb2ff43a268
|
||||
c577ff439eb2ff438345
|
||||
a39cff439eb2ff43c306
|
||||
5afeff439eb2ff439dfe
|
||||
e5b3ff439eb2ff43a6d1
|
||||
2d1fff439eb2ff43a425
|
||||
79bbff439eb2ff437e15
|
||||
b49dff439eb2ff43bc16
|
||||
c94dff439eb2ff438e27
|
||||
a2f6ff439eb2ff43a25e
|
||||
2783ff439eb2ff438ba7
|
||||
97fbff439eb2ff43a0bf
|
||||
c7c5ff439eb2ff43abd5
|
||||
53e9ff439eb2ff43973d
|
||||
a54cff439eb2ff4383ae
|
||||
e336ff439eb2ff439894
|
||||
6e31ff439eb2ff43b3c0
|
||||
c667ff439eb2ff43875c
|
||||
0dafff439eb2ff439a95
|
||||
3487ff439eb2ff43861e
|
||||
eecdff439eb2ff43a248
|
||||
5232ff439eb2ff43aeb6
|
||||
4069ff439eb2ff43b8f2
|
||||
073fff439eb2ff43a06b
|
||||
79cbff439eb2ff4385a5
|
||||
e659ff439eb2ff4395a8
|
||||
7cabff439eb2ff437586
|
||||
6a12ff439eb2ff43a626
|
||||
5cadff439eb2ff4380de
|
||||
cf0eff439eb2ff439c04
|
||||
19ecff439eb2ff439cbe
|
||||
1563ff439eb2ff43a6d1
|
||||
941fff439eb2ff43919e
|
||||
106eff439eb2ff43a592
|
||||
bf4cff439eb2ff438b66
|
||||
f4f6ff439eb2ff439f2a
|
||||
e5bcff439eb2ff43a5de
|
||||
9bdfff439eb2ff43abb7
|
||||
f4b3ff439eb2ff43a24e
|
||||
596aff439eb2ff43c38c
|
||||
6bacff439eb2ff437b96
|
||||
a2bbff439eb2ff43b808
|
||||
4677ff439eb2ff43bf3c
|
||||
9ab8ff439eb2ff43bb62
|
||||
5f0eff439eb2ff43a3e4
|
||||
4c11ff439eb2ff43a3be
|
||||
80800000000000004000
|
||||
80800000000100004001
|
||||
8080ffffffff00003fff
|
||||
80807fffffff80003fff
|
||||
80808000000080004000
|
||||
80804000000040004000
|
||||
8080c0000000c0004000
|
||||
808000bc614e00bca14e
|
||||
8080ff439eb2ff43deb2
|
||||
7f7f0000000000003f01
|
||||
7f7f0000000100003f02
|
||||
7f7fffffffff00003f00
|
||||
7f7f7fffffff80003f00
|
||||
7f7f8000000080003f01
|
||||
7f7f4000000040003f01
|
||||
7f7fc0000000c0003f01
|
||||
7f7f00bc614e00bca04f
|
||||
7f7fff439eb2ff43ddb3
|
||||
807f00000000ffffc080
|
||||
807f00000001ffffc081
|
||||
807fffffffffffffc07f
|
||||
807f7fffffff7fffc07f
|
||||
807f800000007fffc080
|
||||
807f400000003fffc080
|
||||
807fc0000000bfffc080
|
||||
807f00bc614e00bc21ce
|
||||
807fff439eb2ff435f32
|
||||
7f8000000000ffffc080
|
||||
7f8000000001ffffc081
|
||||
7f80ffffffffffffc07f
|
||||
7f807fffffff7fffc07f
|
||||
7f80800000007fffc080
|
||||
7f80400000003fffc080
|
||||
7f80c0000000bfffc080
|
||||
7f8000bc614e00bc21ce
|
||||
7f80ff439eb2ff435f32
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user