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feat: two-flash programming architecture, FPGA_DATA_READY, real JTAG/config pinout

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Establishes the real ESP32<->ECP5 programming architecture: flash #1
(neural-network data, existing V1 subsystem, ball reserved not yet
wired into V2) stays separate from flash #2 (boot bitstream, MSPI
auto-boot, CFG[2:0]=[0,1,0]); ESP32 talks JTAG only (bit-banged, no
hardware JTAG-master peripheral on S3/C6), updating flash #2 through
the ECP5's own internal sysCONFIG-to-SPI bridge, never driving the
flash pins directly -- zero bus contention, confirmed against the real
Lattice hardware checklist and sysCONFIG user guide.

Adds real, verified ball assignments (official Lattice CABGA381 CSV +
Project Trellis iodb.json) for JTAG, PROGRAMN/INITN/DONE, CFG[2:0],
and the MSPI dedicated pins -- all written to docs/pinouts.md.

Implements FPGA_DATA_READY as real RTL: a system-idle detector
(dependency_manager's any_pending OR neural_director's !queue_empty OR
any active slot), sticky on the busy->idle edge, self-clearing on new
work -- not a per-neuron completion pulse, which was confirmed too
fine-grained. Bit-exact regression re-verified at N_SLOTS=4 and 8
(zero cycle-count change), new explicit data_ready assertion check
added to the D-Stress testbench (PASS both configs), and a fresh
Yosys+nextpnr-ecp5 placement check (0 errors, data_ready placed at G3).

Also fixes a real, independently-found bug while editing an adjacent
file: nms_neural_multiprocessor_sdram_unified.v's own sdram_a port was
still [11:0] (12 bits), stale from before the 64MB/13-bit memory
upgrade. Not exercised by the real board-level top (which wires SDRAM
directly, bypassing this wrapper) but WAS silently truncating A12 in
every D-Stress simulation this session, including today's earlier
ERR-0029 verification runs. Assessed impact: all D-Stress test
addresses used this session decode to rows under 4096 (bit 12 never
actually needed), so no false-positive PASS is believed to have
resulted -- but the full 64MB space was never actually exercised
through this wrapper. Fixed; re-verified bit-exact with identical
cycle counts.

See decisions.log DEC-0041 for full detail.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-07 12:46:00 +02:00
co-authored by Claude Sonnet 5
parent 81a9619214
commit 7d6311bce3
11 changed files with 390 additions and 9 deletions
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hardware/v2/constraints/v2_board_top.lpf
+11 -3
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@@ -97,8 +97,16 @@ LOCATE COMP "sdram_dq[15]" SITE "N5"; IOBUF PORT "sdram_dq[15]" IO_TYPE=LVCMOS33
LOCATE COMP "sdram_dqm[0]" SITE "P5"; IOBUF PORT "sdram_dqm[0]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dqm[1]" SITE "N3"; IOBUF PORT "sdram_dqm[1]" IO_TYPE=LVCMOS33;
// All 16 top-level ports of fpga_neural_v2_top are now real-ball
// data_ready (FPGA_DATA_READY, to ESP32): free bank-7 ball, dual-
// function PCLKT7_1 not needed as a PLL input here, reused as plain
// GPIO output -- real ball, verified free (not in any other LOCATE
// COMP in this file) via the Trellis iodb.json + official CSV.
LOCATE COMP "data_ready" SITE "G3"; IOBUF PORT "data_ready" IO_TYPE=LVCMOS33;
// All 17 top-level ports of fpga_neural_v2_top are now real-ball
// assigned: osc_clk, ext_rst_n, spi_sclk, spi_mosi, spi_miso,
// spi_cs_n, sdram_cke, sdram_cs_n, sdram_ras_n, sdram_cas_n,
// sdram_we_n, sdram_ba[1:0], sdram_a[11:0], sdram_dq[15:0],
// sdram_dqm[1:0], pll_locked -- no placeholders remain in THIS LPF.
// sdram_we_n, sdram_ba[1:0], sdram_a[12:0], sdram_dq[15:0],
// sdram_dqm[1:0], data_ready, pll_locked -- no placeholders remain in
// THIS LPF. (sdram_a corrected from a stale [11:0] comment -- the
// real port has been [12:0] since the 64MB memory upgrade.)