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feat: host_mem_bridge.v, word<->burst translator for host DDR3 access (EXP-0071)

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Closes part of the gap found re-auditing spi_host_bridge.v against V3:
V3 had no host raw-memory-access path into DDR3 at all. This module
translates single-16-bit-word req/wr/addr/wdata/lb_n/ub_n transactions
(spi_host_bridge.v's own WRITE_MEM/READ_MEM shape) into BURST_LEN=8
transactions on the shared arbiter, using the project's existing
DQM-style partial-burst masking technique.

Verified standalone against the SDR SDRAM placeholder: 16/16 tests,
0 errors, including cross-word-corruption checks on every burst
offset. Not yet wired into the N=2 system or driven by real SPI
opcode decode.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-17 08:53:23 +02:00
co-authored by Claude Sonnet 5
parent 598feb975b
commit 786464ee21
3 changed files with 335 additions and 0 deletions
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hardware/v2/logs/experiments.log
+51
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@@ -4353,3 +4353,54 @@ not-yet-consumed (no dependency manager in V3 yet); (3) real (not
out-of-context) Vivado P&R using the actual MIG-generated XDC pin/ out-of-context) Vivado P&R using the actual MIG-generated XDC pin/
timing constraints, for genuine board-accurate Fmax signoff -- this timing constraints, for genuine board-accurate Fmax signoff -- this
is the user's own explicit ask and still outstanding. is the user's own explicit ask and still outstanding.
EXP-0071 -- host_mem_bridge.v: word<->burst translator for host raw
DDR3 access, isolated verification (2026-09-17, same autonomous
continuation)
CONTEXT: EXP-0068's spi_host_bridge.v audit found V3 has NO host raw-
memory-access path into DDR3 at all (the WRITE_MEM/READ_MEM opcode
equivalent). spi_host_bridge.v's own mem_req/wr/addr/wdata/lb_n/ub_n
-> rdata/ready port is single-16-bit-WORD granularity (same shape as
V2's real AR-port convention), but V3's shared memory path only
understands BURST_LEN=8 (128-bit) chunks. Wrote hardware/v3/rtl/
host_mem_bridge.v to translate between them, using the exact same
DQM-style partial-burst-mask technique already proven throughout this
project's memory stack (not a new invented mechanism): a single-word
write replicates the word across the whole burst and masks out every
byte except the target word's own 2 mask bits (set from the host's
own lb_n/ub_n); a single-word read fetches the whole burst and
extracts the target word by its offset. Sits as one requester on
sdram_arbiter_n.v (req_active/req_grant/req_req/... naming, matching
that module's own per-slot convention exactly), observing req_grant
once in S_MEMWAIT before firing its own one-shot req_req -- same
EXP-0066 discipline as every other requester in this project.
METHOD: hardware/v3/sim/tb_host_mem_bridge.v, isolated test against
the cheap SDR SDRAM placeholder (sdram_controller.v + sdram_model.v,
same precedent as tb_sdram_arbiter_n.v -- verify new glue logic on the
fast backend before real-DDR3 integration). TEST1: write+read all 8
word offsets within one burst, confirm each is bit-exact. TEST2:
rewrite only word 3, confirm words 0,1,2,4..7 are untouched (the real
risk this module exists to get right -- masking correctness, not just
happy-path data movement). Compiled/run with iverilog+vvp (plain
Verilog, no Xilinx primitives needed at this stage).
RESULT: 16/16 tests, 0 errors. Byte-mask arithmetic (the
ALL_ONES & ~(2'b11<<shift) | ({ub_n,lb_n}<<shift) expression) verified
correct at every one of the 8 possible burst offsets, including the
cross-word-corruption check.
DECISION: host_mem_bridge.v is trusted standalone. Not yet integrated
as a 3rd arbiter requester alongside the 2 packed_slot instances, and
not yet driven by spi_host_bridge.v's real opcode decode -- both still
open.
next_action: (1) wire host_mem_bridge.v as req[2] on a NUM_REQ=3
sdram_arbiter_n.v alongside 2 packed_slot instances and confirm no
regression/contention issue vs EXP-0070's 2-requester result; (2) the
SPI opcode re-audit itself (spi_host_bridge.v's WRITE_JOB dependency
fields vs neural_director_packed.v's simpler job_in_* port) -- this is
the user's own explicit, still-outstanding request, and is the next
priority over further memory-path polish; (3) real Vivado P&R with
the actual MIG-generated XDC constraints, still outstanding.
hardware/v3/rtl/host_mem_bridge.v
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@@ -0,0 +1,123 @@
`timescale 1ns/1ps
// ============================================================
// V3 -- host raw-memory-access bridge: the missing piece flagged
// re-auditing spi_host_bridge.v against V3's real architecture.
// spi_host_bridge.v's WRITE_MEM/READ_MEM opcodes drive a single-
// 16-bit-WORD req/wr/addr/wdata/lb_n/ub_n -> rdata/ready port (the
// SAME shape as V2's real psram_controller.v / sdram_unified_
// backend.v AR port), but V3's shared memory path (sdram_arbiter_n.v
// -> mig_native_adapter.v) only understands BURST_LEN=8 (128-bit)
// chunks. This module is the translator, matching sdram_unified_
// backend.v's own AR-port technique exactly (not reinvented): a
// write masks out every word in the burst except the target one
// (DQM-style byte masking, already how this project's whole memory
// stack works); a read fetches the whole burst and extracts the
// target word combinationally.
//
// Sits as one requester on sdram_arbiter_n.v (alongside N packed_
// slot.v instances) -- `active` is asserted for the WHOLE single-word
// transaction (word-granularity, no multi-burst sequencing needed),
// so mem_grant only needs to be observed once before the one-shot
// ctrl_req fires, same discipline as packed_slot.v's own S_MEMWAIT
// (EXP-0066's real, hard-won lesson).
// ============================================================
module host_mem_bridge #(
parameter BURST_LEN = 8,
parameter ADDR_WIDTH = 25 // word address, matches sdram_arbiter_n.v's own convention
)(
input wire clk,
input wire rst,
// ---- host-facing port (matches spi_host_bridge.v's own
// mem_req/mem_wr/mem_addr/mem_wdata/mem_lb_n/mem_ub_n ->
// mem_rdata/mem_ready convention exactly) ----
input wire mem_req,
input wire mem_wr,
input wire [ADDR_WIDTH-1:0] mem_addr, // WORD address (not burst-aligned)
input wire [15:0] mem_wdata,
input wire mem_lb_n,
input wire mem_ub_n,
output reg [15:0] mem_rdata,
output reg mem_ready,
// ---- arbiter-facing requester port (matches sdram_arbiter_n.v's
// own per-slot req_active/req_grant/req_req/req_wr/req_addr/
// req_wdata/req_wmask -> req_rdata/req_ready/req_busy naming) ----
output wire req_active,
input wire req_grant,
output reg req_req,
output reg req_wr,
output reg [ADDR_WIDTH-1:0] req_addr,
output reg [16*BURST_LEN-1:0] req_wdata,
output reg [2*BURST_LEN-1:0] req_wmask,
input wire [16*BURST_LEN-1:0] req_rdata,
input wire req_ready,
input wire req_busy
);
localparam ALIGN_BITS = $clog2(BURST_LEN);
localparam S_IDLE = 2'd0,
S_MEMWAIT = 2'd1,
S_XFER = 2'd2,
S_DONE = 2'd3;
reg [1:0] state;
reg [ALIGN_BITS-1:0] word_in_block;
assign req_active = (state == S_MEMWAIT) || (state == S_XFER);
always @(posedge clk) begin
if (rst) begin
state <= S_IDLE;
req_req <= 1'b0;
mem_ready <= 1'b0;
end else begin
req_req <= 1'b0;
mem_ready <= 1'b0;
case (state)
S_IDLE: begin
if (mem_req) begin
req_addr <= {mem_addr[ADDR_WIDTH-1:ALIGN_BITS], {ALIGN_BITS{1'b0}}};
word_in_block <= mem_addr[ALIGN_BITS-1:0];
req_wr <= mem_wr;
if (mem_wr) begin
// replicate the target word across the whole
// burst; only its own mask bits matter (see
// header -- same DQM-style technique as
// sdram_unified_backend.v's own AR port).
req_wdata <= {BURST_LEN{mem_wdata}};
req_wmask <= {(2*BURST_LEN){1'b1}} &
~(({{(2*BURST_LEN-2){1'b0}}, 2'b11}) << (mem_addr[ALIGN_BITS-1:0]*2)) |
(({{(2*BURST_LEN-2){1'b0}}, mem_ub_n, mem_lb_n}) << (mem_addr[ALIGN_BITS-1:0]*2));
end
state <= S_MEMWAIT;
end
end
S_MEMWAIT: begin
if (req_grant) begin
req_req <= 1'b1;
state <= S_XFER;
end
end
S_XFER: begin
if (req_ready) begin
if (!req_wr)
mem_rdata <= req_rdata[word_in_block*16 +: 16];
state <= S_DONE;
end
end
S_DONE: begin
mem_ready <= 1'b1;
state <= S_IDLE;
end
default: state <= S_IDLE;
endcase
end
end
endmodule
hardware/v3/sim/tb_host_mem_bridge.v
+161
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@@ -0,0 +1,161 @@
`timescale 1ns/1ps
// ============================================================
// Isolated correctness test for host_mem_bridge.v: the word<->burst
// translator that closes the "no host raw-memory-access path" gap
// found re-auditing spi_host_bridge.v against V3 (EXP-0068's audit).
// Uses the cheap SDR SDRAM placeholder backend (sdram_controller.v +
// sdram_model.v), same precedent as tb_sdram_arbiter_n.v: verify new
// glue logic against the fast backend first, real DDR3 integration
// is a separate, later step once this is trusted standalone.
//
// Checks: (a) single-word write only touches its OWN word inside the
// burst (byte masking correctness, lb_n/ub_n both individually and
// together) without corrupting neighboring words in the same burst;
// (b) single-word read extracts the correct word regardless of its
// offset within the burst (all BURST_LEN=8 offsets exercised);
// (c) mem_ready pulses exactly once per transaction.
// ============================================================
module tb;
localparam BURST_LEN = 8;
localparam ROW_BITS = 13;
localparam COL_BITS = 10;
localparam BANK_BITS = 2;
localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
localparam CLK_FREQ_MHZ = 64;
localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
reg clk = 0;
always #(CLK_PERIOD_NS/2.0) clk = ~clk;
reg rst;
wire ctrl_req, ctrl_wr;
wire [ADDR_WIDTH-1:0] ctrl_addr;
wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
wire [2*BURST_LEN-1:0] ctrl_wmask;
wire ctrl_ready, ctrl_busy;
wire cke, cs_n, ras_n, cas_n, we_n;
wire [BANK_BITS-1:0] ba;
wire [ROW_BITS-1:0] a;
wire [15:0] dq;
wire [1:0] dqm;
sdram_controller #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_ctrl (
.clk(clk), .rst(rst),
.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
);
sdram_model #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_mem (
.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
.ba(ba), .a(a), .dq(dq), .dqm(dqm)
);
// single requester -> arbiter isn't even needed for an isolated
// test, but we still exercise the real req_active/req_grant
// handshake shape by tying grant = active (what a 1-requester
// arbiter would produce), so the bridge's own S_MEMWAIT logic is
// exercised exactly as it will be in the real N-requester system.
wire req_active;
wire req_grant = req_active;
reg mem_req, mem_wr, mem_lb_n, mem_ub_n;
reg [ADDR_WIDTH-1:0] mem_addr;
reg [15:0] mem_wdata;
wire [15:0] mem_rdata;
wire mem_ready;
host_mem_bridge #(
.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
) u_bridge (
.clk(clk), .rst(rst),
.mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr),
.mem_wdata(mem_wdata), .mem_lb_n(mem_lb_n), .mem_ub_n(mem_ub_n),
.mem_rdata(mem_rdata), .mem_ready(mem_ready),
.req_active(req_active), .req_grant(req_grant),
.req_req(ctrl_req), .req_wr(ctrl_wr), .req_addr(ctrl_addr),
.req_wdata(ctrl_wdata), .req_wmask(ctrl_wmask),
.req_rdata(ctrl_rdata), .req_ready(ctrl_ready), .req_busy(ctrl_busy)
);
integer errors, tests;
task automatic host_write(input [ADDR_WIDTH-1:0] a, input [15:0] d, input lb_n, input ub_n);
begin
@(posedge clk);
mem_req = 1'b1; mem_wr = 1'b1; mem_addr = a; mem_wdata = d;
mem_lb_n = lb_n; mem_ub_n = ub_n;
@(posedge clk);
mem_req = 1'b0;
while (!mem_ready) @(posedge clk);
@(posedge clk); // settle one cycle before next command
end
endtask
task automatic host_read(input [ADDR_WIDTH-1:0] a, output [15:0] d);
begin
@(posedge clk);
mem_req = 1'b1; mem_wr = 1'b0; mem_addr = a; mem_lb_n = 1'b0; mem_ub_n = 1'b0;
@(posedge clk);
mem_req = 1'b0;
while (!mem_ready) @(posedge clk);
d = mem_rdata;
@(posedge clk);
end
endtask
reg [15:0] got;
integer i;
localparam [ADDR_WIDTH-1:0] BASE = 25'd200; // burst-aligned base (200 % 8 == 0)
initial begin
errors = 0; tests = 0;
rst = 1; mem_req = 0; mem_wr = 0; mem_lb_n = 0; mem_ub_n = 0; mem_addr = 0; mem_wdata = 0;
repeat(5) @(posedge clk);
rst = 0;
@(posedge clk);
$display("=== TEST 1: write+read every word offset within one burst, verify no cross-word corruption ===");
for (i = 0; i < BURST_LEN; i = i + 1) begin
host_write(BASE + i[ADDR_WIDTH-1:0], 16'hA000 + i[15:0], 1'b0, 1'b0);
end
for (i = 0; i < BURST_LEN; i = i + 1) begin
host_read(BASE + i[ADDR_WIDTH-1:0], got);
tests = tests + 1;
if (got !== (16'hA000 + i[15:0])) begin
$display("FAIL offset=%0d: got=%h expected=%h", i, got, 16'hA000+i[15:0]);
errors = errors + 1;
end else begin
$display("PASS offset=%0d: bit-exact (%h)", i, got);
end
end
$display("=== TEST 2: re-write word 3 only, confirm neighbors (0,1,2,4..7) untouched ===");
host_write(BASE + 25'd3, 16'hBEEF, 1'b0, 1'b0);
for (i = 0; i < BURST_LEN; i = i + 1) begin
host_read(BASE + i[ADDR_WIDTH-1:0], got);
tests = tests + 1;
if (i == 3) begin
if (got !== 16'hBEEF) begin
$display("FAIL offset=3 after rewrite: got=%h expected=BEEF", got);
errors = errors + 1;
end else $display("PASS offset=3 after rewrite: bit-exact");
end else begin
if (got !== (16'hA000 + i[15:0])) begin
$display("FAIL offset=%0d corrupted by neighbor write: got=%h expected=%h", i, got, 16'hA000+i[15:0]);
errors = errors + 1;
end else $display("PASS offset=%0d untouched by neighbor write", i);
end
end
$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
if (errors == 0) $display("ALL TESTS PASSED (tb_host_mem_bridge)");
$finish;
end
endmodule