feat: host_mem_bridge.v, word<->burst translator for host DDR3 access (EXP-0071)
Closes part of the gap found re-auditing spi_host_bridge.v against V3: V3 had no host raw-memory-access path into DDR3 at all. This module translates single-16-bit-word req/wr/addr/wdata/lb_n/ub_n transactions (spi_host_bridge.v's own WRITE_MEM/READ_MEM shape) into BURST_LEN=8 transactions on the shared arbiter, using the project's existing DQM-style partial-burst masking technique. Verified standalone against the SDR SDRAM placeholder: 16/16 tests, 0 errors, including cross-word-corruption checks on every burst offset. Not yet wired into the N=2 system or driven by real SPI opcode decode. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
Claude Sonnet 5
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`timescale 1ns/1ps
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// ============================================================
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// V3 -- host raw-memory-access bridge: the missing piece flagged
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// re-auditing spi_host_bridge.v against V3's real architecture.
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// spi_host_bridge.v's WRITE_MEM/READ_MEM opcodes drive a single-
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// 16-bit-WORD req/wr/addr/wdata/lb_n/ub_n -> rdata/ready port (the
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// SAME shape as V2's real psram_controller.v / sdram_unified_
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// backend.v AR port), but V3's shared memory path (sdram_arbiter_n.v
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// -> mig_native_adapter.v) only understands BURST_LEN=8 (128-bit)
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// chunks. This module is the translator, matching sdram_unified_
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// backend.v's own AR-port technique exactly (not reinvented): a
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// write masks out every word in the burst except the target one
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// (DQM-style byte masking, already how this project's whole memory
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// stack works); a read fetches the whole burst and extracts the
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// target word combinationally.
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//
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// Sits as one requester on sdram_arbiter_n.v (alongside N packed_
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// slot.v instances) -- `active` is asserted for the WHOLE single-word
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// transaction (word-granularity, no multi-burst sequencing needed),
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// so mem_grant only needs to be observed once before the one-shot
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// ctrl_req fires, same discipline as packed_slot.v's own S_MEMWAIT
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// (EXP-0066's real, hard-won lesson).
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// ============================================================
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module host_mem_bridge #(
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parameter BURST_LEN = 8,
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parameter ADDR_WIDTH = 25 // word address, matches sdram_arbiter_n.v's own convention
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)(
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input wire clk,
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input wire rst,
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// ---- host-facing port (matches spi_host_bridge.v's own
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// mem_req/mem_wr/mem_addr/mem_wdata/mem_lb_n/mem_ub_n ->
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// mem_rdata/mem_ready convention exactly) ----
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input wire mem_req,
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input wire mem_wr,
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input wire [ADDR_WIDTH-1:0] mem_addr, // WORD address (not burst-aligned)
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input wire [15:0] mem_wdata,
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input wire mem_lb_n,
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input wire mem_ub_n,
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output reg [15:0] mem_rdata,
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output reg mem_ready,
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// ---- arbiter-facing requester port (matches sdram_arbiter_n.v's
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// own per-slot req_active/req_grant/req_req/req_wr/req_addr/
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// req_wdata/req_wmask -> req_rdata/req_ready/req_busy naming) ----
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output wire req_active,
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input wire req_grant,
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output reg req_req,
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output reg req_wr,
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output reg [ADDR_WIDTH-1:0] req_addr,
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output reg [16*BURST_LEN-1:0] req_wdata,
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output reg [2*BURST_LEN-1:0] req_wmask,
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input wire [16*BURST_LEN-1:0] req_rdata,
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input wire req_ready,
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input wire req_busy
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);
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localparam ALIGN_BITS = $clog2(BURST_LEN);
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localparam S_IDLE = 2'd0,
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S_MEMWAIT = 2'd1,
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S_XFER = 2'd2,
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S_DONE = 2'd3;
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reg [1:0] state;
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reg [ALIGN_BITS-1:0] word_in_block;
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assign req_active = (state == S_MEMWAIT) || (state == S_XFER);
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always @(posedge clk) begin
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if (rst) begin
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state <= S_IDLE;
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req_req <= 1'b0;
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mem_ready <= 1'b0;
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end else begin
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req_req <= 1'b0;
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mem_ready <= 1'b0;
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case (state)
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S_IDLE: begin
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if (mem_req) begin
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req_addr <= {mem_addr[ADDR_WIDTH-1:ALIGN_BITS], {ALIGN_BITS{1'b0}}};
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word_in_block <= mem_addr[ALIGN_BITS-1:0];
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req_wr <= mem_wr;
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if (mem_wr) begin
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// replicate the target word across the whole
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// burst; only its own mask bits matter (see
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// header -- same DQM-style technique as
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// sdram_unified_backend.v's own AR port).
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req_wdata <= {BURST_LEN{mem_wdata}};
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req_wmask <= {(2*BURST_LEN){1'b1}} &
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~(({{(2*BURST_LEN-2){1'b0}}, 2'b11}) << (mem_addr[ALIGN_BITS-1:0]*2)) |
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(({{(2*BURST_LEN-2){1'b0}}, mem_ub_n, mem_lb_n}) << (mem_addr[ALIGN_BITS-1:0]*2));
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end
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state <= S_MEMWAIT;
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end
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end
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S_MEMWAIT: begin
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if (req_grant) begin
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req_req <= 1'b1;
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state <= S_XFER;
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end
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end
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S_XFER: begin
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if (req_ready) begin
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if (!req_wr)
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mem_rdata <= req_rdata[word_in_block*16 +: 16];
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state <= S_DONE;
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end
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end
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S_DONE: begin
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mem_ready <= 1'b1;
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state <= S_IDLE;
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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endmodule
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@@ -0,0 +1,161 @@
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`timescale 1ns/1ps
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// ============================================================
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// Isolated correctness test for host_mem_bridge.v: the word<->burst
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// translator that closes the "no host raw-memory-access path" gap
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// found re-auditing spi_host_bridge.v against V3 (EXP-0068's audit).
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// Uses the cheap SDR SDRAM placeholder backend (sdram_controller.v +
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// sdram_model.v), same precedent as tb_sdram_arbiter_n.v: verify new
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// glue logic against the fast backend first, real DDR3 integration
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// is a separate, later step once this is trusted standalone.
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//
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// Checks: (a) single-word write only touches its OWN word inside the
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// burst (byte masking correctness, lb_n/ub_n both individually and
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// together) without corrupting neighboring words in the same burst;
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// (b) single-word read extracts the correct word regardless of its
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// offset within the burst (all BURST_LEN=8 offsets exercised);
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// (c) mem_ready pulses exactly once per transaction.
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// ============================================================
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module tb;
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localparam BURST_LEN = 8;
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localparam ROW_BITS = 13;
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localparam COL_BITS = 10;
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localparam BANK_BITS = 2;
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localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
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localparam CLK_FREQ_MHZ = 64;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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reg rst;
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wire ctrl_req, ctrl_wr;
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wire [ADDR_WIDTH-1:0] ctrl_addr;
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wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
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wire [2*BURST_LEN-1:0] ctrl_wmask;
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wire ctrl_ready, ctrl_busy;
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wire cke, cs_n, ras_n, cas_n, we_n;
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wire [BANK_BITS-1:0] ba;
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wire [ROW_BITS-1:0] a;
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wire [15:0] dq;
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wire [1:0] dqm;
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sdram_controller #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
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.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
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);
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sdram_model #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_mem (
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.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
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.ba(ba), .a(a), .dq(dq), .dqm(dqm)
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);
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// single requester -> arbiter isn't even needed for an isolated
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// test, but we still exercise the real req_active/req_grant
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// handshake shape by tying grant = active (what a 1-requester
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// arbiter would produce), so the bridge's own S_MEMWAIT logic is
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// exercised exactly as it will be in the real N-requester system.
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wire req_active;
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wire req_grant = req_active;
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reg mem_req, mem_wr, mem_lb_n, mem_ub_n;
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reg [ADDR_WIDTH-1:0] mem_addr;
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reg [15:0] mem_wdata;
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wire [15:0] mem_rdata;
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wire mem_ready;
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host_mem_bridge #(
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.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
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) u_bridge (
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.clk(clk), .rst(rst),
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.mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr),
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.mem_wdata(mem_wdata), .mem_lb_n(mem_lb_n), .mem_ub_n(mem_ub_n),
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.mem_rdata(mem_rdata), .mem_ready(mem_ready),
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.req_active(req_active), .req_grant(req_grant),
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.req_req(ctrl_req), .req_wr(ctrl_wr), .req_addr(ctrl_addr),
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.req_wdata(ctrl_wdata), .req_wmask(ctrl_wmask),
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.req_rdata(ctrl_rdata), .req_ready(ctrl_ready), .req_busy(ctrl_busy)
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);
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integer errors, tests;
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task automatic host_write(input [ADDR_WIDTH-1:0] a, input [15:0] d, input lb_n, input ub_n);
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begin
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@(posedge clk);
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mem_req = 1'b1; mem_wr = 1'b1; mem_addr = a; mem_wdata = d;
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mem_lb_n = lb_n; mem_ub_n = ub_n;
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@(posedge clk);
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mem_req = 1'b0;
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while (!mem_ready) @(posedge clk);
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@(posedge clk); // settle one cycle before next command
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end
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endtask
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task automatic host_read(input [ADDR_WIDTH-1:0] a, output [15:0] d);
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begin
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@(posedge clk);
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mem_req = 1'b1; mem_wr = 1'b0; mem_addr = a; mem_lb_n = 1'b0; mem_ub_n = 1'b0;
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@(posedge clk);
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mem_req = 1'b0;
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while (!mem_ready) @(posedge clk);
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d = mem_rdata;
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@(posedge clk);
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end
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endtask
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reg [15:0] got;
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integer i;
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localparam [ADDR_WIDTH-1:0] BASE = 25'd200; // burst-aligned base (200 % 8 == 0)
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initial begin
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errors = 0; tests = 0;
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rst = 1; mem_req = 0; mem_wr = 0; mem_lb_n = 0; mem_ub_n = 0; mem_addr = 0; mem_wdata = 0;
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repeat(5) @(posedge clk);
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rst = 0;
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@(posedge clk);
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$display("=== TEST 1: write+read every word offset within one burst, verify no cross-word corruption ===");
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for (i = 0; i < BURST_LEN; i = i + 1) begin
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host_write(BASE + i[ADDR_WIDTH-1:0], 16'hA000 + i[15:0], 1'b0, 1'b0);
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end
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for (i = 0; i < BURST_LEN; i = i + 1) begin
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host_read(BASE + i[ADDR_WIDTH-1:0], got);
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tests = tests + 1;
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if (got !== (16'hA000 + i[15:0])) begin
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$display("FAIL offset=%0d: got=%h expected=%h", i, got, 16'hA000+i[15:0]);
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errors = errors + 1;
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end else begin
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$display("PASS offset=%0d: bit-exact (%h)", i, got);
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end
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end
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$display("=== TEST 2: re-write word 3 only, confirm neighbors (0,1,2,4..7) untouched ===");
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host_write(BASE + 25'd3, 16'hBEEF, 1'b0, 1'b0);
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for (i = 0; i < BURST_LEN; i = i + 1) begin
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host_read(BASE + i[ADDR_WIDTH-1:0], got);
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tests = tests + 1;
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if (i == 3) begin
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if (got !== 16'hBEEF) begin
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$display("FAIL offset=3 after rewrite: got=%h expected=BEEF", got);
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errors = errors + 1;
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end else $display("PASS offset=3 after rewrite: bit-exact");
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end else begin
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if (got !== (16'hA000 + i[15:0])) begin
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$display("FAIL offset=%0d corrupted by neighbor write: got=%h expected=%h", i, got, 16'hA000+i[15:0]);
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errors = errors + 1;
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end else $display("PASS offset=%0d untouched by neighbor write", i);
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end
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end
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$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
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if (errors == 0) $display("ALL TESTS PASSED (tb_host_mem_bridge)");
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$finish;
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end
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endmodule
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