docs: log real Vivado stale-source bug + final flash-bridge P&R signoff (EXP-0078)
Found and fixed a real Vivado project-management bug: two source files (n2_system_ddr3_top.v, spi_host_bridge_v3.v) had stale imported copies (plus a duplicate at a second path) that silently kept being used in synth+impl despite live edits, making the first "flash bridge included" P&R run silently synthesize the OLD design (STARTUPE2 Used=0/1 gave it away). Fixed by removing the stale/duplicate entries and re-adding both files as direct (non-copied) references. Final real P&R: STARTUPE2 Used=1/1 (confirms the flash bridge is genuinely placed/routed), timing still closes but margin is now thinner and real: WNS +0.013ns, WHS +0.032ns, 0 failing endpoints. 5213 LUTs, 16 DSP48E1. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
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Claude Sonnet 5
@@ -4868,3 +4868,68 @@ real, not yet done, disclosed as the immediate next_action.
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next_action: real in-context P&R re-verification (synth+impl) with
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next_action: real in-context P&R re-verification (synth+impl) with
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flash_spi_master.v + the new XDC pin/PERSIST constraints included --
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flash_spi_master.v + the new XDC pin/PERSIST constraints included --
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first real placement check for STARTUPE2 in this project.
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first real placement check for STARTUPE2 in this project.
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EXP-0078 -- real toolchain bug found+fixed: Vivado project had stale
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imported source copies; final real P&R with the flash bridge
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genuinely included (2026-09-19/20, same autonomous continuation)
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CONTEXT: after EXP-0077's flash_spi_master.v + FLASH_XFER integration,
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the first re-run of the real P&R (adding flash_spi_master.v to the
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project and re-running synth+impl) produced IDENTICAL timing/
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utilization numbers to EXP-0076's own run (same WNS, same LUT count),
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and the utilization report showed STARTUPE2 Used=0/1 -- a red flag,
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since flash_spi_master.v genuinely instantiates one.
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ROOT CAUSE (a real Vivado project-management bug, not an RTL issue):
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the Vivado project had IMPORTED (copied) n2_system_ddr3_top.v and
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spi_host_bridge_v3.v into NeuralProcessor.srcs/sources_1/imports/ at
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some earlier point in this session, and every subsequent `add_files`/
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`update_compile_order` call silently kept using those STALE COPIES --
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none of EXP-0077's edits (the flash bridge ports/instantiation) had
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actually reached the compiled design at all. Worse: a SECOND, separate
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duplicate copy of both files existed at a different imports/ path
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(imports/rtl/... vs imports/hardware/v3/rtl/...), from an earlier
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add_files call made from a different working directory -- real
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evidence that this kind of stale-copy drift can silently accumulate
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across a long session unless explicitly checked.
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FIX: diffed every one of the project's own "imports/" file copies
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against their live hardware/v3 (or v2) source on disk -- found exactly
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these two stale/duplicated files (all others were already in sync).
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Removed both duplicate/stale entries and re-added n2_system_ddr3_top.v
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and spi_host_bridge_v3.v pointing DIRECTLY at their canonical live
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path (matching flash_spi_master.v's own already-correct, non-copied
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reference) -- self-updating going forward, no import step to go stale
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again.
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RESULT (the real, final, trustworthy P&R): route_design 100%, 0
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errors. STARTUPE2 Used=1/1 (100%) -- confirms the flash bridge is
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genuinely placed and routed this time, not silently dropped. Timing
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still closes but with a real, measurably thinner margin now that the
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actual flash-bridge logic (including its own CCLK routing through
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STARTUPE2) is truly part of the design: WNS = +0.013ns (down from
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EXP-0076's +0.040/+0.056ns line of results), WHS = +0.032ns, still
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0/17473 failing setup endpoints and 0/17470 failing hold endpoints.
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5213 LUTs (8.22%, +40 vs EXP-0076's 5173 for the flash bridge itself),
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16 DSP48E1 (6.67%, unchanged), 0 Block RAM.
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DECISION: this is the current, final, genuinely trustworthy timing/
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resource signoff -- real DDR3, real pin constraints, real register
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file, real flash-bridge with real STARTUPE2 placement, all verified
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together. The margin is real but now quite thin (+0.013ns) -- any
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FUTURE logic addition to this design should be re-verified with a
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fresh real P&R before being trusted, not assumed to still close.
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LESSON (general, not just for this project): in any long Vivado batch-
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TCL session that repeatedly edits already-added RTL files, explicitly
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diff every "imports/" copy against its live source before trusting a
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P&R result -- `add_files`/`update_compile_order` alone do NOT
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guarantee an already-imported file gets refreshed from a later edit,
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and a stale copy produces no error, no warning, just silently wrong
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(unchanged) synthesis results.
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next_action: none blocking. This is a stable, real, verified
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checkpoint. Remaining open work (scaling past N=2, a real activation-
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fetch engine, PCB-specific pin constraints once the board layout is
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underway, ESP32-side JTAG bootstrap firmware) is all disclosed and
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outside this experiment's own scope.
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