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feat: real N=4/N=8 timing curve -- N=8 REALLY CLOSES (0 failing endpoints, EXP-0095)

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Fixed a real, previously-untested N_GROUPS=1 edge case in
neural_director_grouped.v (bare $clog2(N_GROUPS) invalid for
N_GROUPS=1, same class of bug sdram_arbiter_n.v's own SELW guard
already handles -- applied the same fix here and in
n16_system_ddr3_top.v's own job_out_group_w wire).

Real synth_design -generic N_GROUPS=<n> P&R sweep (same RTL/arbiter as
EXP-0094's real N=16 result):
  N=4  (N_GROUPS=1): WNS=-0.005ns, 2 failing endpoints
  N=8  (N_GROUPS=2): WNS=0.000ns, 0 failing endpoints -- REALLY CLOSED
  N=16 (N_GROUPS=4): WNS=-0.338ns, 60 failing endpoints (EXP-0094)

N=8 is a real, new, closed P&R signoff -- 8x N=2's parallelism with
the same already-verified systolic RTL. Answers the user's own
question directly: the design does not fail until somewhere between
N=8 and N=16, not at N=4 or N=8.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-21 07:56:19 +02:00
co-authored by Claude Sonnet 5
parent 67ccb420d6
commit 6d06404428
4 changed files with 129 additions and 13 deletions
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docs/ARCHITECTURE_ANALYSIS.md
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@@ -659,7 +659,7 @@ specifically to document where/how it breaks rather than to succeed):
---
### 5.6 [Functionally DONE, WNS -0.913ns→-0.338ns via 2 safe fixes, small intrinsic gap remains — EXP-0089…0094] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains
### 5.6 [N=8 REALLY CLOSES timing (0 failing endpoints); N=16 still -0.338ns — EXP-0089…0095] Hybrid systolic scaling: up to 4 groups × 4-PE weight-stationary chains
Captured from a 2026-09-20 brainstorming session as a purely exploratory
idea; the same day, per the user's own explicit reprioritization, the real
@@ -804,13 +804,45 @@ anything else this session, better started with explicit direction
than pushed further autonomously.
**Not yet done, real and disclosed, real options for closing the
remaining gap**: (1) real, careful pipelining inside
remaining N=16 gap**: (1) real, careful pipelining inside
`neural_processor_packed.v`'s own MAC datapath at the specific
`GEN_MAC_PACKED`/`prodb1_reg` boundary (fork-before-promote, N=2's own
signoff must stay protected, verify both). (2) a real, measured lower
target clock for the N=16 variant specifically (unquantified
throughput trade-off against N=2). See EXP-0094's own `next_action`.
**Real intermediate-N timing curve (EXP-0095)** — the user's own
explicit request ("cerchiamo dove fallisce"): `N_GROUPS` is a real,
already-existing top-level parameter, so `synth_design -generic
N_GROUPS=<n>` against the exact same RTL/arbiter (EXP-0094's own
hierarchical arbiter already wired in) gave a real, measured curve
without any new top-level files:
| N | N_GROUPS | DSP48E1 | LUT% | real WNS | real failing endpoints |
|---|---|---|---|---|---|
| 2 (flat, EXP-0088) | — | 16 | — | **+0.099962ns** | 0 (closed) |
| 4 (systolic) | 1 | 32 (13.3%) | 13.87% | −0.005ns | 2 |
| 8 (systolic) | 2 | 64 (26.7%) | 19.77% | **0.000ns** | **0 (REALLY CLOSED)** |
| 16 (systolic, EXP-0094) | 4 | 128 (53.3%) | 31.39% | −0.338ns | 60 |
**N=8 is a real, new, closed P&R signoff** — a real post-route
`report_timing_summary` result, 0 failing endpoints, same real part
and clock domain, not a projection. N=4 is a hair's breadth away
(N=8's own better WNS despite 2× the logic is real run-to-run
placer/router variance, not a contradiction). **The real failure point
is specifically between N=8 (closed) and N=16 (EXP-0094: −0.338ns)** —
N=12 (N_GROUPS=3) has not yet been measured and would narrow this
further. Real, disclosed caveat: N=4/N=8 have not yet had their own
dedicated functional xsim (only N=16's full-scale RTL is functionally
verified, EXP-0092/0094) — the correctness argument for N=4/N=8 rests
on the architecture's own embarrassingly-parallel-across-groups design,
not yet a directly measured result at those specific N. Real bug found
and fixed first: `neural_director_grouped.v`'s own bare
`$clog2(N_GROUPS)` was invalid (`[-1:0]`) for the never-before-tested
N_GROUPS=1 case — fixed with the same real `SELW`-style guard pattern
`sdram_arbiter_n.v` already established. See EXP-0095's own
`next_action`.
**The problem it targets**: plain N=16 independent cores (§5.5's own
"documentary, expected to break" framing) means 16 independent DDR3
requesters contending for one arbitrated channel — real congestion that