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feat(v2): M8 PSRAM integration - real V1 backend shared across concurrent slots

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neural_multiprocessor.v wraps dataflow_core.v (M7, unmodified) around
the real, unmodified V1 PSRAM backend chain (int8_memory_access ->
memory_interface -> psram_controller), funneling N_SLOTS independent
Memory Backend Interface ports through a new generic N-port arbiter
(slot_mem_arbiter.v) inspired by (not copied from) V1's own
mem_arbiter.v.

Real concurrent-slot simulation immediately surfaced a genuine bug
(ERR-0008): memory_manager/prefetch_engine's byte-level backend
protocol is fire-and-forget (a single-cycle mem_req pulse with no
accept handshake) - correct for M4's direct 1:1 connection, but a
naive arbiter silently drops a pulse arriving while the shared bus is
owned by another slot, hanging that slot forever. Fixed with a
per-port pending-request latch, the same "queue, don't drop" idiom
already used by memory_manager's own pf_pending register (ERR-0006).

Verified (Verilator): 4/4 PASS with 2 slots genuinely contending for
one real PSRAM port (444 cycles). No regression on M4's own
testbench. Real synthesis + nextpnr-ecp5 P&R (no harness needed - real
PSRAM pins keep the top-level at 157 pins): 0 problems, Fmax 142.45
MHz, PASS at 80MHz.

Arbitration policy is fixed lowest-index priority, not fairness-
balanced (DEC-0010) - consistent with every other "simplest correct
policy first" scheduling choice in this roadmap, revisited only if
M9's real measurement shows starvation matters.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0010)/
experiments (EXP-0009)/errors (ERR-0008)/development.log, ROADMAP.md
updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 15:13:11 +02:00
co-authored by Claude Sonnet 5
parent 77baa8fc16
commit 6cff2c8a7c
12 changed files with 732 additions and 1 deletions
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hardware/v2/logs/synthesis.log
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@@ -63,3 +63,16 @@ CHECK: 0 problems on both configs (same 32 benign "multiple conflicting
deliberately NOT instantiated inside dataflow_core yet (decisions.log
DEC-0009). DSP scales exactly 8/slot (matches P_IN=8, consistent with
every prior per-processor DSP measurement since M1/M2).
[2026-09-05] EXP-0009 -- neural_multiprocessor (M8, N_SLOTS=2, real
standalone top-level synthesis -- no timing harness needed: real PSRAM
pins replace dataflow_core's wide per-slot arrays, total 157 port bits,
well under the LFE5U-45F-8BG381's ~245 TRELLIS_IO budget)
LUT4=3145 CCU2C=388 TRELLIS_FF=3659 MULT18X18D=16 DP16KD=0
TRELLIS_DPR16X4=45 (small LUT-based distributed RAM, inferred from
neural_director's shallow QUEUE_DEPTH-entry job queue -- not BRAM,
same primitive class already seen in M7's own harness stat)
$_TBUF_=16 (tri-state buffers for the bidirectional psram_dq bus,
from V1's own unmodified psram_controller.v)
CHECK: 0 problems (same 32 benign "multiple conflicting drivers for
...neural_processor.\gi" warnings documented since EXP-0001).