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feat(v2): M8 PSRAM integration - real V1 backend shared across concurrent slots

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neural_multiprocessor.v wraps dataflow_core.v (M7, unmodified) around
the real, unmodified V1 PSRAM backend chain (int8_memory_access ->
memory_interface -> psram_controller), funneling N_SLOTS independent
Memory Backend Interface ports through a new generic N-port arbiter
(slot_mem_arbiter.v) inspired by (not copied from) V1's own
mem_arbiter.v.

Real concurrent-slot simulation immediately surfaced a genuine bug
(ERR-0008): memory_manager/prefetch_engine's byte-level backend
protocol is fire-and-forget (a single-cycle mem_req pulse with no
accept handshake) - correct for M4's direct 1:1 connection, but a
naive arbiter silently drops a pulse arriving while the shared bus is
owned by another slot, hanging that slot forever. Fixed with a
per-port pending-request latch, the same "queue, don't drop" idiom
already used by memory_manager's own pf_pending register (ERR-0006).

Verified (Verilator): 4/4 PASS with 2 slots genuinely contending for
one real PSRAM port (444 cycles). No regression on M4's own
testbench. Real synthesis + nextpnr-ecp5 P&R (no harness needed - real
PSRAM pins keep the top-level at 157 pins): 0 problems, Fmax 142.45
MHz, PASS at 80MHz.

Arbitration policy is fixed lowest-index priority, not fairness-
balanced (DEC-0010) - consistent with every other "simplest correct
policy first" scheduling choice in this roadmap, revisited only if
M9's real measurement shows starvation matters.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0010)/
experiments (EXP-0009)/errors (ERR-0008)/development.log, ROADMAP.md
updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 15:13:11 +02:00
co-authored by Claude Sonnet 5
parent 77baa8fc16
commit 6cff2c8a7c
12 changed files with 732 additions and 1 deletions
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hardware/v2/logs/development.log
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@@ -206,3 +206,27 @@ decision: see decisions.log DEC-0009 (M3 buffers not wired in yet, no
next_action: M8 -- PSRAM integration. Wire the real (unmodified) V1
PSRAM backend chain through dataflow_core end-to-end and measure/
design whatever N_SLOTS>1 arbitration real contention requires.
[2026-09-05] M8 -- hardware/v2/rtl/neural_multiprocessor.v +
hardware/v2/rtl/slot_mem_arbiter.v
reason: roadmap M8 -- "Integrare il controller V1 senza modificarlo
inizialmente. Misurare il comportamento reale." dataflow_core.v (M7,
untouched) now shares the real, unmodified V1 PSRAM backend chain
(int8_memory_access -> memory_interface -> psram_controller) across
N_SLOTS genuinely concurrent memory_manager instances, via a new
generic N-port arbiter inspired by (not copied from) V1's own
mem_arbiter.v.
result: real concurrent-slot simulation immediately surfaced a real
bug (errors.log ERR-0008: the byte-level backend's fire-and-forget
request pulse gets silently dropped by a naive arbiter under
contention) -- fixed with a pending-request latch. After the fix:
4/4 test PASS (2 concurrent slots genuinely contending for one real
PSRAM port, 444 cycles). Real synthesis: 0 problems, LUT4=3145/
CCU2C=388/FF=3659/DSP=16, real Fmax 142.45 MHz (PASS at 80MHz, no
harness needed -- real PSRAM pins keep the top-level pin count at
157). No regression on M4's own testbench.
errors: see errors.log ERR-0008 (real RTL bug, found and fixed).
decision: see decisions.log DEC-0010 (fixed-priority arbitration, no
fairness yet -- deferred pending real measured need).
next_action: M9 -- Full benchmark (§32): V1-vs-V2 comparison table,
every number labeled THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.