feat(v2): M8 PSRAM integration - real V1 backend shared across concurrent slots
neural_multiprocessor.v wraps dataflow_core.v (M7, unmodified) around the real, unmodified V1 PSRAM backend chain (int8_memory_access -> memory_interface -> psram_controller), funneling N_SLOTS independent Memory Backend Interface ports through a new generic N-port arbiter (slot_mem_arbiter.v) inspired by (not copied from) V1's own mem_arbiter.v. Real concurrent-slot simulation immediately surfaced a genuine bug (ERR-0008): memory_manager/prefetch_engine's byte-level backend protocol is fire-and-forget (a single-cycle mem_req pulse with no accept handshake) - correct for M4's direct 1:1 connection, but a naive arbiter silently drops a pulse arriving while the shared bus is owned by another slot, hanging that slot forever. Fixed with a per-port pending-request latch, the same "queue, don't drop" idiom already used by memory_manager's own pf_pending register (ERR-0006). Verified (Verilator): 4/4 PASS with 2 slots genuinely contending for one real PSRAM port (444 cycles). No regression on M4's own testbench. Real synthesis + nextpnr-ecp5 P&R (no harness needed - real PSRAM pins keep the top-level at 157 pins): 0 problems, Fmax 142.45 MHz, PASS at 80MHz. Arbitration policy is fixed lowest-index priority, not fairness- balanced (DEC-0010) - consistent with every other "simplest correct policy first" scheduling choice in this roadmap, revisited only if M9's real measurement shows starvation matters. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0010)/ experiments (EXP-0009)/errors (ERR-0008)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
@@ -103,3 +103,17 @@ uses 32/72 (44%), consistent with DEC-0005's finding that DSP, not
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LUT/FF, is the first resource to saturate as concurrency grows (M2's
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own N_PROCESSORS=8 measurement: 88%). BRAM=0 on both is expected --
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M3's buffers are not wired into dataflow_core yet (DEC-0009).
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[2026-09-05] M8 Neural Multiprocessor top (real standalone synthesis +
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P&R, no harness needed -- real PSRAM pins keep the bare top-level
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pin count at 157, under the TRELLIS_IO budget)
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| Module (config) | Fmax (POST-P&R) | LUT4 | CCU2C | FF | DSP | BRAM |
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|--------------------------------------|------------------|------|-------|------|-----|------|
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| neural_multiprocessor (N_SLOTS=2) | 142.45 MHz | 3145 | 388 | 3659 | 16 | 0 |
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Compare to M7's dataflow_core alone (N_SLOTS=2): 165.15 MHz / LUT4=2127
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/ CCU2C=248 / FF=2505 / DSP=16. Adding the real V1 PSRAM chain +
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slot_mem_arbiter costs ~1000 LUT4/140 CCU2C/1150 FF and drops Fmax by
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~23 MHz (165.15 -> 142.45) -- both real, measured costs of real PSRAM
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integration, not assumed.
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@@ -521,3 +521,64 @@ oversight.
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STATUS:
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ACCEPTED
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DEC-0010
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DATE: 2026-09-05
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DECISION:
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slot_mem_arbiter.v (M8) arbitrates dataflow_core's N_SLOTS independent
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Memory Backend Interface ports down to the ONE real PSRAM port using
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FIXED, lowest-port-index priority (not round-robin/least-loaded/
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fair-share), with a per-port single-entry pending-request latch (see
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errors.log ERR-0008) so a fire-and-forget request pulse arriving
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during contention is queued, never dropped.
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WHY:
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Fixed lowest-index priority is the same "first-found, simplest
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correct policy first" starting point already chosen for
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neural_director's first-free slot scheduling (decisions.log DEC-0007)
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and dependency_manager's first-ready dispatch -- consistent with this
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whole roadmap's own pattern of shipping the simplest policy that is
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provably correct, then revisiting fairness/throughput ONLY once real
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measured data (M9) shows it actually matters for a real workload.
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Under sustained heavy contention a low-index slot COULD in principle
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starve a higher-index one (an unfair, but not incorrect, outcome);
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this is an honestly-acknowledged limitation of a first cut, not an
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oversight. The pending-latch discipline (ERR-0008) is not a policy
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choice but a correctness requirement -- discovered empirically via
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real concurrent-slot simulation, not designed in from the start (an
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example of the mandate's own point, §22/§30: real measurement finds
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real problems that a purely theoretical design would not).
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EVIDENCE:
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hardware/v2/sim/tb_neural_multiprocessor.v -- 4/4 PASS with N_SLOTS=2
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genuinely concurrent slots (node0/node1, no dependencies, dispatched
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back-to-back) contending for the one real PSRAM port through the real
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V1 backend chain; both complete correctly and node2 (depends on both)
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dispatches only once they genuinely do. No starvation observed in this
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small a test (2 slots, one short job each) -- a real starvation
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measurement would need a longer-running, higher-N_SLOTS workload,
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deferred to M9's own benchmark.
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ALTERNATIVES:
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1. Round-robin or least-recently-served fairness now. Rejected: no
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measured evidence yet (M9 not run) that fixed-priority starvation
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is a real problem for the graph workloads this system targets --
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adding fairness logic before a measured need is speculative
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complexity, the same reasoning DEC-0007 already applied to
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neural_director's own scheduling policy.
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2. Give each slot its own dedicated PSRAM port (no arbitration at
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all). Rejected: real PSRAM hardware has exactly one physical port
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(the whole reason this module exists) -- not an option on real
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hardware, only in simulation.
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RESULT:
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slot_mem_arbiter.v as implemented: fixed lowest-index priority,
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single-entry pending-request latch per port (mandatory for
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correctness, not a policy choice). Fairness/throughput-aware
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scheduling explicitly deferred to a future measurement-driven
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decision, not missing by oversight.
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STATUS:
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ACCEPTED
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@@ -206,3 +206,27 @@ decision: see decisions.log DEC-0009 (M3 buffers not wired in yet, no
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next_action: M8 -- PSRAM integration. Wire the real (unmodified) V1
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PSRAM backend chain through dataflow_core end-to-end and measure/
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design whatever N_SLOTS>1 arbitration real contention requires.
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[2026-09-05] M8 -- hardware/v2/rtl/neural_multiprocessor.v +
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hardware/v2/rtl/slot_mem_arbiter.v
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reason: roadmap M8 -- "Integrare il controller V1 senza modificarlo
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inizialmente. Misurare il comportamento reale." dataflow_core.v (M7,
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untouched) now shares the real, unmodified V1 PSRAM backend chain
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(int8_memory_access -> memory_interface -> psram_controller) across
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N_SLOTS genuinely concurrent memory_manager instances, via a new
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generic N-port arbiter inspired by (not copied from) V1's own
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mem_arbiter.v.
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result: real concurrent-slot simulation immediately surfaced a real
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bug (errors.log ERR-0008: the byte-level backend's fire-and-forget
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request pulse gets silently dropped by a naive arbiter under
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contention) -- fixed with a pending-request latch. After the fix:
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4/4 test PASS (2 concurrent slots genuinely contending for one real
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PSRAM port, 444 cycles). Real synthesis: 0 problems, LUT4=3145/
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CCU2C=388/FF=3659/DSP=16, real Fmax 142.45 MHz (PASS at 80MHz, no
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harness needed -- real PSRAM pins keep the top-level pin count at
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157). No regression on M4's own testbench.
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errors: see errors.log ERR-0008 (real RTL bug, found and fixed).
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decision: see decisions.log DEC-0010 (fixed-priority arbitration, no
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fairness yet -- deferred pending real measured need).
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next_action: M9 -- Full benchmark (§32): V1-vs-V2 comparison table,
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every number labeled THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.
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@@ -203,3 +203,54 @@ WORKAROUND: set the parameter on the TOP module being synthesized
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STATUS: WORKED AROUND. A build-script ordering detail, not a defect in
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dataflow_core.v or harness_dataflow_core.v themselves -- noted here
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so a future N_SLOTS sweep (M9/M10) does not re-trip over it.
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ERR-0008 (real RTL bug in the first draft of hardware/v2/rtl/slot_mem_arbiter.v, FOUND AND FIXED)
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DATE: 2026-09-05
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MODULE: hardware/v2/rtl/slot_mem_arbiter.v (M8, new)
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SYMPTOM: hardware/v2/sim/tb_neural_multiprocessor.v -- node0 (slot 0)
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completes correctly (result=48), but node1 (slot 1, dispatched
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concurrently to node0) never completes; its byte-level backend
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request appears to simply vanish, and the slot hangs forever
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(watchdog timeout at 20000 cycles, result stays 0).
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ROOT CAUSE: memory_manager.v/prefetch_engine.v's own byte-level
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backend protocol (mem_req/mem_wr/mem_addr/mem_wdata/mem_rdata/
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mem_ready) is FIRE-AND-FORGET: mem_req is asserted for exactly ONE
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clock cycle per byte transaction, with no separate "request
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accepted" acknowledgment -- only `mem_ready` (transaction
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COMPLETION) exists. M4's own testbench (tb_memory_manager.v) never
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exposed this because it connects exactly ONE memory_manager directly
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to int8_memory_access, which is always idle and therefore always
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able to accept that single pulse the instant it fires. The first
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arbiter draft only granted a port while its s_req was LIVE that same
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cycle -- if slot 1's one-cycle pulse arrived on a cycle where the
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arbiter was already owned by slot 0, the pulse was gone the very
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next cycle with no record of it ever having happened, and slot 1's
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prefetch_engine sat in ST_READ_X/ST_READ_W waiting forever for a
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mem_ready that could never arrive (its request never reached
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int8_memory_access at all).
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DIAGNOSIS METHOD: ran the M8 testbench, observed node0 (whichever slot
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the Director happened to grant the shared bus to first) complete
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while node1 (the other, concurrently-dispatched slot) hung; traced
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the fire-and-forget nature of mem_req directly in
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prefetch_engine.v's own state machine (`mem_req <= 1'b1;` appearing
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only inside single-cycle state-transition branches, unconditionally
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cleared to 0 every other cycle) -- confirmed the arbiter's naive
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"grant only while req is live" logic could not possibly catch a
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pulse arriving during contention.
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FIX: every incoming s_req pulse is now LATCHED into a per-port
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`pending` register (capturing wr/addr/wdata the same cycle),
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regardless of arbiter state -- the same single-entry "queue, don't
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drop the request" idiom already used by memory_manager's own
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pf_pending register (ERR-0006 fix #1). Grants are drawn from
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`pending`, never from a live s_req directly. This adds a uniform
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minimum 1-cycle latency to every byte transaction (a real, honestly
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measured cost of sharing one PSRAM port across N_SLOTS -- see
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timing.log/benchmark.log EXP-0009), but never drops a request
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regardless of contention.
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VERIFICATION: hardware/v2/sim/tb_neural_multiprocessor.v -- 4/4 PASS
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after the fix (444 cycles end-to-end, vs the buggy draft's 20000-
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cycle watchdog timeout). hardware/v2/sim/tb_memory_manager.v (M4,
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untouched) re-run unchanged -- still 3/3 PASS, confirming the fix is
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entirely contained inside the new arbiter module.
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STATUS: FIXED, verified end-to-end with the real (unmodified) V1
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PSRAM backend chain and real concurrent multi-slot contention.
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@@ -401,3 +401,35 @@ next_action: M8 -- PSRAM integration. Wire the real (unmodified) V1
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psram_controller) end-to-end through dataflow_core, and design/
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measure whatever N_SLOTS>1 arbitration across ONE physical PSRAM
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port actually requires.
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[2026-09-05] EXP-0009 -- hardware/v2/rtl/neural_multiprocessor.v (M8,
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real PSRAM integration)
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test: hardware/v2/sim/tb_neural_multiprocessor.v -- same 3-node DAG as
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EXP-0008, now routed through the REAL, UNMODIFIED V1 PSRAM backend
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chain shared across N_SLOTS=2 genuinely concurrent memory_manager
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instances via the new slot_mem_arbiter.v
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL:
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SIMULATED: 4/4 PASS after fixing a real dropped-request bug in the
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arbiter's first draft (errors.log ERR-0008) -- 444 cycles
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end-to-end. hardware/v2/sim/tb_memory_manager.v (M4, untouched)
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re-confirmed 3/3 PASS, no regression.
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SYNTHESIZED (real standalone top-level, no harness needed -- 157
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port bits, real PSRAM pins keep it under the TRELLIS_IO budget):
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0 CHECK problems, LUT4=3145, CCU2C=388, TRELLIS_FF=3659,
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MULT18X18D=16, DP16KD=0.
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POST-P&R (real): Fmax=142.45 MHz -- PASS at 80MHz.
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errors: one real RTL bug (errors.log ERR-0008) -- the first arbiter
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draft silently dropped a request pulse arriving during contention;
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fixed with a per-port pending-request latch, the same "queue, don't
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drop" idiom already used by memory_manager's own pf_pending register
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(ERR-0006).
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decision: see decisions.log DEC-0010 (fixed lowest-index priority
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arbitration, not fairness-balanced -- consistent with every other
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scheduling policy chosen so far in this roadmap; revisit only if
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M9's real measurement shows starvation actually matters).
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next_action: M9 -- Full benchmark. Produce the V1-vs-V2 comparison
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table mandated by §32 (Fmax, LUT, FF, DSP, BRAM, MAC/cycle,
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cycles/neuron, neurons/s, stall %, memory/processor utilization,
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effective MAC/s), each number labeled THEORETICAL/SIMULATED/
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SYNTHESIZED/POST-P&R per §30.
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@@ -75,3 +75,23 @@ PASS/FAIL: 4/4 PASS -- node0=48, node1=8 (both real neural_processor
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dependency-manager-to-director wake-up loop closes correctly
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end-to-end with real hardware in between, not just in isolation
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(M6's own testbench already proved the wake-up logic alone)
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[2026-09-05] EXP-0009 -- hardware/v2/sim/tb_neural_multiprocessor.v
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test: same 3-node DAG as EXP-0008 (node0/node1 independent, node2
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depends on both), routed through neural_multiprocessor.v (M8): the
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REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access ->
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memory_interface -> psram_controller -> psram_model) shared across
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N_SLOTS=2 genuinely concurrent memory_manager instances via the new
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slot_mem_arbiter.v -- node0 and node1 are registered back-to-back
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with no dependencies, so both dispatch to their slots essentially
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simultaneously and genuinely contend for the one real PSRAM port.
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS after fixing a real dropped-request bug in the
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first arbiter draft (errors.log ERR-0008) -- node0=48, node1=8
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(concurrent, real PSRAM, real arbitration), node2=40 dispatched only
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after both genuinely completed. 444 cycles end-to-end (vs 20000-cycle
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watchdog timeout with the buggy first draft, where node1's request
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was silently dropped and its slot hung forever).
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regression: hardware/v2/sim/tb_memory_manager.v (M4) re-run unchanged
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(no M4 file touched) -- still 3/3 PASS, identical cycle counts
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(446/166/728), confirming slot_mem_arbiter.v is purely additive.
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@@ -63,3 +63,16 @@ CHECK: 0 problems on both configs (same 32 benign "multiple conflicting
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deliberately NOT instantiated inside dataflow_core yet (decisions.log
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DEC-0009). DSP scales exactly 8/slot (matches P_IN=8, consistent with
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every prior per-processor DSP measurement since M1/M2).
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[2026-09-05] EXP-0009 -- neural_multiprocessor (M8, N_SLOTS=2, real
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standalone top-level synthesis -- no timing harness needed: real PSRAM
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pins replace dataflow_core's wide per-slot arrays, total 157 port bits,
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well under the LFE5U-45F-8BG381's ~245 TRELLIS_IO budget)
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LUT4=3145 CCU2C=388 TRELLIS_FF=3659 MULT18X18D=16 DP16KD=0
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TRELLIS_DPR16X4=45 (small LUT-based distributed RAM, inferred from
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neural_director's shallow QUEUE_DEPTH-entry job queue -- not BRAM,
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same primitive class already seen in M7's own harness stat)
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$_TBUF_=16 (tri-state buffers for the bidirectional psram_dq bus,
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from V1's own unmodified psram_controller.v)
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CHECK: 0 problems (same 32 benign "multiple conflicting drivers for
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...neural_processor.\gi" warnings documented since EXP-0001).
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@@ -65,3 +65,8 @@ Fmax drops as N_SLOTS grows (more concurrent memory_manager+
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neural_processor instances competing for the same routing fabric
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around the shared neural_director/dependency_manager hub) -- both
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configs still clear the 80MHz target with real margin.
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[2026-09-05] EXP-0009 -- neural_multiprocessor (M8, N_SLOTS=2, real
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standalone synthesis, no harness needed), real nextpnr-ecp5 --45k
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--package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 142.45 MHz -- PASS at 80MHz (real place&route measurement)
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