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docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq

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New brief (N=8 timing closure, LFE5U-85F retarget, 4/8/16 x 1/2-bank SDRAM
sweep). Phase 0: no RTL changes, only measure the current baseline.

ERR-0030: constraints/v2_unified.lpf's FREQUENCY PORT "clk" was still 80MHz,
a leftover from the STEP19 freeze, never updated to the project's real
64MHz target -- fixed (LPF only, zero RTL/datapath effect).

ERR-0031 (bigger one): the first two synthesis attempts targeted
nms_neural_multiprocessor_sdram_unified.v, which is NOT the real
board-level top -- it's an obsolete wrapper only exercised by one
testbench now. The real target is fpga_neural_v2_top.v (adds the real
PLL, reset_sync, spi_host_bridge, and a second arbitration level), which
is what actually goes through synthesis+P&R for hardware. Re-targeted
correctly, matched against constraints/v2_board_top.lpf (all 17 ports
real-ball-assigned).

An N_SLOTS=8 P&R attempt against the WRONG (wrapper) target ran for 2h42m
without converging on a single seed; discarded rather than trusted.
N_SLOTS=8 baseline deferred by explicit user request until N_SLOTS=4 is
fully understood -- re-attempt against the correct fpga_neural_v2_top
target with an agreed time budget.

Result (EXP-0049, fresh 8-seed nextpnr-ecp5 P&R, real pins): N_SLOTS=4
8/8 PASS at 64MHz, worst-seed 81.20MHz, mean 91.05MHz. Higher than
DEC-0042's historical worst/best (64.55/77.21MHz) despite identical RTL --
disclosed, unresolved (leading hypothesis: nextpnr-ecp5 build/version
difference), adopted as the operative baseline for this session's
toolchain going forward. Full writeup in errors.log/timing.log/
experiments.log (EXP-0049).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
michele
2026-09-15 20:28:16 +00:00
co-authored by Claude Sonnet 5
parent 8b8ca239ca
commit 685a4d6cfe
21 changed files with 573188 additions and 1290227 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v2/constraints/v2_unified.lpf
+9 -1
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@@ -32,7 +32,15 @@
BLOCK ASYNCPATHS;
BLOCK RESETPATHS;
FREQUENCY PORT "clk" 80 MHZ;
// Updated from the STEP19 freeze's original 80 MHz to the project's
// current 64 MHz target (see decisions.log DEC-0038+/errors.log
// ERR-0029/DEC-0042): this file's own FREQUENCY directive was never
// bumped down when the achievable target moved from 80 to 64 MHz,
// silently making every nextpnr PASS/FAIL label using this LPF report
// against the wrong, stale bar (only the achieved MHz number itself
// was real; the FAIL/PASS annotation next to it was not) -- see
// errors.log for the disclosed fix.
FREQUENCY PORT "clk" 64 MHZ;
LOCATE COMP "clk" SITE "H5";
IOBUF PORT "clk" IO_TYPE=LVCMOS33;
hardware/v2/logs/errors.log
+91
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@@ -1463,3 +1463,94 @@ trace). N_SLOTS=4 remains 8/8 PASS at 64MHz but with reduced margin,
disclosed above -- flagged, not hidden, per this project's own real-
data-only reporting standard. File changed: hardware/v2/nms/rtl/
sdram_unified_backend.v.
ERR-0030 -- constraints/v2_unified.lpf's FREQUENCY PORT "clk" directive
was stale at 80 MHz, silently mislabeling every real-pin-constrained
nextpnr PASS/FAIL result against the wrong bar
DATE: 2026-09-15
CONTEXT: new brief to close N=8 timing, retarget to LFE5U-85F, and
sweep 4/8/16 processors x 1/2 SDRAM banks. Phase 0 baseline: re-ran
nms_neural_multiprocessor_sdram_unified (N_SLOTS=4/8) through the real
existing flow. First attempt used `--lpf-allow-unconstrained` with NO
`--lpf` file at all (no real pin locations) -- achieved Fmax came out
implausibly high (N=4 worst-seed 86.86MHz, mean ~100MHz across 8
seeds) versus the last real production baseline (DEC-0042: N=4
worst-seed 64.55MHz). Re-ran the same N=4 netlist WITH the real
`constraints/v2_unified.lpf` (real H5/B4 clk/rst balls, real SDRAM
balls) -- achieved Fmax dropped to a much more plausible 70.03MHz
(seed0), confirming free/unconstrained IO placement was the source of
the gap, not an RTL difference.
ROOT CAUSE (real, found while investigating): `v2_unified.lpf` line 35
still reads `FREQUENCY PORT "clk" 80 MHZ` from its original STEP19
freeze -- never updated when the project's achievable/target bar moved
to 64MHz (DEC-0038 onward). Passing `--freq 64` on the nextpnr-ecp5
command line does NOT override this: nextpnr uses the LPF's own
explicit per-port FREQUENCY constraint for any port that has one, and
`--freq` only supplies a default for ports left unconstrained. Real
effect verified: with the LPF loaded, nextpnr-ecp5 reported "70.03 MHz
(FAIL at 80.00 MHz)" even with `--freq 64` passed on the command line --
the achieved-MHz number itself was real, but the PASS/FAIL label next
to it was being judged against the wrong, stale 80MHz bar the whole
time this LPF has been used for any 64MHz-era measurement.
FIX: updated `constraints/v2_unified.lpf` line 35 to `FREQUENCY PORT
"clk" 64 MHZ`, with a comment explaining why. This does not touch any
physical pin/ball assignment (SDRAM/clk/rst LOCATE COMP lines are
unchanged) and has zero effect on RTL/datapath semantics -- it only
corrects which frequency nextpnr-ecp5 optimizes/labels against.
OPEN QUESTION (disclosed, not resolved here): it is not established
whether earlier 64MHz-labeled results in decisions.log (e.g. DEC-0042)
were themselves generated WITH this same stale-80MHz LPF (in which
case their own PASS/FAIL labels would have the same defect, though
their raw achieved-MHz numbers would remain valid and comparable) or
via a different invocation (e.g. no LPF, matching this session's first,
discarded attempt). Re-verify against a fresh N=4 8-seed sweep with the
corrected LPF before treating DEC-0042's specific pass-count (8/8) as
still authoritative under real pin constraints.
ERR-0031 -- Phase 0 baseline was being measured against the wrong
top-level module (nms_neural_multiprocessor_sdram_unified.v, an
obsolete testbench-only wrapper), giving falsely-optimistic Fmax
DATE: 2026-09-15
CONTEXT: same brief as ERR-0030. After fixing the stale 80MHz LPF
constraint, re-ran the N=4 8-seed sweep against
`nms_neural_multiprocessor_sdram_unified.v` + `constraints/
v2_unified.lpf`: 8/8 PASS at 64MHz, worst-seed 84.91MHz, mean 92.65MHz
-- still implausibly high, HIGHER than DEC-0042's own best-case seed
(77.21MHz), not just its worst.
ROOT CAUSE (found by re-reading decisions.log DEC-0038 entry, which
explicitly documents this): `nms_neural_multiprocessor_sdram_unified.v`
is NOT instantiated by the real board-level top. Per decisions.log's
own prior finding (search "NOT instantiated by the real board-level
top"), `fpga_neural_v2_top.v` instantiates `nms_dataflow_core_sdram`
and `sdram_unified_backend` directly, bypassing this wrapper entirely.
The wrapper is only still used by one testbench
(`tb_nms_dstress_sdram_unified.v`) as a bit-exact regression oracle --
it was never the real synthesis target. `constraints/v2_unified.lpf`
itself says as much in its own superseding file's header
(`v2_board_top.lpf`: "This supersedes ... v2_unified.lpf"), which this
session missed on the first two attempts.
The real board top adds an EHXPLLL PLL (16MHz osc -> 64MHz internal),
a reset_sync POR synchronizer, a real spi_host_bridge (replacing the
wrapper's raw 110-pin reg_* testbench bus), and a SECOND arbitration
level (host SPI raw-memory port vs. compute AR stream) -- all real
logic and real routing congestion the wrapper never has, which is
exactly why the wrapper measured faster.
FIX: re-target synthesis+P&R to `hardware/v2/nms/rtl/
fpga_neural_v2_top.v` (chparam N_SLOTS) with `hardware/v2/constraints/
v2_board_top.lpf` (all 17 real ports ball-assigned; PLL's own
FREQUENCY_PIN_CLKI=16/FREQUENCY_PIN_CLKOP=64 attributes read
automatically by nextpnr-ecp5 for the internal clock domain, no manual
--freq needed). Sanity check, single seed: 72.23MHz achieved, PASS at
64MHz -- squarely inside DEC-0042/ERR-0029's real historical range
(60-77MHz), confirming this is now the right target.
LESSON: ERR-0030's fix (to v2_unified.lpf) was not wrong on its own
terms (the 80MHz value really was stale) but was applied to a file
that should not be used for this brief's baseline going forward --
`v2_unified.lpf` remains valid only for whoever still exercises the
`nms_neural_multiprocessor_sdram_unified.v` testbench wrapper, not for
any real hardware Fmax claim.
STATUS: Phase 0 N=4 baseline being re-measured now against the correct
target (fresh 8-seed sweep in progress). N=8 baseline deferred by user
request until N=4 is fully understood.
hardware/v2/logs/experiments.log
+24
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@@ -2901,3 +2901,27 @@ decision: ACCEPT the single-SDRAM architecture as the STEP19 hardware
operation) is fully achieved, and the timing regression is reported
as a real, unresolved CRITICAL item for follow-up (see DEC-0034),
not hidden or worked around by reverting to two chips.
EXP-0049 -- Phase 0 baseline for the new N=8-timing/85F-retarget/
SDRAM-bank sweep brief (2026-09-15)
config: fpga_neural_v2_top (real board-level top), N_SLOTS=4, RTL
bit-identical to DEC-0042's frozen state (no RTL changes)
action: real Yosys synthesis + fresh 8-seed nextpnr-ecp5 P&R, real
physical pins (constraints/v2_board_top.lpf), real PLL-derived 64MHz
internal clock domain
result: 8/8 PASS at 64MHz. Fmax worst=81.20MHz, mean=91.05MHz (full
per-seed numbers and utilization in synthesis.log/timing.log).
Resources: LUT4 6905/43848 (15%), DFF 6527/43848 (14%), MULT18X18D
32/72 (44%), DP16KD 0/108 (0%).
decision: adopted as the operative Phase-0 BASELINE row (see
timing.log for the disclosed, unresolved discrepancy vs DEC-0042's
own historical numbers, and STEP19-era experiments.log precedent
showing N=4 Fmax as high as 81.84MHz on a related pre-fix config --
this range is not without precedent in this project's own history).
N_SLOTS=8 baseline deferred by explicit user request after the wrong
synthesis target (obsolete nms_neural_multiprocessor_sdram_unified.v
wrapper, see ERR-0031) caused a 2h42m non-converging P&R run;
N_SLOTS=8 to be re-attempted against fpga_neural_v2_top with an
agreed time budget.
next_action: Phase 1 (N=8 timing fix) blocked on N_SLOTS=8 baseline;
in the meantime this N_SLOTS=4 baseline is committed to branch v21.
hardware/v2/logs/synthesis.log
+14
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@@ -122,3 +122,17 @@ N_SLOTS=4: LUT4=9158 CCU2C=698 TRELLIS_FF=7986 MULT18X18D=32 DP16KD=0
CHECK: 0 problems on all three (same benign warnings as always).
Resource cost is modest (activation_cache itself is small -- a
16-tile x 64-bit store plus N_SLOTS-way pending/hit logic).
[2026-09-15] EXP-0049 -- fpga_neural_v2_top (real board-level top,
N_SLOTS=4), real synthesis via the corrected flow (see errors.log
ERR-0030/ERR-0031)
LUT4=6905 (15%) DFF=6527 (14%) MULT18X18D=32/72 (44%) DP16KD=0/108
(0%) EHXPLLL=1/4 (25%) TRELLIS_IO=47/245 (19%)
CHECK: 0 problems. File list: dependency_manager.v, neural_director.v,
neural_processor.v, prefetch_engine.v, weight_prefetch_engine_wide.v,
nms_activation_replicated.v, nms_activation_fill_ctrl_v3.v,
nms_weight_packed.v, nms_memory_manager_stream_wide.v,
nms_dataflow_core_sdram.v, slot_mem_arbiter.v, slot_mem_arbiter_wide.v,
sdram_controller.v, sdram_unified_backend.v, ecp5_pll_sys_clk.v,
reset_sync.v, spi_host_bridge.v, fpga_neural_v2_top.v.
Log: hardware/v2/nms/synthesis/nms_multiproc_n4/yosys.log
hardware/v2/logs/timing.log
+48
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@@ -141,3 +141,51 @@ DEC-0015's own arbiter widening did. N_SLOTS=4 is no longer a passing
80MHz design point with the cache active -- see decisions.log
DEC-0016 for the full analysis and why N_SLOTS=2 (the recommended
default, DEC-0014) is unaffected in its own recommendation.
[2026-09-15] EXP-0049 -- fpga_neural_v2_top (real board-level top,
N_SLOTS=4), real nextpnr-ecp5 --45k --package CABGA381 --speed 8
--lpf hardware/v2/constraints/v2_board_top.lpf (real ball-assigned
pins; internal 64MHz clock domain derived from EHXPLLL's own
FREQUENCY_PIN_CLKI=16/CLKOP=64 attributes, no --freq needed), fresh
8-seed sweep
Fmax (clock net off sdram_clk/EHXPLLL CLKOP, PASS bar 64MHz): seed0
81.20, seed1 98.82, seed2 88.25, seed3 92.43, seed4 94.22, seed5 86.95,
seed6 96.01, seed7 90.55 MHz. n=8, worst=81.20 MHz, mean=91.05 MHz,
8/8 PASS at 64MHz.
BASELINE row for the new N=8-timing/85F-retarget/SDRAM-bank-sweep
brief (Phase 0). RTL is bit-identical to DEC-0042's own frozen N_SLOTS=4
production state (no RTL changes since, only docs commits) -- this
measurement is against the SAME dependency_manager.v pending_count fix
DEC-0042 itself introduced.
DISCLOSED, UNRESOLVED DISCREPANCY vs DEC-0042's own recorded N_SLOTS=4
@ 64MHz numbers (worst-seed 64.55MHz, best-seed 77.21MHz, 8/8 PASS):
this session's worst-seed (81.20MHz) exceeds DEC-0042's own best-seed.
Both this session's ERR-0030 (stale 80MHz LPF frequency) and ERR-0031
(wrong top-level target, the obsolete nms_neural_multiprocessor_
sdram_unified.v wrapper) were real, found-and-fixed mistakes made
earlier in this same session while trying to reproduce the baseline --
but after correcting BOTH (real fpga_neural_v2_top.v target, real
v2_board_top.lpf, verified 8/8 PASS at 64MHz, single-seed sanity check
of 72.23MHz independently reproduced close to DEC-0042's range before
this full 8-seed run), the full sweep still came out systematically
higher than DEC-0042's historical numbers. No further RTL/config
difference was found (same file list role, same default parameters:
N_NODES=16, MAX_TILES=16, QUEUE_DEPTH=8, PREFETCH_DISTANCE=8). Leading
hypothesis, NOT verified: nextpnr-ecp5 build/version difference between
this session's toolchain (OSS CAD Suite, nextpnr-0.11.1-27-g6030081a)
and whatever build produced DEC-0042's numbers (version not recorded
in any prior log entry) -- placer heuristics/effort can genuinely
differ across nextpnr releases for the same netlist+constraints.
DECISION: treat THIS session's 8-seed numbers (worst 81.20MHz, mean
91.05MHz, 8/8 PASS) as the operative Phase-0 BASELINE for judging
Phase 1 interventions going forward, since they are the ones this
session's own toolchain will keep reproducing -- but do not claim
DEC-0042's specific historical numbers are wrong; both may be real
under their own respective toolchains. See sweep_results.md (Phase 4)
BASELINE row.
STATUS: N_SLOTS=4 baseline established (8/8 PASS @ 64MHz, real
board-level top+constraints). N_SLOTS=8 baseline deferred (user
request, 2026-09-15) after an N=8 P&R run against the WRONG target
(the obsolete wrapper, since discarded) stalled for 2h42m without
converging on a single seed -- to be re-attempted against the correct
fpga_neural_v2_top target, with a time budget decided before re-running.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr.log
-552
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@@ -1,552 +0,0 @@
Info: Logic utilisation before packing:
Info: Total LUT4s: 4846/43848 11%
Info: logic LUTs: 2812/43848 6%
Info: carry LUTs: 996/43848 2%
Info: RAM LUTs: 692/ 5481 12%
Info: RAMW LUTs: 346/10962 3%
Info: Total DFFs: 6004/43848 13%
Info: Packing IOs..
Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2736 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x649504e0
Info: Device utilisation:
Info: TRELLIS_IO: 157/ 245 64%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6004/ 43848 13%
Info: TRELLIS_COMB: 5080/ 43848 11%
Info: TRELLIS_RAMW: 173/ 5481 3%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 6193 cells, random placement wirelen = 501683.
Info: at initial placer iter 0, wirelen = 18522
Info: at initial placer iter 1, wirelen = 15366
Info: at initial placer iter 2, wirelen = 14364
Info: at initial placer iter 3, wirelen = 13481
Info: Running main analytical placer, max placement attempts per cell = 16379226.
Info: at iteration #1, type ALL: wirelen solved = 13356, spread = 91775, legal = 102139; time = 0.14s
Info: at iteration #2, type ALL: wirelen solved = 20348, spread = 65450, legal = 76519; time = 0.10s
Info: at iteration #3, type ALL: wirelen solved = 24614, spread = 57698, legal = 66114; time = 0.09s
Info: at iteration #4, type ALL: wirelen solved = 28073, spread = 53999, legal = 65606; time = 0.10s
Info: at iteration #5, type ALL: wirelen solved = 28434, spread = 52381, legal = 65600; time = 0.10s
Info: at iteration #6, type ALL: wirelen solved = 29167, spread = 50620, legal = 63488; time = 0.11s
Info: at iteration #7, type ALL: wirelen solved = 29950, spread = 51283, legal = 63584; time = 0.10s
Info: at iteration #8, type ALL: wirelen solved = 30855, spread = 50533, legal = 61410; time = 0.10s
Info: at iteration #9, type ALL: wirelen solved = 31395, spread = 50508, legal = 60313; time = 0.09s
Info: at iteration #10, type ALL: wirelen solved = 32403, spread = 50131, legal = 61572; time = 0.11s
Info: at iteration #11, type ALL: wirelen solved = 32885, spread = 50204, legal = 61427; time = 0.10s
Info: at iteration #12, type ALL: wirelen solved = 33025, spread = 51042, legal = 62928; time = 0.10s
Info: at iteration #13, type ALL: wirelen solved = 33453, spread = 51250, legal = 60701; time = 0.08s
Info: at iteration #14, type ALL: wirelen solved = 33853, spread = 52032, legal = 64518; time = 0.09s
Info: HeAP Placer Time: 1.99s
Info: of which solving equations: 1.01s
Info: of which spreading cells: 0.18s
Info: of which strict legalisation: 0.46s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 204, wirelen = 60313
Info: at iteration #5: temp = 0.000000, timing cost = 150, wirelen = 54376
Info: at iteration #10: temp = 0.000000, timing cost = 136, wirelen = 52588
Info: at iteration #15: temp = 0.000000, timing cost = 133, wirelen = 51968
Info: at iteration #20: temp = 0.000000, timing cost = 133, wirelen = 51723
Info: at iteration #25: temp = 0.000000, timing cost = 133, wirelen = 51589
Info: at iteration #25: temp = 0.000000, timing cost = 133, wirelen = 51590
Info: SA placement time 4.18s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 48.70 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> <async> : 12.27 ns
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 18.50 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.64 ns
Info: Slack histogram:
Info: legend: * represents 51 endpoint(s)
Info: + represents [1,51) endpoint(s)
Info: [ -8033, -7035) |+
Info: [ -7035, -6037) |+
Info: [ -6037, -5039) |
Info: [ -5039, -4041) |
Info: [ -4041, -3043) |
Info: [ -3043, -2045) |
Info: [ -2045, -1047) |
Info: [ -1047, -49) |
Info: [ -49, 949) |+
Info: [ 949, 1947) |*+
Info: [ 1947, 2945) |*******+
Info: [ 2945, 3943) |***+
Info: [ 3943, 4941) |*****+
Info: [ 4941, 5939) |***********+
Info: [ 5939, 6937) |***************+
Info: [ 6937, 7935) |*********************+
Info: [ 7935, 8933) |*************************************+
Info: [ 8933, 9931) |************************************************************
Info: [ 9931, 10929) |***********************************************************+
Info: [ 10929, 11927) |****************************************************+
Info: Checksum: 0x7342e501
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 30507 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 31 968 | 31 968 | 29549| 0.24 0.24|
Info: 2000 | 131 1868 | 100 900 | 28655| 0.14 0.38|
Info: 3000 | 212 2787 | 81 919 | 27753| 0.13 0.51|
Info: 4000 | 270 3729 | 58 942 | 26815| 0.13 0.64|
Info: 5000 | 447 4552 | 177 823 | 26025| 0.11 0.75|
Info: 6000 | 500 5499 | 53 947 | 25084| 0.09 0.84|
Info: 7000 | 597 6368 | 97 869 | 24211| 0.12 0.96|
Info: 8000 | 696 7255 | 99 887 | 23327| 0.11 1.08|
Info: 9000 | 776 8174 | 80 919 | 22413| 0.10 1.18|
Info: 10000 | 825 9125 | 49 951 | 21464| 0.10 1.28|
Info: 11000 | 865 10085 | 40 960 | 20513| 0.10 1.38|
Info: 12000 | 917 11026 | 52 941 | 19566| 0.13 1.51|
Info: 13000 | 972 11968 | 55 942 | 18633| 0.08 1.59|
Info: 14000 | 1037 12887 | 65 919 | 17735| 0.11 1.70|
Info: 15000 | 1085 13823 | 48 936 | 16788| 0.08 1.78|
Info: 16000 | 1126 14775 | 41 952 | 15844| 0.09 1.87|
Info: 17000 | 1169 15711 | 43 936 | 14899| 0.08 1.96|
Info: 18000 | 1200 16627 | 31 916 | 13934| 0.09 2.05|
Info: 19000 | 1243 17551 | 43 924 | 12980| 0.08 2.12|
Info: 20000 | 1276 18433 | 33 882 | 12015| 0.08 2.20|
Info: 21000 | 1314 19344 | 38 911 | 11057| 0.06 2.26|
Info: 22000 | 1349 20244 | 35 900 | 10101| 0.08 2.35|
Info: 23000 | 1404 21102 | 55 858 | 9173| 0.06 2.41|
Info: 24000 | 1449 21998 | 45 896 | 8226| 0.11 2.52|
Info: 25000 | 1496 22909 | 47 911 | 7276| 0.06 2.59|
Info: 26000 | 1587 23817 | 91 908 | 6402| 0.15 2.74|
Info: 27000 | 1672 24732 | 85 915 | 5516| 0.08 2.81|
Info: 28000 | 1825 25579 | 153 847 | 4756| 0.18 2.99|
Info: 29000 | 1958 26446 | 133 867 | 3926| 0.10 3.09|
Info: 30000 | 2056 27326 | 98 880 | 3049| 0.15 3.24|
Info: 31000 | 2142 28190 | 86 864 | 2149| 0.25 3.49|
Info: 32000 | 2264 29037 | 122 847 | 1336| 0.37 3.86|
Info: 33000 | 2437 29828 | 173 791 | 612| 0.57 4.44|
Info: 33917 | 2655 30496 | 218 668 | 0| 1.12 5.56|
Info: Routing complete.
Info: Router1 time 5.56s
Info: Checksum: 0x198c1857
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.GEN_SLOT[0].u_mm.x_base_reg_TRELLIS_FF_Q_19.Q
Info: routing 0.89 1.29 Net u_dataflow_core.job_x_base_flat[19] (46,30) -> (46,33)
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:38.44-38.55
Info: logic 0.18 1.47 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: routing 0.00 1.47 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT (46,33) -> (46,33)
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
Info: logic 0.13 1.59 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.00 1.59 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1 (46,33) -> (46,33)
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
Info: logic 0.18 1.77 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.88 2.65 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1_D[3] (46,33) -> (47,36)
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.84 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z_1.F
Info: routing 1.01 3.84 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D[2] (47,36) -> (37,37)
Info: Sink u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.02 Source u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.F
Info: routing 0.52 4.54 Net u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_en_TRELLIS_FF_Q_DI_LUT4_Z_C[1] (37,37) -> (38,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.72 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info: routing 0.33 5.05 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D[1] (38,37) -> (38,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.23 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D.F
Info: routing 0.86 6.08 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z[1] (38,37) -> (36,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 6.44 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
Info: routing 0.00 6.44 Net $nextpnr_CCU2C_35$CIN (36,36) -> (36,36)
Info: Sink $nextpnr_CCU2C_35$CCU2_COMB0.FCI
Info: logic 0.33 6.77 Source $nextpnr_CCU2C_35$CCU2_COMB0.F
Info: routing 0.37 7.14 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0[4] (36,36) -> (38,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.32 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z_LUT4_Z.F
Info: routing 0.47 7.79 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[2] (38,36) -> (38,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D_1_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.97 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D_1_Z_LUT4_Z.F
Info: routing 0.90 8.87 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D_1_Z[1] (38,36) -> (34,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 9.23 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 9.23 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_FCI_INT (34,35) -> (34,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 9.23 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 9.23 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_CIN (34,35) -> (35,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.28 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_COMB0.FCO
Info: routing 0.00 9.28 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_FCI_INT (35,35) -> (35,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_COMB1.FCI
Info: logic 0.00 9.28 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1$CCU2_COMB1.FCO
Info: routing 0.00 9.28 Net $nextpnr_CCU2C_31$CIN (35,35) -> (35,35)
Info: Sink $nextpnr_CCU2C_31$CCU2_COMB0.FCI
Info: logic 0.33 9.61 Source $nextpnr_CCU2C_31$CCU2_COMB0.F
Info: routing 0.40 10.01 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT (35,35) -> (36,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D.D
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.18 10.19 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D.F
Info: routing 0.78 10.96 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D_Z_LUT4_Z_C[2] (36,33) -> (35,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.14 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z.F
Info: routing 1.01 12.15 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_C[1] (35,35) -> (33,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 12.50 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.50 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (33,33) -> (34,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.56 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 12.56 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,33) -> (34,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 12.56 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.56 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (34,33) -> (34,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.62 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 12.62 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,33) -> (34,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 12.62 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.62 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (34,33) -> (34,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.67 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 12.67 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (34,33) -> (34,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 12.67 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.67 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT_CIN (34,33) -> (34,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.73 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 12.73 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_FCI_INT (34,33) -> (34,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 12.73 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.73 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_CIN (34,33) -> (35,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_COMB0.FCO
Info: routing 0.00 12.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_FCI_INT (35,33) -> (35,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_COMB1.FCI
Info: logic 0.00 12.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1$CCU2_COMB1.FCO
Info: routing 0.00 12.78 Net $nextpnr_CCU2C_33$CIN (35,33) -> (35,33)
Info: Sink $nextpnr_CCU2C_33$CCU2_COMB0.FCI
Info: logic 0.33 13.11 Source $nextpnr_CCU2C_33$CCU2_COMB0.F
Info: routing 0.34 13.46 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_COUT (35,33) -> (37,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D.D
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.18 13.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B1_LUT4_Z_C_CCU2C_B1_COUT_LUT4_D.F
Info: routing 0.22 13.85 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C[2] (37,33) -> (37,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 14.03 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F
Info: routing 1.01 15.05 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1 (37,33) -> (35,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: logic 0.35 15.40 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 15.40 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,32) -> (35,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 15.46 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 15.46 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,32) -> (35,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 15.46 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 15.46 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,32) -> (36,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 15.51 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 15.51 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,32) -> (36,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 15.51 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 15.51 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,32) -> (36,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 15.57 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 15.57 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,32) -> (36,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 15.57 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 15.57 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,32) -> (36,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 15.63 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 15.63 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,32) -> (36,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 15.63 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 15.63 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,32) -> (36,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 15.68 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 15.68 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,32) -> (36,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 15.68 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 15.68 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN (36,32) -> (37,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 15.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 15.74 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (37,32) -> (37,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 15.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 15.74 Net $nextpnr_CCU2C_25$CIN (37,32) -> (37,32)
Info: Sink $nextpnr_CCU2C_25$CCU2_COMB0.FCI
Info: logic 0.33 16.07 Source $nextpnr_CCU2C_25$CCU2_COMB0.F
Info: routing 0.82 16.89 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR[2] (37,32) -> (46,31)
Info: Sink u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 17.07 Source u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.F
Info: routing 0.59 17.66 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B_Z (46,31) -> (41,29)
Info: Sink u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_21.CE
Info: setup 0.00 17.66 Source u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_21.CE
Info: 6.26 ns logic, 11.40 ns routing
Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: type curr total name
Info: source 0.00 0.00 Source reg_node_id[1]$tr_io.O
Info: routing 4.96 4.96 Net reg_node_id[1]$TRELLIS_IO_IN (90,44) -> (17,15)
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_C_LUT4_Z_1.C
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
Info: logic 0.18 5.14 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.88 6.02 Net reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0[2] (17,15) -> (18,14)
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C_LUT4_Z_2.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.20 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C_LUT4_Z_2.F
Info: routing 0.58 6.77 Net reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C[4] (18,14) -> (16,15)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 6.97 Source reg_ready_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info: routing 0.29 7.26 Net reg_ready_PFUMX_Z_C0_LUT4_Z_D[3] (16,15) -> (16,15)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.43 Source reg_ready_PFUMX_Z_C0_LUT4_Z.F
Info: routing 0.51 7.94 Net reg_ready_PFUMX_Z_C0[4] (16,15) -> (16,16)
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 8.13 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 1.25 9.38 Net reg_ready$TRELLIS_IO_OUT (16,16) -> (0,17)
Info: Sink reg_ready$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
Info: 0.93 ns logic, 8.45 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source reg_node_id[1]$tr_io.O
Info: routing 4.96 4.96 Net reg_node_id[1]$TRELLIS_IO_IN (90,44) -> (17,15)
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_C_LUT4_Z_1.C
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
Info: logic 0.18 5.14 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.88 6.02 Net reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0[2] (17,15) -> (18,14)
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C_LUT4_Z_2.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.20 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C_LUT4_Z_2.F
Info: routing 0.58 6.77 Net reg_ready_PFUMX_Z_C0_PFUMX_Z_1_C0_LUT4_Z_1_C[4] (18,14) -> (16,15)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 6.97 Source reg_ready_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info: routing 0.29 7.26 Net reg_ready_PFUMX_Z_C0_LUT4_Z_D[3] (16,15) -> (16,15)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.43 Source reg_ready_PFUMX_Z_C0_LUT4_Z.F
Info: routing 0.51 7.94 Net reg_ready_PFUMX_Z_C0[4] (16,15) -> (16,16)
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 8.13 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 1.31 9.44 Net reg_ready$TRELLIS_IO_OUT (16,16) -> (26,25)
Info: Sink reg_valid_LUT4_B.D
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
Info: logic 0.18 9.62 Source reg_valid_LUT4_B.F
Info: routing 1.47 11.09 Net reg_valid_LUT4_B_Z[2] (26,25) -> (16,17)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.27 Source u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.F
Info: routing 0.86 12.13 Net u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z_D[2] (16,17) -> (13,12)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 12.31 Source u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info: routing 0.39 12.70 Net u_dataflow_core.u_dep_mgr.node_resolved[12]_TRELLIS_FF_Q_LSR[1] (13,12) -> (13,12)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[50]_LUT4_B_Z_PFUMX_ALUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 12.88 Source u_dataflow_core.u_dep_mgr.node_producer_ids[50]_LUT4_B_Z_PFUMX_ALUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.72 13.60 Net u_dataflow_core.u_dep_mgr.node_producer_ids[50]_LUT4_B_Z_PFUMX_ALUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (13,12) -> (15,13)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_CE_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 13.78 Source u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_CE_LUT4_Z.F
Info: routing 0.58 14.36 Net u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_CE (15,13) -> (17,14)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_1.CE
Info: setup 0.00 14.36 Source u_dataflow_core.u_dep_mgr.node_state[12]_TRELLIS_FF_Q_1.CE
Info: 1.83 ns logic, 12.53 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_psram_ctrl.dq_oe_TRELLIS_FF_Q.Q
Info: routing 4.60 4.99 Net u_psram_ctrl.dq_oe (51,8) -> (11,64)
Info: Sink psram_dq[6]$tr_io$invert_T.A
Info: Defined in:
Info: hardware/v1/rtl/psram_controller.v:188.27-188.32
Info: logic 0.18 5.17 Source psram_dq[6]$tr_io$invert_T.F
Info: routing 0.86 6.03 Net psram_dq[6]$tr_io$invert_T$conn$Z (11,64) -> (11,71)
Info: Sink psram_dq[6]$tr_io.T
Info: 0.57 ns logic, 5.46 ns routing
ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 56.62 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> <async> : 9.38 ns
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 14.36 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.03 ns
Info: Slack histogram:
Info: legend: * represents 59 endpoint(s)
Info: + represents [1,59) endpoint(s)
Info: [ -5161, -4313) |+
Info: [ -4313, -3465) |+
Info: [ -3465, -2617) |
Info: [ -2617, -1769) |
Info: [ -1769, -921) |
Info: [ -921, -73) |
Info: [ -73, 775) |
Info: [ 775, 1623) |
Info: [ 1623, 2471) |+
Info: [ 2471, 3319) |*+
Info: [ 3319, 4167) |******+
Info: [ 4167, 5015) |*+
Info: [ 5015, 5863) |****+
Info: [ 5863, 6711) |*********+
Info: [ 6711, 7559) |**********+
Info: [ 7559, 8407) |*****************+
Info: [ 8407, 9255) |************************+
Info: [ 9255, 10103) |************************************************+
Info: [ 10103, 10951) |************************************************************
Info: [ 10951, 11799) |*******************************************************+
0 warnings, 1 error
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed0.log
+407
View File
@@ -0,0 +1,407 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 664680.
Info: at initial placer iter 0, wirelen = 4133
Info: at initial placer iter 1, wirelen = 3182
Info: at initial placer iter 2, wirelen = 3156
Info: at initial placer iter 3, wirelen = 3396
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3086, spread = 111145, legal = 129244; time = 0.60s
Info: at iteration #2, type ALL: wirelen solved = 12402, spread = 85214, legal = 103100; time = 0.49s
Info: at iteration #3, type ALL: wirelen solved = 20047, spread = 77846, legal = 92001; time = 0.41s
Info: at iteration #4, type ALL: wirelen solved = 24325, spread = 71204, legal = 88132; time = 0.43s
Info: at iteration #5, type ALL: wirelen solved = 26567, spread = 69032, legal = 86727; time = 0.44s
Info: at iteration #6, type ALL: wirelen solved = 28109, spread = 69033, legal = 82585; time = 0.39s
Info: at iteration #7, type ALL: wirelen solved = 30841, spread = 67648, legal = 81646; time = 0.42s
Info: at iteration #8, type ALL: wirelen solved = 31193, spread = 66517, legal = 82404; time = 0.42s
Info: at iteration #9, type ALL: wirelen solved = 32060, spread = 65855, legal = 81233; time = 0.36s
Info: at iteration #10, type ALL: wirelen solved = 32211, spread = 68190, legal = 82078; time = 0.33s
Info: at iteration #11, type ALL: wirelen solved = 34272, spread = 68133, legal = 82417; time = 0.35s
Info: at iteration #12, type ALL: wirelen solved = 34894, spread = 68739, legal = 80890; time = 0.38s
Info: at iteration #13, type ALL: wirelen solved = 35680, spread = 67838, legal = 84257; time = 0.42s
Info: at iteration #14, type ALL: wirelen solved = 35537, spread = 67735, legal = 82031; time = 0.33s
Info: at iteration #15, type ALL: wirelen solved = 35984, spread = 67845, legal = 81553; time = 0.43s
Info: at iteration #16, type ALL: wirelen solved = 36390, spread = 68149, legal = 83055; time = 0.39s
Info: at iteration #17, type ALL: wirelen solved = 37027, spread = 68348, legal = 81915; time = 0.33s
Info: HeAP Placer Time: 9.86s
Info: of which solving equations: 4.87s
Info: of which spreading cells: 0.77s
Info: of which strict legalisation: 2.12s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1092, wirelen = 80890
Info: at iteration #5: temp = 0.000000, timing cost = 1360, wirelen = 74943
Info: at iteration #10: temp = 0.000000, timing cost = 865, wirelen = 72983
Info: at iteration #15: temp = 0.000000, timing cost = 848, wirelen = 72519
Info: at iteration #20: temp = 0.000000, timing cost = 840, wirelen = 72349
Info: at iteration #25: temp = 0.000000, timing cost = 838, wirelen = 72261
Info: at iteration #28: temp = 0.000000, timing cost = 947, wirelen = 72239
Info: SA placement time 25.66s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 72.23 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.62 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.93 ns
Info: Slack histogram:
Info: legend: * represents 38 endpoint(s)
Info: + represents [1,38) endpoint(s)
Info: [ 1780, 2444) |+
Info: [ 2444, 3108) |
Info: [ 3108, 3772) |*+
Info: [ 3772, 4436) |****+
Info: [ 4436, 5100) |***+
Info: [ 5100, 5764) |******+
Info: [ 5764, 6428) |********+
Info: [ 6428, 7092) |********+
Info: [ 7092, 7756) |***************+
Info: [ 7756, 8420) |******************+
Info: [ 8420, 9084) |***********************+
Info: [ 9084, 9748) |*************************************+
Info: [ 9748, 10412) |********************************************+
Info: [ 10412, 11076) |************************************+
Info: [ 11076, 11740) |***********************************+
Info: [ 11740, 12404) |*****************************************+
Info: [ 12404, 13068) |************************************************************
Info: [ 13068, 13732) |****************************************************+
Info: [ 13732, 14396) |*****************************************************+
Info: [ 14396, 15060) |********************************************+
Info: Checksum: 0xc812ecb1
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39389 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 485 514 | 485 514 | 39053| 1.68 1.68|
Info: 2000 | 781 1218 | 296 704 | 38581| 1.21 2.89|
Info: 3000 | 1110 1889 | 329 671 | 38084| 0.94 3.83|
Info: 4000 | 1176 2823 | 66 934 | 37200| 0.54 4.37|
Info: 5000 | 1337 3662 | 161 839 | 36525| 0.77 5.13|
Info: 6000 | 1499 4500 | 162 838 | 35834| 0.76 5.89|
Info: 7000 | 1609 5390 | 110 890 | 35059| 0.48 6.37|
Info: 8000 | 1713 6286 | 104 896 | 34343| 0.54 6.92|
Info: 9000 | 1827 7172 | 114 886 | 33705| 0.60 7.51|
Info: 10000 | 1950 8049 | 123 877 | 32990| 0.51 8.03|
Info: 11000 | 2083 8916 | 133 867 | 32198| 0.56 8.59|
Info: 12000 | 2206 9793 | 123 877 | 31494| 0.74 9.33|
Info: 13000 | 2315 10684 | 109 891 | 30877| 0.76 10.09|
Info: 14000 | 2466 11533 | 151 849 | 30109| 0.41 10.50|
Info: 15000 | 2630 12369 | 164 836 | 29407| 0.45 10.95|
Info: 16000 | 2770 13229 | 140 860 | 28669| 0.35 11.30|
Info: 17000 | 2921 14078 | 151 849 | 27973| 0.44 11.74|
Info: 18000 | 3087 14912 | 166 834 | 27356| 0.80 12.54|
Info: 19000 | 3260 15739 | 173 827 | 26748| 0.73 13.27|
Info: 20000 | 3507 16492 | 247 753 | 26069| 0.43 13.70|
Info: 21000 | 3761 17238 | 254 746 | 25409| 0.70 14.40|
Info: 22000 | 3984 18015 | 223 777 | 24750| 0.44 14.84|
Info: 23000 | 4201 18798 | 217 783 | 24192| 0.50 15.34|
Info: 24000 | 4415 19582 | 214 784 | 23607| 0.51 15.85|
Info: 25000 | 4717 20279 | 302 697 | 23015| 0.41 16.26|
Info: 26000 | 5074 20914 | 357 635 | 22464| 0.51 16.77|
Info: 27000 | 5306 21660 | 232 746 | 21802| 0.46 17.24|
Info: 28000 | 5530 22393 | 224 733 | 21125| 0.50 17.74|
Info: 29000 | 5776 23095 | 246 702 | 20474| 0.54 18.28|
Info: 30000 | 6001 23819 | 225 724 | 19879| 0.45 18.73|
Info: 31000 | 6221 24551 | 220 732 | 19277| 0.46 19.19|
Info: 32000 | 6468 25232 | 247 681 | 18624| 0.54 19.73|
Info: 33000 | 6694 25961 | 226 729 | 17968| 0.70 20.43|
Info: 34000 | 6893 26690 | 199 729 | 17250| 0.51 20.94|
Info: 35000 | 7168 27398 | 275 708 | 16740| 0.68 21.62|
Info: 36000 | 7394 28150 | 226 752 | 16268| 0.58 22.20|
Info: 37000 | 7658 28855 | 264 705 | 15733| 0.64 22.85|
Info: 38000 | 7881 29593 | 223 738 | 15023| 0.62 23.46|
Info: 39000 | 8231 30237 | 350 644 | 14769| 2.80 26.26|
Info: 40000 | 8472 30962 | 241 725 | 14195| 0.64 26.90|
Info: 41000 | 8703 31655 | 231 693 | 13645| 0.74 27.64|
Info: 42000 | 8891 32416 | 188 761 | 13111| 0.77 28.41|
Info: 43000 | 9142 33137 | 251 721 | 12546| 0.64 29.06|
Info: 44000 | 9361 33874 | 219 737 | 12137| 0.64 29.69|
Info: 45000 | 9618 34588 | 257 714 | 11824| 0.79 30.48|
Info: 46000 | 9792 35377 | 174 789 | 11370| 0.84 31.32|
Info: 47000 | 10022 36101 | 230 724 | 10797| 0.59 31.91|
Info: 48000 | 10264 36852 | 242 751 | 10556| 1.06 32.96|
Info: 49000 | 10467 37595 | 203 743 | 9998| 0.80 33.76|
Info: 50000 | 10568 38425 | 101 830 | 9147| 0.42 34.18|
Info: 51000 | 10745 39225 | 177 800 | 8795| 0.85 35.03|
Info: 52000 | 11022 39947 | 277 722 | 8474| 1.26 36.28|
Info: 53000 | 11135 40746 | 113 799 | 7634| 0.31 36.60|
Info: 54000 | 11249 41556 | 114 810 | 6812| 0.39 36.99|
Info: 55000 | 11583 42222 | 334 666 | 6561| 1.05 38.04|
Info: 56000 | 11892 42906 | 309 684 | 6204| 1.39 39.43|
Info: 57000 | 12095 43697 | 203 791 | 5692| 0.72 40.15|
Info: 58000 | 12242 44550 | 147 853 | 5350| 0.57 40.72|
Info: 59000 | 12542 45243 | 300 693 | 4975| 0.81 41.52|
Info: 60000 | 12994 45791 | 452 548 | 4807| 1.39 42.91|
Info: 61000 | 13390 46395 | 396 604 | 4700| 1.26 44.18|
Info: 62000 | 13750 47035 | 360 640 | 4481| 1.16 45.34|
Info: 63000 | 13960 47823 | 210 788 | 3854| 0.55 45.89|
Info: 64000 | 14241 48542 | 281 719 | 3416| 0.83 46.72|
Info: 65000 | 14637 49146 | 396 604 | 3265| 1.71 48.44|
Info: 66000 | 14967 49816 | 330 670 | 3164| 1.51 49.94|
Info: 67000 | 15464 50319 | 497 503 | 2977| 1.76 51.71|
Info: 68000 | 15812 50971 | 348 652 | 2515| 0.98 52.69|
Info: 69000 | 16047 51719 | 235 748 | 1870| 0.60 53.28|
Info: 70000 | 16254 52401 | 207 682 | 1255| 1.19 54.47|
Info: 71000 | 16583 53018 | 329 617 | 945| 1.31 55.78|
Info: 72000 | 16844 53694 | 261 676 | 560| 1.21 56.99|
Info: 72686 | 16927 54202 | 83 508 | 0| 0.53 57.52|
Info: Routing complete.
Info: Router1 time 57.52s
Info: Checksum: 0x95485497
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q.Q
Info: routing 1.02 1.42 Net u_arbiter_wide.m_addr[1] (24,4) -> (23,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_1.B
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.60 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_1.F
Info: routing 0.51 2.11 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D[0] (23,8) -> (22,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.A
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.29 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.F
Info: routing 0.66 2.94 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (22,8) -> (22,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.12 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.45 3.58 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (22,7) -> (22,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.76 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.34 4.10 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (22,7) -> (21,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.28 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.76 5.04 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (21,7) -> (14,7)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.22 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.65 5.87 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (14,7) -> (15,5)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.05 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.17 6.22 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (15,5) -> (15,5)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 6.40 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.35 6.76 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (15,5) -> (15,5)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.94 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 2.81 9.75 Net u_host_arb.m_wr_LUT4_C_Z[3] (15,5) -> (5,45)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.93 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 2.09 12.02 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (5,45) -> (5,7)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 12.20 Source u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.F
Info: routing 0.12 12.32 Net u_sdram_backend.state_TRELLIS_FF_Q_3_DI (5,7) -> (5,7)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: setup 0.00 12.32 Source u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: 2.38 ns logic, 9.94 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source ext_rst_n$tr_io.O
Info: routing 0.77 0.77 Net ext_rst_n$TRELLIS_IO_IN (0,14) -> (2,14)
Info: Sink ext_rst_n_LUT4_D.D
Info: Defined in:
Info: hardware/v2/rtl/reset_sync.v:18.17-18.26
Info: logic 0.18 0.95 Source ext_rst_n_LUT4_D.F
Info: routing 2.72 3.67 Net ext_rst_n_LUT4_D_Z (2,14) -> (17,40)
Info: Sink ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: setup 0.29 3.96 Source ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: 0.47 ns logic, 3.49 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_2.Q
Info: routing 1.22 1.61 Net u_spi_bridge.byte_idx[2] (20,33) -> (19,29)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.79 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.34 2.13 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (19,29) -> (19,29)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.31 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 2.01 4.32 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (19,29) -> (14,56)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.50 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.80 5.30 Net spi_miso_LUT4_Z_B[2] (14,56) -> (15,57)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.48 Source spi_miso_LUT4_Z.F
Info: routing 1.53 7.01 Net spi_miso$TRELLIS_IO_OUT (15,57) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.89 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 81.20 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.96 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.01 ns
Info: Slack histogram:
Info: legend: * represents 40 endpoint(s)
Info: + represents [1,40) endpoint(s)
Info: [ 3309, 3890) |+
Info: [ 3890, 4471) |+
Info: [ 4471, 5052) |+
Info: [ 5052, 5633) |+
Info: [ 5633, 6214) |*+
Info: [ 6214, 6795) |******+
Info: [ 6795, 7376) |********+
Info: [ 7376, 7957) |******+
Info: [ 7957, 8538) |*********+
Info: [ 8538, 9119) |************+
Info: [ 9119, 9700) |****************+
Info: [ 9700, 10281) |**************************+
Info: [ 10281, 10862) |********************************+
Info: [ 10862, 11443) |*****************************************+
Info: [ 11443, 12024) |****************************************+
Info: [ 12024, 12605) |****************************************+
Info: [ 12605, 13186) |********************************************************+
Info: [ 13186, 13767) |*****************************************************+
Info: [ 13767, 14348) |************************************************************
Info: [ 14348, 14929) |**************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed1.log
+400
View File
@@ -0,0 +1,400 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 655670.
Info: at initial placer iter 0, wirelen = 3827
Info: at initial placer iter 1, wirelen = 3206
Info: at initial placer iter 2, wirelen = 3155
Info: at initial placer iter 3, wirelen = 3232
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3130, spread = 109014, legal = 126494; time = 0.52s
Info: at iteration #2, type ALL: wirelen solved = 13231, spread = 79811, legal = 97134; time = 0.48s
Info: at iteration #3, type ALL: wirelen solved = 18697, spread = 72512, legal = 87983; time = 0.49s
Info: at iteration #4, type ALL: wirelen solved = 23287, spread = 70058, legal = 86103; time = 0.43s
Info: at iteration #5, type ALL: wirelen solved = 26264, spread = 67123, legal = 84736; time = 0.46s
Info: at iteration #6, type ALL: wirelen solved = 27184, spread = 65554, legal = 81619; time = 0.49s
Info: at iteration #7, type ALL: wirelen solved = 28331, spread = 64778, legal = 81607; time = 0.41s
Info: at iteration #8, type ALL: wirelen solved = 28958, spread = 64602, legal = 80938; time = 0.40s
Info: at iteration #9, type ALL: wirelen solved = 29749, spread = 64076, legal = 81736; time = 0.37s
Info: at iteration #10, type ALL: wirelen solved = 30280, spread = 63693, legal = 79295; time = 0.35s
Info: at iteration #11, type ALL: wirelen solved = 30964, spread = 63529, legal = 80035; time = 0.37s
Info: at iteration #12, type ALL: wirelen solved = 31577, spread = 63732, legal = 80122; time = 0.42s
Info: at iteration #13, type ALL: wirelen solved = 32309, spread = 64165, legal = 81845; time = 0.39s
Info: at iteration #14, type ALL: wirelen solved = 33191, spread = 63991, legal = 80333; time = 0.39s
Info: at iteration #15, type ALL: wirelen solved = 33371, spread = 64423, legal = 79749; time = 0.37s
Info: HeAP Placer Time: 9.08s
Info: of which solving equations: 4.34s
Info: of which spreading cells: 0.63s
Info: of which strict legalisation: 2.18s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1848, wirelen = 79295
Info: at iteration #5: temp = 0.000000, timing cost = 1158, wirelen = 72990
Info: at iteration #10: temp = 0.000000, timing cost = 1636, wirelen = 71066
Info: at iteration #15: temp = 0.000000, timing cost = 1651, wirelen = 70413
Info: at iteration #20: temp = 0.000000, timing cost = 1556, wirelen = 70115
Info: at iteration #25: temp = 0.000000, timing cost = 1596, wirelen = 69993
Info: at iteration #30: temp = 0.000000, timing cost = 1545, wirelen = 69963
Info: at iteration #31: temp = 0.000000, timing cost = 1560, wirelen = 69952
Info: SA placement time 29.80s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 81.02 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 5.07 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.63 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 3282, 3871) |*+
Info: [ 3871, 4460) |**+
Info: [ 4460, 5049) |****+
Info: [ 5049, 5638) |*****+
Info: [ 5638, 6227) |*******+
Info: [ 6227, 6816) |*******+
Info: [ 6816, 7405) |********+
Info: [ 7405, 7994) |************+
Info: [ 7994, 8583) |****************************+
Info: [ 8583, 9172) |**************************************+
Info: [ 9172, 9761) |**********************************+
Info: [ 9761, 10350) |********************************************+
Info: [ 10350, 10939) |**************************************+
Info: [ 10939, 11528) |***************************+
Info: [ 11528, 12117) |***************************+
Info: [ 12117, 12706) |*****************************************+
Info: [ 12706, 13295) |*******************************************************+
Info: [ 13295, 13884) |************************************************************
Info: [ 13884, 14473) |**********************************************+
Info: [ 14473, 15062) |********************************************+
Info: Checksum: 0x9d313277
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39258 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 693 306 | 693 306 | 39096| 1.46 1.46|
Info: 2000 | 1126 873 | 433 567 | 39076| 1.53 2.99|
Info: 3000 | 1530 1469 | 404 596 | 38869| 1.26 4.25|
Info: 4000 | 2003 1996 | 473 527 | 38635| 1.30 5.54|
Info: 5000 | 2497 2502 | 494 506 | 38323| 0.91 6.46|
Info: 6000 | 2713 3286 | 216 784 | 37633| 0.88 7.34|
Info: 7000 | 2846 4153 | 133 867 | 36825| 0.52 7.86|
Info: 8000 | 2993 5006 | 147 853 | 36050| 0.44 8.31|
Info: 9000 | 3085 5914 | 92 908 | 35184| 0.67 8.97|
Info: 10000 | 3210 6789 | 125 875 | 34448| 0.63 9.61|
Info: 11000 | 3365 7634 | 155 845 | 33777| 0.54 10.15|
Info: 12000 | 3488 8511 | 123 877 | 32921| 0.45 10.60|
Info: 13000 | 3604 9395 | 116 884 | 32117| 0.61 11.21|
Info: 14000 | 3753 10246 | 149 851 | 31414| 0.43 11.65|
Info: 15000 | 3859 11140 | 106 894 | 30625| 0.52 12.16|
Info: 16000 | 3988 12011 | 129 871 | 29811| 0.50 12.66|
Info: 17000 | 4095 12904 | 107 893 | 28950| 0.46 13.12|
Info: 18000 | 4245 13754 | 150 850 | 28148| 0.42 13.54|
Info: 19000 | 4404 14595 | 159 841 | 27427| 0.53 14.07|
Info: 20000 | 4564 15435 | 160 840 | 26641| 0.47 14.54|
Info: 21000 | 4759 16240 | 195 805 | 25996| 0.53 15.06|
Info: 22000 | 4950 17049 | 191 809 | 25381| 0.61 15.68|
Info: 23000 | 5146 17853 | 196 804 | 24686| 0.46 16.13|
Info: 24000 | 5365 18634 | 219 781 | 24022| 0.56 16.69|
Info: 25000 | 5569 19430 | 204 796 | 23322| 0.57 17.26|
Info: 26000 | 5849 20129 | 280 699 | 22848| 1.00 18.25|
Info: 27000 | 6046 20912 | 197 783 | 22131| 0.48 18.74|
Info: 28000 | 6296 21636 | 250 724 | 21735| 0.42 19.16|
Info: 29000 | 6526 22357 | 230 721 | 21082| 0.46 19.61|
Info: 30000 | 6821 23023 | 295 666 | 20691| 0.79 20.41|
Info: 31000 | 7079 23727 | 258 704 | 20077| 0.46 20.87|
Info: 32000 | 7357 24421 | 278 694 | 19443| 0.47 21.34|
Info: 33000 | 7631 25119 | 274 698 | 18810| 0.58 21.93|
Info: 34000 | 7858 25850 | 227 731 | 18131| 0.46 22.39|
Info: 35000 | 8109 26568 | 251 718 | 17565| 0.62 23.01|
Info: 36000 | 8335 27283 | 226 715 | 16860| 0.58 23.58|
Info: 37000 | 8595 27983 | 260 700 | 16322| 0.66 24.24|
Info: 38000 | 8823 28692 | 228 709 | 15646| 0.55 24.79|
Info: 39000 | 9053 29430 | 230 738 | 14965| 0.70 25.49|
Info: 40000 | 9280 30155 | 227 725 | 14422| 0.51 26.00|
Info: 41000 | 9440 30940 | 160 785 | 13686| 0.70 26.70|
Info: 42000 | 9608 31707 | 168 767 | 12934| 0.42 27.12|
Info: 43000 | 9801 32456 | 193 749 | 12413| 0.58 27.70|
Info: 44000 | 10006 33208 | 205 752 | 11792| 0.76 28.46|
Info: 45000 | 10231 33961 | 225 753 | 11237| 0.63 29.09|
Info: 46000 | 10445 34688 | 214 727 | 10562| 0.63 29.72|
Info: 47000 | 10748 35366 | 303 678 | 10280| 1.19 30.91|
Info: 48000 | 10906 36162 | 158 796 | 9566| 0.64 31.55|
Info: 49000 | 11138 36866 | 232 704 | 9099| 0.81 32.35|
Info: 50000 | 11379 37605 | 241 739 | 8636| 1.15 33.50|
Info: 51000 | 11614 38353 | 235 748 | 8095| 0.74 34.25|
Info: 52000 | 11760 39156 | 146 803 | 7362| 0.42 34.66|
Info: 53000 | 11955 39884 | 195 728 | 6759| 0.56 35.22|
Info: 54000 | 12264 40569 | 309 685 | 6419| 1.09 36.31|
Info: 55000 | 12519 41299 | 255 730 | 6110| 1.07 37.38|
Info: 56000 | 12652 42139 | 133 840 | 5354| 0.35 37.73|
Info: 57000 | 12880 42905 | 228 766 | 4884| 0.78 38.51|
Info: 58000 | 13308 43477 | 428 572 | 4732| 1.40 39.91|
Info: 59000 | 13659 44126 | 351 649 | 4477| 1.03 40.94|
Info: 60000 | 13934 44849 | 275 723 | 4173| 1.05 41.99|
Info: 61000 | 14150 45633 | 216 784 | 3535| 0.54 42.54|
Info: 62000 | 14543 46240 | 393 607 | 3185| 1.17 43.71|
Info: 63000 | 14992 46791 | 449 551 | 2965| 1.31 45.01|
Info: 64000 | 15372 47411 | 380 620 | 2691| 1.33 46.34|
Info: 65000 | 15705 48078 | 333 667 | 2320| 0.83 47.17|
Info: 66000 | 15884 48850 | 179 772 | 1640| 0.62 47.79|
Info: 67000 | 16167 49509 | 283 659 | 1310| 1.04 48.83|
Info: 68000 | 16364 50216 | 197 707 | 835| 0.77 49.60|
Info: 69000 | 16564 50946 | 200 730 | 461| 0.74 50.34|
Info: 69905 | 16847 51501 | 283 555 | 0| 1.00 51.34|
Info: Routing complete.
Info: Router1 time 51.34s
Info: Checksum: 0xfd994332
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_23.Q
Info: routing 0.78 1.17 Net u_arbiter_wide.m_addr[24] (25,2) -> (24,5)
Info: Sink u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.A
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.36 Source u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.F
Info: routing 0.60 1.96 Net u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z_D[3] (24,5) -> (24,5)
Info: Sink u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.14 Source u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z.F
Info: routing 0.64 2.78 Net u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z[3] (24,5) -> (23,5)
Info: Sink u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.96 Source u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D.F
Info: routing 0.45 3.41 Net u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z[3] (23,5) -> (23,5)
Info: Sink u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.59 Source u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.63 4.22 Net u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z[3] (23,5) -> (25,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.41 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1.F
Info: routing 0.90 5.30 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[1] (25,5) -> (15,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.B
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.48 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.34 5.83 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (15,7) -> (15,7)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 6.01 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.34 6.35 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (15,7) -> (15,7)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.53 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 1.52 8.05 Net u_host_arb.m_wr_LUT4_C_Z[3] (15,7) -> (6,17)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.23 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 1.89 10.12 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (6,17) -> (10,44)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_5.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 10.12 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_5.CE
Info: 2.02 ns logic, 8.10 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 3.06 3.06 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (12,2)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.24 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.63 3.88 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D[2] (12,2) -> (14,2)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.05 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z.F
Info: routing 0.12 4.17 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI (14,2) -> (14,2)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35.DI
Info: setup 0.00 4.17 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35.DI
Info: 0.36 ns logic, 3.81 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 0.94 1.33 Net u_spi_bridge.byte_idx[3] (24,42) -> (23,38)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.51 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.62 2.14 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (23,38) -> (23,38)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.32 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.42 3.73 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (23,38) -> (16,45)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.91 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.50 4.41 Net spi_miso_LUT4_Z_B[2] (16,45) -> (17,45)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.59 Source spi_miso_LUT4_Z.F
Info: routing 2.20 6.80 Net spi_miso$TRELLIS_IO_OUT (17,45) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.68 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 98.82 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.17 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.80 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 5506, 5977) |+
Info: [ 5977, 6448) |+
Info: [ 6448, 6919) |****+
Info: [ 6919, 7390) |******+
Info: [ 7390, 7861) |********+
Info: [ 7861, 8332) |*******+
Info: [ 8332, 8803) |********+
Info: [ 8803, 9274) |************+
Info: [ 9274, 9745) |****************+
Info: [ 9745, 10216) |******************************+
Info: [ 10216, 10687) |*********************************+
Info: [ 10687, 11158) |*********************************+
Info: [ 11158, 11629) |*************************************+
Info: [ 11629, 12100) |******************************************+
Info: [ 12100, 12571) |*****************************+
Info: [ 12571, 13042) |***************************+
Info: [ 13042, 13513) |******************************************+
Info: [ 13513, 13984) |************************************************************
Info: [ 13984, 14455) |************************************************************
Info: [ 14455, 14926) |*****************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed2.log
+410
View File
@@ -0,0 +1,410 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 655030.
Info: at initial placer iter 0, wirelen = 3962
Info: at initial placer iter 1, wirelen = 3211
Info: at initial placer iter 2, wirelen = 3093
Info: at initial placer iter 3, wirelen = 2985
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 2941, spread = 115246, legal = 127776; time = 0.49s
Info: at iteration #2, type ALL: wirelen solved = 13107, spread = 84959, legal = 96142; time = 0.43s
Info: at iteration #3, type ALL: wirelen solved = 19618, spread = 74146, legal = 85837; time = 0.43s
Info: at iteration #4, type ALL: wirelen solved = 25379, spread = 70995, legal = 85148; time = 0.41s
Info: at iteration #5, type ALL: wirelen solved = 26790, spread = 69359, legal = 85551; time = 0.43s
Info: at iteration #6, type ALL: wirelen solved = 29110, spread = 66873, legal = 82846; time = 0.38s
Info: at iteration #7, type ALL: wirelen solved = 29658, spread = 66046, legal = 81698; time = 0.37s
Info: at iteration #8, type ALL: wirelen solved = 30830, spread = 69832, legal = 82932; time = 0.41s
Info: at iteration #9, type ALL: wirelen solved = 33846, spread = 69400, legal = 86531; time = 0.41s
Info: at iteration #10, type ALL: wirelen solved = 34265, spread = 68266, legal = 83836; time = 0.36s
Info: at iteration #11, type ALL: wirelen solved = 34380, spread = 67939, legal = 81038; time = 0.37s
Info: at iteration #12, type ALL: wirelen solved = 34715, spread = 68037, legal = 84566; time = 0.43s
Info: at iteration #13, type ALL: wirelen solved = 35337, spread = 68443, legal = 83899; time = 0.40s
Info: at iteration #14, type ALL: wirelen solved = 35790, spread = 68542, legal = 83721; time = 0.40s
Info: at iteration #15, type ALL: wirelen solved = 36382, spread = 68588, legal = 83108; time = 0.42s
Info: at iteration #16, type ALL: wirelen solved = 36751, spread = 68704, legal = 83352; time = 0.44s
Info: HeAP Placer Time: 9.44s
Info: of which solving equations: 4.82s
Info: of which spreading cells: 0.70s
Info: of which strict legalisation: 1.96s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1922, wirelen = 81038
Info: at iteration #5: temp = 0.000000, timing cost = 1579, wirelen = 75036
Info: at iteration #10: temp = 0.000000, timing cost = 1188, wirelen = 72869
Info: at iteration #15: temp = 0.000000, timing cost = 1208, wirelen = 72253
Info: at iteration #20: temp = 0.000000, timing cost = 1201, wirelen = 72048
Info: at iteration #22: temp = 0.000000, timing cost = 1197, wirelen = 72025
Info: SA placement time 20.66s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 74.68 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.45 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.00 ns
Info: Slack histogram:
Info: legend: * represents 33 endpoint(s)
Info: + represents [1,33) endpoint(s)
Info: [ 2234, 2875) |*+
Info: [ 2875, 3516) |**+
Info: [ 3516, 4157) |****+
Info: [ 4157, 4798) |*****+
Info: [ 4798, 5439) |********+
Info: [ 5439, 6080) |**********+
Info: [ 6080, 6721) |***************+
Info: [ 6721, 7362) |******************************+
Info: [ 7362, 8003) |********************************************+
Info: [ 8003, 8644) |******************************************+
Info: [ 8644, 9285) |******************************+
Info: [ 9285, 9926) |*******************************+
Info: [ 9926, 10567) |*******************************+
Info: [ 10567, 11208) |****************+
Info: [ 11208, 11849) |********************+
Info: [ 11849, 12490) |***************************************+
Info: [ 12490, 13131) |***********************************************************+
Info: [ 13131, 13772) |************************************************************
Info: [ 13772, 14413) |********************************************************+
Info: [ 14413, 15054) |**************************************************+
Info: Checksum: 0x5a66600d
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39414 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 472 527 | 472 527 | 39020| 1.60 1.60|
Info: 2000 | 816 1183 | 344 656 | 38680| 1.14 2.74|
Info: 3000 | 1193 1806 | 377 623 | 38340| 1.33 4.07|
Info: 4000 | 1480 2519 | 287 713 | 37758| 1.01 5.09|
Info: 5000 | 1586 3413 | 106 894 | 36962| 0.64 5.72|
Info: 6000 | 1789 4210 | 203 797 | 36346| 0.65 6.38|
Info: 7000 | 1967 5032 | 178 822 | 35636| 0.73 7.11|
Info: 8000 | 2102 5897 | 135 865 | 34933| 0.90 8.01|
Info: 9000 | 2276 6723 | 174 826 | 34305| 1.32 9.33|
Info: 10000 | 2484 7515 | 208 792 | 33752| 1.32 10.65|
Info: 11000 | 2585 8414 | 101 899 | 32938| 0.58 11.23|
Info: 12000 | 2668 9331 | 83 917 | 32078| 0.46 11.68|
Info: 13000 | 2759 10240 | 91 909 | 31331| 0.37 12.06|
Info: 14000 | 2925 11074 | 166 834 | 30639| 0.51 12.56|
Info: 15000 | 3075 11924 | 150 850 | 29844| 0.45 13.02|
Info: 16000 | 3214 12785 | 139 861 | 29113| 0.49 13.51|
Info: 17000 | 3407 13592 | 193 807 | 28571| 0.45 13.96|
Info: 18000 | 3600 14399 | 193 807 | 27864| 0.41 14.37|
Info: 19000 | 3796 15203 | 196 804 | 27189| 0.47 14.85|
Info: 20000 | 3965 16034 | 169 831 | 26462| 0.53 15.38|
Info: 21000 | 4285 16714 | 320 680 | 25902| 0.45 15.83|
Info: 22000 | 4500 17499 | 215 785 | 25266| 0.49 16.32|
Info: 23000 | 4739 18260 | 239 761 | 24593| 0.40 16.72|
Info: 24000 | 4900 19099 | 161 839 | 23861| 0.53 17.25|
Info: 25000 | 5120 19878 | 220 779 | 23220| 0.44 17.69|
Info: 26000 | 5391 20604 | 271 726 | 23108| 0.92 18.62|
Info: 27000 | 5613 21382 | 222 778 | 22637| 0.97 19.59|
Info: 28000 | 5918 22061 | 305 679 | 22032| 0.42 20.00|
Info: 29000 | 6279 22682 | 361 621 | 21494| 0.41 20.41|
Info: 30000 | 6616 23312 | 337 630 | 20996| 0.49 20.90|
Info: 31000 | 6867 24028 | 251 716 | 20333| 0.47 21.37|
Info: 32000 | 7108 24738 | 241 710 | 19668| 0.44 21.82|
Info: 33000 | 7319 25472 | 211 734 | 19078| 0.49 22.31|
Info: 34000 | 7506 26222 | 187 750 | 18420| 0.45 22.76|
Info: 35000 | 7750 26950 | 244 728 | 17852| 0.58 23.33|
Info: 36000 | 7989 27677 | 239 727 | 17193| 0.59 23.92|
Info: 37000 | 8220 28393 | 231 716 | 16526| 0.52 24.44|
Info: 38000 | 8439 29114 | 219 721 | 16127| 0.61 25.04|
Info: 39000 | 8655 29856 | 216 742 | 15598| 0.74 25.78|
Info: 40000 | 8889 30587 | 234 731 | 14946| 0.55 26.33|
Info: 41000 | 9113 31322 | 224 735 | 14417| 0.56 26.89|
Info: 42000 | 9334 32059 | 221 737 | 13933| 0.66 27.55|
Info: 43000 | 9529 32824 | 195 765 | 13291| 0.60 28.16|
Info: 44000 | 9765 33513 | 236 689 | 12874| 0.85 29.01|
Info: 45000 | 9925 34321 | 160 808 | 12537| 0.78 29.79|
Info: 46000 | 10088 35128 | 163 807 | 11838| 0.55 30.34|
Info: 47000 | 10287 35867 | 199 739 | 11396| 0.72 31.06|
Info: 48000 | 10584 36558 | 297 691 | 10878| 0.73 31.79|
Info: 49000 | 10821 37310 | 237 752 | 10450| 0.90 32.70|
Info: 50000 | 10997 38053 | 176 743 | 9769| 0.53 33.23|
Info: 51000 | 11183 38835 | 186 782 | 9151| 0.49 33.71|
Info: 52000 | 11422 39557 | 239 722 | 8636| 0.82 34.53|
Info: 53000 | 11536 40376 | 114 819 | 7820| 0.56 35.09|
Info: 54000 | 11756 41092 | 220 716 | 7223| 0.68 35.77|
Info: 55000 | 11960 41872 | 204 780 | 6897| 0.79 36.57|
Info: 56000 | 12280 42550 | 320 678 | 6511| 1.03 37.59|
Info: 57000 | 12697 43133 | 417 583 | 6460| 1.44 39.04|
Info: 58000 | 12926 43891 | 229 758 | 6066| 0.86 39.90|
Info: 59000 | 13069 44724 | 143 833 | 5349| 0.50 40.40|
Info: 60000 | 13371 45420 | 302 696 | 4936| 0.91 41.31|
Info: 61000 | 13757 46034 | 386 614 | 4648| 1.39 42.69|
Info: 62000 | 14117 46666 | 360 632 | 4350| 1.26 43.95|
Info: 63000 | 14294 47489 | 177 823 | 3578| 0.35 44.30|
Info: 64000 | 14644 48139 | 350 650 | 3364| 1.35 45.65|
Info: 65000 | 15073 48710 | 429 571 | 3197| 1.69 47.34|
Info: 66000 | 15446 49337 | 373 627 | 2989| 1.55 48.90|
Info: 67000 | 15824 49959 | 378 622 | 2565| 1.10 49.99|
Info: 68000 | 16106 50677 | 282 718 | 2142| 0.75 50.74|
Info: 69000 | 16308 51423 | 202 746 | 1541| 0.82 51.56|
Info: 70000 | 16527 52084 | 219 661 | 923| 0.85 52.41|
Info: 71000 | 16911 52662 | 384 578 | 746| 1.39 53.80|
Info: 72000 | 17253 53254 | 342 592 | 397| 1.09 54.89|
Info: 72770 | 17468 53745 | 215 491 | 0| 0.90 55.80|
Info: Routing complete.
Info: Router1 time 55.80s
Info: Checksum: 0x935e25cb
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_18.Q
Info: routing 0.70 1.09 Net u_arbiter_wide.m_addr[19] (18,6) -> (20,6)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z_D_LUT4_Z.A
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.27 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z_D_LUT4_Z.F
Info: routing 0.74 2.01 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z_D[2] (20,6) -> (20,9)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.19 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z.F
Info: routing 0.45 2.64 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z[0] (20,9) -> (20,9)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.A
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.82 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.F
Info: routing 0.32 3.14 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z[3] (20,9) -> (20,9)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.33 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.68 4.01 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z[3] (20,9) -> (20,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.19 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.88 5.07 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[1] (20,7) -> (13,7)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.25 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.50 5.75 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (13,7) -> (13,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.93 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.60 6.53 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (13,7) -> (13,3)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 6.71 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.03 6.75 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (13,3) -> (13,3)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.93 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 2.28 9.20 Net u_host_arb.m_wr_LUT4_C_Z[3] (13,3) -> (4,33)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.39 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 1.65 11.03 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (4,33) -> (7,8)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.21 Source u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.F
Info: routing 0.12 11.33 Net u_sdram_backend.state_TRELLIS_FF_Q_3_DI (7,8) -> (7,8)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: setup 0.00 11.33 Source u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: 2.38 ns logic, 8.96 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 2.79 2.79 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (13,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 2.97 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.67 3.63 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D[2] (13,9) -> (12,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.82 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z.F
Info: routing 0.12 3.93 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI (12,9) -> (12,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51.DI
Info: setup 0.00 3.93 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51.DI
Info: 0.36 ns logic, 3.57 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_2.Q
Info: routing 1.28 1.67 Net u_spi_bridge.byte_idx[2] (21,56) -> (21,41)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.85 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.84 2.69 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (21,41) -> (20,45)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.87 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.14 4.01 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (20,45) -> (12,57)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.19 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.62 4.80 Net spi_miso_LUT4_Z_B[2] (12,57) -> (12,57)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.99 Source spi_miso_LUT4_Z.F
Info: routing 1.46 6.45 Net spi_miso$TRELLIS_IO_OUT (12,57) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.33 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 88.25 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.93 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.45 ns
Info: Slack histogram:
Info: legend: * represents 38 endpoint(s)
Info: + represents [1,38) endpoint(s)
Info: [ 4294, 4826) |+
Info: [ 4826, 5358) |+
Info: [ 5358, 5890) |+
Info: [ 5890, 6422) |***+
Info: [ 6422, 6954) |*****+
Info: [ 6954, 7486) |**********+
Info: [ 7486, 8018) |********+
Info: [ 8018, 8550) |************+
Info: [ 8550, 9082) |************+
Info: [ 9082, 9614) |************************+
Info: [ 9614, 10146) |*******************************************+
Info: [ 10146, 10678) |*****************************************+
Info: [ 10678, 11210) |************************************+
Info: [ 11210, 11742) |****************************+
Info: [ 11742, 12274) |********************************+
Info: [ 12274, 12806) |********************************+
Info: [ 12806, 13338) |*****************************************+
Info: [ 13338, 13870) |*****************************************************+
Info: [ 13870, 14402) |************************************************************
Info: [ 14402, 14934) |*************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed3.log
+398
View File
@@ -0,0 +1,398 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 664743.
Info: at initial placer iter 0, wirelen = 3679
Info: at initial placer iter 1, wirelen = 3262
Info: at initial placer iter 2, wirelen = 3061
Info: at initial placer iter 3, wirelen = 3146
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3007, spread = 111430, legal = 128172; time = 0.51s
Info: at iteration #2, type ALL: wirelen solved = 12169, spread = 80051, legal = 94988; time = 0.46s
Info: at iteration #3, type ALL: wirelen solved = 18837, spread = 71939, legal = 88497; time = 0.44s
Info: at iteration #4, type ALL: wirelen solved = 22992, spread = 69314, legal = 85813; time = 0.46s
Info: at iteration #5, type ALL: wirelen solved = 26132, spread = 66108, legal = 81806; time = 0.39s
Info: at iteration #6, type ALL: wirelen solved = 27501, spread = 66274, legal = 80141; time = 0.37s
Info: at iteration #7, type ALL: wirelen solved = 29268, spread = 65007, legal = 82054; time = 0.50s
Info: at iteration #8, type ALL: wirelen solved = 29608, spread = 64907, legal = 82065; time = 0.50s
Info: at iteration #9, type ALL: wirelen solved = 30207, spread = 64649, legal = 80874; time = 0.42s
Info: at iteration #10, type ALL: wirelen solved = 30969, spread = 64440, legal = 79251; time = 0.38s
Info: at iteration #11, type ALL: wirelen solved = 31424, spread = 65098, legal = 78914; time = 0.39s
Info: at iteration #12, type ALL: wirelen solved = 32740, spread = 66049, legal = 80698; time = 0.38s
Info: at iteration #13, type ALL: wirelen solved = 33705, spread = 64898, legal = 79207; time = 0.41s
Info: at iteration #14, type ALL: wirelen solved = 34833, spread = 66931, legal = 80217; time = 0.37s
Info: at iteration #15, type ALL: wirelen solved = 35608, spread = 67387, legal = 80401; time = 0.37s
Info: at iteration #16, type ALL: wirelen solved = 36304, spread = 66987, legal = 78361; time = 0.37s
Info: at iteration #17, type ALL: wirelen solved = 36488, spread = 67341, legal = 78026; time = 0.38s
Info: at iteration #18, type ALL: wirelen solved = 36913, spread = 66941, legal = 81760; time = 0.37s
Info: at iteration #19, type ALL: wirelen solved = 37228, spread = 67336, legal = 79815; time = 0.50s
Info: at iteration #20, type ALL: wirelen solved = 37541, spread = 67771, legal = 78911; time = 0.32s
Info: at iteration #21, type ALL: wirelen solved = 37898, spread = 67671, legal = 79244; time = 0.41s
Info: at iteration #22, type ALL: wirelen solved = 38263, spread = 68210, legal = 80382; time = 0.39s
Info: HeAP Placer Time: 12.71s
Info: of which solving equations: 6.11s
Info: of which spreading cells: 1.00s
Info: of which strict legalisation: 2.80s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1201, wirelen = 78026
Info: at iteration #5: temp = 0.000000, timing cost = 1601, wirelen = 73061
Info: at iteration #10: temp = 0.000000, timing cost = 972, wirelen = 71811
Info: at iteration #15: temp = 0.000000, timing cost = 975, wirelen = 71455
Info: at iteration #20: temp = 0.000000, timing cost = 1067, wirelen = 71329
Info: at iteration #20: temp = 0.000000, timing cost = 1065, wirelen = 71335
Info: SA placement time 17.35s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 73.11 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.58 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.76 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 1947, 2603) |+
Info: [ 2603, 3259) |+
Info: [ 3259, 3915) |***+
Info: [ 3915, 4571) |*****+
Info: [ 4571, 5227) |*******+
Info: [ 5227, 5883) |*****+
Info: [ 5883, 6539) |*******+
Info: [ 6539, 7195) |**********+
Info: [ 7195, 7851) |********************+
Info: [ 7851, 8507) |*********************************+
Info: [ 8507, 9163) |*************************************************+
Info: [ 9163, 9819) |*****************************************+
Info: [ 9819, 10475) |*****************************************+
Info: [ 10475, 11131) |****************************+
Info: [ 11131, 11787) |***********************+
Info: [ 11787, 12443) |***************************************+
Info: [ 12443, 13099) |*****************************************************+
Info: [ 13099, 13755) |************************************************************
Info: [ 13755, 14411) |***************************************************+
Info: [ 14411, 15067) |**********************************************+
Info: Checksum: 0xe0d6d18e
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39482 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 475 524 | 475 524 | 39125| 1.34 1.34|
Info: 2000 | 722 1277 | 247 753 | 38672| 1.33 2.67|
Info: 3000 | 909 2090 | 187 813 | 37922| 0.75 3.41|
Info: 4000 | 982 3017 | 73 927 | 37234| 0.47 3.89|
Info: 5000 | 1097 3902 | 115 885 | 36648| 0.64 4.52|
Info: 6000 | 1211 4788 | 114 886 | 35815| 0.49 5.01|
Info: 7000 | 1391 5608 | 180 820 | 35108| 0.70 5.72|
Info: 8000 | 1541 6458 | 150 850 | 34406| 0.75 6.47|
Info: 9000 | 1581 7418 | 40 960 | 33451| 0.40 6.87|
Info: 10000 | 1704 8295 | 123 877 | 32615| 0.39 7.25|
Info: 11000 | 1838 9161 | 134 866 | 31902| 0.52 7.77|
Info: 12000 | 1956 10043 | 118 882 | 31113| 0.62 8.39|
Info: 13000 | 2068 10931 | 112 888 | 30292| 0.35 8.74|
Info: 14000 | 2206 11793 | 138 862 | 29480| 0.47 9.21|
Info: 15000 | 2399 12600 | 193 807 | 28749| 0.40 9.61|
Info: 16000 | 2543 13456 | 144 856 | 27958| 0.45 10.05|
Info: 17000 | 2705 14294 | 162 838 | 27295| 0.46 10.52|
Info: 18000 | 2823 15176 | 118 882 | 26505| 0.43 10.95|
Info: 19000 | 2984 16015 | 161 839 | 25795| 0.40 11.35|
Info: 20000 | 3149 16850 | 165 835 | 25050| 0.50 11.85|
Info: 21000 | 3312 17687 | 163 837 | 24308| 0.41 12.26|
Info: 22000 | 3505 18493 | 193 806 | 23601| 0.42 12.68|
Info: 23000 | 3780 19210 | 275 717 | 22955| 0.39 13.07|
Info: 24000 | 4142 19840 | 362 630 | 22361| 0.36 13.44|
Info: 25000 | 4422 20525 | 280 685 | 21677| 0.38 13.81|
Info: 26000 | 4696 21199 | 274 674 | 21018| 0.37 14.18|
Info: 27000 | 4916 21933 | 220 734 | 20283| 0.48 14.66|
Info: 28000 | 5067 22742 | 151 809 | 19486| 0.44 15.10|
Info: 29000 | 5264 23495 | 197 753 | 18729| 0.40 15.50|
Info: 30000 | 5474 24248 | 210 753 | 17993| 0.45 15.96|
Info: 31000 | 5681 24990 | 207 742 | 17268| 0.45 16.41|
Info: 32000 | 5870 25732 | 189 742 | 16621| 0.47 16.88|
Info: 33000 | 6073 26480 | 203 748 | 15878| 0.44 17.32|
Info: 34000 | 6231 27258 | 158 778 | 15065| 0.42 17.74|
Info: 35000 | 6378 28018 | 147 760 | 14267| 0.39 18.13|
Info: 36000 | 6547 28777 | 169 759 | 13638| 0.50 18.63|
Info: 37000 | 6700 29582 | 153 805 | 12871| 0.55 19.18|
Info: 38000 | 6851 30366 | 151 784 | 12095| 0.51 19.69|
Info: 39000 | 6991 31182 | 140 816 | 11360| 0.63 20.32|
Info: 40000 | 7146 31999 | 155 817 | 10690| 0.58 20.90|
Info: 41000 | 7291 32802 | 145 803 | 9936| 0.68 21.59|
Info: 42000 | 7399 33615 | 108 813 | 9129| 0.54 22.13|
Info: 43000 | 7603 34384 | 204 769 | 8496| 0.86 22.98|
Info: 44000 | 7706 35203 | 103 819 | 7648| 0.60 23.58|
Info: 45000 | 7857 36005 | 151 802 | 6999| 0.55 24.13|
Info: 46000 | 8064 36782 | 207 777 | 6560| 0.80 24.93|
Info: 47000 | 8352 37485 | 288 703 | 6177| 1.34 26.27|
Info: 48000 | 8479 38315 | 127 830 | 5402| 0.44 26.71|
Info: 49000 | 8698 39091 | 219 776 | 4783| 0.76 27.47|
Info: 50000 | 9063 39726 | 365 635 | 4454| 1.29 28.76|
Info: 51000 | 9260 40523 | 197 797 | 3759| 0.49 29.26|
Info: 52000 | 9516 41267 | 256 744 | 3263| 0.87 30.13|
Info: 53000 | 9876 41907 | 360 640 | 3232| 1.12 31.25|
Info: 54000 | 10242 42541 | 366 634 | 2954| 1.22 32.47|
Info: 55000 | 10565 43218 | 323 677 | 2546| 0.96 33.43|
Info: 56000 | 10848 43935 | 283 717 | 2187| 0.93 34.37|
Info: 57000 | 10999 44676 | 151 741 | 1408| 0.80 35.17|
Info: 58000 | 11353 45255 | 354 579 | 1035| 1.02 36.19|
Info: 59000 | 11530 45974 | 177 719 | 341| 0.70 36.88|
Info: 59458 | 11599 46302 | 69 328 | 0| 0.35 37.24|
Info: Routing complete.
Info: Router1 time 37.24s
Info: Checksum: 0x4e49b5c8
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_director.job_out_slot_TRELLIS_FF_Q.Q
Info: routing 1.09 1.49 Net u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0[4] (23,40) -> (25,30)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z_LUT4_Z.D
Info: Defined in:
Info: hardware/v2/rtl/neural_director.v:73.39-73.51
Info: logic 0.18 1.67 Source u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z_LUT4_Z.F
Info: routing 1.39 3.06 Net u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z[5] (25,30) -> (26,42)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z_PFUMX_C0_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 3.25 Source u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: routing 1.22 4.47 Net u_dataflow_core.u_dep_mgr.node_producer_ids[15]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z_C[4] (26,42) -> (22,33)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 4.66 Source u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.27 4.93 Net u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_C0[4] (22,33) -> (22,33)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 5.12 Source u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.75 5.87 Net u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0[4] (22,33) -> (23,36)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 6.07 Source u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info: routing 0.47 6.54 Net u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z[5] (23,36) -> (23,37)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[14]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 6.73 Source u_dataflow_core.u_dep_mgr.node_state[14]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.89 7.62 Net u_dataflow_core.u_dep_mgr.node_state[14]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_D_Z[5] (23,37) -> (24,41)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 7.82 Source u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.00 7.82 Net u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1 (24,41) -> (24,41)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
Info: logic 0.18 8.00 Source u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.82 8.82 Net u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z[5] (24,41) -> (25,45)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 9.01 Source u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.70 9.71 Net u_dataflow_core.u_dep_mgr.node_resolved[11]_TRELLIS_FF_Q_2_DI_LUT4_Z_C_LUT4_D_Z_LUT4_Z_1_D_LUT4_D_1_Z[4] (25,45) -> (24,47)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 9.90 Source u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.92 10.82 Net u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q_DI (24,47) -> (23,42)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q.M
Info: setup 0.00 10.82 Source u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q.M
Info: 2.30 ns logic, 8.52 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 3.12 3.12 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (13,7)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.30 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.69 3.99 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D[2] (13,7) -> (13,6)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.17 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z.F
Info: routing 0.12 4.28 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI (13,6) -> (13,6)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51.DI
Info: setup 0.00 4.28 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51.DI
Info: 0.36 ns logic, 3.92 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 1.03 1.43 Net u_spi_bridge.byte_idx[3] (19,52) -> (21,48)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.61 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.17 1.78 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (21,48) -> (21,48)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.96 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.81 2.77 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (21,48) -> (16,48)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.95 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 1.14 4.09 Net spi_miso_LUT4_Z_B[2] (16,48) -> (16,54)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.28 Source spi_miso_LUT4_Z.F
Info: routing 1.86 6.14 Net spi_miso$TRELLIS_IO_OUT (16,54) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.02 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 92.43 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.28 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.14 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 4806, 5312) |+
Info: [ 5312, 5818) |**+
Info: [ 5818, 6324) |**+
Info: [ 6324, 6830) |**+
Info: [ 6830, 7336) |******+
Info: [ 7336, 7842) |*********+
Info: [ 7842, 8348) |**********+
Info: [ 8348, 8854) |**********+
Info: [ 8854, 9360) |***********+
Info: [ 9360, 9866) |********************+
Info: [ 9866, 10372) |******************************+
Info: [ 10372, 10878) |*************************************************+
Info: [ 10878, 11384) |************************************+
Info: [ 11384, 11890) |******************************************+
Info: [ 11890, 12396) |***********************************+
Info: [ 12396, 12902) |******************************+
Info: [ 12902, 13408) |*****************************************+
Info: [ 13408, 13914) |*****************************************************+
Info: [ 13914, 14420) |************************************************************
Info: [ 14420, 14926) |***********************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed4.log
+404
View File
@@ -0,0 +1,404 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 665354.
Info: at initial placer iter 0, wirelen = 3823
Info: at initial placer iter 1, wirelen = 3248
Info: at initial placer iter 2, wirelen = 3043
Info: at initial placer iter 3, wirelen = 3116
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3008, spread = 111060, legal = 126956; time = 0.50s
Info: at iteration #2, type ALL: wirelen solved = 12675, spread = 81942, legal = 97252; time = 0.45s
Info: at iteration #3, type ALL: wirelen solved = 19570, spread = 72038, legal = 88404; time = 0.50s
Info: at iteration #4, type ALL: wirelen solved = 23775, spread = 68858, legal = 84735; time = 0.47s
Info: at iteration #5, type ALL: wirelen solved = 26419, spread = 67156, legal = 83186; time = 0.47s
Info: at iteration #6, type ALL: wirelen solved = 27305, spread = 66515, legal = 81140; time = 0.40s
Info: at iteration #7, type ALL: wirelen solved = 28670, spread = 65617, legal = 81992; time = 0.40s
Info: at iteration #8, type ALL: wirelen solved = 29818, spread = 65582, legal = 82545; time = 0.36s
Info: at iteration #9, type ALL: wirelen solved = 30687, spread = 67127, legal = 79744; time = 0.34s
Info: at iteration #10, type ALL: wirelen solved = 32928, spread = 69762, legal = 81597; time = 0.39s
Info: at iteration #11, type ALL: wirelen solved = 35460, spread = 69492, legal = 83803; time = 0.40s
Info: at iteration #12, type ALL: wirelen solved = 36065, spread = 68501, legal = 82712; time = 0.40s
Info: at iteration #13, type ALL: wirelen solved = 36458, spread = 67718, legal = 83242; time = 0.37s
Info: at iteration #14, type ALL: wirelen solved = 36273, spread = 69530, legal = 79474; time = 0.36s
Info: at iteration #15, type ALL: wirelen solved = 37214, spread = 68862, legal = 84101; time = 0.42s
Info: at iteration #16, type ALL: wirelen solved = 37355, spread = 69275, legal = 82613; time = 0.35s
Info: at iteration #17, type ALL: wirelen solved = 37816, spread = 69305, legal = 84580; time = 0.41s
Info: at iteration #18, type ALL: wirelen solved = 38288, spread = 69360, legal = 82286; time = 0.35s
Info: at iteration #19, type ALL: wirelen solved = 38706, spread = 69484, legal = 81801; time = 0.36s
Info: HeAP Placer Time: 10.99s
Info: of which solving equations: 5.30s
Info: of which spreading cells: 0.85s
Info: of which strict legalisation: 2.38s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1383, wirelen = 79474
Info: at iteration #5: temp = 0.000000, timing cost = 1522, wirelen = 73788
Info: at iteration #10: temp = 0.000000, timing cost = 1422, wirelen = 72608
Info: at iteration #15: temp = 0.000000, timing cost = 1479, wirelen = 72135
Info: at iteration #20: temp = 0.000000, timing cost = 1634, wirelen = 71921
Info: at iteration #21: temp = 0.000000, timing cost = 1631, wirelen = 71893
Info: SA placement time 20.23s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 79.25 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.81 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.99 ns
Info: Slack histogram:
Info: legend: * represents 33 endpoint(s)
Info: + represents [1,33) endpoint(s)
Info: [ 3007, 3610) |+
Info: [ 3610, 4213) |*+
Info: [ 4213, 4816) |***+
Info: [ 4816, 5419) |***+
Info: [ 5419, 6022) |*********+
Info: [ 6022, 6625) |**********+
Info: [ 6625, 7228) |*************+
Info: [ 7228, 7831) |***************+
Info: [ 7831, 8434) |**************************+
Info: [ 8434, 9037) |*******************************+
Info: [ 9037, 9640) |****************************************+
Info: [ 9640, 10243) |****************************************+
Info: [ 10243, 10846) |************************************+
Info: [ 10846, 11449) |************************************+
Info: [ 11449, 12052) |************************************+
Info: [ 12052, 12655) |******************************************+
Info: [ 12655, 13258) |************************************************************
Info: [ 13258, 13861) |****************************************************+
Info: [ 13861, 14464) |************************************************+
Info: [ 14464, 15067) |*************************************************+
Info: Checksum: 0xe06743c5
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39441 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 676 323 | 676 323 | 39282| 1.49 1.49|
Info: 2000 | 1126 873 | 450 550 | 39060| 1.37 2.86|
Info: 3000 | 1511 1488 | 385 615 | 38714| 1.13 3.99|
Info: 4000 | 1885 2114 | 374 626 | 38225| 1.00 4.99|
Info: 5000 | 2079 2920 | 194 806 | 37596| 0.74 5.73|
Info: 6000 | 2184 3815 | 105 895 | 36840| 0.51 6.24|
Info: 7000 | 2332 4667 | 148 852 | 36099| 0.81 7.05|
Info: 8000 | 2437 5562 | 105 895 | 35333| 0.54 7.59|
Info: 9000 | 2701 6298 | 264 736 | 34815| 1.01 8.60|
Info: 10000 | 2778 7221 | 77 923 | 34057| 0.41 9.02|
Info: 11000 | 2855 8144 | 77 923 | 33275| 0.43 9.45|
Info: 12000 | 2949 9050 | 94 906 | 32438| 0.54 9.98|
Info: 13000 | 3070 9929 | 121 879 | 31697| 0.48 10.47|
Info: 14000 | 3211 10788 | 141 859 | 30954| 0.64 11.11|
Info: 15000 | 3360 11639 | 149 851 | 30400| 0.47 11.58|
Info: 16000 | 3536 12463 | 176 824 | 29903| 0.54 12.12|
Info: 17000 | 3726 13273 | 190 810 | 29571| 0.40 12.53|
Info: 18000 | 3938 14061 | 212 788 | 29030| 2.03 14.56|
Info: 19000 | 4167 14832 | 229 771 | 28586| 1.10 15.66|
Info: 20000 | 4385 15614 | 218 782 | 28245| 0.49 16.15|
Info: 21000 | 4505 16494 | 120 880 | 27650| 0.37 16.51|
Info: 22000 | 4692 17307 | 187 813 | 27027| 0.42 16.93|
Info: 23000 | 4903 18096 | 211 789 | 26326| 0.56 17.48|
Info: 24000 | 5120 18879 | 217 783 | 25650| 0.49 17.97|
Info: 25000 | 5360 19639 | 240 760 | 25204| 0.43 18.40|
Info: 26000 | 5594 20405 | 234 766 | 24656| 0.53 18.93|
Info: 27000 | 5852 21147 | 258 742 | 24240| 0.58 19.51|
Info: 28000 | 6125 21874 | 273 727 | 23601| 0.38 19.89|
Info: 29000 | 6385 22614 | 260 740 | 23124| 0.61 20.50|
Info: 30000 | 6623 23375 | 238 761 | 22613| 0.53 21.04|
Info: 31000 | 6886 24079 | 263 704 | 22013| 0.46 21.49|
Info: 32000 | 7122 24795 | 236 716 | 21446| 0.49 21.99|
Info: 33000 | 7384 25480 | 262 685 | 20889| 0.42 22.40|
Info: 34000 | 7765 26058 | 381 578 | 20345| 0.48 22.89|
Info: 35000 | 8066 26720 | 301 662 | 19777| 0.44 23.33|
Info: 36000 | 8408 27360 | 342 640 | 19215| 0.45 23.78|
Info: 37000 | 8690 28020 | 282 660 | 18647| 0.55 24.33|
Info: 38000 | 8954 28721 | 264 701 | 18130| 0.57 24.90|
Info: 39000 | 9242 29417 | 288 696 | 17691| 0.98 25.89|
Info: 40000 | 9473 30145 | 231 728 | 17056| 0.48 26.37|
Info: 41000 | 9669 30897 | 196 752 | 16415| 0.51 26.88|
Info: 42000 | 9875 31654 | 206 757 | 15717| 0.50 27.38|
Info: 43000 | 10101 32375 | 226 721 | 15079| 0.49 27.87|
Info: 44000 | 10350 33109 | 249 734 | 14691| 0.77 28.64|
Info: 45000 | 10579 33866 | 229 757 | 14177| 1.02 29.66|
Info: 46000 | 10783 34598 | 204 732 | 13466| 0.61 30.27|
Info: 47000 | 10950 35341 | 167 743 | 12751| 0.60 30.87|
Info: 48000 | 11140 36084 | 190 743 | 12138| 0.52 31.40|
Info: 49000 | 11375 36809 | 235 725 | 11602| 0.79 32.19|
Info: 50000 | 11582 37579 | 207 770 | 10998| 0.88 33.07|
Info: 51000 | 11775 38339 | 193 760 | 10391| 0.72 33.79|
Info: 52000 | 12010 39097 | 235 758 | 9850| 0.79 34.58|
Info: 53000 | 12138 39881 | 128 784 | 9101| 0.46 35.04|
Info: 54000 | 12344 40663 | 206 782 | 8585| 0.93 35.97|
Info: 55000 | 12509 41421 | 165 758 | 7931| 0.49 36.46|
Info: 56000 | 12707 42206 | 198 785 | 7494| 0.76 37.22|
Info: 57000 | 12851 42968 | 144 762 | 6840| 0.43 37.65|
Info: 58000 | 13134 43683 | 283 715 | 6364| 1.25 38.91|
Info: 59000 | 13312 44482 | 178 799 | 5848| 0.67 39.58|
Info: 60000 | 13418 45365 | 106 883 | 5004| 0.32 39.90|
Info: 61000 | 13777 46006 | 359 641 | 4782| 1.29 41.18|
Info: 62000 | 14145 46638 | 368 632 | 4731| 1.35 42.53|
Info: 63000 | 14471 47312 | 326 674 | 4552| 1.00 43.53|
Info: 64000 | 14701 48082 | 230 770 | 3918| 0.63 44.16|
Info: 65000 | 14960 48823 | 259 741 | 3346| 0.87 45.03|
Info: 66000 | 15337 49446 | 377 623 | 3164| 1.21 46.24|
Info: 67000 | 15664 50119 | 327 673 | 3011| 1.25 47.49|
Info: 68000 | 15914 50869 | 250 750 | 2436| 0.70 48.19|
Info: 69000 | 16133 51625 | 219 756 | 1787| 0.58 48.77|
Info: 70000 | 16253 52376 | 120 751 | 1005| 0.67 49.44|
Info: 71000 | 16343 53135 | 90 759 | 144| 0.69 50.13|
Info: 71146 | 16346 53243 | 3 108 | 0| 0.16 50.29|
Info: Routing complete.
Info: Router1 time 50.29s
Info: Checksum: 0x9bf9af99
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q.Q
Info: routing 0.90 1.29 Net u_arbiter_wide.m_addr[1] (15,4) -> (15,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_1.B
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.47 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_1.F
Info: routing 0.60 2.07 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D[0] (15,7) -> (15,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.A
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.25 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.F
Info: routing 0.53 2.78 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (15,7) -> (14,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.96 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.45 3.42 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (14,7) -> (14,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.60 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.60 4.20 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (14,7) -> (14,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.38 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.85 5.23 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (14,7) -> (12,8)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.41 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.36 5.77 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (12,8) -> (12,8)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.95 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.47 6.42 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (12,8) -> (13,12)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 6.60 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.36 6.97 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (13,12) -> (13,12)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.15 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 1.02 8.17 Net u_host_arb.m_wr_LUT4_C_Z[3] (13,12) -> (5,18)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.35 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 2.26 10.61 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (5,18) -> (5,57)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_8.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 10.61 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_8.CE
Info: 2.19 ns logic, 8.42 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[0]$tr_io.O
Info: routing 3.36 3.36 Net sdram_dq[0]$TRELLIS_IO_IN (0,26) -> (12,6)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_48_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.54 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_48_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.72 4.26 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_48_DI_LUT4_Z_D[2] (12,6) -> (13,5)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.44 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112_DI_LUT4_Z.F
Info: routing 0.12 4.56 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112_DI (13,5) -> (13,5)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112.DI
Info: setup 0.00 4.56 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112.DI
Info: 0.36 ns logic, 4.20 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q.Q
Info: routing 1.55 1.94 Net u_spi_bridge.byte_idx[0] (21,47) -> (21,26)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.12 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 2.09 4.21 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (21,26) -> (15,56)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.39 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.44 4.83 Net spi_miso_LUT4_Z_B[2] (15,56) -> (16,56)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.01 Source spi_miso_LUT4_Z.F
Info: routing 1.48 6.49 Net spi_miso$TRELLIS_IO_OUT (16,56) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 0.94 ns logic, 5.56 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 94.22 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.56 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.49 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 5012, 5508) |+
Info: [ 5508, 6004) |*+
Info: [ 6004, 6500) |***+
Info: [ 6500, 6996) |****+
Info: [ 6996, 7492) |******+
Info: [ 7492, 7988) |*******+
Info: [ 7988, 8484) |***********+
Info: [ 8484, 8980) |*************+
Info: [ 8980, 9476) |***************+
Info: [ 9476, 9972) |*************************+
Info: [ 9972, 10468) |*******************************+
Info: [ 10468, 10964) |***************************************+
Info: [ 10964, 11460) |**************************************+
Info: [ 11460, 11956) |************************************+
Info: [ 11956, 12452) |**************************************+
Info: [ 12452, 12948) |**************************************************+
Info: [ 12948, 13444) |**********************************************+
Info: [ 13444, 13940) |*******************************************************+
Info: [ 13940, 14436) |************************************************************
Info: [ 14436, 14932) |*************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed5.log
+391
View File
@@ -0,0 +1,391 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 652028.
Info: at initial placer iter 0, wirelen = 3714
Info: at initial placer iter 1, wirelen = 3306
Info: at initial placer iter 2, wirelen = 3140
Info: at initial placer iter 3, wirelen = 3093
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3292, spread = 111450, legal = 125640; time = 0.48s
Info: at iteration #2, type ALL: wirelen solved = 12489, spread = 84015, legal = 97642; time = 0.43s
Info: at iteration #3, type ALL: wirelen solved = 20103, spread = 72651, legal = 86958; time = 0.47s
Info: at iteration #4, type ALL: wirelen solved = 23708, spread = 70133, legal = 87621; time = 0.50s
Info: at iteration #5, type ALL: wirelen solved = 25645, spread = 67729, legal = 84477; time = 0.41s
Info: at iteration #6, type ALL: wirelen solved = 26619, spread = 66406, legal = 80494; time = 0.41s
Info: at iteration #7, type ALL: wirelen solved = 27537, spread = 65375, legal = 81688; time = 0.40s
Info: at iteration #8, type ALL: wirelen solved = 28365, spread = 65612, legal = 80930; time = 0.43s
Info: at iteration #9, type ALL: wirelen solved = 29553, spread = 67858, legal = 81892; time = 0.43s
Info: at iteration #10, type ALL: wirelen solved = 31925, spread = 69560, legal = 80742; time = 0.40s
Info: at iteration #11, type ALL: wirelen solved = 33586, spread = 69204, legal = 77791; time = 0.35s
Info: at iteration #12, type ALL: wirelen solved = 34385, spread = 68629, legal = 81183; time = 0.35s
Info: at iteration #13, type ALL: wirelen solved = 34445, spread = 68383, legal = 81209; time = 0.41s
Info: at iteration #14, type ALL: wirelen solved = 34771, spread = 68801, legal = 83592; time = 0.38s
Info: at iteration #15, type ALL: wirelen solved = 35340, spread = 68411, legal = 81890; time = 0.39s
Info: at iteration #16, type ALL: wirelen solved = 35627, spread = 68678, legal = 82269; time = 0.37s
Info: HeAP Placer Time: 9.46s
Info: of which solving equations: 4.74s
Info: of which spreading cells: 0.71s
Info: of which strict legalisation: 1.94s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1442, wirelen = 77791
Info: at iteration #5: temp = 0.000000, timing cost = 1356, wirelen = 72049
Info: at iteration #10: temp = 0.000000, timing cost = 885, wirelen = 70691
Info: at iteration #15: temp = 0.000000, timing cost = 849, wirelen = 70380
Info: at iteration #20: temp = 0.000000, timing cost = 841, wirelen = 70180
Info: at iteration #25: temp = 0.000000, timing cost = 830, wirelen = 70040
Info: at iteration #28: temp = 0.000000, timing cost = 831, wirelen = 70005
Info: SA placement time 25.76s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 70.83 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.51 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 9.18 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 1507, 2185) |+
Info: [ 2185, 2863) |+
Info: [ 2863, 3541) |+
Info: [ 3541, 4219) |*****+
Info: [ 4219, 4897) |******+
Info: [ 4897, 5575) |*********+
Info: [ 5575, 6253) |*********+
Info: [ 6253, 6931) |**********+
Info: [ 6931, 7609) |************************+
Info: [ 7609, 8287) |*********************************+
Info: [ 8287, 8965) |**********************************************+
Info: [ 8965, 9643) |***********************************+
Info: [ 9643, 10321) |********************************+
Info: [ 10321, 10999) |**************************+
Info: [ 10999, 11677) |********************+
Info: [ 11677, 12355) |*********************************+
Info: [ 12355, 13033) |**************************************************+
Info: [ 13033, 13711) |************************************************************
Info: [ 13711, 14389) |***************************************************+
Info: [ 14389, 15067) |*********************************************+
Info: Checksum: 0x6abd595c
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39479 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 429 570 | 429 570 | 39015| 1.55 1.55|
Info: 2000 | 669 1330 | 240 760 | 38340| 0.80 2.34|
Info: 3000 | 831 2168 | 162 838 | 37558| 0.68 3.03|
Info: 4000 | 893 3106 | 62 938 | 36667| 0.47 3.49|
Info: 5000 | 1062 3937 | 169 831 | 35993| 0.59 4.09|
Info: 6000 | 1203 4796 | 141 859 | 35298| 0.70 4.79|
Info: 7000 | 1345 5654 | 142 858 | 34742| 0.71 5.50|
Info: 8000 | 1472 6527 | 127 873 | 34045| 0.56 6.06|
Info: 9000 | 1529 7470 | 57 943 | 33150| 0.50 6.56|
Info: 10000 | 1713 8286 | 184 816 | 32501| 0.96 7.52|
Info: 11000 | 1836 9163 | 123 877 | 31778| 0.60 8.12|
Info: 12000 | 1927 10072 | 91 909 | 30912| 0.43 8.55|
Info: 13000 | 2047 10952 | 120 880 | 30118| 0.67 9.21|
Info: 14000 | 2131 11868 | 84 916 | 29309| 0.49 9.71|
Info: 15000 | 2242 12757 | 111 889 | 28541| 0.51 10.22|
Info: 16000 | 2364 13635 | 122 878 | 27815| 0.42 10.64|
Info: 17000 | 2559 14440 | 195 805 | 27340| 0.64 11.28|
Info: 18000 | 2703 15296 | 144 856 | 26614| 0.55 11.83|
Info: 19000 | 2865 16134 | 162 838 | 25917| 0.40 12.23|
Info: 20000 | 3093 16906 | 228 772 | 25233| 0.43 12.66|
Info: 21000 | 3250 17749 | 157 843 | 24488| 0.38 13.04|
Info: 22000 | 3477 18521 | 227 772 | 23824| 0.56 13.60|
Info: 23000 | 3815 19182 | 338 661 | 23284| 0.46 14.07|
Info: 24000 | 4083 19914 | 268 732 | 22679| 0.54 14.61|
Info: 25000 | 4321 20658 | 238 744 | 22133| 0.44 15.05|
Info: 26000 | 4526 21439 | 205 781 | 21537| 0.55 15.60|
Info: 27000 | 4793 22128 | 267 689 | 20913| 0.41 16.01|
Info: 28000 | 4993 22879 | 200 751 | 20252| 0.43 16.44|
Info: 29000 | 5230 23583 | 237 704 | 19585| 0.43 16.88|
Info: 30000 | 5462 24273 | 232 690 | 18922| 0.39 17.27|
Info: 31000 | 5650 25027 | 188 754 | 18180| 0.51 17.79|
Info: 32000 | 5857 25778 | 207 751 | 17507| 0.49 18.28|
Info: 33000 | 6077 26542 | 220 764 | 16957| 1.36 19.64|
Info: 34000 | 6221 27321 | 144 779 | 16181| 0.47 20.11|
Info: 35000 | 6452 28043 | 231 722 | 15568| 0.54 20.65|
Info: 36000 | 6660 28800 | 208 757 | 14916| 0.56 21.22|
Info: 37000 | 6835 29553 | 175 753 | 14124| 0.45 21.67|
Info: 38000 | 7054 30316 | 219 763 | 13755| 1.23 22.89|
Info: 39000 | 7214 31082 | 160 766 | 13058| 0.45 23.34|
Info: 40000 | 7376 31865 | 162 783 | 12331| 0.49 23.83|
Info: 41000 | 7535 32660 | 159 795 | 11698| 0.66 24.49|
Info: 42000 | 7694 33464 | 159 804 | 10992| 0.57 25.06|
Info: 43000 | 7880 34263 | 186 799 | 10401| 0.94 25.99|
Info: 44000 | 7997 35066 | 117 803 | 9572| 0.39 26.38|
Info: 45000 | 8106 35897 | 109 831 | 8731| 0.49 26.87|
Info: 46000 | 8298 36670 | 192 773 | 8115| 0.75 27.62|
Info: 47000 | 8393 37482 | 95 812 | 7300| 0.33 27.95|
Info: 48000 | 8583 38265 | 190 783 | 6595| 0.68 28.63|
Info: 49000 | 8763 39037 | 180 772 | 6140| 0.78 29.41|
Info: 50000 | 8892 39896 | 129 859 | 5496| 0.44 29.85|
Info: 51000 | 9112 40675 | 220 779 | 4978| 0.83 30.68|
Info: 52000 | 9505 41282 | 393 607 | 4735| 1.29 31.98|
Info: 53000 | 9726 42057 | 221 775 | 4223| 0.76 32.73|
Info: 54000 | 9900 42883 | 174 826 | 3445| 0.50 33.23|
Info: 55000 | 10291 43492 | 391 609 | 3223| 1.43 34.66|
Info: 56000 | 10686 44097 | 395 605 | 2953| 1.21 35.86|
Info: 57000 | 10891 44892 | 205 795 | 2346| 0.60 36.47|
Info: 58000 | 11041 45676 | 150 784 | 1590| 0.57 37.04|
Info: 59000 | 11157 46403 | 116 727 | 796| 0.60 37.63|
Info: 60000 | 11364 47119 | 207 716 | 308| 1.25 38.89|
Info: 60407 | 11397 47453 | 33 334 | 0| 0.28 39.16|
Info: Routing complete.
Info: Router1 time 39.16s
Info: Checksum: 0x2fb02924
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_4.Q
Info: routing 0.79 1.18 Net u_arbiter_wide.m_addr[5] (17,11) -> (17,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_2.B
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.36 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_2.F
Info: routing 0.60 1.96 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D[1] (17,7) -> (17,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.B
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.14 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.F
Info: routing 0.52 2.66 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (17,7) -> (17,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.85 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.45 3.30 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (17,8) -> (17,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.48 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.45 3.93 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (17,8) -> (17,8)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.11 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.18 5.29 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (17,8) -> (13,16)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.47 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.00 6.47 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (13,16) -> (14,9)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.65 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.78 7.43 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (14,9) -> (15,13)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 7.61 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.17 7.79 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (15,13) -> (15,13)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.97 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 1.11 9.07 Net u_host_arb.m_wr_LUT4_C_Z[3] (15,13) -> (6,21)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.25 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 2.25 11.50 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (6,21) -> (3,54)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 11.50 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q.CE
Info: 2.19 ns logic, 9.31 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 2.71 2.71 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (11,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 2.89 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.69 3.58 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D[2] (11,9) -> (12,8)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.76 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115_DI_LUT4_Z.F
Info: routing 0.12 3.88 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115_DI (12,8) -> (12,8)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115.DI
Info: setup 0.00 3.88 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115.DI
Info: 0.36 ns logic, 3.52 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q.Q
Info: routing 1.42 1.81 Net u_spi_bridge.byte_idx[0] (22,51) -> (22,30)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.99 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.88 3.87 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (22,30) -> (15,57)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.05 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.80 4.85 Net spi_miso_LUT4_Z_B[2] (15,57) -> (18,57)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.03 Source spi_miso_LUT4_Z.F
Info: routing 1.65 6.68 Net spi_miso$TRELLIS_IO_OUT (18,57) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 0.94 ns logic, 5.74 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 86.95 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.88 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.68 ns
Info: Slack histogram:
Info: legend: * represents 38 endpoint(s)
Info: + represents [1,38) endpoint(s)
Info: [ 4124, 4665) |+
Info: [ 4665, 5206) |+
Info: [ 5206, 5747) |*+
Info: [ 5747, 6288) |**+
Info: [ 6288, 6829) |*****+
Info: [ 6829, 7370) |********+
Info: [ 7370, 7911) |*****+
Info: [ 7911, 8452) |***********+
Info: [ 8452, 8993) |****************+
Info: [ 8993, 9534) |********************+
Info: [ 9534, 10075) |***********************************+
Info: [ 10075, 10616) |**************************************+
Info: [ 10616, 11157) |***************************************+
Info: [ 11157, 11698) |******************************+
Info: [ 11698, 12239) |**********************************+
Info: [ 12239, 12780) |******************************+
Info: [ 12780, 13321) |*************************************************+
Info: [ 13321, 13862) |*******************************************************+
Info: [ 13862, 14403) |************************************************************
Info: [ 14403, 14944) |************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed6.log
+402
View File
@@ -0,0 +1,402 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 653149.
Info: at initial placer iter 0, wirelen = 3728
Info: at initial placer iter 1, wirelen = 3229
Info: at initial placer iter 2, wirelen = 3142
Info: at initial placer iter 3, wirelen = 3088
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3089, spread = 113935, legal = 130601; time = 0.47s
Info: at iteration #2, type ALL: wirelen solved = 12854, spread = 81908, legal = 97493; time = 0.43s
Info: at iteration #3, type ALL: wirelen solved = 19569, spread = 71889, legal = 90858; time = 0.52s
Info: at iteration #4, type ALL: wirelen solved = 24226, spread = 66935, legal = 82654; time = 0.39s
Info: at iteration #5, type ALL: wirelen solved = 25768, spread = 66254, legal = 83971; time = 0.48s
Info: at iteration #6, type ALL: wirelen solved = 26901, spread = 65525, legal = 82834; time = 0.42s
Info: at iteration #7, type ALL: wirelen solved = 27650, spread = 65492, legal = 82841; time = 0.44s
Info: at iteration #8, type ALL: wirelen solved = 28809, spread = 65793, legal = 81456; time = 0.39s
Info: at iteration #9, type ALL: wirelen solved = 29996, spread = 66330, legal = 80505; time = 0.38s
Info: at iteration #10, type ALL: wirelen solved = 31755, spread = 67387, legal = 80671; time = 0.42s
Info: at iteration #11, type ALL: wirelen solved = 33379, spread = 65525, legal = 81860; time = 0.41s
Info: at iteration #12, type ALL: wirelen solved = 33278, spread = 70894, legal = 81378; time = 0.37s
Info: at iteration #13, type ALL: wirelen solved = 36236, spread = 69967, legal = 82289; time = 0.40s
Info: at iteration #14, type ALL: wirelen solved = 36398, spread = 69855, legal = 79257; time = 0.38s
Info: at iteration #15, type ALL: wirelen solved = 36668, spread = 69679, legal = 79976; time = 0.37s
Info: at iteration #16, type ALL: wirelen solved = 36947, spread = 69358, legal = 81699; time = 0.42s
Info: at iteration #17, type ALL: wirelen solved = 37359, spread = 69559, legal = 80854; time = 0.45s
Info: at iteration #18, type ALL: wirelen solved = 37512, spread = 69640, legal = 79462; time = 0.42s
Info: at iteration #19, type ALL: wirelen solved = 37966, spread = 69563, legal = 81375; time = 0.36s
Info: HeAP Placer Time: 11.22s
Info: of which solving equations: 5.26s
Info: of which spreading cells: 0.86s
Info: of which strict legalisation: 2.52s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1040, wirelen = 79257
Info: at iteration #5: temp = 0.000000, timing cost = 1417, wirelen = 73531
Info: at iteration #10: temp = 0.000000, timing cost = 1327, wirelen = 72227
Info: at iteration #15: temp = 0.000000, timing cost = 1293, wirelen = 71777
Info: at iteration #20: temp = 0.000000, timing cost = 1276, wirelen = 71618
Info: at iteration #20: temp = 0.000000, timing cost = 1274, wirelen = 71620
Info: SA placement time 18.65s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 75.51 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.87 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.56 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 2382, 3016) |+
Info: [ 3016, 3650) |**+
Info: [ 3650, 4284) |*+
Info: [ 4284, 4918) |*****+
Info: [ 4918, 5552) |******+
Info: [ 5552, 6186) |******+
Info: [ 6186, 6820) |**********+
Info: [ 6820, 7454) |****************+
Info: [ 7454, 8088) |**********************+
Info: [ 8088, 8722) |*********************************+
Info: [ 8722, 9356) |****************************************+
Info: [ 9356, 9990) |***************************************+
Info: [ 9990, 10624) |*******************************+
Info: [ 10624, 11258) |*********************************+
Info: [ 11258, 11892) |************************************+
Info: [ 11892, 12526) |*****************************************+
Info: [ 12526, 13160) |************************************************************
Info: [ 13160, 13794) |**************************************************+
Info: [ 13794, 14428) |************************************************+
Info: [ 14428, 15062) |***********************************************+
Info: Checksum: 0x47624ea3
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39492 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 467 532 | 467 532 | 39202| 1.40 1.40|
Info: 2000 | 912 1087 | 445 555 | 38943| 1.33 2.74|
Info: 3000 | 1149 1850 | 237 763 | 38329| 0.91 3.65|
Info: 4000 | 1446 2553 | 297 703 | 37724| 0.89 4.53|
Info: 5000 | 1551 3448 | 105 895 | 37030| 0.69 5.22|
Info: 6000 | 1710 4289 | 159 841 | 36379| 0.73 5.96|
Info: 7000 | 1854 5145 | 144 856 | 35862| 0.70 6.65|
Info: 8000 | 1972 6027 | 118 882 | 35082| 0.52 7.17|
Info: 9000 | 2075 6924 | 103 897 | 34229| 0.54 7.71|
Info: 10000 | 2163 7836 | 88 912 | 33479| 0.36 8.07|
Info: 11000 | 2284 8715 | 121 879 | 32836| 0.52 8.59|
Info: 12000 | 2390 9609 | 106 894 | 32100| 0.56 9.15|
Info: 13000 | 2526 10473 | 136 864 | 31477| 0.72 9.87|
Info: 14000 | 2646 11353 | 120 880 | 30686| 0.41 10.28|
Info: 15000 | 2764 12235 | 118 882 | 30078| 0.44 10.72|
Info: 16000 | 2915 13084 | 151 849 | 29314| 0.47 11.19|
Info: 17000 | 3034 13965 | 119 881 | 28507| 0.56 11.75|
Info: 18000 | 3185 14814 | 151 849 | 27768| 0.50 12.25|
Info: 19000 | 3353 15646 | 168 832 | 27312| 0.63 12.88|
Info: 20000 | 3565 16434 | 212 788 | 26725| 0.46 13.34|
Info: 21000 | 3774 17225 | 209 791 | 26155| 0.61 13.95|
Info: 22000 | 3928 18071 | 154 846 | 25470| 0.53 14.48|
Info: 23000 | 4104 18895 | 176 824 | 24798| 0.48 14.96|
Info: 24000 | 4337 19662 | 233 767 | 24245| 0.72 15.67|
Info: 25000 | 4569 20430 | 232 768 | 23629| 0.49 16.17|
Info: 26000 | 4811 21187 | 242 757 | 23075| 0.82 16.99|
Info: 27000 | 5024 21958 | 213 771 | 22355| 0.52 17.51|
Info: 28000 | 5280 22686 | 256 728 | 21901| 0.55 18.07|
Info: 29000 | 5530 23402 | 250 716 | 21449| 0.48 18.55|
Info: 30000 | 5780 24108 | 250 706 | 20761| 0.45 19.01|
Info: 31000 | 6041 24804 | 261 696 | 20236| 0.78 19.78|
Info: 32000 | 6299 25513 | 258 709 | 19727| 0.53 20.31|
Info: 33000 | 6597 26187 | 298 674 | 19150| 0.52 20.83|
Info: 34000 | 6927 26803 | 330 616 | 18571| 0.46 21.29|
Info: 35000 | 7155 27502 | 228 699 | 17936| 0.44 21.73|
Info: 36000 | 7399 28230 | 244 728 | 17291| 0.52 22.26|
Info: 37000 | 7579 28990 | 180 760 | 16650| 0.64 22.90|
Info: 38000 | 7786 29760 | 207 770 | 15898| 0.42 23.31|
Info: 39000 | 8018 30521 | 232 761 | 15658| 1.05 24.37|
Info: 40000 | 8220 31287 | 202 766 | 14959| 0.51 24.88|
Info: 41000 | 8411 32019 | 191 732 | 14324| 0.61 25.49|
Info: 42000 | 8626 32766 | 215 747 | 13722| 0.60 26.10|
Info: 43000 | 8825 33534 | 199 768 | 13078| 0.67 26.77|
Info: 44000 | 9046 34235 | 221 701 | 12430| 0.59 27.36|
Info: 45000 | 9239 34980 | 193 745 | 11787| 0.74 28.10|
Info: 46000 | 9457 35714 | 218 734 | 11155| 0.75 28.85|
Info: 47000 | 9693 36455 | 236 741 | 10723| 0.78 29.63|
Info: 48000 | 10007 37129 | 314 674 | 10394| 0.98 30.61|
Info: 49000 | 10136 37934 | 129 805 | 9605| 0.45 31.06|
Info: 50000 | 10290 38747 | 154 813 | 9031| 0.60 31.66|
Info: 51000 | 10515 39501 | 225 754 | 8493| 1.09 32.76|
Info: 52000 | 10707 40244 | 192 743 | 7805| 0.44 33.20|
Info: 53000 | 10840 41026 | 133 782 | 7092| 0.42 33.63|
Info: 54000 | 11004 41840 | 164 814 | 6474| 0.71 34.33|
Info: 55000 | 11253 42558 | 249 718 | 5947| 0.98 35.32|
Info: 56000 | 11376 43409 | 123 851 | 5136| 0.38 35.69|
Info: 57000 | 11651 44134 | 275 725 | 4795| 1.14 36.83|
Info: 58000 | 11906 44877 | 255 743 | 4203| 1.01 37.84|
Info: 59000 | 12103 45680 | 197 803 | 3515| 0.58 38.42|
Info: 60000 | 12435 46348 | 332 668 | 3210| 1.31 39.73|
Info: 61000 | 12778 47005 | 343 657 | 3020| 1.85 41.59|
Info: 62000 | 13090 47693 | 312 688 | 2495| 1.01 42.60|
Info: 63000 | 13246 48493 | 156 800 | 1722| 0.55 43.14|
Info: 64000 | 13425 49225 | 179 732 | 1333| 1.26 44.41|
Info: 65000 | 13645 49922 | 220 697 | 715| 0.97 45.37|
Info: 66000 | 13895 50593 | 250 671 | 238| 1.27 46.65|
Info: 66629 | 14073 50999 | 178 406 | 0| 0.72 47.36|
Info: Routing complete.
Info: Router1 time 47.36s
Info: Checksum: 0xc68b6218
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_director.job_out_slot_TRELLIS_FF_Q.Q
Info: routing 0.92 1.32 Net u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0[4] (26,39) -> (24,27)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[12]_LUT4_C_Z_PFUMX_Z_1_C0_L6MUX21_Z_1_SD_LUT4_Z.D
Info: Defined in:
Info: hardware/v2/rtl/neural_director.v:73.39-73.51
Info: logic 0.18 1.50 Source u_dataflow_core.u_dep_mgr.node_state[12]_LUT4_C_Z_PFUMX_Z_1_C0_L6MUX21_Z_1_SD_LUT4_Z.F
Info: routing 1.25 2.74 Net u_dataflow_core.u_dep_mgr.node_state[12]_LUT4_C_Z_PFUMX_Z_1_C0_L6MUX21_Z_1_SD[4] (24,27) -> (26,40)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[27]_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 2.94 Source u_dataflow_core.u_dep_mgr.node_producer_ids[27]_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 1.42 4.36 Net u_dataflow_core.u_dep_mgr.node_producer_ids[15]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z_C[3] (26,40) -> (26,55)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.53 Source u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C.F
Info: routing 0.32 4.86 Net u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z[3] (26,55) -> (26,55)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.04 Source u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D.F
Info: routing 0.00 5.04 Net u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z (26,55) -> (26,55)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
Info: logic 0.13 5.16 Source u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
Info: routing 0.63 5.80 Net u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[0] (26,55) -> (26,56)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_D.A
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.98 Source u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_D.F
Info: routing 1.25 7.23 Net u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_D_Z[4] (26,56) -> (26,40)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 7.42 Source u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.48 7.90 Net u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z[5] (26,40) -> (25,40)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 8.09 Source u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A.OFX
Info: routing 0.00 8.09 Net u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z (25,40) -> (25,40)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
Info: logic 0.18 8.27 Source u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.99 9.26 Net u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_D1_Z[2] (25,40) -> (27,35)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_LSR_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.44 Source u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info: routing 0.69 10.13 Net u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_LSR (27,35) -> (27,31)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_2.LSR
Info: setup 0.29 10.42 Source u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_2.LSR
Info: 2.47 ns logic, 7.95 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 3.28 3.28 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (12,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.46 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.78 4.24 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D[2] (12,9) -> (12,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.43 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z.F
Info: routing 0.12 4.54 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI (12,9) -> (12,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35.DI
Info: setup 0.00 4.54 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35.DI
Info: 0.36 ns logic, 4.18 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 0.91 1.31 Net u_spi_bridge.byte_idx[3] (21,33) -> (21,32)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.49 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.47 1.96 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (21,32) -> (21,32)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.14 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.87 4.01 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (21,32) -> (14,57)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.19 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.67 4.86 Net spi_miso_LUT4_Z_B[2] (14,57) -> (17,57)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.03 Source spi_miso_LUT4_Z.F
Info: routing 1.60 6.64 Net spi_miso$TRELLIS_IO_OUT (17,57) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.52 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 96.01 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.54 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.64 ns
Info: Slack histogram:
Info: legend: * represents 33 endpoint(s)
Info: + represents [1,33) endpoint(s)
Info: [ 5209, 5695) |+
Info: [ 5695, 6181) |**+
Info: [ 6181, 6667) |****+
Info: [ 6667, 7153) |*****+
Info: [ 7153, 7639) |********+
Info: [ 7639, 8125) |********+
Info: [ 8125, 8611) |********+
Info: [ 8611, 9097) |************+
Info: [ 9097, 9583) |*****************+
Info: [ 9583, 10069) |*************************+
Info: [ 10069, 10555) |************************************+
Info: [ 10555, 11041) |********************************************+
Info: [ 11041, 11527) |*********************************************+
Info: [ 11527, 12013) |*************************************+
Info: [ 12013, 12499) |********************************************+
Info: [ 12499, 12985) |**********************************************+
Info: [ 12985, 13471) |*******************************************************+
Info: [ 13471, 13957) |********************************************************+
Info: [ 13957, 14443) |************************************************************
Info: [ 14443, 14929) |*************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed7.log
+394
View File
@@ -0,0 +1,394 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 659893.
Info: at initial placer iter 0, wirelen = 3804
Info: at initial placer iter 1, wirelen = 3418
Info: at initial placer iter 2, wirelen = 3166
Info: at initial placer iter 3, wirelen = 3156
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3096, spread = 111406, legal = 125486; time = 0.53s
Info: at iteration #2, type ALL: wirelen solved = 12698, spread = 81233, legal = 97847; time = 0.52s
Info: at iteration #3, type ALL: wirelen solved = 19122, spread = 72009, legal = 88536; time = 0.50s
Info: at iteration #4, type ALL: wirelen solved = 22864, spread = 67327, legal = 85354; time = 0.44s
Info: at iteration #5, type ALL: wirelen solved = 24628, spread = 65589, legal = 80927; time = 0.39s
Info: at iteration #6, type ALL: wirelen solved = 25853, spread = 65011, legal = 81238; time = 0.46s
Info: at iteration #7, type ALL: wirelen solved = 27382, spread = 63244, legal = 79647; time = 0.46s
Info: at iteration #8, type ALL: wirelen solved = 28170, spread = 63034, legal = 79694; time = 0.40s
Info: at iteration #9, type ALL: wirelen solved = 28883, spread = 63060, legal = 80527; time = 0.41s
Info: at iteration #10, type ALL: wirelen solved = 29696, spread = 62909, legal = 81324; time = 0.44s
Info: at iteration #11, type ALL: wirelen solved = 30752, spread = 62896, legal = 80283; time = 0.43s
Info: at iteration #12, type ALL: wirelen solved = 31448, spread = 62563, legal = 81569; time = 0.43s
Info: HeAP Placer Time: 7.93s
Info: of which solving equations: 3.95s
Info: of which spreading cells: 0.52s
Info: of which strict legalisation: 1.85s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1276, wirelen = 79647
Info: at iteration #5: temp = 0.000000, timing cost = 1232, wirelen = 73781
Info: at iteration #10: temp = 0.000000, timing cost = 1417, wirelen = 71986
Info: at iteration #15: temp = 0.000000, timing cost = 1243, wirelen = 71482
Info: at iteration #20: temp = 0.000000, timing cost = 1359, wirelen = 71286
Info: at iteration #25: temp = 0.000000, timing cost = 1211, wirelen = 71193
Info: at iteration #28: temp = 0.000000, timing cost = 1385, wirelen = 71165
Info: SA placement time 25.66s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 75.96 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.45 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.99 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 2460, 3090) |+
Info: [ 3090, 3720) |*+
Info: [ 3720, 4350) |*+
Info: [ 4350, 4980) |****+
Info: [ 4980, 5610) |*****+
Info: [ 5610, 6240) |*********+
Info: [ 6240, 6870) |********+
Info: [ 6870, 7500) |********+
Info: [ 7500, 8130) |*******************+
Info: [ 8130, 8760) |**************************+
Info: [ 8760, 9390) |***********************************+
Info: [ 9390, 10020) |****************************************+
Info: [ 10020, 10650) |**************************************+
Info: [ 10650, 11280) |********************************+
Info: [ 11280, 11910) |****************************+
Info: [ 11910, 12540) |***********************************+
Info: [ 12540, 13170) |*******************************************************+
Info: [ 13170, 13800) |************************************************************
Info: [ 13800, 14430) |********************************************+
Info: [ 14430, 15060) |*********************************************+
Info: Checksum: 0xb2c62bb6
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39305 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 648 351 | 648 351 | 39084| 1.56 1.56|
Info: 2000 | 1167 832 | 519 481 | 38773| 1.32 2.89|
Info: 3000 | 1508 1491 | 341 659 | 38348| 1.39 4.28|
Info: 4000 | 1776 2223 | 268 732 | 37825| 1.24 5.52|
Info: 5000 | 1933 3066 | 157 843 | 37141| 0.57 6.09|
Info: 6000 | 2046 3953 | 113 887 | 36364| 0.53 6.61|
Info: 7000 | 2154 4845 | 108 892 | 35523| 0.37 6.98|
Info: 8000 | 2242 5757 | 88 912 | 34666| 0.46 7.45|
Info: 9000 | 2353 6646 | 111 889 | 33869| 0.37 7.82|
Info: 10000 | 2467 7532 | 114 886 | 33075| 0.48 8.30|
Info: 11000 | 2565 8434 | 98 902 | 32276| 0.38 8.68|
Info: 12000 | 2635 9364 | 70 930 | 31392| 0.43 9.11|
Info: 13000 | 2740 10259 | 105 895 | 30571| 0.34 9.45|
Info: 14000 | 2870 11129 | 130 870 | 29863| 0.39 9.85|
Info: 15000 | 3002 11997 | 132 868 | 29118| 0.50 10.35|
Info: 16000 | 3156 12843 | 154 846 | 28398| 0.37 10.71|
Info: 17000 | 3277 13722 | 121 879 | 27645| 0.39 11.10|
Info: 18000 | 3533 14466 | 256 744 | 27197| 1.65 12.74|
Info: 19000 | 3640 15359 | 107 893 | 26361| 0.38 13.13|
Info: 20000 | 3782 16217 | 142 858 | 25694| 0.35 13.48|
Info: 21000 | 4023 16976 | 241 759 | 25023| 0.44 13.92|
Info: 22000 | 4192 17807 | 169 831 | 24385| 0.39 14.31|
Info: 23000 | 4368 18628 | 176 821 | 23684| 0.48 14.79|
Info: 24000 | 4641 19348 | 273 720 | 23194| 0.56 15.35|
Info: 25000 | 4875 20098 | 234 750 | 22651| 0.35 15.71|
Info: 26000 | 5157 20794 | 282 696 | 22122| 0.46 16.17|
Info: 27000 | 5477 21431 | 320 637 | 21521| 0.46 16.63|
Info: 28000 | 5754 22117 | 277 686 | 20895| 0.38 17.00|
Info: 29000 | 5986 22841 | 232 724 | 20214| 0.42 17.42|
Info: 30000 | 6241 23555 | 255 714 | 19612| 0.49 17.92|
Info: 31000 | 6507 24270 | 266 715 | 19013| 0.44 18.36|
Info: 32000 | 6746 25011 | 239 741 | 18362| 0.58 18.93|
Info: 33000 | 7019 25697 | 273 686 | 17785| 0.53 19.47|
Info: 34000 | 7256 26401 | 237 704 | 17265| 0.54 20.01|
Info: 35000 | 7496 27097 | 240 696 | 16642| 0.60 20.61|
Info: 36000 | 7752 27808 | 256 711 | 16088| 0.74 21.35|
Info: 37000 | 7982 28527 | 230 719 | 15452| 0.53 21.87|
Info: 38000 | 8191 29261 | 209 734 | 14842| 0.65 22.52|
Info: 39000 | 8350 30037 | 159 776 | 14120| 0.57 23.09|
Info: 40000 | 8514 30839 | 164 802 | 13616| 0.66 23.75|
Info: 41000 | 8687 31639 | 173 800 | 13031| 0.57 24.32|
Info: 42000 | 8841 32408 | 154 769 | 12413| 0.59 24.90|
Info: 43000 | 8993 33207 | 152 799 | 11666| 0.66 25.56|
Info: 44000 | 9216 33950 | 223 743 | 11003| 0.60 26.17|
Info: 45000 | 9495 34651 | 279 701 | 10555| 1.06 27.23|
Info: 46000 | 9683 35402 | 188 751 | 9884| 0.59 27.82|
Info: 47000 | 9832 36197 | 149 795 | 9127| 0.47 28.29|
Info: 48000 | 10182 36823 | 350 626 | 8676| 1.01 29.30|
Info: 49000 | 10313 37608 | 131 785 | 7869| 0.31 29.61|
Info: 50000 | 10454 38412 | 141 804 | 7160| 0.41 30.02|
Info: 51000 | 10638 39205 | 184 793 | 6485| 0.71 30.73|
Info: 52000 | 10861 39962 | 223 757 | 5850| 0.81 31.54|
Info: 53000 | 10995 40790 | 134 828 | 5111| 0.40 31.94|
Info: 54000 | 11420 41365 | 425 575 | 4836| 1.02 32.97|
Info: 55000 | 11741 42044 | 321 679 | 4570| 1.09 34.05|
Info: 56000 | 12032 42751 | 291 707 | 4094| 1.12 35.18|
Info: 57000 | 12275 43508 | 243 757 | 3475| 0.74 35.91|
Info: 58000 | 12694 44089 | 419 581 | 3248| 1.32 37.23|
Info: 59000 | 13098 44685 | 404 596 | 3240| 1.57 38.80|
Info: 60000 | 13504 45279 | 406 594 | 3019| 1.44 40.24|
Info: 61000 | 13859 45924 | 355 645 | 2674| 0.97 41.21|
Info: 62000 | 14148 46635 | 289 711 | 2496| 0.98 42.19|
Info: 63000 | 14432 47348 | 284 713 | 1948| 0.61 42.80|
Info: 64000 | 14664 48081 | 232 733 | 1743| 0.77 43.57|
Info: 65000 | 14811 48801 | 147 720 | 992| 0.66 44.23|
Info: 66000 | 15036 49482 | 225 681 | 476| 0.97 45.20|
Info: 66865 | 15175 50133 | 139 651 | 0| 0.67 45.87|
Info: Routing complete.
Info: Router1 time 45.87s
Info: Checksum: 0xc233a902
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_sdram_backend.w_cache_addr[2]_TRELLIS_FF_Q_19.Q
Info: routing 0.87 1.26 Net u_sdram_backend.w_cache_addr[2][19] (24,3) -> (24,3)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z_D_LUT4_Z_2.D
Info: logic 0.18 1.44 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z_D_LUT4_Z_2.F
Info: routing 0.60 2.04 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z_D[1] (24,3) -> (24,3)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z.B
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.22 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z.F
Info: routing 0.85 3.07 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D[3] (24,3) -> (23,2)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.25 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2.F
Info: routing 0.60 3.85 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z[2] (23,2) -> (23,2)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.03 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 1.28 5.32 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[1] (23,2) -> (13,6)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.50 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.80 6.30 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (13,6) -> (18,5)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.48 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.48 6.95 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (18,5) -> (18,5)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 7.13 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.34 7.47 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (18,5) -> (18,5)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.65 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 1.81 9.46 Net u_host_arb.m_wr_LUT4_C_Z[3] (18,5) -> (7,21)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.64 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 1.11 10.75 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (7,21) -> (10,4)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 10.93 Source u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.F
Info: routing 0.12 11.04 Net u_sdram_backend.state_TRELLIS_FF_Q_3_DI (10,4) -> (10,4)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: setup 0.00 11.04 Source u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: 2.19 ns logic, 8.85 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[2]$tr_io.O
Info: routing 3.35 3.35 Net sdram_dq[2]$TRELLIS_IO_IN (0,29) -> (15,4)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.53 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.63 4.16 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D[2] (15,4) -> (17,4)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.34 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z.F
Info: routing 0.12 4.46 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI (17,4) -> (17,4)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50.DI
Info: setup 0.00 4.46 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50.DI
Info: 0.36 ns logic, 4.10 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 0.99 1.39 Net u_spi_bridge.byte_idx[3] (25,33) -> (25,26)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.57 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.65 2.22 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (25,26) -> (24,26)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.40 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 2.01 4.41 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (24,26) -> (16,45)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.59 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.50 5.09 Net spi_miso_LUT4_Z_B[2] (16,45) -> (17,45)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.27 Source spi_miso_LUT4_Z.F
Info: routing 2.06 7.33 Net spi_miso$TRELLIS_IO_OUT (17,45) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 6.21 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 90.55 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.46 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.33 ns
Info: Slack histogram:
Info: legend: * represents 42 endpoint(s)
Info: + represents [1,42) endpoint(s)
Info: [ 4581, 5098) |+
Info: [ 5098, 5615) |+
Info: [ 5615, 6132) |**+
Info: [ 6132, 6649) |**+
Info: [ 6649, 7166) |******+
Info: [ 7166, 7683) |******+
Info: [ 7683, 8200) |*******+
Info: [ 8200, 8717) |*******+
Info: [ 8717, 9234) |***********+
Info: [ 9234, 9751) |***************+
Info: [ 9751, 10268) |*********************+
Info: [ 10268, 10785) |**********************************+
Info: [ 10785, 11302) |**************************************+
Info: [ 11302, 11819) |***********************************+
Info: [ 11819, 12336) |***********************************+
Info: [ 12336, 12853) |*****************************+
Info: [ 12853, 13370) |***************************************+
Info: [ 13370, 13887) |************************************************************
Info: [ 13887, 14404) |*************************************************+
Info: [ 14404, 14921) |******************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/top.config
+187682 -149310
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hardware/v2/nms/synthesis/nms_multiproc_n4/top.json
+365213 -230483
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hardware/v2/nms/synthesis/nms_multiproc_n4/yosys.log
+16901 -13095
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hardware/v2/nms/synthesis/nms_multiproc_n8/nextpnr.log
-894
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@@ -1,894 +0,0 @@
Info: Logic utilisation before packing:
Info: Total LUT4s: 8523/43848 19%
Info: logic LUTs: 4805/43848 10%
Info: carry LUTs: 1912/43848 4%
Info: RAM LUTs: 1204/ 5481 21%
Info: RAMW LUTs: 602/10962 5%
Info: Total DFFs: 10966/43848 25%
Info: Packing IOs..
Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 4999 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xcd88748e
Info: Device utilisation:
Info: TRELLIS_IO: 157/ 245 64%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 10966/ 43848 25%
Info: TRELLIS_COMB: 8953/ 43848 20%
Info: TRELLIS_RAMW: 301/ 5481 5%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 10928 cells, random placement wirelen = 888368.
Info: at initial placer iter 0, wirelen = 17970
Info: at initial placer iter 1, wirelen = 15622
Info: at initial placer iter 2, wirelen = 15109
Info: at initial placer iter 3, wirelen = 14883
Info: Running main analytical placer, max placement attempts per cell = 52234420.
Info: at iteration #1, type ALL: wirelen solved = 13670, spread = 212169, legal = 250678; time = 0.82s
Info: at iteration #2, type ALL: wirelen solved = 31315, spread = 142620, legal = 180431; time = 0.78s
Info: at iteration #3, type ALL: wirelen solved = 39835, spread = 128648, legal = 158988; time = 0.72s
Info: at iteration #4, type ALL: wirelen solved = 44200, spread = 120379, legal = 150878; time = 0.71s
Info: at iteration #5, type ALL: wirelen solved = 46996, spread = 121353, legal = 151998; time = 0.73s
Info: at iteration #6, type ALL: wirelen solved = 50066, spread = 121356, legal = 149815; time = 0.70s
Info: at iteration #7, type ALL: wirelen solved = 52166, spread = 122431, legal = 152767; time = 0.69s
Info: at iteration #8, type ALL: wirelen solved = 52945, spread = 125389, legal = 151575; time = 0.71s
Info: at iteration #9, type ALL: wirelen solved = 54575, spread = 126100, legal = 157631; time = 0.69s
Info: at iteration #10, type ALL: wirelen solved = 55469, spread = 126053, legal = 162107; time = 0.70s
Info: at iteration #11, type ALL: wirelen solved = 55395, spread = 129268, legal = 159748; time = 0.70s
Info: HeAP Placer Time: 8.99s
Info: of which solving equations: 1.79s
Info: of which spreading cells: 0.28s
Info: of which strict legalisation: 6.38s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 432, wirelen = 149815
Info: at iteration #5: temp = 0.000000, timing cost = 343, wirelen = 136392
Info: at iteration #10: temp = 0.000000, timing cost = 326, wirelen = 133037
Info: at iteration #15: temp = 0.000000, timing cost = 319, wirelen = 131916
Info: at iteration #20: temp = 0.000000, timing cost = 315, wirelen = 131398
Info: at iteration #25: temp = 0.000000, timing cost = 315, wirelen = 131063
Info: at iteration #30: temp = 0.000000, timing cost = 314, wirelen = 130888
Info: at iteration #35: temp = 0.000000, timing cost = 317, wirelen = 130821
Info: at iteration #36: temp = 0.000000, timing cost = 316, wirelen = 130811
Info: SA placement time 13.51s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 29.59 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> <async> : 12.76 ns
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 14.75 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.88 ns
Info: Slack histogram:
Info: legend: * represents 147 endpoint(s)
Info: + represents [1,147) endpoint(s)
Info: [-21293, -19632) |+
Info: [-19632, -17971) |
Info: [-17971, -16310) |
Info: [-16310, -14649) |
Info: [-14649, -12988) |
Info: [-12988, -11327) |
Info: [-11327, -9666) |
Info: [ -9666, -8005) |
Info: [ -8005, -6344) |
Info: [ -6344, -4683) |
Info: [ -4683, -3022) |+
Info: [ -3022, -1361) |+
Info: [ -1361, 300) |+
Info: [ 300, 1961) |*+
Info: [ 1961, 3622) |***+
Info: [ 3622, 5283) |*********+
Info: [ 5283, 6944) |****************+
Info: [ 6944, 8605) |********************************+
Info: [ 8605, 10266) |************************************************************
Info: [ 10266, 11927) |*****************************************************+
Info: Checksum: 0x929bb535
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 53981 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 202 797 | 202 797 | 53224| 0.60 0.60|
Info: 2000 | 338 1661 | 136 864 | 52429| 0.27 0.87|
Info: 3000 | 513 2486 | 175 825 | 51709| 0.33 1.20|
Info: 4000 | 677 3322 | 164 836 | 50934| 0.15 1.35|
Info: 5000 | 931 4068 | 254 746 | 50228| 0.13 1.48|
Info: 6000 | 1114 4885 | 183 817 | 49438| 0.14 1.62|
Info: 7000 | 1306 5693 | 192 808 | 48684| 0.18 1.79|
Info: 8000 | 1542 6457 | 236 764 | 47987| 0.17 1.97|
Info: 9000 | 1745 7254 | 203 797 | 47265| 0.14 2.11|
Info: 10000 | 1825 8174 | 80 920 | 46478| 0.13 2.23|
Info: 11000 | 1938 8990 | 113 816 | 45622| 0.13 2.37|
Info: 12000 | 2210 9704 | 272 714 | 44953| 0.11 2.47|
Info: 13000 | 2391 10501 | 181 797 | 44157| 0.10 2.58|
Info: 14000 | 2431 11461 | 40 960 | 43213| 0.13 2.71|
Info: 15000 | 2518 12373 | 87 912 | 42322| 0.12 2.83|
Info: 16000 | 2597 13292 | 79 919 | 41521| 0.13 2.96|
Info: 17000 | 2677 14212 | 80 920 | 40712| 0.13 3.08|
Info: 18000 | 2742 15146 | 65 934 | 39910| 0.13 3.22|
Info: 19000 | 2799 16089 | 57 943 | 39085| 0.17 3.39|
Info: 20000 | 2833 17055 | 34 966 | 38166| 0.13 3.52|
Info: 21000 | 2900 17987 | 67 932 | 37307| 0.11 3.63|
Info: 22000 | 2961 18926 | 61 939 | 36469| 0.14 3.77|
Info: 23000 | 3006 19881 | 45 955 | 35534| 0.11 3.88|
Info: 24000 | 3057 20829 | 51 948 | 34692| 0.12 4.00|
Info: 25000 | 3113 21770 | 56 941 | 33777| 0.10 4.11|
Info: 26000 | 3198 22677 | 85 907 | 32952| 0.13 4.24|
Info: 27000 | 3248 23622 | 50 945 | 32023| 0.12 4.36|
Info: 28000 | 3308 24554 | 60 932 | 31196| 0.11 4.46|
Info: 29000 | 3369 25466 | 61 912 | 30279| 0.12 4.58|
Info: 30000 | 3419 26397 | 50 931 | 29350| 0.10 4.68|
Info: 31000 | 3487 27314 | 68 917 | 28492| 0.11 4.79|
Info: 32000 | 3523 28264 | 36 950 | 27538| 0.11 4.89|
Info: 33000 | 3560 29207 | 37 943 | 26588| 0.13 5.02|
Info: 34000 | 3632 30093 | 72 886 | 25697| 0.13 5.15|
Info: 35000 | 3725 30970 | 93 877 | 24940| 0.16 5.30|
Info: 36000 | 3799 31827 | 74 857 | 24092| 0.12 5.43|
Info: 37000 | 3951 32641 | 152 814 | 23320| 0.19 5.62|
Info: 38000 | 4008 33541 | 57 900 | 22411| 0.11 5.73|
Info: 39000 | 4073 34418 | 65 877 | 21504| 0.12 5.85|
Info: 40000 | 4157 35313 | 84 895 | 20622| 0.17 6.02|
Info: 41000 | 4224 36173 | 67 860 | 19827| 0.13 6.16|
Info: 42000 | 4262 37061 | 38 888 | 18875| 0.09 6.25|
Info: 43000 | 4343 37914 | 81 853 | 17986| 0.14 6.39|
Info: 44000 | 4518 38715 | 175 801 | 17276| 0.26 6.64|
Info: 45000 | 4550 39596 | 32 881 | 16316| 0.07 6.71|
Info: 46000 | 4632 40443 | 82 847 | 15503| 0.12 6.83|
Info: 47000 | 4687 41294 | 55 851 | 14568| 0.09 6.93|
Info: 48000 | 4894 42085 | 207 791 | 13913| 0.28 7.20|
Info: 49000 | 5067 42851 | 173 766 | 13288| 0.20 7.41|
Info: 50000 | 5132 43738 | 65 887 | 12378| 0.09 7.50|
Info: 51000 | 5243 44614 | 111 876 | 11588| 0.11 7.61|
Info: 52000 | 5455 45402 | 212 788 | 10951| 0.28 7.89|
Info: 53000 | 5595 46262 | 140 860 | 10252| 0.19 8.08|
Info: 54000 | 5658 47199 | 63 937 | 9334| 0.08 8.16|
Info: 55000 | 5860 47997 | 202 798 | 8870| 0.29 8.45|
Info: 56000 | 6121 48736 | 261 739 | 8240| 0.36 8.81|
Info: 57000 | 6210 49647 | 89 911 | 7407| 0.13 8.93|
Info: 58000 | 6376 50481 | 166 834 | 6673| 0.17 9.10|
Info: 59000 | 6521 51336 | 145 855 | 5822| 0.10 9.20|
Info: 60000 | 6664 52183 | 143 847 | 5269| 0.23 9.43|
Info: 61000 | 6903 52920 | 239 737 | 4885| 0.30 9.73|
Info: 62000 | 7054 53744 | 151 824 | 4324| 0.29 10.02|
Info: 63000 | 7209 54544 | 155 800 | 3747| 0.26 10.29|
Info: 64000 | 7412 55314 | 203 770 | 3236| 0.35 10.64|
Info: 65000 | 7574 56105 | 162 791 | 2585| 0.30 10.95|
Info: 66000 | 7732 56912 | 158 807 | 1972| 0.37 11.32|
Info: 67000 | 7922 57684 | 190 772 | 1420| 0.50 11.82|
Info: 68000 | 8106 58470 | 184 786 | 848| 0.36 12.18|
Info: 69000 | 8265 59285 | 159 815 | 339| 0.36 12.53|
Info: 69653 | 8375 59807 | 110 522 | 0| 0.28 12.81|
Info: Routing complete.
Info: Router1 time 12.81s
Info: Checksum: 0xbb354049
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_act_fill.resident_tag_TRELLIS_FF_Q_7.Q
Info: routing 0.89 1.28 Net u_dataflow_core.act_resident_tag[8] (40,40) -> (37,40)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.46 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_Z.F
Info: routing 0.89 2.35 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C[0] (37,40) -> (37,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_A_Z_PFUMX_ALUT_BLUT_LUT4_Z.A
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.31 2.66 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_A_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
Info: routing 0.81 3.47 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_LUT4_Z_1_C_LUT4_A_Z_PFUMX_ALUT_Z[2] (37,37) -> (35,38)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_A_Z_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.65 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_A_Z_LUT4_Z_1.F
Info: routing 0.72 4.37 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_SD_L6MUX21_Z_1_SD_LUT4_A_Z[5] (35,38) -> (34,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D_Z_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 4.56 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D_Z_LUT4_Z_C_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.86 5.43 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D_Z_LUT4_Z_C[1] (34,39) -> (35,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 5.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 5.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,35) -> (35,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 5.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 5.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,35) -> (35,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 5.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 5.84 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,35) -> (35,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 5.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 5.84 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,35) -> (35,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 5.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 5.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (35,35) -> (35,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 5.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 5.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (35,35) -> (36,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 5.95 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 5.95 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,35) -> (36,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 5.95 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 5.95 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,35) -> (36,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 6.01 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 6.01 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,35) -> (36,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 6.01 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 6.01 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,35) -> (36,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 6.06 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 6.06 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,35) -> (36,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 6.06 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 6.06 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (36,35) -> (36,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 6.12 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 6.12 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (36,35) -> (36,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 6.12 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 6.12 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (36,35) -> (37,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 6.17 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
Info: routing 0.00 6.17 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (37,35) -> (37,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
Info: logic 0.00 6.17 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
Info: routing 0.00 6.17 Net $nextpnr_CCU2C_171$CIN (37,35) -> (37,35)
Info: Sink $nextpnr_CCU2C_171$CCU2_COMB0.FCI
Info: logic 0.33 6.50 Source $nextpnr_CCU2C_171$CCU2_COMB0.F
Info: routing 0.55 7.05 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (37,35) -> (36,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.23 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
Info: routing 0.84 8.07 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[2] (36,36) -> (38,40)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.26 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z.F
Info: routing 0.84 9.09 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[1] (38,40) -> (38,38)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 9.45 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
Info: routing 0.00 9.45 Net $nextpnr_CCU2C_183$CIN (38,38) -> (38,38)
Info: Sink $nextpnr_CCU2C_183$CCU2_COMB0.FCI
Info: logic 0.33 9.77 Source $nextpnr_CCU2C_183$CCU2_COMB0.F
Info: routing 0.52 10.30 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (38,38) -> (38,39)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 10.48 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
Info: routing 0.80 11.28 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[2] (38,39) -> (37,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.46 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F
Info: routing 0.85 12.31 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1[1] (37,36) -> (38,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 12.67 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.67 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,37) -> (38,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.72 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 12.72 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (38,37) -> (38,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 12.72 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.72 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,37) -> (39,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 12.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,37) -> (39,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 12.78 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.78 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,37) -> (39,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 12.84 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,37) -> (39,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 12.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.84 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,37) -> (39,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 12.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,37) -> (39,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 12.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (39,37) -> (39,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.95 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 12.95 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (39,37) -> (39,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 12.95 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 12.95 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (39,37) -> (40,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.00 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
Info: routing 0.00 13.00 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (40,37) -> (40,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
Info: logic 0.00 13.00 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
Info: routing 0.00 13.00 Net $nextpnr_CCU2C_195$CIN (40,37) -> (40,37)
Info: Sink $nextpnr_CCU2C_195$CCU2_COMB0.FCI
Info: logic 0.33 13.33 Source $nextpnr_CCU2C_195$CCU2_COMB0.F
Info: routing 0.56 13.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (40,37) -> (42,38)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 14.07 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
Info: routing 1.00 15.08 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C[2] (42,38) -> (37,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 15.26 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_Z_1.F
Info: routing 0.80 16.06 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT[3] (37,36) -> (38,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 16.41 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 16.41 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,36) -> (39,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 16.47 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 16.47 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,36) -> (39,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 16.47 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 16.47 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,36) -> (39,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 16.52 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 16.52 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,36) -> (39,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 16.52 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 16.52 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,36) -> (39,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 16.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 16.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,36) -> (39,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 16.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 16.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (39,36) -> (39,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 16.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 16.64 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (39,36) -> (39,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 16.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 16.64 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (39,36) -> (40,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 16.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
Info: routing 0.00 16.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (40,36) -> (40,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
Info: logic 0.00 16.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
Info: routing 0.00 16.69 Net $nextpnr_CCU2C_199$CIN (40,36) -> (40,36)
Info: Sink $nextpnr_CCU2C_199$CCU2_COMB0.FCI
Info: logic 0.33 17.02 Source $nextpnr_CCU2C_199$CCU2_COMB0.F
Info: routing 0.79 17.81 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z_D[4] (40,36) -> (43,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_C_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 17.99 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_C_Z_LUT4_Z.F
Info: routing 0.35 18.34 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C_LUT4_Z_C[2] (43,37) -> (43,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 18.52 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B1_LUT4_Z_C_LUT4_Z.F
Info: routing 1.01 19.53 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_B1_LUT4_Z_C[1] (43,35) -> (42,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 19.89 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 19.89 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (42,37) -> (43,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 19.94 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
Info: routing 0.00 19.94 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (43,37) -> (43,37)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
Info: logic 0.00 19.94 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
Info: routing 0.00 19.94 Net $nextpnr_CCU2C_201$CIN (43,37) -> (43,37)
Info: Sink $nextpnr_CCU2C_201$CCU2_COMB0.FCI
Info: logic 0.33 20.27 Source $nextpnr_CCU2C_201$CCU2_COMB0.F
Info: routing 0.39 20.66 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (43,37) -> (44,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 20.84 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
Info: routing 0.62 21.46 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_B1_LUT4_Z_C[2] (44,36) -> (37,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 21.64 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F
Info: routing 0.74 22.38 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1[1] (37,35) -> (41,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 22.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 22.74 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (41,36) -> (41,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 22.79 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 22.79 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (41,36) -> (41,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 22.79 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 22.79 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (41,36) -> (41,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 22.85 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 22.85 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (41,36) -> (41,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 22.85 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 22.85 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (41,36) -> (42,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 22.91 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 22.91 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (42,36) -> (42,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 22.91 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 22.91 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (42,36) -> (42,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 22.96 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 22.96 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (42,36) -> (42,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 22.96 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 22.96 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (42,36) -> (42,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 23.02 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 23.02 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (42,36) -> (42,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 23.02 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 23.02 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (42,36) -> (42,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 23.07 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 23.07 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (42,36) -> (42,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 23.07 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 23.07 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN (42,36) -> (43,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 23.13 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
Info: routing 0.00 23.13 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (43,36) -> (43,36)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
Info: logic 0.00 23.13 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
Info: routing 0.00 23.13 Net $nextpnr_CCU2C_17$CIN (43,36) -> (43,36)
Info: Sink $nextpnr_CCU2C_17$CCU2_COMB0.FCI
Info: logic 0.33 23.46 Source $nextpnr_CCU2C_17$CCU2_COMB0.F
Info: routing 0.56 24.02 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT (43,36) -> (42,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 24.20 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_COUT_LUT4_D.F
Info: routing 0.94 25.13 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C[2] (42,35) -> (40,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_C.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 25.31 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_C.F
Info: routing 1.04 26.35 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_C_Z[3] (40,32) -> (39,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.35 26.71 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 26.71 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,35) -> (39,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 26.77 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 26.77 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,35) -> (39,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 26.77 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 26.77 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,35) -> (40,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 26.82 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 26.82 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (40,35) -> (40,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 26.82 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 26.82 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (40,35) -> (40,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 26.88 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 26.88 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (40,35) -> (40,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 26.88 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 26.88 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (40,35) -> (40,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 26.93 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 26.93 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (40,35) -> (40,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 26.93 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 26.93 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT_CIN (40,35) -> (40,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 26.99 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 26.99 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_FCI_INT (40,35) -> (40,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 26.99 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 26.99 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_CIN (40,35) -> (41,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:85.21-85.59
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 27.05 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB0.FCO
Info: routing 0.00 27.05 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_FCI_INT (41,35) -> (41,35)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCI
Info: logic 0.00 27.05 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0$CCU2_COMB1.FCO
Info: routing 0.00 27.05 Net $nextpnr_CCU2C_1$CIN (41,35) -> (41,35)
Info: Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info: logic 0.33 27.37 Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info: routing 0.84 28.21 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_B0_LUT4_Z_C_CCU2C_B0_COUT[4] (41,35) -> (40,32)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 28.41 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.81 29.22 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1 (40,32) -> (38,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: logic 0.35 29.58 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 29.58 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,33) -> (38,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 29.63 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 29.63 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (38,33) -> (38,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 29.63 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 29.63 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (38,33) -> (39,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 29.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 29.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,33) -> (39,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 29.69 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 29.69 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,33) -> (39,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 29.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 29.74 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,33) -> (39,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 29.74 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 29.74 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,33) -> (39,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 29.80 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 29.80 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,33) -> (39,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 29.80 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 29.80 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (39,33) -> (39,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 29.86 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 29.86 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (39,33) -> (39,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 29.86 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 29.86 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT_CIN (39,33) -> (40,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_fill_ctrl.v:158.51-158.79
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 29.91 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 29.91 Net u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (40,33) -> (40,33)
Info: Sink u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 29.91 Source u_dataflow_core.u_act_fill.state_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 29.91 Net $nextpnr_CCU2C_3$CIN (40,33) -> (40,33)
Info: Sink $nextpnr_CCU2C_3$CCU2_COMB0.FCI
Info: logic 0.33 30.24 Source $nextpnr_CCU2C_3$CCU2_COMB0.F
Info: routing 0.80 31.04 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR[2] (40,33) -> (40,37)
Info: Sink u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 31.22 Source u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B.F
Info: routing 0.59 31.82 Net u_dataflow_core.u_act_fill.pf_start_TRELLIS_FF_Q_LSR_LUT4_B_Z (40,37) -> (41,38)
Info: Sink u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_20.CE
Info: setup 0.00 31.82 Source u_dataflow_core.u_act_fill.pf_addr_TRELLIS_FF_Q_20.CE
Info: 11.38 ns logic, 20.44 ns routing
Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: type curr total name
Info: source 0.00 0.00 Source reg_node_id[1]$tr_io.O
Info: routing 3.02 3.02 Net reg_node_id[1]$TRELLIS_IO_IN (60,0) -> (48,40)
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_1.C
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
Info: logic 0.18 3.20 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_1.F
Info: routing 0.99 4.19 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2_D[2] (48,40) -> (52,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.37 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2.F
Info: routing 0.32 4.69 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D[2] (52,40) -> (52,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.87 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
Info: routing 0.64 5.51 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[3] (52,40) -> (50,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.69 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
Info: routing 0.56 6.26 Net reg_ready_PFUMX_Z_C0[4] (50,40) -> (49,41)
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 6.45 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 3.80 10.24 Net reg_ready$TRELLIS_IO_OUT (49,41) -> (0,59)
Info: Sink reg_ready$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
Info: 0.91 ns logic, 9.33 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source reg_node_id[1]$tr_io.O
Info: routing 3.02 3.02 Net reg_node_id[1]$TRELLIS_IO_IN (60,0) -> (48,40)
Info: Sink reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_1.C
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:54.51-54.62
Info: logic 0.18 3.20 Source reg_ready_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_1.F
Info: routing 0.99 4.19 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2_D[2] (48,40) -> (52,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.37 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z_2.F
Info: routing 0.32 4.69 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D[2] (52,40) -> (52,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.87 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
Info: routing 0.64 5.51 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[3] (52,40) -> (50,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.69 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
Info: routing 0.56 6.26 Net reg_ready_PFUMX_Z_C0[4] (50,40) -> (49,41)
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 6.45 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.73 7.18 Net reg_ready$TRELLIS_IO_OUT (49,41) -> (54,41)
Info: Sink reg_valid_LUT4_B.D
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
Info: logic 0.18 7.36 Source reg_valid_LUT4_B.F
Info: routing 4.27 11.63 Net reg_valid_LUT4_B_Z[2] (54,41) -> (11,8)
Info: Sink u_dataflow_core.u_dep_mgr.node_x_base.0.5$DPRAM_COMB3.WRE
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.27 11.90 Source u_dataflow_core.u_dep_mgr.node_x_base.0.5$DPRAM_COMB3.WRE
Info: 1.36 ns logic, 10.54 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_dep_mgr.node_state[6]_TRELLIS_FF_Q_1.Q
Info: routing 0.99 1.38 Net u_dataflow_core.u_dep_mgr.first_ready_idx_PFUMX_Z_C0_LUT4_Z_D_PFUMX_Z_C0_PFUMX_Z_C0[0] (54,37) -> (53,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.56 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D_LUT4_Z.F
Info: routing 0.64 2.20 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1_D[1] (53,40) -> (52,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.38 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1_D_LUT4_Z_1.F
Info: routing 0.64 3.02 Net reg_ready_PFUMX_Z_C0_LUT4_Z_1_D[3] (52,40) -> (50,40)
Info: Sink reg_ready_PFUMX_Z_C0_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.20 Source reg_ready_PFUMX_Z_C0_LUT4_Z_1.F
Info: routing 0.56 3.77 Net reg_ready_PFUMX_Z_C0[4] (50,40) -> (49,41)
Info: Sink reg_ready_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 3.96 Source reg_ready_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 3.80 7.76 Net reg_ready$TRELLIS_IO_OUT (49,41) -> (0,59)
Info: Sink reg_ready$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/dependency_manager.v:53.52-53.61
Info: 1.13 ns logic, 6.63 ns routing
ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 31.43 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> <async> : 10.24 ns
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.90 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.76 ns
Info: Slack histogram:
Info: legend: * represents 176 endpoint(s)
Info: + represents [1,176) endpoint(s)
Info: [-19315, -17759) |+
Info: [-17759, -16203) |
Info: [-16203, -14647) |
Info: [-14647, -13091) |
Info: [-13091, -11535) |
Info: [-11535, -9979) |
Info: [ -9979, -8423) |
Info: [ -8423, -6867) |
Info: [ -6867, -5311) |
Info: [ -5311, -3755) |
Info: [ -3755, -2199) |
Info: [ -2199, -643) |
Info: [ -643, 913) |+
Info: [ 913, 2469) |+
Info: [ 2469, 4025) |**+
Info: [ 4025, 5581) |*******+
Info: [ 5581, 7137) |********+
Info: [ 7137, 8693) |*********************+
Info: [ 8693, 10249) |***********************************************+
Info: [ 10249, 11805) |************************************************************
0 warnings, 1 error
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n8/top.config
-301503
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hardware/v2/nms/synthesis/nms_multiproc_n8/top.json
-575514
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hardware/v2/nms/synthesis/nms_multiproc_n8/yosys.log
-18875
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