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docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq

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New brief (N=8 timing closure, LFE5U-85F retarget, 4/8/16 x 1/2-bank SDRAM
sweep). Phase 0: no RTL changes, only measure the current baseline.

ERR-0030: constraints/v2_unified.lpf's FREQUENCY PORT "clk" was still 80MHz,
a leftover from the STEP19 freeze, never updated to the project's real
64MHz target -- fixed (LPF only, zero RTL/datapath effect).

ERR-0031 (bigger one): the first two synthesis attempts targeted
nms_neural_multiprocessor_sdram_unified.v, which is NOT the real
board-level top -- it's an obsolete wrapper only exercised by one
testbench now. The real target is fpga_neural_v2_top.v (adds the real
PLL, reset_sync, spi_host_bridge, and a second arbitration level), which
is what actually goes through synthesis+P&R for hardware. Re-targeted
correctly, matched against constraints/v2_board_top.lpf (all 17 ports
real-ball-assigned).

An N_SLOTS=8 P&R attempt against the WRONG (wrapper) target ran for 2h42m
without converging on a single seed; discarded rather than trusted.
N_SLOTS=8 baseline deferred by explicit user request until N_SLOTS=4 is
fully understood -- re-attempt against the correct fpga_neural_v2_top
target with an agreed time budget.

Result (EXP-0049, fresh 8-seed nextpnr-ecp5 P&R, real pins): N_SLOTS=4
8/8 PASS at 64MHz, worst-seed 81.20MHz, mean 91.05MHz. Higher than
DEC-0042's historical worst/best (64.55/77.21MHz) despite identical RTL --
disclosed, unresolved (leading hypothesis: nextpnr-ecp5 build/version
difference), adopted as the operative baseline for this session's
toolchain going forward. Full writeup in errors.log/timing.log/
experiments.log (EXP-0049).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
michele
2026-09-15 20:28:16 +00:00
co-authored by Claude Sonnet 5
parent 8b8ca239ca
commit 685a4d6cfe
21 changed files with 573188 additions and 1290227 deletions
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hardware/v2/logs/synthesis.log
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@@ -122,3 +122,17 @@ N_SLOTS=4: LUT4=9158 CCU2C=698 TRELLIS_FF=7986 MULT18X18D=32 DP16KD=0
CHECK: 0 problems on all three (same benign warnings as always).
Resource cost is modest (activation_cache itself is small -- a
16-tile x 64-bit store plus N_SLOTS-way pending/hit logic).
[2026-09-15] EXP-0049 -- fpga_neural_v2_top (real board-level top,
N_SLOTS=4), real synthesis via the corrected flow (see errors.log
ERR-0030/ERR-0031)
LUT4=6905 (15%) DFF=6527 (14%) MULT18X18D=32/72 (44%) DP16KD=0/108
(0%) EHXPLLL=1/4 (25%) TRELLIS_IO=47/245 (19%)
CHECK: 0 problems. File list: dependency_manager.v, neural_director.v,
neural_processor.v, prefetch_engine.v, weight_prefetch_engine_wide.v,
nms_activation_replicated.v, nms_activation_fill_ctrl_v3.v,
nms_weight_packed.v, nms_memory_manager_stream_wide.v,
nms_dataflow_core_sdram.v, slot_mem_arbiter.v, slot_mem_arbiter_wide.v,
sdram_controller.v, sdram_unified_backend.v, ecp5_pll_sys_clk.v,
reset_sync.v, spi_host_bridge.v, fpga_neural_v2_top.v.
Log: hardware/v2/nms/synthesis/nms_multiproc_n4/yosys.log